Commit | Line | Data |
---|---|---|
d129bceb PO |
1 | /* |
2 | * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver | |
3 | * | |
4 | * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
d129bceb PO |
10 | */ |
11 | ||
d129bceb PO |
12 | #include <linux/delay.h> |
13 | #include <linux/highmem.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | ||
17 | #include <linux/mmc/host.h> | |
18 | #include <linux/mmc/protocol.h> | |
19 | ||
20 | #include <asm/scatterlist.h> | |
21 | ||
22 | #include "sdhci.h" | |
23 | ||
24 | #define DRIVER_NAME "sdhci" | |
d129bceb | 25 | |
d129bceb | 26 | #define DBG(f, x...) \ |
c6563178 | 27 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 28 | |
67435274 PO |
29 | static unsigned int debug_nodma = 0; |
30 | static unsigned int debug_forcedma = 0; | |
df673b22 | 31 | static unsigned int debug_quirks = 0; |
67435274 | 32 | |
645289dc | 33 | #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) |
98608076 | 34 | #define SDHCI_QUIRK_FORCE_DMA (1<<1) |
8a4da143 PO |
35 | /* Controller doesn't like some resets when there is no card inserted. */ |
36 | #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) | |
9e9dc5f2 | 37 | #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) |
645289dc | 38 | |
d129bceb | 39 | static const struct pci_device_id pci_ids[] __devinitdata = { |
645289dc PO |
40 | { |
41 | .vendor = PCI_VENDOR_ID_RICOH, | |
42 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
43 | .subvendor = PCI_VENDOR_ID_IBM, | |
44 | .subdevice = PCI_ANY_ID, | |
98608076 PO |
45 | .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET | |
46 | SDHCI_QUIRK_FORCE_DMA, | |
47 | }, | |
48 | ||
49 | { | |
50 | .vendor = PCI_VENDOR_ID_RICOH, | |
51 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
52 | .subvendor = PCI_ANY_ID, | |
53 | .subdevice = PCI_ANY_ID, | |
8a4da143 PO |
54 | .driver_data = SDHCI_QUIRK_FORCE_DMA | |
55 | SDHCI_QUIRK_NO_CARD_NO_RESET, | |
98608076 PO |
56 | }, |
57 | ||
58 | { | |
59 | .vendor = PCI_VENDOR_ID_TI, | |
60 | .device = PCI_DEVICE_ID_TI_XX21_XX11_SD, | |
61 | .subvendor = PCI_ANY_ID, | |
62 | .subdevice = PCI_ANY_ID, | |
63 | .driver_data = SDHCI_QUIRK_FORCE_DMA, | |
645289dc PO |
64 | }, |
65 | ||
9e9dc5f2 DS |
66 | { |
67 | .vendor = PCI_VENDOR_ID_ENE, | |
68 | .device = PCI_DEVICE_ID_ENE_CB712_SD, | |
69 | .subvendor = PCI_ANY_ID, | |
70 | .subdevice = PCI_ANY_ID, | |
71 | .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE, | |
72 | }, | |
73 | ||
645289dc PO |
74 | { /* Generic SD host controller */ |
75 | PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) | |
76 | }, | |
77 | ||
d129bceb PO |
78 | { /* end: all zeroes */ }, |
79 | }; | |
80 | ||
81 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
82 | ||
83 | static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *); | |
84 | static void sdhci_finish_data(struct sdhci_host *); | |
85 | ||
86 | static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); | |
87 | static void sdhci_finish_command(struct sdhci_host *); | |
88 | ||
89 | static void sdhci_dumpregs(struct sdhci_host *host) | |
90 | { | |
91 | printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n"); | |
92 | ||
93 | printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", | |
94 | readl(host->ioaddr + SDHCI_DMA_ADDRESS), | |
95 | readw(host->ioaddr + SDHCI_HOST_VERSION)); | |
96 | printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", | |
97 | readw(host->ioaddr + SDHCI_BLOCK_SIZE), | |
98 | readw(host->ioaddr + SDHCI_BLOCK_COUNT)); | |
99 | printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", | |
100 | readl(host->ioaddr + SDHCI_ARGUMENT), | |
101 | readw(host->ioaddr + SDHCI_TRANSFER_MODE)); | |
102 | printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", | |
103 | readl(host->ioaddr + SDHCI_PRESENT_STATE), | |
104 | readb(host->ioaddr + SDHCI_HOST_CONTROL)); | |
105 | printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", | |
106 | readb(host->ioaddr + SDHCI_POWER_CONTROL), | |
107 | readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL)); | |
108 | printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", | |
109 | readb(host->ioaddr + SDHCI_WALK_UP_CONTROL), | |
110 | readw(host->ioaddr + SDHCI_CLOCK_CONTROL)); | |
111 | printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", | |
112 | readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL), | |
113 | readl(host->ioaddr + SDHCI_INT_STATUS)); | |
114 | printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", | |
115 | readl(host->ioaddr + SDHCI_INT_ENABLE), | |
116 | readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)); | |
117 | printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", | |
118 | readw(host->ioaddr + SDHCI_ACMD12_ERR), | |
119 | readw(host->ioaddr + SDHCI_SLOT_INT_STATUS)); | |
120 | printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n", | |
121 | readl(host->ioaddr + SDHCI_CAPABILITIES), | |
122 | readl(host->ioaddr + SDHCI_MAX_CURRENT)); | |
123 | ||
124 | printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); | |
125 | } | |
126 | ||
127 | /*****************************************************************************\ | |
128 | * * | |
129 | * Low level functions * | |
130 | * * | |
131 | \*****************************************************************************/ | |
132 | ||
133 | static void sdhci_reset(struct sdhci_host *host, u8 mask) | |
134 | { | |
e16514d8 PO |
135 | unsigned long timeout; |
136 | ||
8a4da143 PO |
137 | if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
138 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & | |
139 | SDHCI_CARD_PRESENT)) | |
140 | return; | |
141 | } | |
142 | ||
d129bceb PO |
143 | writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET); |
144 | ||
e16514d8 | 145 | if (mask & SDHCI_RESET_ALL) |
d129bceb PO |
146 | host->clock = 0; |
147 | ||
e16514d8 PO |
148 | /* Wait max 100 ms */ |
149 | timeout = 100; | |
150 | ||
151 | /* hw clears the bit when it's done */ | |
152 | while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) { | |
153 | if (timeout == 0) { | |
acf1da45 | 154 | printk(KERN_ERR "%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
155 | mmc_hostname(host->mmc), (int)mask); |
156 | sdhci_dumpregs(host); | |
157 | return; | |
158 | } | |
159 | timeout--; | |
160 | mdelay(1); | |
d129bceb PO |
161 | } |
162 | } | |
163 | ||
164 | static void sdhci_init(struct sdhci_host *host) | |
165 | { | |
166 | u32 intmask; | |
167 | ||
168 | sdhci_reset(host, SDHCI_RESET_ALL); | |
169 | ||
3192a28f PO |
170 | intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
171 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | | |
172 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | |
173 | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | | |
a406f5a3 | 174 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | |
3192a28f | 175 | SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE; |
d129bceb PO |
176 | |
177 | writel(intmask, host->ioaddr + SDHCI_INT_ENABLE); | |
178 | writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
d129bceb PO |
179 | } |
180 | ||
181 | static void sdhci_activate_led(struct sdhci_host *host) | |
182 | { | |
183 | u8 ctrl; | |
184 | ||
185 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
186 | ctrl |= SDHCI_CTRL_LED; | |
187 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
188 | } | |
189 | ||
190 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
191 | { | |
192 | u8 ctrl; | |
193 | ||
194 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
195 | ctrl &= ~SDHCI_CTRL_LED; | |
196 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
197 | } | |
198 | ||
199 | /*****************************************************************************\ | |
200 | * * | |
201 | * Core functions * | |
202 | * * | |
203 | \*****************************************************************************/ | |
204 | ||
2a22b14e | 205 | static inline char* sdhci_sg_to_buffer(struct sdhci_host* host) |
d129bceb | 206 | { |
2a22b14e | 207 | return page_address(host->cur_sg->page) + host->cur_sg->offset; |
d129bceb PO |
208 | } |
209 | ||
210 | static inline int sdhci_next_sg(struct sdhci_host* host) | |
211 | { | |
212 | /* | |
213 | * Skip to next SG entry. | |
214 | */ | |
215 | host->cur_sg++; | |
216 | host->num_sg--; | |
217 | ||
218 | /* | |
219 | * Any entries left? | |
220 | */ | |
221 | if (host->num_sg > 0) { | |
222 | host->offset = 0; | |
223 | host->remain = host->cur_sg->length; | |
224 | } | |
225 | ||
226 | return host->num_sg; | |
227 | } | |
228 | ||
a406f5a3 | 229 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 230 | { |
a406f5a3 PO |
231 | int blksize, chunk_remain; |
232 | u32 data; | |
d129bceb | 233 | char *buffer; |
a406f5a3 | 234 | int size; |
d129bceb | 235 | |
a406f5a3 | 236 | DBG("PIO reading\n"); |
d129bceb | 237 | |
a406f5a3 PO |
238 | blksize = host->data->blksz; |
239 | chunk_remain = 0; | |
240 | data = 0; | |
d129bceb | 241 | |
2a22b14e | 242 | buffer = sdhci_sg_to_buffer(host) + host->offset; |
d129bceb | 243 | |
a406f5a3 PO |
244 | while (blksize) { |
245 | if (chunk_remain == 0) { | |
246 | data = readl(host->ioaddr + SDHCI_BUFFER); | |
247 | chunk_remain = min(blksize, 4); | |
248 | } | |
d129bceb | 249 | |
a406f5a3 PO |
250 | size = min(host->size, host->remain); |
251 | size = min(size, chunk_remain); | |
d129bceb | 252 | |
a406f5a3 PO |
253 | chunk_remain -= size; |
254 | blksize -= size; | |
255 | host->offset += size; | |
256 | host->remain -= size; | |
257 | host->size -= size; | |
258 | while (size) { | |
259 | *buffer = data & 0xFF; | |
260 | buffer++; | |
261 | data >>= 8; | |
262 | size--; | |
263 | } | |
d129bceb | 264 | |
a406f5a3 | 265 | if (host->remain == 0) { |
a406f5a3 PO |
266 | if (sdhci_next_sg(host) == 0) { |
267 | BUG_ON(blksize != 0); | |
268 | return; | |
269 | } | |
2a22b14e | 270 | buffer = sdhci_sg_to_buffer(host); |
d129bceb | 271 | } |
a406f5a3 | 272 | } |
a406f5a3 | 273 | } |
d129bceb | 274 | |
a406f5a3 PO |
275 | static void sdhci_write_block_pio(struct sdhci_host *host) |
276 | { | |
277 | int blksize, chunk_remain; | |
278 | u32 data; | |
279 | char *buffer; | |
280 | int bytes, size; | |
d129bceb | 281 | |
a406f5a3 PO |
282 | DBG("PIO writing\n"); |
283 | ||
284 | blksize = host->data->blksz; | |
285 | chunk_remain = 4; | |
286 | data = 0; | |
d129bceb | 287 | |
a406f5a3 | 288 | bytes = 0; |
2a22b14e | 289 | buffer = sdhci_sg_to_buffer(host) + host->offset; |
d129bceb | 290 | |
a406f5a3 PO |
291 | while (blksize) { |
292 | size = min(host->size, host->remain); | |
293 | size = min(size, chunk_remain); | |
294 | ||
295 | chunk_remain -= size; | |
296 | blksize -= size; | |
d129bceb PO |
297 | host->offset += size; |
298 | host->remain -= size; | |
d129bceb | 299 | host->size -= size; |
a406f5a3 PO |
300 | while (size) { |
301 | data >>= 8; | |
302 | data |= (u32)*buffer << 24; | |
303 | buffer++; | |
304 | size--; | |
305 | } | |
306 | ||
307 | if (chunk_remain == 0) { | |
308 | writel(data, host->ioaddr + SDHCI_BUFFER); | |
309 | chunk_remain = min(blksize, 4); | |
310 | } | |
d129bceb PO |
311 | |
312 | if (host->remain == 0) { | |
d129bceb | 313 | if (sdhci_next_sg(host) == 0) { |
a406f5a3 | 314 | BUG_ON(blksize != 0); |
d129bceb PO |
315 | return; |
316 | } | |
2a22b14e | 317 | buffer = sdhci_sg_to_buffer(host); |
d129bceb PO |
318 | } |
319 | } | |
a406f5a3 PO |
320 | } |
321 | ||
322 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
323 | { | |
324 | u32 mask; | |
325 | ||
326 | BUG_ON(!host->data); | |
327 | ||
328 | if (host->size == 0) | |
329 | return; | |
330 | ||
331 | if (host->data->flags & MMC_DATA_READ) | |
332 | mask = SDHCI_DATA_AVAILABLE; | |
333 | else | |
334 | mask = SDHCI_SPACE_AVAILABLE; | |
335 | ||
336 | while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { | |
337 | if (host->data->flags & MMC_DATA_READ) | |
338 | sdhci_read_block_pio(host); | |
339 | else | |
340 | sdhci_write_block_pio(host); | |
d129bceb | 341 | |
a406f5a3 PO |
342 | if (host->size == 0) |
343 | break; | |
344 | ||
345 | BUG_ON(host->num_sg == 0); | |
346 | } | |
d129bceb | 347 | |
a406f5a3 | 348 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
349 | } |
350 | ||
351 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) | |
352 | { | |
1c8cde92 PO |
353 | u8 count; |
354 | unsigned target_timeout, current_timeout; | |
d129bceb PO |
355 | |
356 | WARN_ON(host->data); | |
357 | ||
c7fa9963 | 358 | if (data == NULL) |
d129bceb | 359 | return; |
d129bceb PO |
360 | |
361 | DBG("blksz %04x blks %04x flags %08x\n", | |
a3fd4a1b | 362 | data->blksz, data->blocks, data->flags); |
d129bceb PO |
363 | DBG("tsac %d ms nsac %d clk\n", |
364 | data->timeout_ns / 1000000, data->timeout_clks); | |
365 | ||
bab76961 PO |
366 | /* Sanity checks */ |
367 | BUG_ON(data->blksz * data->blocks > 524288); | |
fe4a3c7a | 368 | BUG_ON(data->blksz > host->mmc->max_blk_size); |
1d676e02 | 369 | BUG_ON(data->blocks > 65535); |
d129bceb | 370 | |
1c8cde92 PO |
371 | /* timeout in us */ |
372 | target_timeout = data->timeout_ns / 1000 + | |
373 | data->timeout_clks / host->clock; | |
d129bceb | 374 | |
1c8cde92 PO |
375 | /* |
376 | * Figure out needed cycles. | |
377 | * We do this in steps in order to fit inside a 32 bit int. | |
378 | * The first step is the minimum timeout, which will have a | |
379 | * minimum resolution of 6 bits: | |
380 | * (1) 2^13*1000 > 2^22, | |
381 | * (2) host->timeout_clk < 2^16 | |
382 | * => | |
383 | * (1) / (2) > 2^6 | |
384 | */ | |
385 | count = 0; | |
386 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
387 | while (current_timeout < target_timeout) { | |
388 | count++; | |
389 | current_timeout <<= 1; | |
390 | if (count >= 0xF) | |
391 | break; | |
392 | } | |
393 | ||
394 | if (count >= 0xF) { | |
395 | printk(KERN_WARNING "%s: Too large timeout requested!\n", | |
396 | mmc_hostname(host->mmc)); | |
397 | count = 0xE; | |
398 | } | |
399 | ||
400 | writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL); | |
d129bceb PO |
401 | |
402 | if (host->flags & SDHCI_USE_DMA) { | |
403 | int count; | |
404 | ||
405 | count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len, | |
406 | (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE); | |
407 | BUG_ON(count != 1); | |
408 | ||
409 | writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS); | |
410 | } else { | |
a3fd4a1b | 411 | host->size = data->blksz * data->blocks; |
d129bceb PO |
412 | |
413 | host->cur_sg = data->sg; | |
414 | host->num_sg = data->sg_len; | |
415 | ||
416 | host->offset = 0; | |
417 | host->remain = host->cur_sg->length; | |
418 | } | |
c7fa9963 | 419 | |
bab76961 PO |
420 | /* We do not handle DMA boundaries, so set it to max (512 KiB) */ |
421 | writew(SDHCI_MAKE_BLKSZ(7, data->blksz), | |
422 | host->ioaddr + SDHCI_BLOCK_SIZE); | |
c7fa9963 PO |
423 | writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT); |
424 | } | |
425 | ||
426 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
427 | struct mmc_data *data) | |
428 | { | |
429 | u16 mode; | |
430 | ||
431 | WARN_ON(host->data); | |
432 | ||
433 | if (data == NULL) | |
434 | return; | |
435 | ||
436 | mode = SDHCI_TRNS_BLK_CNT_EN; | |
437 | if (data->blocks > 1) | |
438 | mode |= SDHCI_TRNS_MULTI; | |
439 | if (data->flags & MMC_DATA_READ) | |
440 | mode |= SDHCI_TRNS_READ; | |
441 | if (host->flags & SDHCI_USE_DMA) | |
442 | mode |= SDHCI_TRNS_DMA; | |
443 | ||
444 | writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE); | |
d129bceb PO |
445 | } |
446 | ||
447 | static void sdhci_finish_data(struct sdhci_host *host) | |
448 | { | |
449 | struct mmc_data *data; | |
d129bceb PO |
450 | u16 blocks; |
451 | ||
452 | BUG_ON(!host->data); | |
453 | ||
454 | data = host->data; | |
455 | host->data = NULL; | |
456 | ||
457 | if (host->flags & SDHCI_USE_DMA) { | |
458 | pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len, | |
459 | (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE); | |
d129bceb PO |
460 | } |
461 | ||
462 | /* | |
463 | * Controller doesn't count down when in single block mode. | |
464 | */ | |
465 | if ((data->blocks == 1) && (data->error == MMC_ERR_NONE)) | |
466 | blocks = 0; | |
467 | else | |
468 | blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT); | |
a3fd4a1b | 469 | data->bytes_xfered = data->blksz * (data->blocks - blocks); |
d129bceb PO |
470 | |
471 | if ((data->error == MMC_ERR_NONE) && blocks) { | |
472 | printk(KERN_ERR "%s: Controller signalled completion even " | |
acf1da45 PO |
473 | "though there were blocks left.\n", |
474 | mmc_hostname(host->mmc)); | |
d129bceb | 475 | data->error = MMC_ERR_FAILED; |
4cca56c5 | 476 | } else if (host->size != 0) { |
acf1da45 | 477 | printk(KERN_ERR "%s: %d bytes were left untransferred.\n", |
d129bceb PO |
478 | mmc_hostname(host->mmc), host->size); |
479 | data->error = MMC_ERR_FAILED; | |
480 | } | |
481 | ||
482 | DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered); | |
483 | ||
484 | if (data->stop) { | |
485 | /* | |
486 | * The controller needs a reset of internal state machines | |
487 | * upon error conditions. | |
488 | */ | |
489 | if (data->error != MMC_ERR_NONE) { | |
490 | sdhci_reset(host, SDHCI_RESET_CMD); | |
491 | sdhci_reset(host, SDHCI_RESET_DATA); | |
492 | } | |
493 | ||
494 | sdhci_send_command(host, data->stop); | |
495 | } else | |
496 | tasklet_schedule(&host->finish_tasklet); | |
497 | } | |
498 | ||
499 | static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) | |
500 | { | |
501 | int flags; | |
fd2208d7 | 502 | u32 mask; |
7cb2c76f | 503 | unsigned long timeout; |
d129bceb PO |
504 | |
505 | WARN_ON(host->cmd); | |
506 | ||
507 | DBG("Sending cmd (%x)\n", cmd->opcode); | |
508 | ||
509 | /* Wait max 10 ms */ | |
7cb2c76f | 510 | timeout = 10; |
fd2208d7 PO |
511 | |
512 | mask = SDHCI_CMD_INHIBIT; | |
513 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
514 | mask |= SDHCI_DATA_INHIBIT; | |
515 | ||
516 | /* We shouldn't wait for data inihibit for stop commands, even | |
517 | though they might use busy signaling */ | |
518 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
519 | mask &= ~SDHCI_DATA_INHIBIT; | |
520 | ||
521 | while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { | |
7cb2c76f | 522 | if (timeout == 0) { |
d129bceb | 523 | printk(KERN_ERR "%s: Controller never released " |
acf1da45 | 524 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb PO |
525 | sdhci_dumpregs(host); |
526 | cmd->error = MMC_ERR_FAILED; | |
527 | tasklet_schedule(&host->finish_tasklet); | |
528 | return; | |
529 | } | |
7cb2c76f PO |
530 | timeout--; |
531 | mdelay(1); | |
532 | } | |
d129bceb PO |
533 | |
534 | mod_timer(&host->timer, jiffies + 10 * HZ); | |
535 | ||
536 | host->cmd = cmd; | |
537 | ||
538 | sdhci_prepare_data(host, cmd->data); | |
539 | ||
540 | writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT); | |
541 | ||
c7fa9963 PO |
542 | sdhci_set_transfer_mode(host, cmd->data); |
543 | ||
d129bceb | 544 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
acf1da45 | 545 | printk(KERN_ERR "%s: Unsupported response type!\n", |
d129bceb PO |
546 | mmc_hostname(host->mmc)); |
547 | cmd->error = MMC_ERR_INVALID; | |
548 | tasklet_schedule(&host->finish_tasklet); | |
549 | return; | |
550 | } | |
551 | ||
552 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
553 | flags = SDHCI_CMD_RESP_NONE; | |
554 | else if (cmd->flags & MMC_RSP_136) | |
555 | flags = SDHCI_CMD_RESP_LONG; | |
556 | else if (cmd->flags & MMC_RSP_BUSY) | |
557 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
558 | else | |
559 | flags = SDHCI_CMD_RESP_SHORT; | |
560 | ||
561 | if (cmd->flags & MMC_RSP_CRC) | |
562 | flags |= SDHCI_CMD_CRC; | |
563 | if (cmd->flags & MMC_RSP_OPCODE) | |
564 | flags |= SDHCI_CMD_INDEX; | |
565 | if (cmd->data) | |
566 | flags |= SDHCI_CMD_DATA; | |
567 | ||
fb61e289 | 568 | writew(SDHCI_MAKE_CMD(cmd->opcode, flags), |
d129bceb PO |
569 | host->ioaddr + SDHCI_COMMAND); |
570 | } | |
571 | ||
572 | static void sdhci_finish_command(struct sdhci_host *host) | |
573 | { | |
574 | int i; | |
575 | ||
576 | BUG_ON(host->cmd == NULL); | |
577 | ||
578 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
579 | if (host->cmd->flags & MMC_RSP_136) { | |
580 | /* CRC is stripped so we need to do some shifting. */ | |
581 | for (i = 0;i < 4;i++) { | |
582 | host->cmd->resp[i] = readl(host->ioaddr + | |
583 | SDHCI_RESPONSE + (3-i)*4) << 8; | |
584 | if (i != 3) | |
585 | host->cmd->resp[i] |= | |
586 | readb(host->ioaddr + | |
587 | SDHCI_RESPONSE + (3-i)*4-1); | |
588 | } | |
589 | } else { | |
590 | host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE); | |
591 | } | |
592 | } | |
593 | ||
594 | host->cmd->error = MMC_ERR_NONE; | |
595 | ||
596 | DBG("Ending cmd (%x)\n", host->cmd->opcode); | |
597 | ||
3192a28f | 598 | if (host->cmd->data) |
d129bceb | 599 | host->data = host->cmd->data; |
3192a28f | 600 | else |
d129bceb PO |
601 | tasklet_schedule(&host->finish_tasklet); |
602 | ||
603 | host->cmd = NULL; | |
604 | } | |
605 | ||
606 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | |
607 | { | |
608 | int div; | |
609 | u16 clk; | |
7cb2c76f | 610 | unsigned long timeout; |
d129bceb PO |
611 | |
612 | if (clock == host->clock) | |
613 | return; | |
614 | ||
615 | writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
616 | ||
617 | if (clock == 0) | |
618 | goto out; | |
619 | ||
620 | for (div = 1;div < 256;div *= 2) { | |
621 | if ((host->max_clk / div) <= clock) | |
622 | break; | |
623 | } | |
624 | div >>= 1; | |
625 | ||
626 | clk = div << SDHCI_DIVIDER_SHIFT; | |
627 | clk |= SDHCI_CLOCK_INT_EN; | |
628 | writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
629 | ||
630 | /* Wait max 10 ms */ | |
7cb2c76f PO |
631 | timeout = 10; |
632 | while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL)) | |
633 | & SDHCI_CLOCK_INT_STABLE)) { | |
634 | if (timeout == 0) { | |
acf1da45 PO |
635 | printk(KERN_ERR "%s: Internal clock never " |
636 | "stabilised.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
637 | sdhci_dumpregs(host); |
638 | return; | |
639 | } | |
7cb2c76f PO |
640 | timeout--; |
641 | mdelay(1); | |
642 | } | |
d129bceb PO |
643 | |
644 | clk |= SDHCI_CLOCK_CARD_EN; | |
645 | writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
646 | ||
647 | out: | |
648 | host->clock = clock; | |
649 | } | |
650 | ||
146ad66e PO |
651 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
652 | { | |
653 | u8 pwr; | |
654 | ||
655 | if (host->power == power) | |
656 | return; | |
657 | ||
9e9dc5f2 DS |
658 | if (power == (unsigned short)-1) { |
659 | writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); | |
146ad66e | 660 | goto out; |
9e9dc5f2 DS |
661 | } |
662 | ||
663 | /* | |
664 | * Spec says that we should clear the power reg before setting | |
665 | * a new value. Some controllers don't seem to like this though. | |
666 | */ | |
667 | if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) | |
668 | writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); | |
146ad66e PO |
669 | |
670 | pwr = SDHCI_POWER_ON; | |
671 | ||
672 | switch (power) { | |
673 | case MMC_VDD_170: | |
674 | case MMC_VDD_180: | |
675 | case MMC_VDD_190: | |
676 | pwr |= SDHCI_POWER_180; | |
677 | break; | |
678 | case MMC_VDD_290: | |
679 | case MMC_VDD_300: | |
680 | case MMC_VDD_310: | |
681 | pwr |= SDHCI_POWER_300; | |
682 | break; | |
683 | case MMC_VDD_320: | |
684 | case MMC_VDD_330: | |
685 | case MMC_VDD_340: | |
686 | pwr |= SDHCI_POWER_330; | |
687 | break; | |
688 | default: | |
689 | BUG(); | |
690 | } | |
691 | ||
692 | writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); | |
693 | ||
694 | out: | |
695 | host->power = power; | |
696 | } | |
697 | ||
d129bceb PO |
698 | /*****************************************************************************\ |
699 | * * | |
700 | * MMC callbacks * | |
701 | * * | |
702 | \*****************************************************************************/ | |
703 | ||
704 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
705 | { | |
706 | struct sdhci_host *host; | |
707 | unsigned long flags; | |
708 | ||
709 | host = mmc_priv(mmc); | |
710 | ||
711 | spin_lock_irqsave(&host->lock, flags); | |
712 | ||
713 | WARN_ON(host->mrq != NULL); | |
714 | ||
715 | sdhci_activate_led(host); | |
716 | ||
717 | host->mrq = mrq; | |
718 | ||
719 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { | |
720 | host->mrq->cmd->error = MMC_ERR_TIMEOUT; | |
721 | tasklet_schedule(&host->finish_tasklet); | |
722 | } else | |
723 | sdhci_send_command(host, mrq->cmd); | |
724 | ||
5f25a66f | 725 | mmiowb(); |
d129bceb PO |
726 | spin_unlock_irqrestore(&host->lock, flags); |
727 | } | |
728 | ||
729 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
730 | { | |
731 | struct sdhci_host *host; | |
732 | unsigned long flags; | |
733 | u8 ctrl; | |
734 | ||
735 | host = mmc_priv(mmc); | |
736 | ||
737 | spin_lock_irqsave(&host->lock, flags); | |
738 | ||
d129bceb PO |
739 | /* |
740 | * Reset the chip on each power off. | |
741 | * Should clear out any weird states. | |
742 | */ | |
743 | if (ios->power_mode == MMC_POWER_OFF) { | |
744 | writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
d129bceb | 745 | sdhci_init(host); |
d129bceb PO |
746 | } |
747 | ||
748 | sdhci_set_clock(host, ios->clock); | |
749 | ||
750 | if (ios->power_mode == MMC_POWER_OFF) | |
146ad66e | 751 | sdhci_set_power(host, -1); |
d129bceb | 752 | else |
146ad66e | 753 | sdhci_set_power(host, ios->vdd); |
d129bceb PO |
754 | |
755 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
cd9277c0 | 756 | |
d129bceb PO |
757 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
758 | ctrl |= SDHCI_CTRL_4BITBUS; | |
759 | else | |
760 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
cd9277c0 PO |
761 | |
762 | if (ios->timing == MMC_TIMING_SD_HS) | |
763 | ctrl |= SDHCI_CTRL_HISPD; | |
764 | else | |
765 | ctrl &= ~SDHCI_CTRL_HISPD; | |
766 | ||
d129bceb PO |
767 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); |
768 | ||
5f25a66f | 769 | mmiowb(); |
d129bceb PO |
770 | spin_unlock_irqrestore(&host->lock, flags); |
771 | } | |
772 | ||
773 | static int sdhci_get_ro(struct mmc_host *mmc) | |
774 | { | |
775 | struct sdhci_host *host; | |
776 | unsigned long flags; | |
777 | int present; | |
778 | ||
779 | host = mmc_priv(mmc); | |
780 | ||
781 | spin_lock_irqsave(&host->lock, flags); | |
782 | ||
783 | present = readl(host->ioaddr + SDHCI_PRESENT_STATE); | |
784 | ||
785 | spin_unlock_irqrestore(&host->lock, flags); | |
786 | ||
787 | return !(present & SDHCI_WRITE_PROTECT); | |
788 | } | |
789 | ||
ab7aefd0 | 790 | static const struct mmc_host_ops sdhci_ops = { |
d129bceb PO |
791 | .request = sdhci_request, |
792 | .set_ios = sdhci_set_ios, | |
793 | .get_ro = sdhci_get_ro, | |
794 | }; | |
795 | ||
796 | /*****************************************************************************\ | |
797 | * * | |
798 | * Tasklets * | |
799 | * * | |
800 | \*****************************************************************************/ | |
801 | ||
802 | static void sdhci_tasklet_card(unsigned long param) | |
803 | { | |
804 | struct sdhci_host *host; | |
805 | unsigned long flags; | |
806 | ||
807 | host = (struct sdhci_host*)param; | |
808 | ||
809 | spin_lock_irqsave(&host->lock, flags); | |
810 | ||
811 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { | |
812 | if (host->mrq) { | |
813 | printk(KERN_ERR "%s: Card removed during transfer!\n", | |
814 | mmc_hostname(host->mmc)); | |
815 | printk(KERN_ERR "%s: Resetting controller.\n", | |
816 | mmc_hostname(host->mmc)); | |
817 | ||
818 | sdhci_reset(host, SDHCI_RESET_CMD); | |
819 | sdhci_reset(host, SDHCI_RESET_DATA); | |
820 | ||
821 | host->mrq->cmd->error = MMC_ERR_FAILED; | |
822 | tasklet_schedule(&host->finish_tasklet); | |
823 | } | |
824 | } | |
825 | ||
826 | spin_unlock_irqrestore(&host->lock, flags); | |
827 | ||
828 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
829 | } | |
830 | ||
831 | static void sdhci_tasklet_finish(unsigned long param) | |
832 | { | |
833 | struct sdhci_host *host; | |
834 | unsigned long flags; | |
835 | struct mmc_request *mrq; | |
836 | ||
837 | host = (struct sdhci_host*)param; | |
838 | ||
839 | spin_lock_irqsave(&host->lock, flags); | |
840 | ||
841 | del_timer(&host->timer); | |
842 | ||
843 | mrq = host->mrq; | |
844 | ||
845 | DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode); | |
846 | ||
847 | /* | |
848 | * The controller needs a reset of internal state machines | |
849 | * upon error conditions. | |
850 | */ | |
851 | if ((mrq->cmd->error != MMC_ERR_NONE) || | |
852 | (mrq->data && ((mrq->data->error != MMC_ERR_NONE) || | |
853 | (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) { | |
645289dc PO |
854 | |
855 | /* Some controllers need this kick or reset won't work here */ | |
856 | if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { | |
857 | unsigned int clock; | |
858 | ||
859 | /* This is to force an update */ | |
860 | clock = host->clock; | |
861 | host->clock = 0; | |
862 | sdhci_set_clock(host, clock); | |
863 | } | |
864 | ||
865 | /* Spec says we should do both at the same time, but Ricoh | |
866 | controllers do not like that. */ | |
d129bceb PO |
867 | sdhci_reset(host, SDHCI_RESET_CMD); |
868 | sdhci_reset(host, SDHCI_RESET_DATA); | |
869 | } | |
870 | ||
871 | host->mrq = NULL; | |
872 | host->cmd = NULL; | |
873 | host->data = NULL; | |
874 | ||
875 | sdhci_deactivate_led(host); | |
876 | ||
5f25a66f | 877 | mmiowb(); |
d129bceb PO |
878 | spin_unlock_irqrestore(&host->lock, flags); |
879 | ||
880 | mmc_request_done(host->mmc, mrq); | |
881 | } | |
882 | ||
883 | static void sdhci_timeout_timer(unsigned long data) | |
884 | { | |
885 | struct sdhci_host *host; | |
886 | unsigned long flags; | |
887 | ||
888 | host = (struct sdhci_host*)data; | |
889 | ||
890 | spin_lock_irqsave(&host->lock, flags); | |
891 | ||
892 | if (host->mrq) { | |
acf1da45 PO |
893 | printk(KERN_ERR "%s: Timeout waiting for hardware " |
894 | "interrupt.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
895 | sdhci_dumpregs(host); |
896 | ||
897 | if (host->data) { | |
898 | host->data->error = MMC_ERR_TIMEOUT; | |
899 | sdhci_finish_data(host); | |
900 | } else { | |
901 | if (host->cmd) | |
902 | host->cmd->error = MMC_ERR_TIMEOUT; | |
903 | else | |
904 | host->mrq->cmd->error = MMC_ERR_TIMEOUT; | |
905 | ||
906 | tasklet_schedule(&host->finish_tasklet); | |
907 | } | |
908 | } | |
909 | ||
5f25a66f | 910 | mmiowb(); |
d129bceb PO |
911 | spin_unlock_irqrestore(&host->lock, flags); |
912 | } | |
913 | ||
914 | /*****************************************************************************\ | |
915 | * * | |
916 | * Interrupt handling * | |
917 | * * | |
918 | \*****************************************************************************/ | |
919 | ||
920 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
921 | { | |
922 | BUG_ON(intmask == 0); | |
923 | ||
924 | if (!host->cmd) { | |
925 | printk(KERN_ERR "%s: Got command interrupt even though no " | |
926 | "command operation was in progress.\n", | |
927 | mmc_hostname(host->mmc)); | |
d129bceb PO |
928 | sdhci_dumpregs(host); |
929 | return; | |
930 | } | |
931 | ||
932 | if (intmask & SDHCI_INT_RESPONSE) | |
933 | sdhci_finish_command(host); | |
934 | else { | |
935 | if (intmask & SDHCI_INT_TIMEOUT) | |
936 | host->cmd->error = MMC_ERR_TIMEOUT; | |
937 | else if (intmask & SDHCI_INT_CRC) | |
938 | host->cmd->error = MMC_ERR_BADCRC; | |
939 | else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) | |
940 | host->cmd->error = MMC_ERR_FAILED; | |
941 | else | |
942 | host->cmd->error = MMC_ERR_INVALID; | |
943 | ||
944 | tasklet_schedule(&host->finish_tasklet); | |
945 | } | |
946 | } | |
947 | ||
948 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) | |
949 | { | |
950 | BUG_ON(intmask == 0); | |
951 | ||
952 | if (!host->data) { | |
953 | /* | |
954 | * A data end interrupt is sent together with the response | |
955 | * for the stop command. | |
956 | */ | |
957 | if (intmask & SDHCI_INT_DATA_END) | |
958 | return; | |
959 | ||
960 | printk(KERN_ERR "%s: Got data interrupt even though no " | |
961 | "data operation was in progress.\n", | |
962 | mmc_hostname(host->mmc)); | |
d129bceb PO |
963 | sdhci_dumpregs(host); |
964 | ||
965 | return; | |
966 | } | |
967 | ||
968 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
969 | host->data->error = MMC_ERR_TIMEOUT; | |
970 | else if (intmask & SDHCI_INT_DATA_CRC) | |
971 | host->data->error = MMC_ERR_BADCRC; | |
972 | else if (intmask & SDHCI_INT_DATA_END_BIT) | |
973 | host->data->error = MMC_ERR_FAILED; | |
974 | ||
975 | if (host->data->error != MMC_ERR_NONE) | |
976 | sdhci_finish_data(host); | |
977 | else { | |
a406f5a3 | 978 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
979 | sdhci_transfer_pio(host); |
980 | ||
981 | if (intmask & SDHCI_INT_DATA_END) | |
982 | sdhci_finish_data(host); | |
983 | } | |
984 | } | |
985 | ||
7d12e780 | 986 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb PO |
987 | { |
988 | irqreturn_t result; | |
989 | struct sdhci_host* host = dev_id; | |
990 | u32 intmask; | |
991 | ||
992 | spin_lock(&host->lock); | |
993 | ||
994 | intmask = readl(host->ioaddr + SDHCI_INT_STATUS); | |
995 | ||
996 | if (!intmask) { | |
997 | result = IRQ_NONE; | |
998 | goto out; | |
999 | } | |
1000 | ||
1001 | DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask); | |
1002 | ||
3192a28f PO |
1003 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
1004 | writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE), | |
1005 | host->ioaddr + SDHCI_INT_STATUS); | |
d129bceb | 1006 | tasklet_schedule(&host->card_tasklet); |
3192a28f | 1007 | } |
d129bceb | 1008 | |
3192a28f | 1009 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
d129bceb | 1010 | |
3192a28f | 1011 | if (intmask & SDHCI_INT_CMD_MASK) { |
d129bceb PO |
1012 | writel(intmask & SDHCI_INT_CMD_MASK, |
1013 | host->ioaddr + SDHCI_INT_STATUS); | |
3192a28f | 1014 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
d129bceb PO |
1015 | } |
1016 | ||
1017 | if (intmask & SDHCI_INT_DATA_MASK) { | |
d129bceb PO |
1018 | writel(intmask & SDHCI_INT_DATA_MASK, |
1019 | host->ioaddr + SDHCI_INT_STATUS); | |
3192a28f | 1020 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
d129bceb PO |
1021 | } |
1022 | ||
1023 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | |
1024 | ||
d129bceb | 1025 | if (intmask & SDHCI_INT_BUS_POWER) { |
3192a28f | 1026 | printk(KERN_ERR "%s: Card is consuming too much power!\n", |
d129bceb | 1027 | mmc_hostname(host->mmc)); |
3192a28f | 1028 | writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS); |
d129bceb PO |
1029 | } |
1030 | ||
3192a28f PO |
1031 | intmask &= SDHCI_INT_BUS_POWER; |
1032 | ||
1033 | if (intmask) { | |
acf1da45 | 1034 | printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", |
3192a28f | 1035 | mmc_hostname(host->mmc), intmask); |
d129bceb PO |
1036 | sdhci_dumpregs(host); |
1037 | ||
d129bceb | 1038 | writel(intmask, host->ioaddr + SDHCI_INT_STATUS); |
3192a28f | 1039 | } |
d129bceb PO |
1040 | |
1041 | result = IRQ_HANDLED; | |
1042 | ||
5f25a66f | 1043 | mmiowb(); |
d129bceb PO |
1044 | out: |
1045 | spin_unlock(&host->lock); | |
1046 | ||
1047 | return result; | |
1048 | } | |
1049 | ||
1050 | /*****************************************************************************\ | |
1051 | * * | |
1052 | * Suspend/resume * | |
1053 | * * | |
1054 | \*****************************************************************************/ | |
1055 | ||
1056 | #ifdef CONFIG_PM | |
1057 | ||
1058 | static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state) | |
1059 | { | |
1060 | struct sdhci_chip *chip; | |
1061 | int i, ret; | |
1062 | ||
1063 | chip = pci_get_drvdata(pdev); | |
1064 | if (!chip) | |
1065 | return 0; | |
1066 | ||
1067 | DBG("Suspending...\n"); | |
1068 | ||
1069 | for (i = 0;i < chip->num_slots;i++) { | |
1070 | if (!chip->hosts[i]) | |
1071 | continue; | |
1072 | ret = mmc_suspend_host(chip->hosts[i]->mmc, state); | |
1073 | if (ret) { | |
1074 | for (i--;i >= 0;i--) | |
1075 | mmc_resume_host(chip->hosts[i]->mmc); | |
1076 | return ret; | |
1077 | } | |
1078 | } | |
1079 | ||
1080 | pci_save_state(pdev); | |
1081 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | |
1082 | pci_disable_device(pdev); | |
1083 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | static int sdhci_resume (struct pci_dev *pdev) | |
1089 | { | |
1090 | struct sdhci_chip *chip; | |
1091 | int i, ret; | |
1092 | ||
1093 | chip = pci_get_drvdata(pdev); | |
1094 | if (!chip) | |
1095 | return 0; | |
1096 | ||
1097 | DBG("Resuming...\n"); | |
1098 | ||
1099 | pci_set_power_state(pdev, PCI_D0); | |
1100 | pci_restore_state(pdev); | |
df1c4b7b PO |
1101 | ret = pci_enable_device(pdev); |
1102 | if (ret) | |
1103 | return ret; | |
d129bceb PO |
1104 | |
1105 | for (i = 0;i < chip->num_slots;i++) { | |
1106 | if (!chip->hosts[i]) | |
1107 | continue; | |
1108 | if (chip->hosts[i]->flags & SDHCI_USE_DMA) | |
1109 | pci_set_master(pdev); | |
1110 | sdhci_init(chip->hosts[i]); | |
5f25a66f | 1111 | mmiowb(); |
d129bceb PO |
1112 | ret = mmc_resume_host(chip->hosts[i]->mmc); |
1113 | if (ret) | |
1114 | return ret; | |
1115 | } | |
1116 | ||
1117 | return 0; | |
1118 | } | |
1119 | ||
1120 | #else /* CONFIG_PM */ | |
1121 | ||
1122 | #define sdhci_suspend NULL | |
1123 | #define sdhci_resume NULL | |
1124 | ||
1125 | #endif /* CONFIG_PM */ | |
1126 | ||
1127 | /*****************************************************************************\ | |
1128 | * * | |
1129 | * Device probing/removal * | |
1130 | * * | |
1131 | \*****************************************************************************/ | |
1132 | ||
1133 | static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot) | |
1134 | { | |
1135 | int ret; | |
4a965505 | 1136 | unsigned int version; |
d129bceb PO |
1137 | struct sdhci_chip *chip; |
1138 | struct mmc_host *mmc; | |
1139 | struct sdhci_host *host; | |
1140 | ||
1141 | u8 first_bar; | |
1142 | unsigned int caps; | |
1143 | ||
1144 | chip = pci_get_drvdata(pdev); | |
1145 | BUG_ON(!chip); | |
1146 | ||
1147 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); | |
1148 | if (ret) | |
1149 | return ret; | |
1150 | ||
1151 | first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; | |
1152 | ||
1153 | if (first_bar > 5) { | |
1154 | printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n"); | |
1155 | return -ENODEV; | |
1156 | } | |
1157 | ||
1158 | if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) { | |
1159 | printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n"); | |
1160 | return -ENODEV; | |
1161 | } | |
1162 | ||
1163 | if (pci_resource_len(pdev, first_bar + slot) != 0x100) { | |
a98087cf PO |
1164 | printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. " |
1165 | "You may experience problems.\n"); | |
d129bceb PO |
1166 | } |
1167 | ||
67435274 PO |
1168 | if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { |
1169 | printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n"); | |
1170 | return -ENODEV; | |
1171 | } | |
1172 | ||
1173 | if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { | |
1174 | printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n"); | |
1175 | return -ENODEV; | |
1176 | } | |
1177 | ||
d129bceb PO |
1178 | mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev); |
1179 | if (!mmc) | |
1180 | return -ENOMEM; | |
1181 | ||
1182 | host = mmc_priv(mmc); | |
1183 | host->mmc = mmc; | |
1184 | ||
8a4da143 PO |
1185 | host->chip = chip; |
1186 | chip->hosts[slot] = host; | |
1187 | ||
d129bceb PO |
1188 | host->bar = first_bar + slot; |
1189 | ||
1190 | host->addr = pci_resource_start(pdev, host->bar); | |
1191 | host->irq = pdev->irq; | |
1192 | ||
1193 | DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq); | |
1194 | ||
1195 | snprintf(host->slot_descr, 20, "sdhci:slot%d", slot); | |
1196 | ||
1197 | ret = pci_request_region(pdev, host->bar, host->slot_descr); | |
1198 | if (ret) | |
1199 | goto free; | |
1200 | ||
1201 | host->ioaddr = ioremap_nocache(host->addr, | |
1202 | pci_resource_len(pdev, host->bar)); | |
1203 | if (!host->ioaddr) { | |
1204 | ret = -ENOMEM; | |
1205 | goto release; | |
1206 | } | |
1207 | ||
d96649ed PO |
1208 | sdhci_reset(host, SDHCI_RESET_ALL); |
1209 | ||
4a965505 PO |
1210 | version = readw(host->ioaddr + SDHCI_HOST_VERSION); |
1211 | version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; | |
1212 | if (version != 0) { | |
1213 | printk(KERN_ERR "%s: Unknown controller version (%d). " | |
8b1b2185 | 1214 | "You may experience problems.\n", host->slot_descr, |
4a965505 | 1215 | version); |
4a965505 PO |
1216 | } |
1217 | ||
d129bceb PO |
1218 | caps = readl(host->ioaddr + SDHCI_CAPABILITIES); |
1219 | ||
67435274 PO |
1220 | if (debug_nodma) |
1221 | DBG("DMA forced off\n"); | |
1222 | else if (debug_forcedma) { | |
1223 | DBG("DMA forced on\n"); | |
1224 | host->flags |= SDHCI_USE_DMA; | |
98608076 PO |
1225 | } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA) |
1226 | host->flags |= SDHCI_USE_DMA; | |
1227 | else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) | |
67435274 PO |
1228 | DBG("Controller doesn't have DMA interface\n"); |
1229 | else if (!(caps & SDHCI_CAN_DO_DMA)) | |
1230 | DBG("Controller doesn't have DMA capability\n"); | |
1231 | else | |
d129bceb PO |
1232 | host->flags |= SDHCI_USE_DMA; |
1233 | ||
1234 | if (host->flags & SDHCI_USE_DMA) { | |
1235 | if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { | |
1236 | printk(KERN_WARNING "%s: No suitable DMA available. " | |
1237 | "Falling back to PIO.\n", host->slot_descr); | |
1238 | host->flags &= ~SDHCI_USE_DMA; | |
1239 | } | |
1240 | } | |
1241 | ||
1242 | if (host->flags & SDHCI_USE_DMA) | |
1243 | pci_set_master(pdev); | |
1244 | else /* XXX: Hack to get MMC layer to avoid highmem */ | |
1245 | pdev->dma_mask = 0; | |
1246 | ||
8ef1a143 PO |
1247 | host->max_clk = |
1248 | (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; | |
1249 | if (host->max_clk == 0) { | |
1250 | printk(KERN_ERR "%s: Hardware doesn't specify base clock " | |
1251 | "frequency.\n", host->slot_descr); | |
1252 | ret = -ENODEV; | |
1253 | goto unmap; | |
1254 | } | |
d129bceb PO |
1255 | host->max_clk *= 1000000; |
1256 | ||
1c8cde92 PO |
1257 | host->timeout_clk = |
1258 | (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
1259 | if (host->timeout_clk == 0) { | |
1260 | printk(KERN_ERR "%s: Hardware doesn't specify timeout clock " | |
1261 | "frequency.\n", host->slot_descr); | |
1262 | ret = -ENODEV; | |
1263 | goto unmap; | |
1264 | } | |
1265 | if (caps & SDHCI_TIMEOUT_CLK_UNIT) | |
1266 | host->timeout_clk *= 1000; | |
d129bceb PO |
1267 | |
1268 | /* | |
1269 | * Set host parameters. | |
1270 | */ | |
1271 | mmc->ops = &sdhci_ops; | |
1272 | mmc->f_min = host->max_clk / 256; | |
1273 | mmc->f_max = host->max_clk; | |
42431acb | 1274 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK; |
d129bceb | 1275 | |
cd9277c0 PO |
1276 | if (caps & SDHCI_CAN_DO_HISPD) |
1277 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; | |
1278 | ||
146ad66e PO |
1279 | mmc->ocr_avail = 0; |
1280 | if (caps & SDHCI_CAN_VDD_330) | |
1281 | mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34; | |
c70840e8 | 1282 | if (caps & SDHCI_CAN_VDD_300) |
146ad66e | 1283 | mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31; |
c70840e8 | 1284 | if (caps & SDHCI_CAN_VDD_180) |
146ad66e PO |
1285 | mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19; |
1286 | ||
1287 | if (mmc->ocr_avail == 0) { | |
1288 | printk(KERN_ERR "%s: Hardware doesn't report any " | |
1289 | "support voltages.\n", host->slot_descr); | |
1290 | ret = -ENODEV; | |
1291 | goto unmap; | |
1292 | } | |
1293 | ||
d129bceb PO |
1294 | spin_lock_init(&host->lock); |
1295 | ||
1296 | /* | |
1297 | * Maximum number of segments. Hardware cannot do scatter lists. | |
1298 | */ | |
1299 | if (host->flags & SDHCI_USE_DMA) | |
1300 | mmc->max_hw_segs = 1; | |
1301 | else | |
1302 | mmc->max_hw_segs = 16; | |
1303 | mmc->max_phys_segs = 16; | |
1304 | ||
1305 | /* | |
bab76961 | 1306 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 1307 | * size (512KiB). |
d129bceb | 1308 | */ |
55db890a | 1309 | mmc->max_req_size = 524288; |
d129bceb PO |
1310 | |
1311 | /* | |
1312 | * Maximum segment size. Could be one segment with the maximum number | |
55db890a | 1313 | * of bytes. |
d129bceb | 1314 | */ |
55db890a | 1315 | mmc->max_seg_size = mmc->max_req_size; |
d129bceb | 1316 | |
fe4a3c7a PO |
1317 | /* |
1318 | * Maximum block size. This varies from controller to controller and | |
1319 | * is specified in the capabilities register. | |
1320 | */ | |
1321 | mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT; | |
1322 | if (mmc->max_blk_size >= 3) { | |
1323 | printk(KERN_ERR "%s: Invalid maximum block size.\n", | |
1324 | host->slot_descr); | |
1325 | ret = -ENODEV; | |
1326 | goto unmap; | |
1327 | } | |
1328 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
1329 | ||
55db890a PO |
1330 | /* |
1331 | * Maximum block count. | |
1332 | */ | |
1333 | mmc->max_blk_count = 65535; | |
1334 | ||
d129bceb PO |
1335 | /* |
1336 | * Init tasklets. | |
1337 | */ | |
1338 | tasklet_init(&host->card_tasklet, | |
1339 | sdhci_tasklet_card, (unsigned long)host); | |
1340 | tasklet_init(&host->finish_tasklet, | |
1341 | sdhci_tasklet_finish, (unsigned long)host); | |
1342 | ||
e4cad1b5 | 1343 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 1344 | |
dace1453 | 1345 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
d129bceb PO |
1346 | host->slot_descr, host); |
1347 | if (ret) | |
8ef1a143 | 1348 | goto untasklet; |
d129bceb PO |
1349 | |
1350 | sdhci_init(host); | |
1351 | ||
1352 | #ifdef CONFIG_MMC_DEBUG | |
1353 | sdhci_dumpregs(host); | |
1354 | #endif | |
1355 | ||
5f25a66f PO |
1356 | mmiowb(); |
1357 | ||
d129bceb PO |
1358 | mmc_add_host(mmc); |
1359 | ||
1360 | printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc), | |
1361 | host->addr, host->irq, | |
1362 | (host->flags & SDHCI_USE_DMA)?"DMA":"PIO"); | |
1363 | ||
1364 | return 0; | |
1365 | ||
8ef1a143 | 1366 | untasklet: |
d129bceb PO |
1367 | tasklet_kill(&host->card_tasklet); |
1368 | tasklet_kill(&host->finish_tasklet); | |
8ef1a143 | 1369 | unmap: |
d129bceb PO |
1370 | iounmap(host->ioaddr); |
1371 | release: | |
1372 | pci_release_region(pdev, host->bar); | |
1373 | free: | |
1374 | mmc_free_host(mmc); | |
1375 | ||
1376 | return ret; | |
1377 | } | |
1378 | ||
1379 | static void sdhci_remove_slot(struct pci_dev *pdev, int slot) | |
1380 | { | |
1381 | struct sdhci_chip *chip; | |
1382 | struct mmc_host *mmc; | |
1383 | struct sdhci_host *host; | |
1384 | ||
1385 | chip = pci_get_drvdata(pdev); | |
1386 | host = chip->hosts[slot]; | |
1387 | mmc = host->mmc; | |
1388 | ||
1389 | chip->hosts[slot] = NULL; | |
1390 | ||
1391 | mmc_remove_host(mmc); | |
1392 | ||
1393 | sdhci_reset(host, SDHCI_RESET_ALL); | |
1394 | ||
1395 | free_irq(host->irq, host); | |
1396 | ||
1397 | del_timer_sync(&host->timer); | |
1398 | ||
1399 | tasklet_kill(&host->card_tasklet); | |
1400 | tasklet_kill(&host->finish_tasklet); | |
1401 | ||
1402 | iounmap(host->ioaddr); | |
1403 | ||
1404 | pci_release_region(pdev, host->bar); | |
1405 | ||
1406 | mmc_free_host(mmc); | |
1407 | } | |
1408 | ||
1409 | static int __devinit sdhci_probe(struct pci_dev *pdev, | |
1410 | const struct pci_device_id *ent) | |
1411 | { | |
1412 | int ret, i; | |
51f82bc0 | 1413 | u8 slots, rev; |
d129bceb PO |
1414 | struct sdhci_chip *chip; |
1415 | ||
1416 | BUG_ON(pdev == NULL); | |
1417 | BUG_ON(ent == NULL); | |
1418 | ||
51f82bc0 PO |
1419 | pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev); |
1420 | ||
1421 | printk(KERN_INFO DRIVER_NAME | |
1422 | ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n", | |
1423 | pci_name(pdev), (int)pdev->vendor, (int)pdev->device, | |
1424 | (int)rev); | |
d129bceb PO |
1425 | |
1426 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); | |
1427 | if (ret) | |
1428 | return ret; | |
1429 | ||
1430 | slots = PCI_SLOT_INFO_SLOTS(slots) + 1; | |
1431 | DBG("found %d slot(s)\n", slots); | |
1432 | if (slots == 0) | |
1433 | return -ENODEV; | |
1434 | ||
1435 | ret = pci_enable_device(pdev); | |
1436 | if (ret) | |
1437 | return ret; | |
1438 | ||
1439 | chip = kzalloc(sizeof(struct sdhci_chip) + | |
1440 | sizeof(struct sdhci_host*) * slots, GFP_KERNEL); | |
1441 | if (!chip) { | |
1442 | ret = -ENOMEM; | |
1443 | goto err; | |
1444 | } | |
1445 | ||
1446 | chip->pdev = pdev; | |
df673b22 PO |
1447 | chip->quirks = ent->driver_data; |
1448 | ||
1449 | if (debug_quirks) | |
1450 | chip->quirks = debug_quirks; | |
d129bceb PO |
1451 | |
1452 | chip->num_slots = slots; | |
1453 | pci_set_drvdata(pdev, chip); | |
1454 | ||
1455 | for (i = 0;i < slots;i++) { | |
1456 | ret = sdhci_probe_slot(pdev, i); | |
1457 | if (ret) { | |
1458 | for (i--;i >= 0;i--) | |
1459 | sdhci_remove_slot(pdev, i); | |
1460 | goto free; | |
1461 | } | |
1462 | } | |
1463 | ||
1464 | return 0; | |
1465 | ||
1466 | free: | |
1467 | pci_set_drvdata(pdev, NULL); | |
1468 | kfree(chip); | |
1469 | ||
1470 | err: | |
1471 | pci_disable_device(pdev); | |
1472 | return ret; | |
1473 | } | |
1474 | ||
1475 | static void __devexit sdhci_remove(struct pci_dev *pdev) | |
1476 | { | |
1477 | int i; | |
1478 | struct sdhci_chip *chip; | |
1479 | ||
1480 | chip = pci_get_drvdata(pdev); | |
1481 | ||
1482 | if (chip) { | |
1483 | for (i = 0;i < chip->num_slots;i++) | |
1484 | sdhci_remove_slot(pdev, i); | |
1485 | ||
1486 | pci_set_drvdata(pdev, NULL); | |
1487 | ||
1488 | kfree(chip); | |
1489 | } | |
1490 | ||
1491 | pci_disable_device(pdev); | |
1492 | } | |
1493 | ||
1494 | static struct pci_driver sdhci_driver = { | |
1495 | .name = DRIVER_NAME, | |
1496 | .id_table = pci_ids, | |
1497 | .probe = sdhci_probe, | |
1498 | .remove = __devexit_p(sdhci_remove), | |
1499 | .suspend = sdhci_suspend, | |
1500 | .resume = sdhci_resume, | |
1501 | }; | |
1502 | ||
1503 | /*****************************************************************************\ | |
1504 | * * | |
1505 | * Driver init/exit * | |
1506 | * * | |
1507 | \*****************************************************************************/ | |
1508 | ||
1509 | static int __init sdhci_drv_init(void) | |
1510 | { | |
1511 | printk(KERN_INFO DRIVER_NAME | |
52fbf9c9 | 1512 | ": Secure Digital Host Controller Interface driver\n"); |
d129bceb PO |
1513 | printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
1514 | ||
1515 | return pci_register_driver(&sdhci_driver); | |
1516 | } | |
1517 | ||
1518 | static void __exit sdhci_drv_exit(void) | |
1519 | { | |
1520 | DBG("Exiting\n"); | |
1521 | ||
1522 | pci_unregister_driver(&sdhci_driver); | |
1523 | } | |
1524 | ||
1525 | module_init(sdhci_drv_init); | |
1526 | module_exit(sdhci_drv_exit); | |
1527 | ||
67435274 PO |
1528 | module_param(debug_nodma, uint, 0444); |
1529 | module_param(debug_forcedma, uint, 0444); | |
df673b22 | 1530 | module_param(debug_quirks, uint, 0444); |
67435274 | 1531 | |
d129bceb PO |
1532 | MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>"); |
1533 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver"); | |
d129bceb | 1534 | MODULE_LICENSE("GPL"); |
67435274 PO |
1535 | |
1536 | MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)"); | |
1537 | MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)"); | |
df673b22 | 1538 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |