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[PATCH] mmc: fix MMIO vs memory races in sdhci
[linux-2.6-block.git] / drivers / mmc / sdhci.c
CommitLineData
d129bceb
PO		 1/*
2 * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
d129bceb
PO		 10 */
11
d129bceb
PO		 12#include <linux/delay.h>
13#include <linux/highmem.h>
14#include <linux/pci.h>
15#include <linux/dma-mapping.h>
16
17#include <linux/mmc/host.h>
18#include <linux/mmc/protocol.h>
19
20#include <asm/scatterlist.h>
21
22#include "sdhci.h"
23
24#define DRIVER_NAME "sdhci"
2c5f3940 25#define DRIVER_VERSION "0.12"
d129bceb
PO		 26
27#define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
28
d129bceb 29#define DBG(f, x...) \
c6563178 30 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 31
67435274
PO		 32static unsigned int debug_nodma = 0;
33static unsigned int debug_forcedma = 0;
df673b22 34static unsigned int debug_quirks = 0;
67435274 35
645289dc 36#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
98608076 37#define SDHCI_QUIRK_FORCE_DMA (1<<1)
645289dc 38
d129bceb 39static const struct pci_device_id pci_ids[] __devinitdata = {
645289dc
PO		 40 {
41 .vendor = PCI_VENDOR_ID_RICOH,
42 .device = PCI_DEVICE_ID_RICOH_R5C822,
43 .subvendor = PCI_VENDOR_ID_IBM,
44 .subdevice = PCI_ANY_ID,
98608076
PO		 45 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
46 SDHCI_QUIRK_FORCE_DMA,
47 },
48
49 {
50 .vendor = PCI_VENDOR_ID_RICOH,
51 .device = PCI_DEVICE_ID_RICOH_R5C822,
52 .subvendor = PCI_ANY_ID,
53 .subdevice = PCI_ANY_ID,
54 .driver_data = SDHCI_QUIRK_FORCE_DMA,
55 },
56
57 {
58 .vendor = PCI_VENDOR_ID_TI,
59 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
60 .subvendor = PCI_ANY_ID,
61 .subdevice = PCI_ANY_ID,
62 .driver_data = SDHCI_QUIRK_FORCE_DMA,
645289dc
PO		 63 },
64
65 { /* Generic SD host controller */
66 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
67 },
68
d129bceb
PO		 69 { /* end: all zeroes */ },
70};
71
72MODULE_DEVICE_TABLE(pci, pci_ids);
73
74static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
75static void sdhci_finish_data(struct sdhci_host *);
76
77static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
78static void sdhci_finish_command(struct sdhci_host *);
79
80static void sdhci_dumpregs(struct sdhci_host *host)
81{
82 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
83
84 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
85 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
86 readw(host->ioaddr + SDHCI_HOST_VERSION));
87 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
88 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
89 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
90 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
91 readl(host->ioaddr + SDHCI_ARGUMENT),
92 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
93 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
94 readl(host->ioaddr + SDHCI_PRESENT_STATE),
95 readb(host->ioaddr + SDHCI_HOST_CONTROL));
96 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
97 readb(host->ioaddr + SDHCI_POWER_CONTROL),
98 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
99 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
100 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
101 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
102 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
103 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
104 readl(host->ioaddr + SDHCI_INT_STATUS));
105 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
106 readl(host->ioaddr + SDHCI_INT_ENABLE),
107 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
108 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
109 readw(host->ioaddr + SDHCI_ACMD12_ERR),
110 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
111 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
112 readl(host->ioaddr + SDHCI_CAPABILITIES),
113 readl(host->ioaddr + SDHCI_MAX_CURRENT));
114
115 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
116}
117
118/*****************************************************************************\
119 * *
120 * Low level functions *
121 * *
122\*****************************************************************************/
123
124static void sdhci_reset(struct sdhci_host *host, u8 mask)
125{
e16514d8
PO		 126 unsigned long timeout;
127
d129bceb
PO		 128 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
129
e16514d8 130 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 131 host->clock = 0;
132
e16514d8
PO		 133 /* Wait max 100 ms */
134 timeout = 100;
135
136 /* hw clears the bit when it's done */
137 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
138 if (timeout == 0) {
139 printk(KERN_ERR "%s: Reset 0x%x never completed. "
140 "Please report this to " BUGMAIL ".\n",
141 mmc_hostname(host->mmc), (int)mask);
142 sdhci_dumpregs(host);
143 return;
144 }
145 timeout--;
146 mdelay(1);
d129bceb
PO		 147 }
148}
149
150static void sdhci_init(struct sdhci_host *host)
151{
152 u32 intmask;
153
154 sdhci_reset(host, SDHCI_RESET_ALL);
155
3192a28f
PO		 156 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
157 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
158 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
159 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 160 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
3192a28f 161 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
d129bceb
PO		 162
163 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
164 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 165}
166
167static void sdhci_activate_led(struct sdhci_host *host)
168{
169 u8 ctrl;
170
171 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
172 ctrl |= SDHCI_CTRL_LED;
173 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
174}
175
176static void sdhci_deactivate_led(struct sdhci_host *host)
177{
178 u8 ctrl;
179
180 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
181 ctrl &= ~SDHCI_CTRL_LED;
182 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
183}
184
185/*****************************************************************************\
186 * *
187 * Core functions *
188 * *
189\*****************************************************************************/
190
191static inline char* sdhci_kmap_sg(struct sdhci_host* host)
192{
193 host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
194 return host->mapped_sg + host->cur_sg->offset;
195}
196
197static inline void sdhci_kunmap_sg(struct sdhci_host* host)
198{
199 kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
200}
201
202static inline int sdhci_next_sg(struct sdhci_host* host)
203{
204 /*
205 * Skip to next SG entry.
206 */
207 host->cur_sg++;
208 host->num_sg--;
209
210 /*
211 * Any entries left?
212 */
213 if (host->num_sg > 0) {
214 host->offset = 0;
215 host->remain = host->cur_sg->length;
216 }
217
218 return host->num_sg;
219}
220
a406f5a3 221static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 222{
a406f5a3
PO		 223 int blksize, chunk_remain;
224 u32 data;
d129bceb 225 char *buffer;
a406f5a3 226 int size;
d129bceb 227
a406f5a3 228 DBG("PIO reading\n");
d129bceb 229
a406f5a3
PO		 230 blksize = host->data->blksz;
231 chunk_remain = 0;
232 data = 0;
d129bceb
PO		 233
234 buffer = sdhci_kmap_sg(host) + host->offset;
235
a406f5a3
PO		 236 while (blksize) {
237 if (chunk_remain == 0) {
238 data = readl(host->ioaddr + SDHCI_BUFFER);
239 chunk_remain = min(blksize, 4);
240 }
d129bceb 241
a406f5a3
PO		 242 size = min(host->size, host->remain);
243 size = min(size, chunk_remain);
d129bceb 244
a406f5a3
PO		 245 chunk_remain -= size;
246 blksize -= size;
247 host->offset += size;
248 host->remain -= size;
249 host->size -= size;
250 while (size) {
251 *buffer = data & 0xFF;
252 buffer++;
253 data >>= 8;
254 size--;
255 }
d129bceb 256
a406f5a3
PO		 257 if (host->remain == 0) {
258 sdhci_kunmap_sg(host);
259 if (sdhci_next_sg(host) == 0) {
260 BUG_ON(blksize != 0);
261 return;
262 }
263 buffer = sdhci_kmap_sg(host);
d129bceb 264 }
a406f5a3 265 }
d129bceb 266
a406f5a3
PO		 267 sdhci_kunmap_sg(host);
268}
d129bceb 269
a406f5a3
PO		 270static void sdhci_write_block_pio(struct sdhci_host *host)
271{
272 int blksize, chunk_remain;
273 u32 data;
274 char *buffer;
275 int bytes, size;
d129bceb 276
a406f5a3
PO		 277 DBG("PIO writing\n");
278
279 blksize = host->data->blksz;
280 chunk_remain = 4;
281 data = 0;
d129bceb 282
a406f5a3
PO		 283 bytes = 0;
284 buffer = sdhci_kmap_sg(host) + host->offset;
d129bceb 285
a406f5a3
PO		 286 while (blksize) {
287 size = min(host->size, host->remain);
288 size = min(size, chunk_remain);
289
290 chunk_remain -= size;
291 blksize -= size;
d129bceb
PO		 292 host->offset += size;
293 host->remain -= size;
d129bceb 294 host->size -= size;
a406f5a3
PO		 295 while (size) {
296 data >>= 8;
297 data |= (u32)*buffer << 24;
298 buffer++;
299 size--;
300 }
301
302 if (chunk_remain == 0) {
303 writel(data, host->ioaddr + SDHCI_BUFFER);
304 chunk_remain = min(blksize, 4);
305 }
d129bceb
PO		 306
307 if (host->remain == 0) {
308 sdhci_kunmap_sg(host);
309 if (sdhci_next_sg(host) == 0) {
a406f5a3 310 BUG_ON(blksize != 0);
d129bceb
PO		 311 return;
312 }
313 buffer = sdhci_kmap_sg(host);
314 }
315 }
316
317 sdhci_kunmap_sg(host);
a406f5a3
PO		 318}
319
320static void sdhci_transfer_pio(struct sdhci_host *host)
321{
322 u32 mask;
323
324 BUG_ON(!host->data);
325
326 if (host->size == 0)
327 return;
328
329 if (host->data->flags & MMC_DATA_READ)
330 mask = SDHCI_DATA_AVAILABLE;
331 else
332 mask = SDHCI_SPACE_AVAILABLE;
333
334 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
335 if (host->data->flags & MMC_DATA_READ)
336 sdhci_read_block_pio(host);
337 else
338 sdhci_write_block_pio(host);
d129bceb 339
a406f5a3
PO		 340 if (host->size == 0)
341 break;
342
343 BUG_ON(host->num_sg == 0);
344 }
d129bceb 345
a406f5a3 346 DBG("PIO transfer complete.\n");
d129bceb
PO		 347}
348
349static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
350{
1c8cde92
PO		 351 u8 count;
352 unsigned target_timeout, current_timeout;
d129bceb
PO		 353
354 WARN_ON(host->data);
355
c7fa9963 356 if (data == NULL)
d129bceb 357 return;
d129bceb
PO		 358
359 DBG("blksz %04x blks %04x flags %08x\n",
a3fd4a1b 360 data->blksz, data->blocks, data->flags);
d129bceb
PO		 361 DBG("tsac %d ms nsac %d clk\n",
362 data->timeout_ns / 1000000, data->timeout_clks);
363
bab76961
PO		 364 /* Sanity checks */
365 BUG_ON(data->blksz * data->blocks > 524288);
1d676e02
PO		 366 BUG_ON(data->blksz > host->max_block);
367 BUG_ON(data->blocks > 65535);
d129bceb 368
1c8cde92
PO		 369 /* timeout in us */
370 target_timeout = data->timeout_ns / 1000 +
371 data->timeout_clks / host->clock;
d129bceb 372
1c8cde92
PO		 373 /*
374 * Figure out needed cycles.
375 * We do this in steps in order to fit inside a 32 bit int.
376 * The first step is the minimum timeout, which will have a
377 * minimum resolution of 6 bits:
378 * (1) 2^13*1000 > 2^22,
379 * (2) host->timeout_clk < 2^16
380 * =>
381 * (1) / (2) > 2^6
382 */
383 count = 0;
384 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
385 while (current_timeout < target_timeout) {
386 count++;
387 current_timeout <<= 1;
388 if (count >= 0xF)
389 break;
390 }
391
392 if (count >= 0xF) {
393 printk(KERN_WARNING "%s: Too large timeout requested!\n",
394 mmc_hostname(host->mmc));
395 count = 0xE;
396 }
397
398 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
d129bceb
PO		 399
400 if (host->flags & SDHCI_USE_DMA) {
401 int count;
402
403 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
404 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
405 BUG_ON(count != 1);
406
407 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
408 } else {
a3fd4a1b 409 host->size = data->blksz * data->blocks;
d129bceb
PO		 410
411 host->cur_sg = data->sg;
412 host->num_sg = data->sg_len;
413
414 host->offset = 0;
415 host->remain = host->cur_sg->length;
416 }
c7fa9963 417
bab76961
PO		 418 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
419 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
420 host->ioaddr + SDHCI_BLOCK_SIZE);
c7fa9963
PO		 421 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
422}
423
424static void sdhci_set_transfer_mode(struct sdhci_host *host,
425 struct mmc_data *data)
426{
427 u16 mode;
428
429 WARN_ON(host->data);
430
431 if (data == NULL)
432 return;
433
434 mode = SDHCI_TRNS_BLK_CNT_EN;
435 if (data->blocks > 1)
436 mode |= SDHCI_TRNS_MULTI;
437 if (data->flags & MMC_DATA_READ)
438 mode |= SDHCI_TRNS_READ;
439 if (host->flags & SDHCI_USE_DMA)
440 mode |= SDHCI_TRNS_DMA;
441
442 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
d129bceb
PO		 443}
444
445static void sdhci_finish_data(struct sdhci_host *host)
446{
447 struct mmc_data *data;
d129bceb
PO		 448 u16 blocks;
449
450 BUG_ON(!host->data);
451
452 data = host->data;
453 host->data = NULL;
454
455 if (host->flags & SDHCI_USE_DMA) {
456 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
457 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
d129bceb
PO		 458 }
459
460 /*
461 * Controller doesn't count down when in single block mode.
462 */
463 if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
464 blocks = 0;
465 else
466 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
a3fd4a1b 467 data->bytes_xfered = data->blksz * (data->blocks - blocks);
d129bceb
PO		 468
469 if ((data->error == MMC_ERR_NONE) && blocks) {
470 printk(KERN_ERR "%s: Controller signalled completion even "
471 "though there were blocks left. Please report this "
472 "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
473 data->error = MMC_ERR_FAILED;
4cca56c5 474 } else if (host->size != 0) {
d129bceb
PO		 475 printk(KERN_ERR "%s: %d bytes were left untransferred. "
476 "Please report this to " BUGMAIL ".\n",
477 mmc_hostname(host->mmc), host->size);
478 data->error = MMC_ERR_FAILED;
479 }
480
481 DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
482
483 if (data->stop) {
484 /*
485 * The controller needs a reset of internal state machines
486 * upon error conditions.
487 */
488 if (data->error != MMC_ERR_NONE) {
489 sdhci_reset(host, SDHCI_RESET_CMD);
490 sdhci_reset(host, SDHCI_RESET_DATA);
491 }
492
493 sdhci_send_command(host, data->stop);
494 } else
495 tasklet_schedule(&host->finish_tasklet);
496}
497
498static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
499{
500 int flags;
fd2208d7 501 u32 mask;
7cb2c76f 502 unsigned long timeout;
d129bceb
PO		 503
504 WARN_ON(host->cmd);
505
506 DBG("Sending cmd (%x)\n", cmd->opcode);
507
508 /* Wait max 10 ms */
7cb2c76f 509 timeout = 10;
fd2208d7
PO		 510
511 mask = SDHCI_CMD_INHIBIT;
512 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
513 mask |= SDHCI_DATA_INHIBIT;
514
515 /* We shouldn't wait for data inihibit for stop commands, even
516 though they might use busy signaling */
517 if (host->mrq->data && (cmd == host->mrq->data->stop))
518 mask &= ~SDHCI_DATA_INHIBIT;
519
520 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 521 if (timeout == 0) {
d129bceb 522 printk(KERN_ERR "%s: Controller never released "
fd2208d7 523 "inhibit bit(s). Please report this to "
d129bceb
PO		 524 BUGMAIL ".\n", mmc_hostname(host->mmc));
525 sdhci_dumpregs(host);
526 cmd->error = MMC_ERR_FAILED;
527 tasklet_schedule(&host->finish_tasklet);
528 return;
529 }
7cb2c76f
PO		 530 timeout--;
531 mdelay(1);
532 }
d129bceb
PO		 533
534 mod_timer(&host->timer, jiffies + 10 * HZ);
535
536 host->cmd = cmd;
537
538 sdhci_prepare_data(host, cmd->data);
539
540 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
541
c7fa9963
PO		 542 sdhci_set_transfer_mode(host, cmd->data);
543
d129bceb
PO		 544 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
545 printk(KERN_ERR "%s: Unsupported response type! "
546 "Please report this to " BUGMAIL ".\n",
547 mmc_hostname(host->mmc));
548 cmd->error = MMC_ERR_INVALID;
549 tasklet_schedule(&host->finish_tasklet);
550 return;
551 }
552
553 if (!(cmd->flags & MMC_RSP_PRESENT))
554 flags = SDHCI_CMD_RESP_NONE;
555 else if (cmd->flags & MMC_RSP_136)
556 flags = SDHCI_CMD_RESP_LONG;
557 else if (cmd->flags & MMC_RSP_BUSY)
558 flags = SDHCI_CMD_RESP_SHORT_BUSY;
559 else
560 flags = SDHCI_CMD_RESP_SHORT;
561
562 if (cmd->flags & MMC_RSP_CRC)
563 flags |= SDHCI_CMD_CRC;
564 if (cmd->flags & MMC_RSP_OPCODE)
565 flags |= SDHCI_CMD_INDEX;
566 if (cmd->data)
567 flags |= SDHCI_CMD_DATA;
568
fb61e289 569 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
d129bceb
PO		 570 host->ioaddr + SDHCI_COMMAND);
571}
572
573static void sdhci_finish_command(struct sdhci_host *host)
574{
575 int i;
576
577 BUG_ON(host->cmd == NULL);
578
579 if (host->cmd->flags & MMC_RSP_PRESENT) {
580 if (host->cmd->flags & MMC_RSP_136) {
581 /* CRC is stripped so we need to do some shifting. */
582 for (i = 0;i < 4;i++) {
583 host->cmd->resp[i] = readl(host->ioaddr +
584 SDHCI_RESPONSE + (3-i)*4) << 8;
585 if (i != 3)
586 host->cmd->resp[i] |=
587 readb(host->ioaddr +
588 SDHCI_RESPONSE + (3-i)*4-1);
589 }
590 } else {
591 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
592 }
593 }
594
595 host->cmd->error = MMC_ERR_NONE;
596
597 DBG("Ending cmd (%x)\n", host->cmd->opcode);
598
3192a28f 599 if (host->cmd->data)
d129bceb 600 host->data = host->cmd->data;
3192a28f 601 else
d129bceb
PO		 602 tasklet_schedule(&host->finish_tasklet);
603
604 host->cmd = NULL;
605}
606
607static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
608{
609 int div;
610 u16 clk;
7cb2c76f 611 unsigned long timeout;
d129bceb
PO		 612
613 if (clock == host->clock)
614 return;
615
616 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
617
618 if (clock == 0)
619 goto out;
620
621 for (div = 1;div < 256;div *= 2) {
622 if ((host->max_clk / div) <= clock)
623 break;
624 }
625 div >>= 1;
626
627 clk = div << SDHCI_DIVIDER_SHIFT;
628 clk |= SDHCI_CLOCK_INT_EN;
629 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
630
631 /* Wait max 10 ms */
7cb2c76f
PO		 632 timeout = 10;
633 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
634 & SDHCI_CLOCK_INT_STABLE)) {
635 if (timeout == 0) {
d129bceb
PO		 636 printk(KERN_ERR "%s: Internal clock never stabilised. "
637 "Please report this to " BUGMAIL ".\n",
638 mmc_hostname(host->mmc));
639 sdhci_dumpregs(host);
640 return;
641 }
7cb2c76f
PO		 642 timeout--;
643 mdelay(1);
644 }
d129bceb
PO		 645
646 clk |= SDHCI_CLOCK_CARD_EN;
647 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
648
649out:
650 host->clock = clock;
651}
652
146ad66e
PO		 653static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
654{
655 u8 pwr;
656
657 if (host->power == power)
658 return;
659
660 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
661
662 if (power == (unsigned short)-1)
663 goto out;
664
665 pwr = SDHCI_POWER_ON;
666
667 switch (power) {
668 case MMC_VDD_170:
669 case MMC_VDD_180:
670 case MMC_VDD_190:
671 pwr |= SDHCI_POWER_180;
672 break;
673 case MMC_VDD_290:
674 case MMC_VDD_300:
675 case MMC_VDD_310:
676 pwr |= SDHCI_POWER_300;
677 break;
678 case MMC_VDD_320:
679 case MMC_VDD_330:
680 case MMC_VDD_340:
681 pwr |= SDHCI_POWER_330;
682 break;
683 default:
684 BUG();
685 }
686
687 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
688
689out:
690 host->power = power;
691}
692
d129bceb
PO		 693/*****************************************************************************\
694 * *
695 * MMC callbacks *
696 * *
697\*****************************************************************************/
698
699static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
700{
701 struct sdhci_host *host;
702 unsigned long flags;
703
704 host = mmc_priv(mmc);
705
706 spin_lock_irqsave(&host->lock, flags);
707
708 WARN_ON(host->mrq != NULL);
709
710 sdhci_activate_led(host);
711
712 host->mrq = mrq;
713
714 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
715 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
716 tasklet_schedule(&host->finish_tasklet);
717 } else
718 sdhci_send_command(host, mrq->cmd);
719
5f25a66f 720 mmiowb();
d129bceb
PO		 721 spin_unlock_irqrestore(&host->lock, flags);
722}
723
724static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
725{
726 struct sdhci_host *host;
727 unsigned long flags;
728 u8 ctrl;
729
730 host = mmc_priv(mmc);
731
732 spin_lock_irqsave(&host->lock, flags);
733
d129bceb
PO		 734 /*
735 * Reset the chip on each power off.
736 * Should clear out any weird states.
737 */
738 if (ios->power_mode == MMC_POWER_OFF) {
739 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb 740 sdhci_init(host);
d129bceb
PO		 741 }
742
743 sdhci_set_clock(host, ios->clock);
744
745 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 746 sdhci_set_power(host, -1);
d129bceb 747 else
146ad66e 748 sdhci_set_power(host, ios->vdd);
d129bceb
PO		 749
750 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
751 if (ios->bus_width == MMC_BUS_WIDTH_4)
752 ctrl |= SDHCI_CTRL_4BITBUS;
753 else
754 ctrl &= ~SDHCI_CTRL_4BITBUS;
755 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
756
5f25a66f 757 mmiowb();
d129bceb
PO		 758 spin_unlock_irqrestore(&host->lock, flags);
759}
760
761static int sdhci_get_ro(struct mmc_host *mmc)
762{
763 struct sdhci_host *host;
764 unsigned long flags;
765 int present;
766
767 host = mmc_priv(mmc);
768
769 spin_lock_irqsave(&host->lock, flags);
770
771 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
772
773 spin_unlock_irqrestore(&host->lock, flags);
774
775 return !(present & SDHCI_WRITE_PROTECT);
776}
777
778static struct mmc_host_ops sdhci_ops = {
779 .request = sdhci_request,
780 .set_ios = sdhci_set_ios,
781 .get_ro = sdhci_get_ro,
782};
783
784/*****************************************************************************\
785 * *
786 * Tasklets *
787 * *
788\*****************************************************************************/
789
790static void sdhci_tasklet_card(unsigned long param)
791{
792 struct sdhci_host *host;
793 unsigned long flags;
794
795 host = (struct sdhci_host*)param;
796
797 spin_lock_irqsave(&host->lock, flags);
798
799 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
800 if (host->mrq) {
801 printk(KERN_ERR "%s: Card removed during transfer!\n",
802 mmc_hostname(host->mmc));
803 printk(KERN_ERR "%s: Resetting controller.\n",
804 mmc_hostname(host->mmc));
805
806 sdhci_reset(host, SDHCI_RESET_CMD);
807 sdhci_reset(host, SDHCI_RESET_DATA);
808
809 host->mrq->cmd->error = MMC_ERR_FAILED;
810 tasklet_schedule(&host->finish_tasklet);
811 }
812 }
813
814 spin_unlock_irqrestore(&host->lock, flags);
815
816 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
817}
818
819static void sdhci_tasklet_finish(unsigned long param)
820{
821 struct sdhci_host *host;
822 unsigned long flags;
823 struct mmc_request *mrq;
824
825 host = (struct sdhci_host*)param;
826
827 spin_lock_irqsave(&host->lock, flags);
828
829 del_timer(&host->timer);
830
831 mrq = host->mrq;
832
833 DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
834
835 /*
836 * The controller needs a reset of internal state machines
837 * upon error conditions.
838 */
839 if ((mrq->cmd->error != MMC_ERR_NONE) ||
840 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
841 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
645289dc
PO		 842
843 /* Some controllers need this kick or reset won't work here */
844 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
845 unsigned int clock;
846
847 /* This is to force an update */
848 clock = host->clock;
849 host->clock = 0;
850 sdhci_set_clock(host, clock);
851 }
852
853 /* Spec says we should do both at the same time, but Ricoh
854 controllers do not like that. */
d129bceb
PO		 855 sdhci_reset(host, SDHCI_RESET_CMD);
856 sdhci_reset(host, SDHCI_RESET_DATA);
857 }
858
859 host->mrq = NULL;
860 host->cmd = NULL;
861 host->data = NULL;
862
863 sdhci_deactivate_led(host);
864
5f25a66f 865 mmiowb();
d129bceb
PO		 866 spin_unlock_irqrestore(&host->lock, flags);
867
868 mmc_request_done(host->mmc, mrq);
869}
870
871static void sdhci_timeout_timer(unsigned long data)
872{
873 struct sdhci_host *host;
874 unsigned long flags;
875
876 host = (struct sdhci_host*)data;
877
878 spin_lock_irqsave(&host->lock, flags);
879
880 if (host->mrq) {
881 printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
882 "Please report this to " BUGMAIL ".\n",
883 mmc_hostname(host->mmc));
884 sdhci_dumpregs(host);
885
886 if (host->data) {
887 host->data->error = MMC_ERR_TIMEOUT;
888 sdhci_finish_data(host);
889 } else {
890 if (host->cmd)
891 host->cmd->error = MMC_ERR_TIMEOUT;
892 else
893 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
894
895 tasklet_schedule(&host->finish_tasklet);
896 }
897 }
898
5f25a66f 899 mmiowb();
d129bceb
PO		 900 spin_unlock_irqrestore(&host->lock, flags);
901}
902
903/*****************************************************************************\
904 * *
905 * Interrupt handling *
906 * *
907\*****************************************************************************/
908
909static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
910{
911 BUG_ON(intmask == 0);
912
913 if (!host->cmd) {
914 printk(KERN_ERR "%s: Got command interrupt even though no "
915 "command operation was in progress.\n",
916 mmc_hostname(host->mmc));
917 printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
918 mmc_hostname(host->mmc));
919 sdhci_dumpregs(host);
920 return;
921 }
922
923 if (intmask & SDHCI_INT_RESPONSE)
924 sdhci_finish_command(host);
925 else {
926 if (intmask & SDHCI_INT_TIMEOUT)
927 host->cmd->error = MMC_ERR_TIMEOUT;
928 else if (intmask & SDHCI_INT_CRC)
929 host->cmd->error = MMC_ERR_BADCRC;
930 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
931 host->cmd->error = MMC_ERR_FAILED;
932 else
933 host->cmd->error = MMC_ERR_INVALID;
934
935 tasklet_schedule(&host->finish_tasklet);
936 }
937}
938
939static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
940{
941 BUG_ON(intmask == 0);
942
943 if (!host->data) {
944 /*
945 * A data end interrupt is sent together with the response
946 * for the stop command.
947 */
948 if (intmask & SDHCI_INT_DATA_END)
949 return;
950
951 printk(KERN_ERR "%s: Got data interrupt even though no "
952 "data operation was in progress.\n",
953 mmc_hostname(host->mmc));
954 printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
955 mmc_hostname(host->mmc));
956 sdhci_dumpregs(host);
957
958 return;
959 }
960
961 if (intmask & SDHCI_INT_DATA_TIMEOUT)
962 host->data->error = MMC_ERR_TIMEOUT;
963 else if (intmask & SDHCI_INT_DATA_CRC)
964 host->data->error = MMC_ERR_BADCRC;
965 else if (intmask & SDHCI_INT_DATA_END_BIT)
966 host->data->error = MMC_ERR_FAILED;
967
968 if (host->data->error != MMC_ERR_NONE)
969 sdhci_finish_data(host);
970 else {
a406f5a3 971 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 972 sdhci_transfer_pio(host);
973
974 if (intmask & SDHCI_INT_DATA_END)
975 sdhci_finish_data(host);
976 }
977}
978
979static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
980{
981 irqreturn_t result;
982 struct sdhci_host* host = dev_id;
983 u32 intmask;
984
985 spin_lock(&host->lock);
986
987 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
988
989 if (!intmask) {
990 result = IRQ_NONE;
991 goto out;
992 }
993
994 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
995
3192a28f
PO		 996 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
997 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
998 host->ioaddr + SDHCI_INT_STATUS);
d129bceb 999 tasklet_schedule(&host->card_tasklet);
3192a28f 1000 }
d129bceb 1001
3192a28f 1002 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1003
3192a28f 1004 if (intmask & SDHCI_INT_CMD_MASK) {
d129bceb
PO		 1005 writel(intmask & SDHCI_INT_CMD_MASK,
1006 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1007 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1008 }
1009
1010 if (intmask & SDHCI_INT_DATA_MASK) {
d129bceb
PO		 1011 writel(intmask & SDHCI_INT_DATA_MASK,
1012 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1013 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1014 }
1015
1016 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1017
d129bceb 1018 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1019 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1020 mmc_hostname(host->mmc));
3192a28f 1021 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
d129bceb
PO		 1022 }
1023
3192a28f
PO		 1024 intmask &= SDHCI_INT_BUS_POWER;
1025
1026 if (intmask) {
1027 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
d129bceb 1028 "report this to " BUGMAIL ".\n",
3192a28f 1029 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1030 sdhci_dumpregs(host);
1031
d129bceb 1032 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1033 }
d129bceb
PO		 1034
1035 result = IRQ_HANDLED;
1036
5f25a66f 1037 mmiowb();
d129bceb
PO		 1038out:
1039 spin_unlock(&host->lock);
1040
1041 return result;
1042}
1043
1044/*****************************************************************************\
1045 * *
1046 * Suspend/resume *
1047 * *
1048\*****************************************************************************/
1049
1050#ifdef CONFIG_PM
1051
1052static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1053{
1054 struct sdhci_chip *chip;
1055 int i, ret;
1056
1057 chip = pci_get_drvdata(pdev);
1058 if (!chip)
1059 return 0;
1060
1061 DBG("Suspending...\n");
1062
1063 for (i = 0;i < chip->num_slots;i++) {
1064 if (!chip->hosts[i])
1065 continue;
1066 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1067 if (ret) {
1068 for (i--;i >= 0;i--)
1069 mmc_resume_host(chip->hosts[i]->mmc);
1070 return ret;
1071 }
1072 }
1073
1074 pci_save_state(pdev);
1075 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1076 pci_disable_device(pdev);
1077 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1078
1079 return 0;
1080}
1081
1082static int sdhci_resume (struct pci_dev *pdev)
1083{
1084 struct sdhci_chip *chip;
1085 int i, ret;
1086
1087 chip = pci_get_drvdata(pdev);
1088 if (!chip)
1089 return 0;
1090
1091 DBG("Resuming...\n");
1092
1093 pci_set_power_state(pdev, PCI_D0);
1094 pci_restore_state(pdev);
1095 pci_enable_device(pdev);
1096
1097 for (i = 0;i < chip->num_slots;i++) {
1098 if (!chip->hosts[i])
1099 continue;
1100 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1101 pci_set_master(pdev);
1102 sdhci_init(chip->hosts[i]);
5f25a66f 1103 mmiowb();
d129bceb
PO		 1104 ret = mmc_resume_host(chip->hosts[i]->mmc);
1105 if (ret)
1106 return ret;
1107 }
1108
1109 return 0;
1110}
1111
1112#else /* CONFIG_PM */
1113
1114#define sdhci_suspend NULL
1115#define sdhci_resume NULL
1116
1117#endif /* CONFIG_PM */
1118
1119/*****************************************************************************\
1120 * *
1121 * Device probing/removal *
1122 * *
1123\*****************************************************************************/
1124
1125static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1126{
1127 int ret;
4a965505 1128 unsigned int version;
d129bceb
PO		 1129 struct sdhci_chip *chip;
1130 struct mmc_host *mmc;
1131 struct sdhci_host *host;
1132
1133 u8 first_bar;
1134 unsigned int caps;
1135
1136 chip = pci_get_drvdata(pdev);
1137 BUG_ON(!chip);
1138
1139 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1140 if (ret)
1141 return ret;
1142
1143 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1144
1145 if (first_bar > 5) {
1146 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1147 return -ENODEV;
1148 }
1149
1150 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1151 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1152 return -ENODEV;
1153 }
1154
1155 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1156 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
1157 return -ENODEV;
1158 }
1159
67435274
PO		 1160 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1161 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1162 return -ENODEV;
1163 }
1164
1165 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1166 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1167 return -ENODEV;
1168 }
1169
d129bceb
PO		 1170 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1171 if (!mmc)
1172 return -ENOMEM;
1173
1174 host = mmc_priv(mmc);
1175 host->mmc = mmc;
1176
1177 host->bar = first_bar + slot;
1178
1179 host->addr = pci_resource_start(pdev, host->bar);
1180 host->irq = pdev->irq;
1181
1182 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1183
1184 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1185
1186 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1187 if (ret)
1188 goto free;
1189
1190 host->ioaddr = ioremap_nocache(host->addr,
1191 pci_resource_len(pdev, host->bar));
1192 if (!host->ioaddr) {
1193 ret = -ENOMEM;
1194 goto release;
1195 }
1196
d96649ed
PO		 1197 sdhci_reset(host, SDHCI_RESET_ALL);
1198
4a965505
PO		 1199 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1200 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1201 if (version != 0) {
1202 printk(KERN_ERR "%s: Unknown controller version (%d). "
8b1b2185 1203 "You may experience problems.\n", host->slot_descr,
4a965505 1204 version);
4a965505
PO		 1205 }
1206
d129bceb
PO		 1207 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1208
67435274
PO		 1209 if (debug_nodma)
1210 DBG("DMA forced off\n");
1211 else if (debug_forcedma) {
1212 DBG("DMA forced on\n");
1213 host->flags |= SDHCI_USE_DMA;
98608076
PO		 1214 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1215 host->flags |= SDHCI_USE_DMA;
1216 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
67435274
PO		 1217 DBG("Controller doesn't have DMA interface\n");
1218 else if (!(caps & SDHCI_CAN_DO_DMA))
1219 DBG("Controller doesn't have DMA capability\n");
1220 else
d129bceb
PO		 1221 host->flags |= SDHCI_USE_DMA;
1222
1223 if (host->flags & SDHCI_USE_DMA) {
1224 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1225 printk(KERN_WARNING "%s: No suitable DMA available. "
1226 "Falling back to PIO.\n", host->slot_descr);
1227 host->flags &= ~SDHCI_USE_DMA;
1228 }
1229 }
1230
1231 if (host->flags & SDHCI_USE_DMA)
1232 pci_set_master(pdev);
1233 else /* XXX: Hack to get MMC layer to avoid highmem */
1234 pdev->dma_mask = 0;
1235
8ef1a143
PO		 1236 host->max_clk =
1237 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1238 if (host->max_clk == 0) {
1239 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1240 "frequency.\n", host->slot_descr);
1241 ret = -ENODEV;
1242 goto unmap;
1243 }
d129bceb
PO		 1244 host->max_clk *= 1000000;
1245
1c8cde92
PO		 1246 host->timeout_clk =
1247 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1248 if (host->timeout_clk == 0) {
1249 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1250 "frequency.\n", host->slot_descr);
1251 ret = -ENODEV;
1252 goto unmap;
1253 }
1254 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1255 host->timeout_clk *= 1000;
d129bceb 1256
1d676e02
PO		 1257 host->max_block = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1258 if (host->max_block >= 3) {
1259 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1260 host->slot_descr);
1261 ret = -ENODEV;
1262 goto unmap;
1263 }
1264 host->max_block = 512 << host->max_block;
1265
d129bceb
PO		 1266 /*
1267 * Set host parameters.
1268 */
1269 mmc->ops = &sdhci_ops;
1270 mmc->f_min = host->max_clk / 256;
1271 mmc->f_max = host->max_clk;
42431acb 1272 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
d129bceb 1273
146ad66e
PO		 1274 mmc->ocr_avail = 0;
1275 if (caps & SDHCI_CAN_VDD_330)
1276 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1277 else if (caps & SDHCI_CAN_VDD_300)
1278 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1279 else if (caps & SDHCI_CAN_VDD_180)
1280 mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
1281
1282 if (mmc->ocr_avail == 0) {
1283 printk(KERN_ERR "%s: Hardware doesn't report any "
1284 "support voltages.\n", host->slot_descr);
1285 ret = -ENODEV;
1286 goto unmap;
1287 }
1288
d129bceb
PO		 1289 spin_lock_init(&host->lock);
1290
1291 /*
1292 * Maximum number of segments. Hardware cannot do scatter lists.
1293 */
1294 if (host->flags & SDHCI_USE_DMA)
1295 mmc->max_hw_segs = 1;
1296 else
1297 mmc->max_hw_segs = 16;
1298 mmc->max_phys_segs = 16;
1299
1300 /*
bab76961
PO		 1301 * Maximum number of sectors in one transfer. Limited by DMA boundary
1302 * size (512KiB), which means (512 KiB/512=) 1024 entries.
d129bceb 1303 */
bab76961 1304 mmc->max_sectors = 1024;
d129bceb
PO		 1305
1306 /*
1307 * Maximum segment size. Could be one segment with the maximum number
1308 * of sectors.
1309 */
1310 mmc->max_seg_size = mmc->max_sectors * 512;
1311
1312 /*
1313 * Init tasklets.
1314 */
1315 tasklet_init(&host->card_tasklet,
1316 sdhci_tasklet_card, (unsigned long)host);
1317 tasklet_init(&host->finish_tasklet,
1318 sdhci_tasklet_finish, (unsigned long)host);
1319
e474c66b 1320 setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
d129bceb 1321
dace1453 1322 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
d129bceb
PO		 1323 host->slot_descr, host);
1324 if (ret)
8ef1a143 1325 goto untasklet;
d129bceb
PO		 1326
1327 sdhci_init(host);
1328
1329#ifdef CONFIG_MMC_DEBUG
1330 sdhci_dumpregs(host);
1331#endif
1332
1333 host->chip = chip;
1334 chip->hosts[slot] = host;
1335
5f25a66f
PO		 1336 mmiowb();
1337
d129bceb
PO		 1338 mmc_add_host(mmc);
1339
1340 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1341 host->addr, host->irq,
1342 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1343
1344 return 0;
1345
8ef1a143 1346untasklet:
d129bceb
PO		 1347 tasklet_kill(&host->card_tasklet);
1348 tasklet_kill(&host->finish_tasklet);
8ef1a143 1349unmap:
d129bceb
PO		 1350 iounmap(host->ioaddr);
1351release:
1352 pci_release_region(pdev, host->bar);
1353free:
1354 mmc_free_host(mmc);
1355
1356 return ret;
1357}
1358
1359static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1360{
1361 struct sdhci_chip *chip;
1362 struct mmc_host *mmc;
1363 struct sdhci_host *host;
1364
1365 chip = pci_get_drvdata(pdev);
1366 host = chip->hosts[slot];
1367 mmc = host->mmc;
1368
1369 chip->hosts[slot] = NULL;
1370
1371 mmc_remove_host(mmc);
1372
1373 sdhci_reset(host, SDHCI_RESET_ALL);
1374
1375 free_irq(host->irq, host);
1376
1377 del_timer_sync(&host->timer);
1378
1379 tasklet_kill(&host->card_tasklet);
1380 tasklet_kill(&host->finish_tasklet);
1381
1382 iounmap(host->ioaddr);
1383
1384 pci_release_region(pdev, host->bar);
1385
1386 mmc_free_host(mmc);
1387}
1388
1389static int __devinit sdhci_probe(struct pci_dev *pdev,
1390 const struct pci_device_id *ent)
1391{
1392 int ret, i;
51f82bc0 1393 u8 slots, rev;
d129bceb
PO		 1394 struct sdhci_chip *chip;
1395
1396 BUG_ON(pdev == NULL);
1397 BUG_ON(ent == NULL);
1398
51f82bc0
PO		 1399 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1400
1401 printk(KERN_INFO DRIVER_NAME
1402 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1403 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1404 (int)rev);
d129bceb
PO		 1405
1406 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1407 if (ret)
1408 return ret;
1409
1410 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1411 DBG("found %d slot(s)\n", slots);
1412 if (slots == 0)
1413 return -ENODEV;
1414
1415 ret = pci_enable_device(pdev);
1416 if (ret)
1417 return ret;
1418
1419 chip = kzalloc(sizeof(struct sdhci_chip) +
1420 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1421 if (!chip) {
1422 ret = -ENOMEM;
1423 goto err;
1424 }
1425
1426 chip->pdev = pdev;
df673b22
PO		 1427 chip->quirks = ent->driver_data;
1428
1429 if (debug_quirks)
1430 chip->quirks = debug_quirks;
d129bceb
PO		 1431
1432 chip->num_slots = slots;
1433 pci_set_drvdata(pdev, chip);
1434
1435 for (i = 0;i < slots;i++) {
1436 ret = sdhci_probe_slot(pdev, i);
1437 if (ret) {
1438 for (i--;i >= 0;i--)
1439 sdhci_remove_slot(pdev, i);
1440 goto free;
1441 }
1442 }
1443
1444 return 0;
1445
1446free:
1447 pci_set_drvdata(pdev, NULL);
1448 kfree(chip);
1449
1450err:
1451 pci_disable_device(pdev);
1452 return ret;
1453}
1454
1455static void __devexit sdhci_remove(struct pci_dev *pdev)
1456{
1457 int i;
1458 struct sdhci_chip *chip;
1459
1460 chip = pci_get_drvdata(pdev);
1461
1462 if (chip) {
1463 for (i = 0;i < chip->num_slots;i++)
1464 sdhci_remove_slot(pdev, i);
1465
1466 pci_set_drvdata(pdev, NULL);
1467
1468 kfree(chip);
1469 }
1470
1471 pci_disable_device(pdev);
1472}
1473
1474static struct pci_driver sdhci_driver = {
1475 .name = DRIVER_NAME,
1476 .id_table = pci_ids,
1477 .probe = sdhci_probe,
1478 .remove = __devexit_p(sdhci_remove),
1479 .suspend = sdhci_suspend,
1480 .resume = sdhci_resume,
1481};
1482
1483/*****************************************************************************\
1484 * *
1485 * Driver init/exit *
1486 * *
1487\*****************************************************************************/
1488
1489static int __init sdhci_drv_init(void)
1490{
1491 printk(KERN_INFO DRIVER_NAME
1492 ": Secure Digital Host Controller Interface driver, "
1493 DRIVER_VERSION "\n");
1494 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1495
1496 return pci_register_driver(&sdhci_driver);
1497}
1498
1499static void __exit sdhci_drv_exit(void)
1500{
1501 DBG("Exiting\n");
1502
1503 pci_unregister_driver(&sdhci_driver);
1504}
1505
1506module_init(sdhci_drv_init);
1507module_exit(sdhci_drv_exit);
1508
67435274
PO		 1509module_param(debug_nodma, uint, 0444);
1510module_param(debug_forcedma, uint, 0444);
df673b22 1511module_param(debug_quirks, uint, 0444);
67435274 1512
d129bceb
PO		 1513MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1514MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1515MODULE_VERSION(DRIVER_VERSION);
1516MODULE_LICENSE("GPL");
67435274
PO		 1517
1518MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1519MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
df673b22 1520MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux 6.x block layer and io_uring tree(s)