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mmc: sdhci: Remove driver version
[linux-2.6-block.git] / drivers / mmc / sdhci.c
CommitLineData
d129bceb
PO		 1/*
2 * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
d129bceb
PO		 10 */
11
d129bceb
PO		 12#include <linux/delay.h>
13#include <linux/highmem.h>
14#include <linux/pci.h>
15#include <linux/dma-mapping.h>
16
17#include <linux/mmc/host.h>
18#include <linux/mmc/protocol.h>
19
20#include <asm/scatterlist.h>
21
22#include "sdhci.h"
23
24#define DRIVER_NAME "sdhci"
d129bceb
PO		 25
26#define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
27
d129bceb 28#define DBG(f, x...) \
c6563178 29 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 30
67435274
PO		 31static unsigned int debug_nodma = 0;
32static unsigned int debug_forcedma = 0;
df673b22 33static unsigned int debug_quirks = 0;
67435274 34
645289dc 35#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
98608076 36#define SDHCI_QUIRK_FORCE_DMA (1<<1)
8a4da143
PO		 37/* Controller doesn't like some resets when there is no card inserted. */
38#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
9e9dc5f2 39#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
645289dc 40
d129bceb 41static const struct pci_device_id pci_ids[] __devinitdata = {
645289dc
PO		 42 {
43 .vendor = PCI_VENDOR_ID_RICOH,
44 .device = PCI_DEVICE_ID_RICOH_R5C822,
45 .subvendor = PCI_VENDOR_ID_IBM,
46 .subdevice = PCI_ANY_ID,
98608076
PO		 47 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
48 SDHCI_QUIRK_FORCE_DMA,
49 },
50
51 {
52 .vendor = PCI_VENDOR_ID_RICOH,
53 .device = PCI_DEVICE_ID_RICOH_R5C822,
54 .subvendor = PCI_ANY_ID,
55 .subdevice = PCI_ANY_ID,
8a4da143
PO		 56 .driver_data = SDHCI_QUIRK_FORCE_DMA |
57 SDHCI_QUIRK_NO_CARD_NO_RESET,
98608076
PO		 58 },
59
60 {
61 .vendor = PCI_VENDOR_ID_TI,
62 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
63 .subvendor = PCI_ANY_ID,
64 .subdevice = PCI_ANY_ID,
65 .driver_data = SDHCI_QUIRK_FORCE_DMA,
645289dc
PO		 66 },
67
9e9dc5f2
DS		 68 {
69 .vendor = PCI_VENDOR_ID_ENE,
70 .device = PCI_DEVICE_ID_ENE_CB712_SD,
71 .subvendor = PCI_ANY_ID,
72 .subdevice = PCI_ANY_ID,
73 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE,
74 },
75
645289dc
PO		 76 { /* Generic SD host controller */
77 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
78 },
79
d129bceb
PO		 80 { /* end: all zeroes */ },
81};
82
83MODULE_DEVICE_TABLE(pci, pci_ids);
84
85static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
86static void sdhci_finish_data(struct sdhci_host *);
87
88static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
89static void sdhci_finish_command(struct sdhci_host *);
90
91static void sdhci_dumpregs(struct sdhci_host *host)
92{
93 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
94
95 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
96 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
97 readw(host->ioaddr + SDHCI_HOST_VERSION));
98 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
99 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
100 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
101 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
102 readl(host->ioaddr + SDHCI_ARGUMENT),
103 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
104 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
105 readl(host->ioaddr + SDHCI_PRESENT_STATE),
106 readb(host->ioaddr + SDHCI_HOST_CONTROL));
107 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
108 readb(host->ioaddr + SDHCI_POWER_CONTROL),
109 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
110 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
111 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
112 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
113 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
114 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
115 readl(host->ioaddr + SDHCI_INT_STATUS));
116 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
117 readl(host->ioaddr + SDHCI_INT_ENABLE),
118 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
119 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
120 readw(host->ioaddr + SDHCI_ACMD12_ERR),
121 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
122 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
123 readl(host->ioaddr + SDHCI_CAPABILITIES),
124 readl(host->ioaddr + SDHCI_MAX_CURRENT));
125
126 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
127}
128
129/*****************************************************************************\
130 * *
131 * Low level functions *
132 * *
133\*****************************************************************************/
134
135static void sdhci_reset(struct sdhci_host *host, u8 mask)
136{
e16514d8
PO		 137 unsigned long timeout;
138
8a4da143
PO		 139 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
140 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
141 SDHCI_CARD_PRESENT))
142 return;
143 }
144
d129bceb
PO		 145 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
146
e16514d8 147 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 148 host->clock = 0;
149
e16514d8
PO		 150 /* Wait max 100 ms */
151 timeout = 100;
152
153 /* hw clears the bit when it's done */
154 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
155 if (timeout == 0) {
156 printk(KERN_ERR "%s: Reset 0x%x never completed. "
157 "Please report this to " BUGMAIL ".\n",
158 mmc_hostname(host->mmc), (int)mask);
159 sdhci_dumpregs(host);
160 return;
161 }
162 timeout--;
163 mdelay(1);
d129bceb
PO		 164 }
165}
166
167static void sdhci_init(struct sdhci_host *host)
168{
169 u32 intmask;
170
171 sdhci_reset(host, SDHCI_RESET_ALL);
172
3192a28f
PO		 173 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
174 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
175 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
176 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 177 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
3192a28f 178 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
d129bceb
PO		 179
180 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
181 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 182}
183
184static void sdhci_activate_led(struct sdhci_host *host)
185{
186 u8 ctrl;
187
188 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
189 ctrl |= SDHCI_CTRL_LED;
190 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
191}
192
193static void sdhci_deactivate_led(struct sdhci_host *host)
194{
195 u8 ctrl;
196
197 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
198 ctrl &= ~SDHCI_CTRL_LED;
199 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
200}
201
202/*****************************************************************************\
203 * *
204 * Core functions *
205 * *
206\*****************************************************************************/
207
2a22b14e 208static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
d129bceb 209{
2a22b14e 210 return page_address(host->cur_sg->page) + host->cur_sg->offset;
d129bceb
PO		 211}
212
213static inline int sdhci_next_sg(struct sdhci_host* host)
214{
215 /*
216 * Skip to next SG entry.
217 */
218 host->cur_sg++;
219 host->num_sg--;
220
221 /*
222 * Any entries left?
223 */
224 if (host->num_sg > 0) {
225 host->offset = 0;
226 host->remain = host->cur_sg->length;
227 }
228
229 return host->num_sg;
230}
231
a406f5a3 232static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 233{
a406f5a3
PO		 234 int blksize, chunk_remain;
235 u32 data;
d129bceb 236 char *buffer;
a406f5a3 237 int size;
d129bceb 238
a406f5a3 239 DBG("PIO reading\n");
d129bceb 240
a406f5a3
PO		 241 blksize = host->data->blksz;
242 chunk_remain = 0;
243 data = 0;
d129bceb 244
2a22b14e 245 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 246
a406f5a3
PO		 247 while (blksize) {
248 if (chunk_remain == 0) {
249 data = readl(host->ioaddr + SDHCI_BUFFER);
250 chunk_remain = min(blksize, 4);
251 }
d129bceb 252
a406f5a3
PO		 253 size = min(host->size, host->remain);
254 size = min(size, chunk_remain);
d129bceb 255
a406f5a3
PO		 256 chunk_remain -= size;
257 blksize -= size;
258 host->offset += size;
259 host->remain -= size;
260 host->size -= size;
261 while (size) {
262 *buffer = data & 0xFF;
263 buffer++;
264 data >>= 8;
265 size--;
266 }
d129bceb 267
a406f5a3 268 if (host->remain == 0) {
a406f5a3
PO		 269 if (sdhci_next_sg(host) == 0) {
270 BUG_ON(blksize != 0);
271 return;
272 }
2a22b14e 273 buffer = sdhci_sg_to_buffer(host);
d129bceb 274 }
a406f5a3 275 }
a406f5a3 276}
d129bceb 277
a406f5a3
PO		 278static void sdhci_write_block_pio(struct sdhci_host *host)
279{
280 int blksize, chunk_remain;
281 u32 data;
282 char *buffer;
283 int bytes, size;
d129bceb 284
a406f5a3
PO		 285 DBG("PIO writing\n");
286
287 blksize = host->data->blksz;
288 chunk_remain = 4;
289 data = 0;
d129bceb 290
a406f5a3 291 bytes = 0;
2a22b14e 292 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 293
a406f5a3
PO		 294 while (blksize) {
295 size = min(host->size, host->remain);
296 size = min(size, chunk_remain);
297
298 chunk_remain -= size;
299 blksize -= size;
d129bceb
PO		 300 host->offset += size;
301 host->remain -= size;
d129bceb 302 host->size -= size;
a406f5a3
PO		 303 while (size) {
304 data >>= 8;
305 data |= (u32)*buffer << 24;
306 buffer++;
307 size--;
308 }
309
310 if (chunk_remain == 0) {
311 writel(data, host->ioaddr + SDHCI_BUFFER);
312 chunk_remain = min(blksize, 4);
313 }
d129bceb
PO		 314
315 if (host->remain == 0) {
d129bceb 316 if (sdhci_next_sg(host) == 0) {
a406f5a3 317 BUG_ON(blksize != 0);
d129bceb
PO		 318 return;
319 }
2a22b14e 320 buffer = sdhci_sg_to_buffer(host);
d129bceb
PO		 321 }
322 }
a406f5a3
PO		 323}
324
325static void sdhci_transfer_pio(struct sdhci_host *host)
326{
327 u32 mask;
328
329 BUG_ON(!host->data);
330
331 if (host->size == 0)
332 return;
333
334 if (host->data->flags & MMC_DATA_READ)
335 mask = SDHCI_DATA_AVAILABLE;
336 else
337 mask = SDHCI_SPACE_AVAILABLE;
338
339 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
340 if (host->data->flags & MMC_DATA_READ)
341 sdhci_read_block_pio(host);
342 else
343 sdhci_write_block_pio(host);
d129bceb 344
a406f5a3
PO		 345 if (host->size == 0)
346 break;
347
348 BUG_ON(host->num_sg == 0);
349 }
d129bceb 350
a406f5a3 351 DBG("PIO transfer complete.\n");
d129bceb
PO		 352}
353
354static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
355{
1c8cde92
PO		 356 u8 count;
357 unsigned target_timeout, current_timeout;
d129bceb
PO		 358
359 WARN_ON(host->data);
360
c7fa9963 361 if (data == NULL)
d129bceb 362 return;
d129bceb
PO		 363
364 DBG("blksz %04x blks %04x flags %08x\n",
a3fd4a1b 365 data->blksz, data->blocks, data->flags);
d129bceb
PO		 366 DBG("tsac %d ms nsac %d clk\n",
367 data->timeout_ns / 1000000, data->timeout_clks);
368
bab76961
PO		 369 /* Sanity checks */
370 BUG_ON(data->blksz * data->blocks > 524288);
fe4a3c7a 371 BUG_ON(data->blksz > host->mmc->max_blk_size);
1d676e02 372 BUG_ON(data->blocks > 65535);
d129bceb 373
1c8cde92
PO		 374 /* timeout in us */
375 target_timeout = data->timeout_ns / 1000 +
376 data->timeout_clks / host->clock;
d129bceb 377
1c8cde92
PO		 378 /*
379 * Figure out needed cycles.
380 * We do this in steps in order to fit inside a 32 bit int.
381 * The first step is the minimum timeout, which will have a
382 * minimum resolution of 6 bits:
383 * (1) 2^13*1000 > 2^22,
384 * (2) host->timeout_clk < 2^16
385 * =>
386 * (1) / (2) > 2^6
387 */
388 count = 0;
389 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
390 while (current_timeout < target_timeout) {
391 count++;
392 current_timeout <<= 1;
393 if (count >= 0xF)
394 break;
395 }
396
397 if (count >= 0xF) {
398 printk(KERN_WARNING "%s: Too large timeout requested!\n",
399 mmc_hostname(host->mmc));
400 count = 0xE;
401 }
402
403 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
d129bceb
PO		 404
405 if (host->flags & SDHCI_USE_DMA) {
406 int count;
407
408 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
409 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
410 BUG_ON(count != 1);
411
412 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
413 } else {
a3fd4a1b 414 host->size = data->blksz * data->blocks;
d129bceb
PO		 415
416 host->cur_sg = data->sg;
417 host->num_sg = data->sg_len;
418
419 host->offset = 0;
420 host->remain = host->cur_sg->length;
421 }
c7fa9963 422
bab76961
PO		 423 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
424 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
425 host->ioaddr + SDHCI_BLOCK_SIZE);
c7fa9963
PO		 426 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
427}
428
429static void sdhci_set_transfer_mode(struct sdhci_host *host,
430 struct mmc_data *data)
431{
432 u16 mode;
433
434 WARN_ON(host->data);
435
436 if (data == NULL)
437 return;
438
439 mode = SDHCI_TRNS_BLK_CNT_EN;
440 if (data->blocks > 1)
441 mode |= SDHCI_TRNS_MULTI;
442 if (data->flags & MMC_DATA_READ)
443 mode |= SDHCI_TRNS_READ;
444 if (host->flags & SDHCI_USE_DMA)
445 mode |= SDHCI_TRNS_DMA;
446
447 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
d129bceb
PO		 448}
449
450static void sdhci_finish_data(struct sdhci_host *host)
451{
452 struct mmc_data *data;
d129bceb
PO		 453 u16 blocks;
454
455 BUG_ON(!host->data);
456
457 data = host->data;
458 host->data = NULL;
459
460 if (host->flags & SDHCI_USE_DMA) {
461 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
462 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
d129bceb
PO		 463 }
464
465 /*
466 * Controller doesn't count down when in single block mode.
467 */
468 if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
469 blocks = 0;
470 else
471 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
a3fd4a1b 472 data->bytes_xfered = data->blksz * (data->blocks - blocks);
d129bceb
PO		 473
474 if ((data->error == MMC_ERR_NONE) && blocks) {
475 printk(KERN_ERR "%s: Controller signalled completion even "
476 "though there were blocks left. Please report this "
477 "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
478 data->error = MMC_ERR_FAILED;
4cca56c5 479 } else if (host->size != 0) {
d129bceb
PO		 480 printk(KERN_ERR "%s: %d bytes were left untransferred. "
481 "Please report this to " BUGMAIL ".\n",
482 mmc_hostname(host->mmc), host->size);
483 data->error = MMC_ERR_FAILED;
484 }
485
486 DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
487
488 if (data->stop) {
489 /*
490 * The controller needs a reset of internal state machines
491 * upon error conditions.
492 */
493 if (data->error != MMC_ERR_NONE) {
494 sdhci_reset(host, SDHCI_RESET_CMD);
495 sdhci_reset(host, SDHCI_RESET_DATA);
496 }
497
498 sdhci_send_command(host, data->stop);
499 } else
500 tasklet_schedule(&host->finish_tasklet);
501}
502
503static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
504{
505 int flags;
fd2208d7 506 u32 mask;
7cb2c76f 507 unsigned long timeout;
d129bceb
PO		 508
509 WARN_ON(host->cmd);
510
511 DBG("Sending cmd (%x)\n", cmd->opcode);
512
513 /* Wait max 10 ms */
7cb2c76f 514 timeout = 10;
fd2208d7
PO		 515
516 mask = SDHCI_CMD_INHIBIT;
517 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
518 mask |= SDHCI_DATA_INHIBIT;
519
520 /* We shouldn't wait for data inihibit for stop commands, even
521 though they might use busy signaling */
522 if (host->mrq->data && (cmd == host->mrq->data->stop))
523 mask &= ~SDHCI_DATA_INHIBIT;
524
525 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 526 if (timeout == 0) {
d129bceb 527 printk(KERN_ERR "%s: Controller never released "
fd2208d7 528 "inhibit bit(s). Please report this to "
d129bceb
PO		 529 BUGMAIL ".\n", mmc_hostname(host->mmc));
530 sdhci_dumpregs(host);
531 cmd->error = MMC_ERR_FAILED;
532 tasklet_schedule(&host->finish_tasklet);
533 return;
534 }
7cb2c76f
PO		 535 timeout--;
536 mdelay(1);
537 }
d129bceb
PO		 538
539 mod_timer(&host->timer, jiffies + 10 * HZ);
540
541 host->cmd = cmd;
542
543 sdhci_prepare_data(host, cmd->data);
544
545 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
546
c7fa9963
PO		 547 sdhci_set_transfer_mode(host, cmd->data);
548
d129bceb
PO		 549 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
550 printk(KERN_ERR "%s: Unsupported response type! "
551 "Please report this to " BUGMAIL ".\n",
552 mmc_hostname(host->mmc));
553 cmd->error = MMC_ERR_INVALID;
554 tasklet_schedule(&host->finish_tasklet);
555 return;
556 }
557
558 if (!(cmd->flags & MMC_RSP_PRESENT))
559 flags = SDHCI_CMD_RESP_NONE;
560 else if (cmd->flags & MMC_RSP_136)
561 flags = SDHCI_CMD_RESP_LONG;
562 else if (cmd->flags & MMC_RSP_BUSY)
563 flags = SDHCI_CMD_RESP_SHORT_BUSY;
564 else
565 flags = SDHCI_CMD_RESP_SHORT;
566
567 if (cmd->flags & MMC_RSP_CRC)
568 flags |= SDHCI_CMD_CRC;
569 if (cmd->flags & MMC_RSP_OPCODE)
570 flags |= SDHCI_CMD_INDEX;
571 if (cmd->data)
572 flags |= SDHCI_CMD_DATA;
573
fb61e289 574 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
d129bceb
PO		 575 host->ioaddr + SDHCI_COMMAND);
576}
577
578static void sdhci_finish_command(struct sdhci_host *host)
579{
580 int i;
581
582 BUG_ON(host->cmd == NULL);
583
584 if (host->cmd->flags & MMC_RSP_PRESENT) {
585 if (host->cmd->flags & MMC_RSP_136) {
586 /* CRC is stripped so we need to do some shifting. */
587 for (i = 0;i < 4;i++) {
588 host->cmd->resp[i] = readl(host->ioaddr +
589 SDHCI_RESPONSE + (3-i)*4) << 8;
590 if (i != 3)
591 host->cmd->resp[i] |=
592 readb(host->ioaddr +
593 SDHCI_RESPONSE + (3-i)*4-1);
594 }
595 } else {
596 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
597 }
598 }
599
600 host->cmd->error = MMC_ERR_NONE;
601
602 DBG("Ending cmd (%x)\n", host->cmd->opcode);
603
3192a28f 604 if (host->cmd->data)
d129bceb 605 host->data = host->cmd->data;
3192a28f 606 else
d129bceb
PO		 607 tasklet_schedule(&host->finish_tasklet);
608
609 host->cmd = NULL;
610}
611
612static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
613{
614 int div;
077df884 615 u8 ctrl;
d129bceb 616 u16 clk;
7cb2c76f 617 unsigned long timeout;
d129bceb
PO		 618
619 if (clock == host->clock)
620 return;
621
622 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
623
077df884
PO		 624 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
625 if (clock > 25000000)
626 ctrl |= SDHCI_CTRL_HISPD;
627 else
628 ctrl &= ~SDHCI_CTRL_HISPD;
629 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
630
d129bceb
PO		 631 if (clock == 0)
632 goto out;
633
634 for (div = 1;div < 256;div *= 2) {
635 if ((host->max_clk / div) <= clock)
636 break;
637 }
638 div >>= 1;
639
640 clk = div << SDHCI_DIVIDER_SHIFT;
641 clk |= SDHCI_CLOCK_INT_EN;
642 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
643
644 /* Wait max 10 ms */
7cb2c76f
PO		 645 timeout = 10;
646 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
647 & SDHCI_CLOCK_INT_STABLE)) {
648 if (timeout == 0) {
d129bceb
PO		 649 printk(KERN_ERR "%s: Internal clock never stabilised. "
650 "Please report this to " BUGMAIL ".\n",
651 mmc_hostname(host->mmc));
652 sdhci_dumpregs(host);
653 return;
654 }
7cb2c76f
PO		 655 timeout--;
656 mdelay(1);
657 }
d129bceb
PO		 658
659 clk |= SDHCI_CLOCK_CARD_EN;
660 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
661
662out:
663 host->clock = clock;
664}
665
146ad66e
PO		 666static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
667{
668 u8 pwr;
669
670 if (host->power == power)
671 return;
672
9e9dc5f2
DS		 673 if (power == (unsigned short)-1) {
674 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e 675 goto out;
9e9dc5f2
DS		 676 }
677
678 /*
679 * Spec says that we should clear the power reg before setting
680 * a new value. Some controllers don't seem to like this though.
681 */
682 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
683 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e
PO		 684
685 pwr = SDHCI_POWER_ON;
686
687 switch (power) {
688 case MMC_VDD_170:
689 case MMC_VDD_180:
690 case MMC_VDD_190:
691 pwr |= SDHCI_POWER_180;
692 break;
693 case MMC_VDD_290:
694 case MMC_VDD_300:
695 case MMC_VDD_310:
696 pwr |= SDHCI_POWER_300;
697 break;
698 case MMC_VDD_320:
699 case MMC_VDD_330:
700 case MMC_VDD_340:
701 pwr |= SDHCI_POWER_330;
702 break;
703 default:
704 BUG();
705 }
706
707 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
708
709out:
710 host->power = power;
711}
712
d129bceb
PO		 713/*****************************************************************************\
714 * *
715 * MMC callbacks *
716 * *
717\*****************************************************************************/
718
719static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
720{
721 struct sdhci_host *host;
722 unsigned long flags;
723
724 host = mmc_priv(mmc);
725
726 spin_lock_irqsave(&host->lock, flags);
727
728 WARN_ON(host->mrq != NULL);
729
730 sdhci_activate_led(host);
731
732 host->mrq = mrq;
733
734 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
735 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
736 tasklet_schedule(&host->finish_tasklet);
737 } else
738 sdhci_send_command(host, mrq->cmd);
739
5f25a66f 740 mmiowb();
d129bceb
PO		 741 spin_unlock_irqrestore(&host->lock, flags);
742}
743
744static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
745{
746 struct sdhci_host *host;
747 unsigned long flags;
748 u8 ctrl;
749
750 host = mmc_priv(mmc);
751
752 spin_lock_irqsave(&host->lock, flags);
753
d129bceb
PO		 754 /*
755 * Reset the chip on each power off.
756 * Should clear out any weird states.
757 */
758 if (ios->power_mode == MMC_POWER_OFF) {
759 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb 760 sdhci_init(host);
d129bceb
PO		 761 }
762
763 sdhci_set_clock(host, ios->clock);
764
765 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 766 sdhci_set_power(host, -1);
d129bceb 767 else
146ad66e 768 sdhci_set_power(host, ios->vdd);
d129bceb
PO		 769
770 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
771 if (ios->bus_width == MMC_BUS_WIDTH_4)
772 ctrl |= SDHCI_CTRL_4BITBUS;
773 else
774 ctrl &= ~SDHCI_CTRL_4BITBUS;
775 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
776
5f25a66f 777 mmiowb();
d129bceb
PO		 778 spin_unlock_irqrestore(&host->lock, flags);
779}
780
781static int sdhci_get_ro(struct mmc_host *mmc)
782{
783 struct sdhci_host *host;
784 unsigned long flags;
785 int present;
786
787 host = mmc_priv(mmc);
788
789 spin_lock_irqsave(&host->lock, flags);
790
791 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
792
793 spin_unlock_irqrestore(&host->lock, flags);
794
795 return !(present & SDHCI_WRITE_PROTECT);
796}
797
ab7aefd0 798static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 799 .request = sdhci_request,
800 .set_ios = sdhci_set_ios,
801 .get_ro = sdhci_get_ro,
802};
803
804/*****************************************************************************\
805 * *
806 * Tasklets *
807 * *
808\*****************************************************************************/
809
810static void sdhci_tasklet_card(unsigned long param)
811{
812 struct sdhci_host *host;
813 unsigned long flags;
814
815 host = (struct sdhci_host*)param;
816
817 spin_lock_irqsave(&host->lock, flags);
818
819 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
820 if (host->mrq) {
821 printk(KERN_ERR "%s: Card removed during transfer!\n",
822 mmc_hostname(host->mmc));
823 printk(KERN_ERR "%s: Resetting controller.\n",
824 mmc_hostname(host->mmc));
825
826 sdhci_reset(host, SDHCI_RESET_CMD);
827 sdhci_reset(host, SDHCI_RESET_DATA);
828
829 host->mrq->cmd->error = MMC_ERR_FAILED;
830 tasklet_schedule(&host->finish_tasklet);
831 }
832 }
833
834 spin_unlock_irqrestore(&host->lock, flags);
835
836 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
837}
838
839static void sdhci_tasklet_finish(unsigned long param)
840{
841 struct sdhci_host *host;
842 unsigned long flags;
843 struct mmc_request *mrq;
844
845 host = (struct sdhci_host*)param;
846
847 spin_lock_irqsave(&host->lock, flags);
848
849 del_timer(&host->timer);
850
851 mrq = host->mrq;
852
853 DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
854
855 /*
856 * The controller needs a reset of internal state machines
857 * upon error conditions.
858 */
859 if ((mrq->cmd->error != MMC_ERR_NONE) ||
860 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
861 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
645289dc
PO		 862
863 /* Some controllers need this kick or reset won't work here */
864 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
865 unsigned int clock;
866
867 /* This is to force an update */
868 clock = host->clock;
869 host->clock = 0;
870 sdhci_set_clock(host, clock);
871 }
872
873 /* Spec says we should do both at the same time, but Ricoh
874 controllers do not like that. */
d129bceb
PO		 875 sdhci_reset(host, SDHCI_RESET_CMD);
876 sdhci_reset(host, SDHCI_RESET_DATA);
877 }
878
879 host->mrq = NULL;
880 host->cmd = NULL;
881 host->data = NULL;
882
883 sdhci_deactivate_led(host);
884
5f25a66f 885 mmiowb();
d129bceb
PO		 886 spin_unlock_irqrestore(&host->lock, flags);
887
888 mmc_request_done(host->mmc, mrq);
889}
890
891static void sdhci_timeout_timer(unsigned long data)
892{
893 struct sdhci_host *host;
894 unsigned long flags;
895
896 host = (struct sdhci_host*)data;
897
898 spin_lock_irqsave(&host->lock, flags);
899
900 if (host->mrq) {
901 printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
902 "Please report this to " BUGMAIL ".\n",
903 mmc_hostname(host->mmc));
904 sdhci_dumpregs(host);
905
906 if (host->data) {
907 host->data->error = MMC_ERR_TIMEOUT;
908 sdhci_finish_data(host);
909 } else {
910 if (host->cmd)
911 host->cmd->error = MMC_ERR_TIMEOUT;
912 else
913 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
914
915 tasklet_schedule(&host->finish_tasklet);
916 }
917 }
918
5f25a66f 919 mmiowb();
d129bceb
PO		 920 spin_unlock_irqrestore(&host->lock, flags);
921}
922
923/*****************************************************************************\
924 * *
925 * Interrupt handling *
926 * *
927\*****************************************************************************/
928
929static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
930{
931 BUG_ON(intmask == 0);
932
933 if (!host->cmd) {
934 printk(KERN_ERR "%s: Got command interrupt even though no "
935 "command operation was in progress.\n",
936 mmc_hostname(host->mmc));
937 printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
938 mmc_hostname(host->mmc));
939 sdhci_dumpregs(host);
940 return;
941 }
942
943 if (intmask & SDHCI_INT_RESPONSE)
944 sdhci_finish_command(host);
945 else {
946 if (intmask & SDHCI_INT_TIMEOUT)
947 host->cmd->error = MMC_ERR_TIMEOUT;
948 else if (intmask & SDHCI_INT_CRC)
949 host->cmd->error = MMC_ERR_BADCRC;
950 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
951 host->cmd->error = MMC_ERR_FAILED;
952 else
953 host->cmd->error = MMC_ERR_INVALID;
954
955 tasklet_schedule(&host->finish_tasklet);
956 }
957}
958
959static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
960{
961 BUG_ON(intmask == 0);
962
963 if (!host->data) {
964 /*
965 * A data end interrupt is sent together with the response
966 * for the stop command.
967 */
968 if (intmask & SDHCI_INT_DATA_END)
969 return;
970
971 printk(KERN_ERR "%s: Got data interrupt even though no "
972 "data operation was in progress.\n",
973 mmc_hostname(host->mmc));
974 printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
975 mmc_hostname(host->mmc));
976 sdhci_dumpregs(host);
977
978 return;
979 }
980
981 if (intmask & SDHCI_INT_DATA_TIMEOUT)
982 host->data->error = MMC_ERR_TIMEOUT;
983 else if (intmask & SDHCI_INT_DATA_CRC)
984 host->data->error = MMC_ERR_BADCRC;
985 else if (intmask & SDHCI_INT_DATA_END_BIT)
986 host->data->error = MMC_ERR_FAILED;
987
988 if (host->data->error != MMC_ERR_NONE)
989 sdhci_finish_data(host);
990 else {
a406f5a3 991 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 992 sdhci_transfer_pio(host);
993
994 if (intmask & SDHCI_INT_DATA_END)
995 sdhci_finish_data(host);
996 }
997}
998
7d12e780 999static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1000{
1001 irqreturn_t result;
1002 struct sdhci_host* host = dev_id;
1003 u32 intmask;
1004
1005 spin_lock(&host->lock);
1006
1007 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1008
1009 if (!intmask) {
1010 result = IRQ_NONE;
1011 goto out;
1012 }
1013
1014 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1015
3192a28f
PO		 1016 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1017 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1018 host->ioaddr + SDHCI_INT_STATUS);
d129bceb 1019 tasklet_schedule(&host->card_tasklet);
3192a28f 1020 }
d129bceb 1021
3192a28f 1022 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1023
3192a28f 1024 if (intmask & SDHCI_INT_CMD_MASK) {
d129bceb
PO		 1025 writel(intmask & SDHCI_INT_CMD_MASK,
1026 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1027 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1028 }
1029
1030 if (intmask & SDHCI_INT_DATA_MASK) {
d129bceb
PO		 1031 writel(intmask & SDHCI_INT_DATA_MASK,
1032 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1033 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1034 }
1035
1036 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1037
d129bceb 1038 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1039 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1040 mmc_hostname(host->mmc));
3192a28f 1041 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
d129bceb
PO		 1042 }
1043
3192a28f
PO		 1044 intmask &= SDHCI_INT_BUS_POWER;
1045
1046 if (intmask) {
1047 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
d129bceb 1048 "report this to " BUGMAIL ".\n",
3192a28f 1049 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1050 sdhci_dumpregs(host);
1051
d129bceb 1052 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1053 }
d129bceb
PO		 1054
1055 result = IRQ_HANDLED;
1056
5f25a66f 1057 mmiowb();
d129bceb
PO		 1058out:
1059 spin_unlock(&host->lock);
1060
1061 return result;
1062}
1063
1064/*****************************************************************************\
1065 * *
1066 * Suspend/resume *
1067 * *
1068\*****************************************************************************/
1069
1070#ifdef CONFIG_PM
1071
1072static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1073{
1074 struct sdhci_chip *chip;
1075 int i, ret;
1076
1077 chip = pci_get_drvdata(pdev);
1078 if (!chip)
1079 return 0;
1080
1081 DBG("Suspending...\n");
1082
1083 for (i = 0;i < chip->num_slots;i++) {
1084 if (!chip->hosts[i])
1085 continue;
1086 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1087 if (ret) {
1088 for (i--;i >= 0;i--)
1089 mmc_resume_host(chip->hosts[i]->mmc);
1090 return ret;
1091 }
1092 }
1093
1094 pci_save_state(pdev);
1095 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1096 pci_disable_device(pdev);
1097 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1098
1099 return 0;
1100}
1101
1102static int sdhci_resume (struct pci_dev *pdev)
1103{
1104 struct sdhci_chip *chip;
1105 int i, ret;
1106
1107 chip = pci_get_drvdata(pdev);
1108 if (!chip)
1109 return 0;
1110
1111 DBG("Resuming...\n");
1112
1113 pci_set_power_state(pdev, PCI_D0);
1114 pci_restore_state(pdev);
df1c4b7b
PO		 1115 ret = pci_enable_device(pdev);
1116 if (ret)
1117 return ret;
d129bceb
PO		 1118
1119 for (i = 0;i < chip->num_slots;i++) {
1120 if (!chip->hosts[i])
1121 continue;
1122 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1123 pci_set_master(pdev);
1124 sdhci_init(chip->hosts[i]);
5f25a66f 1125 mmiowb();
d129bceb
PO		 1126 ret = mmc_resume_host(chip->hosts[i]->mmc);
1127 if (ret)
1128 return ret;
1129 }
1130
1131 return 0;
1132}
1133
1134#else /* CONFIG_PM */
1135
1136#define sdhci_suspend NULL
1137#define sdhci_resume NULL
1138
1139#endif /* CONFIG_PM */
1140
1141/*****************************************************************************\
1142 * *
1143 * Device probing/removal *
1144 * *
1145\*****************************************************************************/
1146
1147static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1148{
1149 int ret;
4a965505 1150 unsigned int version;
d129bceb
PO		 1151 struct sdhci_chip *chip;
1152 struct mmc_host *mmc;
1153 struct sdhci_host *host;
1154
1155 u8 first_bar;
1156 unsigned int caps;
1157
1158 chip = pci_get_drvdata(pdev);
1159 BUG_ON(!chip);
1160
1161 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1162 if (ret)
1163 return ret;
1164
1165 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1166
1167 if (first_bar > 5) {
1168 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1169 return -ENODEV;
1170 }
1171
1172 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1173 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1174 return -ENODEV;
1175 }
1176
1177 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
a98087cf
PO		 1178 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1179 "You may experience problems.\n");
d129bceb
PO		 1180 }
1181
67435274
PO		 1182 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1183 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1184 return -ENODEV;
1185 }
1186
1187 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1188 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1189 return -ENODEV;
1190 }
1191
d129bceb
PO		 1192 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1193 if (!mmc)
1194 return -ENOMEM;
1195
1196 host = mmc_priv(mmc);
1197 host->mmc = mmc;
1198
8a4da143
PO		 1199 host->chip = chip;
1200 chip->hosts[slot] = host;
1201
d129bceb
PO		 1202 host->bar = first_bar + slot;
1203
1204 host->addr = pci_resource_start(pdev, host->bar);
1205 host->irq = pdev->irq;
1206
1207 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1208
1209 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1210
1211 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1212 if (ret)
1213 goto free;
1214
1215 host->ioaddr = ioremap_nocache(host->addr,
1216 pci_resource_len(pdev, host->bar));
1217 if (!host->ioaddr) {
1218 ret = -ENOMEM;
1219 goto release;
1220 }
1221
d96649ed
PO		 1222 sdhci_reset(host, SDHCI_RESET_ALL);
1223
4a965505
PO		 1224 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1225 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1226 if (version != 0) {
1227 printk(KERN_ERR "%s: Unknown controller version (%d). "
8b1b2185 1228 "You may experience problems.\n", host->slot_descr,
4a965505 1229 version);
4a965505
PO		 1230 }
1231
d129bceb
PO		 1232 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1233
67435274
PO		 1234 if (debug_nodma)
1235 DBG("DMA forced off\n");
1236 else if (debug_forcedma) {
1237 DBG("DMA forced on\n");
1238 host->flags |= SDHCI_USE_DMA;
98608076
PO		 1239 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1240 host->flags |= SDHCI_USE_DMA;
1241 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
67435274
PO		 1242 DBG("Controller doesn't have DMA interface\n");
1243 else if (!(caps & SDHCI_CAN_DO_DMA))
1244 DBG("Controller doesn't have DMA capability\n");
1245 else
d129bceb
PO		 1246 host->flags |= SDHCI_USE_DMA;
1247
1248 if (host->flags & SDHCI_USE_DMA) {
1249 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1250 printk(KERN_WARNING "%s: No suitable DMA available. "
1251 "Falling back to PIO.\n", host->slot_descr);
1252 host->flags &= ~SDHCI_USE_DMA;
1253 }
1254 }
1255
1256 if (host->flags & SDHCI_USE_DMA)
1257 pci_set_master(pdev);
1258 else /* XXX: Hack to get MMC layer to avoid highmem */
1259 pdev->dma_mask = 0;
1260
8ef1a143
PO		 1261 host->max_clk =
1262 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1263 if (host->max_clk == 0) {
1264 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1265 "frequency.\n", host->slot_descr);
1266 ret = -ENODEV;
1267 goto unmap;
1268 }
d129bceb
PO		 1269 host->max_clk *= 1000000;
1270
1c8cde92
PO		 1271 host->timeout_clk =
1272 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1273 if (host->timeout_clk == 0) {
1274 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1275 "frequency.\n", host->slot_descr);
1276 ret = -ENODEV;
1277 goto unmap;
1278 }
1279 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1280 host->timeout_clk *= 1000;
d129bceb
PO		 1281
1282 /*
1283 * Set host parameters.
1284 */
1285 mmc->ops = &sdhci_ops;
1286 mmc->f_min = host->max_clk / 256;
1287 mmc->f_max = host->max_clk;
42431acb 1288 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
d129bceb 1289
146ad66e
PO		 1290 mmc->ocr_avail = 0;
1291 if (caps & SDHCI_CAN_VDD_330)
1292 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1293 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1294 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1295 if (caps & SDHCI_CAN_VDD_180)
146ad66e
PO		 1296 mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
1297
077df884
PO		 1298 if ((host->max_clk > 25000000) && !(caps & SDHCI_CAN_DO_HISPD)) {
1299 printk(KERN_ERR "%s: Controller reports > 25 MHz base clock,"
1300 " but no high speed support.\n",
1301 host->slot_descr);
1302 mmc->f_max = 25000000;
1303 }
1304
146ad66e
PO		 1305 if (mmc->ocr_avail == 0) {
1306 printk(KERN_ERR "%s: Hardware doesn't report any "
1307 "support voltages.\n", host->slot_descr);
1308 ret = -ENODEV;
1309 goto unmap;
1310 }
1311
d129bceb
PO		 1312 spin_lock_init(&host->lock);
1313
1314 /*
1315 * Maximum number of segments. Hardware cannot do scatter lists.
1316 */
1317 if (host->flags & SDHCI_USE_DMA)
1318 mmc->max_hw_segs = 1;
1319 else
1320 mmc->max_hw_segs = 16;
1321 mmc->max_phys_segs = 16;
1322
1323 /*
bab76961 1324 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1325 * size (512KiB).
d129bceb 1326 */
55db890a 1327 mmc->max_req_size = 524288;
d129bceb
PO		 1328
1329 /*
1330 * Maximum segment size. Could be one segment with the maximum number
55db890a 1331 * of bytes.
d129bceb 1332 */
55db890a 1333 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1334
fe4a3c7a
PO		 1335 /*
1336 * Maximum block size. This varies from controller to controller and
1337 * is specified in the capabilities register.
1338 */
1339 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1340 if (mmc->max_blk_size >= 3) {
1341 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1342 host->slot_descr);
1343 ret = -ENODEV;
1344 goto unmap;
1345 }
1346 mmc->max_blk_size = 512 << mmc->max_blk_size;
1347
55db890a
PO		 1348 /*
1349 * Maximum block count.
1350 */
1351 mmc->max_blk_count = 65535;
1352
d129bceb
PO		 1353 /*
1354 * Init tasklets.
1355 */
1356 tasklet_init(&host->card_tasklet,
1357 sdhci_tasklet_card, (unsigned long)host);
1358 tasklet_init(&host->finish_tasklet,
1359 sdhci_tasklet_finish, (unsigned long)host);
1360
e4cad1b5 1361 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1362
dace1453 1363 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
d129bceb
PO		 1364 host->slot_descr, host);
1365 if (ret)
8ef1a143 1366 goto untasklet;
d129bceb
PO		 1367
1368 sdhci_init(host);
1369
1370#ifdef CONFIG_MMC_DEBUG
1371 sdhci_dumpregs(host);
1372#endif
1373
5f25a66f
PO		 1374 mmiowb();
1375
d129bceb
PO		 1376 mmc_add_host(mmc);
1377
1378 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1379 host->addr, host->irq,
1380 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1381
1382 return 0;
1383
8ef1a143 1384untasklet:
d129bceb
PO		 1385 tasklet_kill(&host->card_tasklet);
1386 tasklet_kill(&host->finish_tasklet);
8ef1a143 1387unmap:
d129bceb
PO		 1388 iounmap(host->ioaddr);
1389release:
1390 pci_release_region(pdev, host->bar);
1391free:
1392 mmc_free_host(mmc);
1393
1394 return ret;
1395}
1396
1397static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1398{
1399 struct sdhci_chip *chip;
1400 struct mmc_host *mmc;
1401 struct sdhci_host *host;
1402
1403 chip = pci_get_drvdata(pdev);
1404 host = chip->hosts[slot];
1405 mmc = host->mmc;
1406
1407 chip->hosts[slot] = NULL;
1408
1409 mmc_remove_host(mmc);
1410
1411 sdhci_reset(host, SDHCI_RESET_ALL);
1412
1413 free_irq(host->irq, host);
1414
1415 del_timer_sync(&host->timer);
1416
1417 tasklet_kill(&host->card_tasklet);
1418 tasklet_kill(&host->finish_tasklet);
1419
1420 iounmap(host->ioaddr);
1421
1422 pci_release_region(pdev, host->bar);
1423
1424 mmc_free_host(mmc);
1425}
1426
1427static int __devinit sdhci_probe(struct pci_dev *pdev,
1428 const struct pci_device_id *ent)
1429{
1430 int ret, i;
51f82bc0 1431 u8 slots, rev;
d129bceb
PO		 1432 struct sdhci_chip *chip;
1433
1434 BUG_ON(pdev == NULL);
1435 BUG_ON(ent == NULL);
1436
51f82bc0
PO		 1437 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1438
1439 printk(KERN_INFO DRIVER_NAME
1440 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1441 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1442 (int)rev);
d129bceb
PO		 1443
1444 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1445 if (ret)
1446 return ret;
1447
1448 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1449 DBG("found %d slot(s)\n", slots);
1450 if (slots == 0)
1451 return -ENODEV;
1452
1453 ret = pci_enable_device(pdev);
1454 if (ret)
1455 return ret;
1456
1457 chip = kzalloc(sizeof(struct sdhci_chip) +
1458 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1459 if (!chip) {
1460 ret = -ENOMEM;
1461 goto err;
1462 }
1463
1464 chip->pdev = pdev;
df673b22
PO		 1465 chip->quirks = ent->driver_data;
1466
1467 if (debug_quirks)
1468 chip->quirks = debug_quirks;
d129bceb
PO		 1469
1470 chip->num_slots = slots;
1471 pci_set_drvdata(pdev, chip);
1472
1473 for (i = 0;i < slots;i++) {
1474 ret = sdhci_probe_slot(pdev, i);
1475 if (ret) {
1476 for (i--;i >= 0;i--)
1477 sdhci_remove_slot(pdev, i);
1478 goto free;
1479 }
1480 }
1481
1482 return 0;
1483
1484free:
1485 pci_set_drvdata(pdev, NULL);
1486 kfree(chip);
1487
1488err:
1489 pci_disable_device(pdev);
1490 return ret;
1491}
1492
1493static void __devexit sdhci_remove(struct pci_dev *pdev)
1494{
1495 int i;
1496 struct sdhci_chip *chip;
1497
1498 chip = pci_get_drvdata(pdev);
1499
1500 if (chip) {
1501 for (i = 0;i < chip->num_slots;i++)
1502 sdhci_remove_slot(pdev, i);
1503
1504 pci_set_drvdata(pdev, NULL);
1505
1506 kfree(chip);
1507 }
1508
1509 pci_disable_device(pdev);
1510}
1511
1512static struct pci_driver sdhci_driver = {
1513 .name = DRIVER_NAME,
1514 .id_table = pci_ids,
1515 .probe = sdhci_probe,
1516 .remove = __devexit_p(sdhci_remove),
1517 .suspend = sdhci_suspend,
1518 .resume = sdhci_resume,
1519};
1520
1521/*****************************************************************************\
1522 * *
1523 * Driver init/exit *
1524 * *
1525\*****************************************************************************/
1526
1527static int __init sdhci_drv_init(void)
1528{
1529 printk(KERN_INFO DRIVER_NAME
52fbf9c9 1530 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 1531 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1532
1533 return pci_register_driver(&sdhci_driver);
1534}
1535
1536static void __exit sdhci_drv_exit(void)
1537{
1538 DBG("Exiting\n");
1539
1540 pci_unregister_driver(&sdhci_driver);
1541}
1542
1543module_init(sdhci_drv_init);
1544module_exit(sdhci_drv_exit);
1545
67435274
PO		 1546module_param(debug_nodma, uint, 0444);
1547module_param(debug_forcedma, uint, 0444);
df673b22 1548module_param(debug_quirks, uint, 0444);
67435274 1549
d129bceb
PO		 1550MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1551MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
d129bceb 1552MODULE_LICENSE("GPL");
67435274
PO		 1553
1554MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1555MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
df673b22 1556MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux 6.x block layer and io_uring tree(s)