Commit | Line | Data |
---|---|---|
d129bceb PO |
1 | /* |
2 | * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver | |
3 | * | |
4 | * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
d129bceb PO |
10 | */ |
11 | ||
d129bceb PO |
12 | #include <linux/delay.h> |
13 | #include <linux/highmem.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | ||
17 | #include <linux/mmc/host.h> | |
18 | #include <linux/mmc/protocol.h> | |
19 | ||
20 | #include <asm/scatterlist.h> | |
21 | ||
22 | #include "sdhci.h" | |
23 | ||
24 | #define DRIVER_NAME "sdhci" | |
2c5f3940 | 25 | #define DRIVER_VERSION "0.12" |
d129bceb PO |
26 | |
27 | #define BUGMAIL "<sdhci-devel@list.drzeus.cx>" | |
28 | ||
d129bceb | 29 | #define DBG(f, x...) \ |
c6563178 | 30 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 31 | |
67435274 PO |
32 | static unsigned int debug_nodma = 0; |
33 | static unsigned int debug_forcedma = 0; | |
df673b22 | 34 | static unsigned int debug_quirks = 0; |
67435274 | 35 | |
645289dc | 36 | #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) |
98608076 | 37 | #define SDHCI_QUIRK_FORCE_DMA (1<<1) |
8a4da143 PO |
38 | /* Controller doesn't like some resets when there is no card inserted. */ |
39 | #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) | |
9e9dc5f2 | 40 | #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) |
645289dc | 41 | |
d129bceb | 42 | static const struct pci_device_id pci_ids[] __devinitdata = { |
645289dc PO |
43 | { |
44 | .vendor = PCI_VENDOR_ID_RICOH, | |
45 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
46 | .subvendor = PCI_VENDOR_ID_IBM, | |
47 | .subdevice = PCI_ANY_ID, | |
98608076 PO |
48 | .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET | |
49 | SDHCI_QUIRK_FORCE_DMA, | |
50 | }, | |
51 | ||
52 | { | |
53 | .vendor = PCI_VENDOR_ID_RICOH, | |
54 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
55 | .subvendor = PCI_ANY_ID, | |
56 | .subdevice = PCI_ANY_ID, | |
8a4da143 PO |
57 | .driver_data = SDHCI_QUIRK_FORCE_DMA | |
58 | SDHCI_QUIRK_NO_CARD_NO_RESET, | |
98608076 PO |
59 | }, |
60 | ||
61 | { | |
62 | .vendor = PCI_VENDOR_ID_TI, | |
63 | .device = PCI_DEVICE_ID_TI_XX21_XX11_SD, | |
64 | .subvendor = PCI_ANY_ID, | |
65 | .subdevice = PCI_ANY_ID, | |
66 | .driver_data = SDHCI_QUIRK_FORCE_DMA, | |
645289dc PO |
67 | }, |
68 | ||
9e9dc5f2 DS |
69 | { |
70 | .vendor = PCI_VENDOR_ID_ENE, | |
71 | .device = PCI_DEVICE_ID_ENE_CB712_SD, | |
72 | .subvendor = PCI_ANY_ID, | |
73 | .subdevice = PCI_ANY_ID, | |
74 | .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE, | |
75 | }, | |
76 | ||
645289dc PO |
77 | { /* Generic SD host controller */ |
78 | PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) | |
79 | }, | |
80 | ||
d129bceb PO |
81 | { /* end: all zeroes */ }, |
82 | }; | |
83 | ||
84 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
85 | ||
86 | static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *); | |
87 | static void sdhci_finish_data(struct sdhci_host *); | |
88 | ||
89 | static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); | |
90 | static void sdhci_finish_command(struct sdhci_host *); | |
91 | ||
92 | static void sdhci_dumpregs(struct sdhci_host *host) | |
93 | { | |
94 | printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n"); | |
95 | ||
96 | printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", | |
97 | readl(host->ioaddr + SDHCI_DMA_ADDRESS), | |
98 | readw(host->ioaddr + SDHCI_HOST_VERSION)); | |
99 | printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", | |
100 | readw(host->ioaddr + SDHCI_BLOCK_SIZE), | |
101 | readw(host->ioaddr + SDHCI_BLOCK_COUNT)); | |
102 | printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", | |
103 | readl(host->ioaddr + SDHCI_ARGUMENT), | |
104 | readw(host->ioaddr + SDHCI_TRANSFER_MODE)); | |
105 | printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", | |
106 | readl(host->ioaddr + SDHCI_PRESENT_STATE), | |
107 | readb(host->ioaddr + SDHCI_HOST_CONTROL)); | |
108 | printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", | |
109 | readb(host->ioaddr + SDHCI_POWER_CONTROL), | |
110 | readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL)); | |
111 | printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", | |
112 | readb(host->ioaddr + SDHCI_WALK_UP_CONTROL), | |
113 | readw(host->ioaddr + SDHCI_CLOCK_CONTROL)); | |
114 | printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", | |
115 | readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL), | |
116 | readl(host->ioaddr + SDHCI_INT_STATUS)); | |
117 | printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", | |
118 | readl(host->ioaddr + SDHCI_INT_ENABLE), | |
119 | readl(host->ioaddr + SDHCI_SIGNAL_ENABLE)); | |
120 | printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", | |
121 | readw(host->ioaddr + SDHCI_ACMD12_ERR), | |
122 | readw(host->ioaddr + SDHCI_SLOT_INT_STATUS)); | |
123 | printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n", | |
124 | readl(host->ioaddr + SDHCI_CAPABILITIES), | |
125 | readl(host->ioaddr + SDHCI_MAX_CURRENT)); | |
126 | ||
127 | printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); | |
128 | } | |
129 | ||
130 | /*****************************************************************************\ | |
131 | * * | |
132 | * Low level functions * | |
133 | * * | |
134 | \*****************************************************************************/ | |
135 | ||
136 | static void sdhci_reset(struct sdhci_host *host, u8 mask) | |
137 | { | |
e16514d8 PO |
138 | unsigned long timeout; |
139 | ||
8a4da143 PO |
140 | if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
141 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & | |
142 | SDHCI_CARD_PRESENT)) | |
143 | return; | |
144 | } | |
145 | ||
d129bceb PO |
146 | writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET); |
147 | ||
e16514d8 | 148 | if (mask & SDHCI_RESET_ALL) |
d129bceb PO |
149 | host->clock = 0; |
150 | ||
e16514d8 PO |
151 | /* Wait max 100 ms */ |
152 | timeout = 100; | |
153 | ||
154 | /* hw clears the bit when it's done */ | |
155 | while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) { | |
156 | if (timeout == 0) { | |
157 | printk(KERN_ERR "%s: Reset 0x%x never completed. " | |
158 | "Please report this to " BUGMAIL ".\n", | |
159 | mmc_hostname(host->mmc), (int)mask); | |
160 | sdhci_dumpregs(host); | |
161 | return; | |
162 | } | |
163 | timeout--; | |
164 | mdelay(1); | |
d129bceb PO |
165 | } |
166 | } | |
167 | ||
168 | static void sdhci_init(struct sdhci_host *host) | |
169 | { | |
170 | u32 intmask; | |
171 | ||
172 | sdhci_reset(host, SDHCI_RESET_ALL); | |
173 | ||
3192a28f PO |
174 | intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
175 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | | |
176 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | |
177 | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT | | |
a406f5a3 | 178 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | |
3192a28f | 179 | SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE; |
d129bceb PO |
180 | |
181 | writel(intmask, host->ioaddr + SDHCI_INT_ENABLE); | |
182 | writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
d129bceb PO |
183 | } |
184 | ||
185 | static void sdhci_activate_led(struct sdhci_host *host) | |
186 | { | |
187 | u8 ctrl; | |
188 | ||
189 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
190 | ctrl |= SDHCI_CTRL_LED; | |
191 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
192 | } | |
193 | ||
194 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
195 | { | |
196 | u8 ctrl; | |
197 | ||
198 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
199 | ctrl &= ~SDHCI_CTRL_LED; | |
200 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
201 | } | |
202 | ||
203 | /*****************************************************************************\ | |
204 | * * | |
205 | * Core functions * | |
206 | * * | |
207 | \*****************************************************************************/ | |
208 | ||
2a22b14e | 209 | static inline char* sdhci_sg_to_buffer(struct sdhci_host* host) |
d129bceb | 210 | { |
2a22b14e | 211 | return page_address(host->cur_sg->page) + host->cur_sg->offset; |
d129bceb PO |
212 | } |
213 | ||
214 | static inline int sdhci_next_sg(struct sdhci_host* host) | |
215 | { | |
216 | /* | |
217 | * Skip to next SG entry. | |
218 | */ | |
219 | host->cur_sg++; | |
220 | host->num_sg--; | |
221 | ||
222 | /* | |
223 | * Any entries left? | |
224 | */ | |
225 | if (host->num_sg > 0) { | |
226 | host->offset = 0; | |
227 | host->remain = host->cur_sg->length; | |
228 | } | |
229 | ||
230 | return host->num_sg; | |
231 | } | |
232 | ||
a406f5a3 | 233 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 234 | { |
a406f5a3 PO |
235 | int blksize, chunk_remain; |
236 | u32 data; | |
d129bceb | 237 | char *buffer; |
a406f5a3 | 238 | int size; |
d129bceb | 239 | |
a406f5a3 | 240 | DBG("PIO reading\n"); |
d129bceb | 241 | |
a406f5a3 PO |
242 | blksize = host->data->blksz; |
243 | chunk_remain = 0; | |
244 | data = 0; | |
d129bceb | 245 | |
2a22b14e | 246 | buffer = sdhci_sg_to_buffer(host) + host->offset; |
d129bceb | 247 | |
a406f5a3 PO |
248 | while (blksize) { |
249 | if (chunk_remain == 0) { | |
250 | data = readl(host->ioaddr + SDHCI_BUFFER); | |
251 | chunk_remain = min(blksize, 4); | |
252 | } | |
d129bceb | 253 | |
a406f5a3 PO |
254 | size = min(host->size, host->remain); |
255 | size = min(size, chunk_remain); | |
d129bceb | 256 | |
a406f5a3 PO |
257 | chunk_remain -= size; |
258 | blksize -= size; | |
259 | host->offset += size; | |
260 | host->remain -= size; | |
261 | host->size -= size; | |
262 | while (size) { | |
263 | *buffer = data & 0xFF; | |
264 | buffer++; | |
265 | data >>= 8; | |
266 | size--; | |
267 | } | |
d129bceb | 268 | |
a406f5a3 | 269 | if (host->remain == 0) { |
a406f5a3 PO |
270 | if (sdhci_next_sg(host) == 0) { |
271 | BUG_ON(blksize != 0); | |
272 | return; | |
273 | } | |
2a22b14e | 274 | buffer = sdhci_sg_to_buffer(host); |
d129bceb | 275 | } |
a406f5a3 | 276 | } |
a406f5a3 | 277 | } |
d129bceb | 278 | |
a406f5a3 PO |
279 | static void sdhci_write_block_pio(struct sdhci_host *host) |
280 | { | |
281 | int blksize, chunk_remain; | |
282 | u32 data; | |
283 | char *buffer; | |
284 | int bytes, size; | |
d129bceb | 285 | |
a406f5a3 PO |
286 | DBG("PIO writing\n"); |
287 | ||
288 | blksize = host->data->blksz; | |
289 | chunk_remain = 4; | |
290 | data = 0; | |
d129bceb | 291 | |
a406f5a3 | 292 | bytes = 0; |
2a22b14e | 293 | buffer = sdhci_sg_to_buffer(host) + host->offset; |
d129bceb | 294 | |
a406f5a3 PO |
295 | while (blksize) { |
296 | size = min(host->size, host->remain); | |
297 | size = min(size, chunk_remain); | |
298 | ||
299 | chunk_remain -= size; | |
300 | blksize -= size; | |
d129bceb PO |
301 | host->offset += size; |
302 | host->remain -= size; | |
d129bceb | 303 | host->size -= size; |
a406f5a3 PO |
304 | while (size) { |
305 | data >>= 8; | |
306 | data |= (u32)*buffer << 24; | |
307 | buffer++; | |
308 | size--; | |
309 | } | |
310 | ||
311 | if (chunk_remain == 0) { | |
312 | writel(data, host->ioaddr + SDHCI_BUFFER); | |
313 | chunk_remain = min(blksize, 4); | |
314 | } | |
d129bceb PO |
315 | |
316 | if (host->remain == 0) { | |
d129bceb | 317 | if (sdhci_next_sg(host) == 0) { |
a406f5a3 | 318 | BUG_ON(blksize != 0); |
d129bceb PO |
319 | return; |
320 | } | |
2a22b14e | 321 | buffer = sdhci_sg_to_buffer(host); |
d129bceb PO |
322 | } |
323 | } | |
a406f5a3 PO |
324 | } |
325 | ||
326 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
327 | { | |
328 | u32 mask; | |
329 | ||
330 | BUG_ON(!host->data); | |
331 | ||
332 | if (host->size == 0) | |
333 | return; | |
334 | ||
335 | if (host->data->flags & MMC_DATA_READ) | |
336 | mask = SDHCI_DATA_AVAILABLE; | |
337 | else | |
338 | mask = SDHCI_SPACE_AVAILABLE; | |
339 | ||
340 | while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { | |
341 | if (host->data->flags & MMC_DATA_READ) | |
342 | sdhci_read_block_pio(host); | |
343 | else | |
344 | sdhci_write_block_pio(host); | |
d129bceb | 345 | |
a406f5a3 PO |
346 | if (host->size == 0) |
347 | break; | |
348 | ||
349 | BUG_ON(host->num_sg == 0); | |
350 | } | |
d129bceb | 351 | |
a406f5a3 | 352 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
353 | } |
354 | ||
355 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data) | |
356 | { | |
1c8cde92 PO |
357 | u8 count; |
358 | unsigned target_timeout, current_timeout; | |
d129bceb PO |
359 | |
360 | WARN_ON(host->data); | |
361 | ||
c7fa9963 | 362 | if (data == NULL) |
d129bceb | 363 | return; |
d129bceb PO |
364 | |
365 | DBG("blksz %04x blks %04x flags %08x\n", | |
a3fd4a1b | 366 | data->blksz, data->blocks, data->flags); |
d129bceb PO |
367 | DBG("tsac %d ms nsac %d clk\n", |
368 | data->timeout_ns / 1000000, data->timeout_clks); | |
369 | ||
bab76961 PO |
370 | /* Sanity checks */ |
371 | BUG_ON(data->blksz * data->blocks > 524288); | |
fe4a3c7a | 372 | BUG_ON(data->blksz > host->mmc->max_blk_size); |
1d676e02 | 373 | BUG_ON(data->blocks > 65535); |
d129bceb | 374 | |
1c8cde92 PO |
375 | /* timeout in us */ |
376 | target_timeout = data->timeout_ns / 1000 + | |
377 | data->timeout_clks / host->clock; | |
d129bceb | 378 | |
1c8cde92 PO |
379 | /* |
380 | * Figure out needed cycles. | |
381 | * We do this in steps in order to fit inside a 32 bit int. | |
382 | * The first step is the minimum timeout, which will have a | |
383 | * minimum resolution of 6 bits: | |
384 | * (1) 2^13*1000 > 2^22, | |
385 | * (2) host->timeout_clk < 2^16 | |
386 | * => | |
387 | * (1) / (2) > 2^6 | |
388 | */ | |
389 | count = 0; | |
390 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
391 | while (current_timeout < target_timeout) { | |
392 | count++; | |
393 | current_timeout <<= 1; | |
394 | if (count >= 0xF) | |
395 | break; | |
396 | } | |
397 | ||
398 | if (count >= 0xF) { | |
399 | printk(KERN_WARNING "%s: Too large timeout requested!\n", | |
400 | mmc_hostname(host->mmc)); | |
401 | count = 0xE; | |
402 | } | |
403 | ||
404 | writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL); | |
d129bceb PO |
405 | |
406 | if (host->flags & SDHCI_USE_DMA) { | |
407 | int count; | |
408 | ||
409 | count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len, | |
410 | (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE); | |
411 | BUG_ON(count != 1); | |
412 | ||
413 | writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS); | |
414 | } else { | |
a3fd4a1b | 415 | host->size = data->blksz * data->blocks; |
d129bceb PO |
416 | |
417 | host->cur_sg = data->sg; | |
418 | host->num_sg = data->sg_len; | |
419 | ||
420 | host->offset = 0; | |
421 | host->remain = host->cur_sg->length; | |
422 | } | |
c7fa9963 | 423 | |
bab76961 PO |
424 | /* We do not handle DMA boundaries, so set it to max (512 KiB) */ |
425 | writew(SDHCI_MAKE_BLKSZ(7, data->blksz), | |
426 | host->ioaddr + SDHCI_BLOCK_SIZE); | |
c7fa9963 PO |
427 | writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT); |
428 | } | |
429 | ||
430 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
431 | struct mmc_data *data) | |
432 | { | |
433 | u16 mode; | |
434 | ||
435 | WARN_ON(host->data); | |
436 | ||
437 | if (data == NULL) | |
438 | return; | |
439 | ||
440 | mode = SDHCI_TRNS_BLK_CNT_EN; | |
441 | if (data->blocks > 1) | |
442 | mode |= SDHCI_TRNS_MULTI; | |
443 | if (data->flags & MMC_DATA_READ) | |
444 | mode |= SDHCI_TRNS_READ; | |
445 | if (host->flags & SDHCI_USE_DMA) | |
446 | mode |= SDHCI_TRNS_DMA; | |
447 | ||
448 | writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE); | |
d129bceb PO |
449 | } |
450 | ||
451 | static void sdhci_finish_data(struct sdhci_host *host) | |
452 | { | |
453 | struct mmc_data *data; | |
d129bceb PO |
454 | u16 blocks; |
455 | ||
456 | BUG_ON(!host->data); | |
457 | ||
458 | data = host->data; | |
459 | host->data = NULL; | |
460 | ||
461 | if (host->flags & SDHCI_USE_DMA) { | |
462 | pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len, | |
463 | (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE); | |
d129bceb PO |
464 | } |
465 | ||
466 | /* | |
467 | * Controller doesn't count down when in single block mode. | |
468 | */ | |
469 | if ((data->blocks == 1) && (data->error == MMC_ERR_NONE)) | |
470 | blocks = 0; | |
471 | else | |
472 | blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT); | |
a3fd4a1b | 473 | data->bytes_xfered = data->blksz * (data->blocks - blocks); |
d129bceb PO |
474 | |
475 | if ((data->error == MMC_ERR_NONE) && blocks) { | |
476 | printk(KERN_ERR "%s: Controller signalled completion even " | |
477 | "though there were blocks left. Please report this " | |
478 | "to " BUGMAIL ".\n", mmc_hostname(host->mmc)); | |
479 | data->error = MMC_ERR_FAILED; | |
4cca56c5 | 480 | } else if (host->size != 0) { |
d129bceb PO |
481 | printk(KERN_ERR "%s: %d bytes were left untransferred. " |
482 | "Please report this to " BUGMAIL ".\n", | |
483 | mmc_hostname(host->mmc), host->size); | |
484 | data->error = MMC_ERR_FAILED; | |
485 | } | |
486 | ||
487 | DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered); | |
488 | ||
489 | if (data->stop) { | |
490 | /* | |
491 | * The controller needs a reset of internal state machines | |
492 | * upon error conditions. | |
493 | */ | |
494 | if (data->error != MMC_ERR_NONE) { | |
495 | sdhci_reset(host, SDHCI_RESET_CMD); | |
496 | sdhci_reset(host, SDHCI_RESET_DATA); | |
497 | } | |
498 | ||
499 | sdhci_send_command(host, data->stop); | |
500 | } else | |
501 | tasklet_schedule(&host->finish_tasklet); | |
502 | } | |
503 | ||
504 | static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) | |
505 | { | |
506 | int flags; | |
fd2208d7 | 507 | u32 mask; |
7cb2c76f | 508 | unsigned long timeout; |
d129bceb PO |
509 | |
510 | WARN_ON(host->cmd); | |
511 | ||
512 | DBG("Sending cmd (%x)\n", cmd->opcode); | |
513 | ||
514 | /* Wait max 10 ms */ | |
7cb2c76f | 515 | timeout = 10; |
fd2208d7 PO |
516 | |
517 | mask = SDHCI_CMD_INHIBIT; | |
518 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
519 | mask |= SDHCI_DATA_INHIBIT; | |
520 | ||
521 | /* We shouldn't wait for data inihibit for stop commands, even | |
522 | though they might use busy signaling */ | |
523 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
524 | mask &= ~SDHCI_DATA_INHIBIT; | |
525 | ||
526 | while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) { | |
7cb2c76f | 527 | if (timeout == 0) { |
d129bceb | 528 | printk(KERN_ERR "%s: Controller never released " |
fd2208d7 | 529 | "inhibit bit(s). Please report this to " |
d129bceb PO |
530 | BUGMAIL ".\n", mmc_hostname(host->mmc)); |
531 | sdhci_dumpregs(host); | |
532 | cmd->error = MMC_ERR_FAILED; | |
533 | tasklet_schedule(&host->finish_tasklet); | |
534 | return; | |
535 | } | |
7cb2c76f PO |
536 | timeout--; |
537 | mdelay(1); | |
538 | } | |
d129bceb PO |
539 | |
540 | mod_timer(&host->timer, jiffies + 10 * HZ); | |
541 | ||
542 | host->cmd = cmd; | |
543 | ||
544 | sdhci_prepare_data(host, cmd->data); | |
545 | ||
546 | writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT); | |
547 | ||
c7fa9963 PO |
548 | sdhci_set_transfer_mode(host, cmd->data); |
549 | ||
d129bceb PO |
550 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
551 | printk(KERN_ERR "%s: Unsupported response type! " | |
552 | "Please report this to " BUGMAIL ".\n", | |
553 | mmc_hostname(host->mmc)); | |
554 | cmd->error = MMC_ERR_INVALID; | |
555 | tasklet_schedule(&host->finish_tasklet); | |
556 | return; | |
557 | } | |
558 | ||
559 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
560 | flags = SDHCI_CMD_RESP_NONE; | |
561 | else if (cmd->flags & MMC_RSP_136) | |
562 | flags = SDHCI_CMD_RESP_LONG; | |
563 | else if (cmd->flags & MMC_RSP_BUSY) | |
564 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
565 | else | |
566 | flags = SDHCI_CMD_RESP_SHORT; | |
567 | ||
568 | if (cmd->flags & MMC_RSP_CRC) | |
569 | flags |= SDHCI_CMD_CRC; | |
570 | if (cmd->flags & MMC_RSP_OPCODE) | |
571 | flags |= SDHCI_CMD_INDEX; | |
572 | if (cmd->data) | |
573 | flags |= SDHCI_CMD_DATA; | |
574 | ||
fb61e289 | 575 | writew(SDHCI_MAKE_CMD(cmd->opcode, flags), |
d129bceb PO |
576 | host->ioaddr + SDHCI_COMMAND); |
577 | } | |
578 | ||
579 | static void sdhci_finish_command(struct sdhci_host *host) | |
580 | { | |
581 | int i; | |
582 | ||
583 | BUG_ON(host->cmd == NULL); | |
584 | ||
585 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
586 | if (host->cmd->flags & MMC_RSP_136) { | |
587 | /* CRC is stripped so we need to do some shifting. */ | |
588 | for (i = 0;i < 4;i++) { | |
589 | host->cmd->resp[i] = readl(host->ioaddr + | |
590 | SDHCI_RESPONSE + (3-i)*4) << 8; | |
591 | if (i != 3) | |
592 | host->cmd->resp[i] |= | |
593 | readb(host->ioaddr + | |
594 | SDHCI_RESPONSE + (3-i)*4-1); | |
595 | } | |
596 | } else { | |
597 | host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE); | |
598 | } | |
599 | } | |
600 | ||
601 | host->cmd->error = MMC_ERR_NONE; | |
602 | ||
603 | DBG("Ending cmd (%x)\n", host->cmd->opcode); | |
604 | ||
3192a28f | 605 | if (host->cmd->data) |
d129bceb | 606 | host->data = host->cmd->data; |
3192a28f | 607 | else |
d129bceb PO |
608 | tasklet_schedule(&host->finish_tasklet); |
609 | ||
610 | host->cmd = NULL; | |
611 | } | |
612 | ||
613 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | |
614 | { | |
615 | int div; | |
077df884 | 616 | u8 ctrl; |
d129bceb | 617 | u16 clk; |
7cb2c76f | 618 | unsigned long timeout; |
d129bceb PO |
619 | |
620 | if (clock == host->clock) | |
621 | return; | |
622 | ||
623 | writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
624 | ||
077df884 PO |
625 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); |
626 | if (clock > 25000000) | |
627 | ctrl |= SDHCI_CTRL_HISPD; | |
628 | else | |
629 | ctrl &= ~SDHCI_CTRL_HISPD; | |
630 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
631 | ||
d129bceb PO |
632 | if (clock == 0) |
633 | goto out; | |
634 | ||
635 | for (div = 1;div < 256;div *= 2) { | |
636 | if ((host->max_clk / div) <= clock) | |
637 | break; | |
638 | } | |
639 | div >>= 1; | |
640 | ||
641 | clk = div << SDHCI_DIVIDER_SHIFT; | |
642 | clk |= SDHCI_CLOCK_INT_EN; | |
643 | writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
644 | ||
645 | /* Wait max 10 ms */ | |
7cb2c76f PO |
646 | timeout = 10; |
647 | while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL)) | |
648 | & SDHCI_CLOCK_INT_STABLE)) { | |
649 | if (timeout == 0) { | |
d129bceb PO |
650 | printk(KERN_ERR "%s: Internal clock never stabilised. " |
651 | "Please report this to " BUGMAIL ".\n", | |
652 | mmc_hostname(host->mmc)); | |
653 | sdhci_dumpregs(host); | |
654 | return; | |
655 | } | |
7cb2c76f PO |
656 | timeout--; |
657 | mdelay(1); | |
658 | } | |
d129bceb PO |
659 | |
660 | clk |= SDHCI_CLOCK_CARD_EN; | |
661 | writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
662 | ||
663 | out: | |
664 | host->clock = clock; | |
665 | } | |
666 | ||
146ad66e PO |
667 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
668 | { | |
669 | u8 pwr; | |
670 | ||
671 | if (host->power == power) | |
672 | return; | |
673 | ||
9e9dc5f2 DS |
674 | if (power == (unsigned short)-1) { |
675 | writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); | |
146ad66e | 676 | goto out; |
9e9dc5f2 DS |
677 | } |
678 | ||
679 | /* | |
680 | * Spec says that we should clear the power reg before setting | |
681 | * a new value. Some controllers don't seem to like this though. | |
682 | */ | |
683 | if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) | |
684 | writeb(0, host->ioaddr + SDHCI_POWER_CONTROL); | |
146ad66e PO |
685 | |
686 | pwr = SDHCI_POWER_ON; | |
687 | ||
688 | switch (power) { | |
689 | case MMC_VDD_170: | |
690 | case MMC_VDD_180: | |
691 | case MMC_VDD_190: | |
692 | pwr |= SDHCI_POWER_180; | |
693 | break; | |
694 | case MMC_VDD_290: | |
695 | case MMC_VDD_300: | |
696 | case MMC_VDD_310: | |
697 | pwr |= SDHCI_POWER_300; | |
698 | break; | |
699 | case MMC_VDD_320: | |
700 | case MMC_VDD_330: | |
701 | case MMC_VDD_340: | |
702 | pwr |= SDHCI_POWER_330; | |
703 | break; | |
704 | default: | |
705 | BUG(); | |
706 | } | |
707 | ||
708 | writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL); | |
709 | ||
710 | out: | |
711 | host->power = power; | |
712 | } | |
713 | ||
d129bceb PO |
714 | /*****************************************************************************\ |
715 | * * | |
716 | * MMC callbacks * | |
717 | * * | |
718 | \*****************************************************************************/ | |
719 | ||
720 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
721 | { | |
722 | struct sdhci_host *host; | |
723 | unsigned long flags; | |
724 | ||
725 | host = mmc_priv(mmc); | |
726 | ||
727 | spin_lock_irqsave(&host->lock, flags); | |
728 | ||
729 | WARN_ON(host->mrq != NULL); | |
730 | ||
731 | sdhci_activate_led(host); | |
732 | ||
733 | host->mrq = mrq; | |
734 | ||
735 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { | |
736 | host->mrq->cmd->error = MMC_ERR_TIMEOUT; | |
737 | tasklet_schedule(&host->finish_tasklet); | |
738 | } else | |
739 | sdhci_send_command(host, mrq->cmd); | |
740 | ||
5f25a66f | 741 | mmiowb(); |
d129bceb PO |
742 | spin_unlock_irqrestore(&host->lock, flags); |
743 | } | |
744 | ||
745 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
746 | { | |
747 | struct sdhci_host *host; | |
748 | unsigned long flags; | |
749 | u8 ctrl; | |
750 | ||
751 | host = mmc_priv(mmc); | |
752 | ||
753 | spin_lock_irqsave(&host->lock, flags); | |
754 | ||
d129bceb PO |
755 | /* |
756 | * Reset the chip on each power off. | |
757 | * Should clear out any weird states. | |
758 | */ | |
759 | if (ios->power_mode == MMC_POWER_OFF) { | |
760 | writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE); | |
d129bceb | 761 | sdhci_init(host); |
d129bceb PO |
762 | } |
763 | ||
764 | sdhci_set_clock(host, ios->clock); | |
765 | ||
766 | if (ios->power_mode == MMC_POWER_OFF) | |
146ad66e | 767 | sdhci_set_power(host, -1); |
d129bceb | 768 | else |
146ad66e | 769 | sdhci_set_power(host, ios->vdd); |
d129bceb PO |
770 | |
771 | ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL); | |
772 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
773 | ctrl |= SDHCI_CTRL_4BITBUS; | |
774 | else | |
775 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
776 | writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); | |
777 | ||
5f25a66f | 778 | mmiowb(); |
d129bceb PO |
779 | spin_unlock_irqrestore(&host->lock, flags); |
780 | } | |
781 | ||
782 | static int sdhci_get_ro(struct mmc_host *mmc) | |
783 | { | |
784 | struct sdhci_host *host; | |
785 | unsigned long flags; | |
786 | int present; | |
787 | ||
788 | host = mmc_priv(mmc); | |
789 | ||
790 | spin_lock_irqsave(&host->lock, flags); | |
791 | ||
792 | present = readl(host->ioaddr + SDHCI_PRESENT_STATE); | |
793 | ||
794 | spin_unlock_irqrestore(&host->lock, flags); | |
795 | ||
796 | return !(present & SDHCI_WRITE_PROTECT); | |
797 | } | |
798 | ||
ab7aefd0 | 799 | static const struct mmc_host_ops sdhci_ops = { |
d129bceb PO |
800 | .request = sdhci_request, |
801 | .set_ios = sdhci_set_ios, | |
802 | .get_ro = sdhci_get_ro, | |
803 | }; | |
804 | ||
805 | /*****************************************************************************\ | |
806 | * * | |
807 | * Tasklets * | |
808 | * * | |
809 | \*****************************************************************************/ | |
810 | ||
811 | static void sdhci_tasklet_card(unsigned long param) | |
812 | { | |
813 | struct sdhci_host *host; | |
814 | unsigned long flags; | |
815 | ||
816 | host = (struct sdhci_host*)param; | |
817 | ||
818 | spin_lock_irqsave(&host->lock, flags); | |
819 | ||
820 | if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { | |
821 | if (host->mrq) { | |
822 | printk(KERN_ERR "%s: Card removed during transfer!\n", | |
823 | mmc_hostname(host->mmc)); | |
824 | printk(KERN_ERR "%s: Resetting controller.\n", | |
825 | mmc_hostname(host->mmc)); | |
826 | ||
827 | sdhci_reset(host, SDHCI_RESET_CMD); | |
828 | sdhci_reset(host, SDHCI_RESET_DATA); | |
829 | ||
830 | host->mrq->cmd->error = MMC_ERR_FAILED; | |
831 | tasklet_schedule(&host->finish_tasklet); | |
832 | } | |
833 | } | |
834 | ||
835 | spin_unlock_irqrestore(&host->lock, flags); | |
836 | ||
837 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
838 | } | |
839 | ||
840 | static void sdhci_tasklet_finish(unsigned long param) | |
841 | { | |
842 | struct sdhci_host *host; | |
843 | unsigned long flags; | |
844 | struct mmc_request *mrq; | |
845 | ||
846 | host = (struct sdhci_host*)param; | |
847 | ||
848 | spin_lock_irqsave(&host->lock, flags); | |
849 | ||
850 | del_timer(&host->timer); | |
851 | ||
852 | mrq = host->mrq; | |
853 | ||
854 | DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode); | |
855 | ||
856 | /* | |
857 | * The controller needs a reset of internal state machines | |
858 | * upon error conditions. | |
859 | */ | |
860 | if ((mrq->cmd->error != MMC_ERR_NONE) || | |
861 | (mrq->data && ((mrq->data->error != MMC_ERR_NONE) || | |
862 | (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) { | |
645289dc PO |
863 | |
864 | /* Some controllers need this kick or reset won't work here */ | |
865 | if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { | |
866 | unsigned int clock; | |
867 | ||
868 | /* This is to force an update */ | |
869 | clock = host->clock; | |
870 | host->clock = 0; | |
871 | sdhci_set_clock(host, clock); | |
872 | } | |
873 | ||
874 | /* Spec says we should do both at the same time, but Ricoh | |
875 | controllers do not like that. */ | |
d129bceb PO |
876 | sdhci_reset(host, SDHCI_RESET_CMD); |
877 | sdhci_reset(host, SDHCI_RESET_DATA); | |
878 | } | |
879 | ||
880 | host->mrq = NULL; | |
881 | host->cmd = NULL; | |
882 | host->data = NULL; | |
883 | ||
884 | sdhci_deactivate_led(host); | |
885 | ||
5f25a66f | 886 | mmiowb(); |
d129bceb PO |
887 | spin_unlock_irqrestore(&host->lock, flags); |
888 | ||
889 | mmc_request_done(host->mmc, mrq); | |
890 | } | |
891 | ||
892 | static void sdhci_timeout_timer(unsigned long data) | |
893 | { | |
894 | struct sdhci_host *host; | |
895 | unsigned long flags; | |
896 | ||
897 | host = (struct sdhci_host*)data; | |
898 | ||
899 | spin_lock_irqsave(&host->lock, flags); | |
900 | ||
901 | if (host->mrq) { | |
902 | printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. " | |
903 | "Please report this to " BUGMAIL ".\n", | |
904 | mmc_hostname(host->mmc)); | |
905 | sdhci_dumpregs(host); | |
906 | ||
907 | if (host->data) { | |
908 | host->data->error = MMC_ERR_TIMEOUT; | |
909 | sdhci_finish_data(host); | |
910 | } else { | |
911 | if (host->cmd) | |
912 | host->cmd->error = MMC_ERR_TIMEOUT; | |
913 | else | |
914 | host->mrq->cmd->error = MMC_ERR_TIMEOUT; | |
915 | ||
916 | tasklet_schedule(&host->finish_tasklet); | |
917 | } | |
918 | } | |
919 | ||
5f25a66f | 920 | mmiowb(); |
d129bceb PO |
921 | spin_unlock_irqrestore(&host->lock, flags); |
922 | } | |
923 | ||
924 | /*****************************************************************************\ | |
925 | * * | |
926 | * Interrupt handling * | |
927 | * * | |
928 | \*****************************************************************************/ | |
929 | ||
930 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
931 | { | |
932 | BUG_ON(intmask == 0); | |
933 | ||
934 | if (!host->cmd) { | |
935 | printk(KERN_ERR "%s: Got command interrupt even though no " | |
936 | "command operation was in progress.\n", | |
937 | mmc_hostname(host->mmc)); | |
938 | printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n", | |
939 | mmc_hostname(host->mmc)); | |
940 | sdhci_dumpregs(host); | |
941 | return; | |
942 | } | |
943 | ||
944 | if (intmask & SDHCI_INT_RESPONSE) | |
945 | sdhci_finish_command(host); | |
946 | else { | |
947 | if (intmask & SDHCI_INT_TIMEOUT) | |
948 | host->cmd->error = MMC_ERR_TIMEOUT; | |
949 | else if (intmask & SDHCI_INT_CRC) | |
950 | host->cmd->error = MMC_ERR_BADCRC; | |
951 | else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) | |
952 | host->cmd->error = MMC_ERR_FAILED; | |
953 | else | |
954 | host->cmd->error = MMC_ERR_INVALID; | |
955 | ||
956 | tasklet_schedule(&host->finish_tasklet); | |
957 | } | |
958 | } | |
959 | ||
960 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) | |
961 | { | |
962 | BUG_ON(intmask == 0); | |
963 | ||
964 | if (!host->data) { | |
965 | /* | |
966 | * A data end interrupt is sent together with the response | |
967 | * for the stop command. | |
968 | */ | |
969 | if (intmask & SDHCI_INT_DATA_END) | |
970 | return; | |
971 | ||
972 | printk(KERN_ERR "%s: Got data interrupt even though no " | |
973 | "data operation was in progress.\n", | |
974 | mmc_hostname(host->mmc)); | |
975 | printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n", | |
976 | mmc_hostname(host->mmc)); | |
977 | sdhci_dumpregs(host); | |
978 | ||
979 | return; | |
980 | } | |
981 | ||
982 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
983 | host->data->error = MMC_ERR_TIMEOUT; | |
984 | else if (intmask & SDHCI_INT_DATA_CRC) | |
985 | host->data->error = MMC_ERR_BADCRC; | |
986 | else if (intmask & SDHCI_INT_DATA_END_BIT) | |
987 | host->data->error = MMC_ERR_FAILED; | |
988 | ||
989 | if (host->data->error != MMC_ERR_NONE) | |
990 | sdhci_finish_data(host); | |
991 | else { | |
a406f5a3 | 992 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
993 | sdhci_transfer_pio(host); |
994 | ||
995 | if (intmask & SDHCI_INT_DATA_END) | |
996 | sdhci_finish_data(host); | |
997 | } | |
998 | } | |
999 | ||
7d12e780 | 1000 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb PO |
1001 | { |
1002 | irqreturn_t result; | |
1003 | struct sdhci_host* host = dev_id; | |
1004 | u32 intmask; | |
1005 | ||
1006 | spin_lock(&host->lock); | |
1007 | ||
1008 | intmask = readl(host->ioaddr + SDHCI_INT_STATUS); | |
1009 | ||
1010 | if (!intmask) { | |
1011 | result = IRQ_NONE; | |
1012 | goto out; | |
1013 | } | |
1014 | ||
1015 | DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask); | |
1016 | ||
3192a28f PO |
1017 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
1018 | writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE), | |
1019 | host->ioaddr + SDHCI_INT_STATUS); | |
d129bceb | 1020 | tasklet_schedule(&host->card_tasklet); |
3192a28f | 1021 | } |
d129bceb | 1022 | |
3192a28f | 1023 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
d129bceb | 1024 | |
3192a28f | 1025 | if (intmask & SDHCI_INT_CMD_MASK) { |
d129bceb PO |
1026 | writel(intmask & SDHCI_INT_CMD_MASK, |
1027 | host->ioaddr + SDHCI_INT_STATUS); | |
3192a28f | 1028 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
d129bceb PO |
1029 | } |
1030 | ||
1031 | if (intmask & SDHCI_INT_DATA_MASK) { | |
d129bceb PO |
1032 | writel(intmask & SDHCI_INT_DATA_MASK, |
1033 | host->ioaddr + SDHCI_INT_STATUS); | |
3192a28f | 1034 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
d129bceb PO |
1035 | } |
1036 | ||
1037 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | |
1038 | ||
d129bceb | 1039 | if (intmask & SDHCI_INT_BUS_POWER) { |
3192a28f | 1040 | printk(KERN_ERR "%s: Card is consuming too much power!\n", |
d129bceb | 1041 | mmc_hostname(host->mmc)); |
3192a28f | 1042 | writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS); |
d129bceb PO |
1043 | } |
1044 | ||
3192a28f PO |
1045 | intmask &= SDHCI_INT_BUS_POWER; |
1046 | ||
1047 | if (intmask) { | |
1048 | printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please " | |
d129bceb | 1049 | "report this to " BUGMAIL ".\n", |
3192a28f | 1050 | mmc_hostname(host->mmc), intmask); |
d129bceb PO |
1051 | sdhci_dumpregs(host); |
1052 | ||
d129bceb | 1053 | writel(intmask, host->ioaddr + SDHCI_INT_STATUS); |
3192a28f | 1054 | } |
d129bceb PO |
1055 | |
1056 | result = IRQ_HANDLED; | |
1057 | ||
5f25a66f | 1058 | mmiowb(); |
d129bceb PO |
1059 | out: |
1060 | spin_unlock(&host->lock); | |
1061 | ||
1062 | return result; | |
1063 | } | |
1064 | ||
1065 | /*****************************************************************************\ | |
1066 | * * | |
1067 | * Suspend/resume * | |
1068 | * * | |
1069 | \*****************************************************************************/ | |
1070 | ||
1071 | #ifdef CONFIG_PM | |
1072 | ||
1073 | static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state) | |
1074 | { | |
1075 | struct sdhci_chip *chip; | |
1076 | int i, ret; | |
1077 | ||
1078 | chip = pci_get_drvdata(pdev); | |
1079 | if (!chip) | |
1080 | return 0; | |
1081 | ||
1082 | DBG("Suspending...\n"); | |
1083 | ||
1084 | for (i = 0;i < chip->num_slots;i++) { | |
1085 | if (!chip->hosts[i]) | |
1086 | continue; | |
1087 | ret = mmc_suspend_host(chip->hosts[i]->mmc, state); | |
1088 | if (ret) { | |
1089 | for (i--;i >= 0;i--) | |
1090 | mmc_resume_host(chip->hosts[i]->mmc); | |
1091 | return ret; | |
1092 | } | |
1093 | } | |
1094 | ||
1095 | pci_save_state(pdev); | |
1096 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | |
1097 | pci_disable_device(pdev); | |
1098 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1099 | ||
1100 | return 0; | |
1101 | } | |
1102 | ||
1103 | static int sdhci_resume (struct pci_dev *pdev) | |
1104 | { | |
1105 | struct sdhci_chip *chip; | |
1106 | int i, ret; | |
1107 | ||
1108 | chip = pci_get_drvdata(pdev); | |
1109 | if (!chip) | |
1110 | return 0; | |
1111 | ||
1112 | DBG("Resuming...\n"); | |
1113 | ||
1114 | pci_set_power_state(pdev, PCI_D0); | |
1115 | pci_restore_state(pdev); | |
df1c4b7b PO |
1116 | ret = pci_enable_device(pdev); |
1117 | if (ret) | |
1118 | return ret; | |
d129bceb PO |
1119 | |
1120 | for (i = 0;i < chip->num_slots;i++) { | |
1121 | if (!chip->hosts[i]) | |
1122 | continue; | |
1123 | if (chip->hosts[i]->flags & SDHCI_USE_DMA) | |
1124 | pci_set_master(pdev); | |
1125 | sdhci_init(chip->hosts[i]); | |
5f25a66f | 1126 | mmiowb(); |
d129bceb PO |
1127 | ret = mmc_resume_host(chip->hosts[i]->mmc); |
1128 | if (ret) | |
1129 | return ret; | |
1130 | } | |
1131 | ||
1132 | return 0; | |
1133 | } | |
1134 | ||
1135 | #else /* CONFIG_PM */ | |
1136 | ||
1137 | #define sdhci_suspend NULL | |
1138 | #define sdhci_resume NULL | |
1139 | ||
1140 | #endif /* CONFIG_PM */ | |
1141 | ||
1142 | /*****************************************************************************\ | |
1143 | * * | |
1144 | * Device probing/removal * | |
1145 | * * | |
1146 | \*****************************************************************************/ | |
1147 | ||
1148 | static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot) | |
1149 | { | |
1150 | int ret; | |
4a965505 | 1151 | unsigned int version; |
d129bceb PO |
1152 | struct sdhci_chip *chip; |
1153 | struct mmc_host *mmc; | |
1154 | struct sdhci_host *host; | |
1155 | ||
1156 | u8 first_bar; | |
1157 | unsigned int caps; | |
1158 | ||
1159 | chip = pci_get_drvdata(pdev); | |
1160 | BUG_ON(!chip); | |
1161 | ||
1162 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); | |
1163 | if (ret) | |
1164 | return ret; | |
1165 | ||
1166 | first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; | |
1167 | ||
1168 | if (first_bar > 5) { | |
1169 | printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n"); | |
1170 | return -ENODEV; | |
1171 | } | |
1172 | ||
1173 | if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) { | |
1174 | printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n"); | |
1175 | return -ENODEV; | |
1176 | } | |
1177 | ||
1178 | if (pci_resource_len(pdev, first_bar + slot) != 0x100) { | |
a98087cf PO |
1179 | printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. " |
1180 | "You may experience problems.\n"); | |
d129bceb PO |
1181 | } |
1182 | ||
67435274 PO |
1183 | if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { |
1184 | printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n"); | |
1185 | return -ENODEV; | |
1186 | } | |
1187 | ||
1188 | if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { | |
1189 | printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n"); | |
1190 | return -ENODEV; | |
1191 | } | |
1192 | ||
d129bceb PO |
1193 | mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev); |
1194 | if (!mmc) | |
1195 | return -ENOMEM; | |
1196 | ||
1197 | host = mmc_priv(mmc); | |
1198 | host->mmc = mmc; | |
1199 | ||
8a4da143 PO |
1200 | host->chip = chip; |
1201 | chip->hosts[slot] = host; | |
1202 | ||
d129bceb PO |
1203 | host->bar = first_bar + slot; |
1204 | ||
1205 | host->addr = pci_resource_start(pdev, host->bar); | |
1206 | host->irq = pdev->irq; | |
1207 | ||
1208 | DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq); | |
1209 | ||
1210 | snprintf(host->slot_descr, 20, "sdhci:slot%d", slot); | |
1211 | ||
1212 | ret = pci_request_region(pdev, host->bar, host->slot_descr); | |
1213 | if (ret) | |
1214 | goto free; | |
1215 | ||
1216 | host->ioaddr = ioremap_nocache(host->addr, | |
1217 | pci_resource_len(pdev, host->bar)); | |
1218 | if (!host->ioaddr) { | |
1219 | ret = -ENOMEM; | |
1220 | goto release; | |
1221 | } | |
1222 | ||
d96649ed PO |
1223 | sdhci_reset(host, SDHCI_RESET_ALL); |
1224 | ||
4a965505 PO |
1225 | version = readw(host->ioaddr + SDHCI_HOST_VERSION); |
1226 | version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; | |
1227 | if (version != 0) { | |
1228 | printk(KERN_ERR "%s: Unknown controller version (%d). " | |
8b1b2185 | 1229 | "You may experience problems.\n", host->slot_descr, |
4a965505 | 1230 | version); |
4a965505 PO |
1231 | } |
1232 | ||
d129bceb PO |
1233 | caps = readl(host->ioaddr + SDHCI_CAPABILITIES); |
1234 | ||
67435274 PO |
1235 | if (debug_nodma) |
1236 | DBG("DMA forced off\n"); | |
1237 | else if (debug_forcedma) { | |
1238 | DBG("DMA forced on\n"); | |
1239 | host->flags |= SDHCI_USE_DMA; | |
98608076 PO |
1240 | } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA) |
1241 | host->flags |= SDHCI_USE_DMA; | |
1242 | else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) | |
67435274 PO |
1243 | DBG("Controller doesn't have DMA interface\n"); |
1244 | else if (!(caps & SDHCI_CAN_DO_DMA)) | |
1245 | DBG("Controller doesn't have DMA capability\n"); | |
1246 | else | |
d129bceb PO |
1247 | host->flags |= SDHCI_USE_DMA; |
1248 | ||
1249 | if (host->flags & SDHCI_USE_DMA) { | |
1250 | if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { | |
1251 | printk(KERN_WARNING "%s: No suitable DMA available. " | |
1252 | "Falling back to PIO.\n", host->slot_descr); | |
1253 | host->flags &= ~SDHCI_USE_DMA; | |
1254 | } | |
1255 | } | |
1256 | ||
1257 | if (host->flags & SDHCI_USE_DMA) | |
1258 | pci_set_master(pdev); | |
1259 | else /* XXX: Hack to get MMC layer to avoid highmem */ | |
1260 | pdev->dma_mask = 0; | |
1261 | ||
8ef1a143 PO |
1262 | host->max_clk = |
1263 | (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; | |
1264 | if (host->max_clk == 0) { | |
1265 | printk(KERN_ERR "%s: Hardware doesn't specify base clock " | |
1266 | "frequency.\n", host->slot_descr); | |
1267 | ret = -ENODEV; | |
1268 | goto unmap; | |
1269 | } | |
d129bceb PO |
1270 | host->max_clk *= 1000000; |
1271 | ||
1c8cde92 PO |
1272 | host->timeout_clk = |
1273 | (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
1274 | if (host->timeout_clk == 0) { | |
1275 | printk(KERN_ERR "%s: Hardware doesn't specify timeout clock " | |
1276 | "frequency.\n", host->slot_descr); | |
1277 | ret = -ENODEV; | |
1278 | goto unmap; | |
1279 | } | |
1280 | if (caps & SDHCI_TIMEOUT_CLK_UNIT) | |
1281 | host->timeout_clk *= 1000; | |
d129bceb PO |
1282 | |
1283 | /* | |
1284 | * Set host parameters. | |
1285 | */ | |
1286 | mmc->ops = &sdhci_ops; | |
1287 | mmc->f_min = host->max_clk / 256; | |
1288 | mmc->f_max = host->max_clk; | |
42431acb | 1289 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK; |
d129bceb | 1290 | |
146ad66e PO |
1291 | mmc->ocr_avail = 0; |
1292 | if (caps & SDHCI_CAN_VDD_330) | |
1293 | mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34; | |
c70840e8 | 1294 | if (caps & SDHCI_CAN_VDD_300) |
146ad66e | 1295 | mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31; |
c70840e8 | 1296 | if (caps & SDHCI_CAN_VDD_180) |
146ad66e PO |
1297 | mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19; |
1298 | ||
077df884 PO |
1299 | if ((host->max_clk > 25000000) && !(caps & SDHCI_CAN_DO_HISPD)) { |
1300 | printk(KERN_ERR "%s: Controller reports > 25 MHz base clock," | |
1301 | " but no high speed support.\n", | |
1302 | host->slot_descr); | |
1303 | mmc->f_max = 25000000; | |
1304 | } | |
1305 | ||
146ad66e PO |
1306 | if (mmc->ocr_avail == 0) { |
1307 | printk(KERN_ERR "%s: Hardware doesn't report any " | |
1308 | "support voltages.\n", host->slot_descr); | |
1309 | ret = -ENODEV; | |
1310 | goto unmap; | |
1311 | } | |
1312 | ||
d129bceb PO |
1313 | spin_lock_init(&host->lock); |
1314 | ||
1315 | /* | |
1316 | * Maximum number of segments. Hardware cannot do scatter lists. | |
1317 | */ | |
1318 | if (host->flags & SDHCI_USE_DMA) | |
1319 | mmc->max_hw_segs = 1; | |
1320 | else | |
1321 | mmc->max_hw_segs = 16; | |
1322 | mmc->max_phys_segs = 16; | |
1323 | ||
1324 | /* | |
bab76961 | 1325 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 1326 | * size (512KiB). |
d129bceb | 1327 | */ |
55db890a | 1328 | mmc->max_req_size = 524288; |
d129bceb PO |
1329 | |
1330 | /* | |
1331 | * Maximum segment size. Could be one segment with the maximum number | |
55db890a | 1332 | * of bytes. |
d129bceb | 1333 | */ |
55db890a | 1334 | mmc->max_seg_size = mmc->max_req_size; |
d129bceb | 1335 | |
fe4a3c7a PO |
1336 | /* |
1337 | * Maximum block size. This varies from controller to controller and | |
1338 | * is specified in the capabilities register. | |
1339 | */ | |
1340 | mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT; | |
1341 | if (mmc->max_blk_size >= 3) { | |
1342 | printk(KERN_ERR "%s: Invalid maximum block size.\n", | |
1343 | host->slot_descr); | |
1344 | ret = -ENODEV; | |
1345 | goto unmap; | |
1346 | } | |
1347 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
1348 | ||
55db890a PO |
1349 | /* |
1350 | * Maximum block count. | |
1351 | */ | |
1352 | mmc->max_blk_count = 65535; | |
1353 | ||
d129bceb PO |
1354 | /* |
1355 | * Init tasklets. | |
1356 | */ | |
1357 | tasklet_init(&host->card_tasklet, | |
1358 | sdhci_tasklet_card, (unsigned long)host); | |
1359 | tasklet_init(&host->finish_tasklet, | |
1360 | sdhci_tasklet_finish, (unsigned long)host); | |
1361 | ||
e4cad1b5 | 1362 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 1363 | |
dace1453 | 1364 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
d129bceb PO |
1365 | host->slot_descr, host); |
1366 | if (ret) | |
8ef1a143 | 1367 | goto untasklet; |
d129bceb PO |
1368 | |
1369 | sdhci_init(host); | |
1370 | ||
1371 | #ifdef CONFIG_MMC_DEBUG | |
1372 | sdhci_dumpregs(host); | |
1373 | #endif | |
1374 | ||
5f25a66f PO |
1375 | mmiowb(); |
1376 | ||
d129bceb PO |
1377 | mmc_add_host(mmc); |
1378 | ||
1379 | printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc), | |
1380 | host->addr, host->irq, | |
1381 | (host->flags & SDHCI_USE_DMA)?"DMA":"PIO"); | |
1382 | ||
1383 | return 0; | |
1384 | ||
8ef1a143 | 1385 | untasklet: |
d129bceb PO |
1386 | tasklet_kill(&host->card_tasklet); |
1387 | tasklet_kill(&host->finish_tasklet); | |
8ef1a143 | 1388 | unmap: |
d129bceb PO |
1389 | iounmap(host->ioaddr); |
1390 | release: | |
1391 | pci_release_region(pdev, host->bar); | |
1392 | free: | |
1393 | mmc_free_host(mmc); | |
1394 | ||
1395 | return ret; | |
1396 | } | |
1397 | ||
1398 | static void sdhci_remove_slot(struct pci_dev *pdev, int slot) | |
1399 | { | |
1400 | struct sdhci_chip *chip; | |
1401 | struct mmc_host *mmc; | |
1402 | struct sdhci_host *host; | |
1403 | ||
1404 | chip = pci_get_drvdata(pdev); | |
1405 | host = chip->hosts[slot]; | |
1406 | mmc = host->mmc; | |
1407 | ||
1408 | chip->hosts[slot] = NULL; | |
1409 | ||
1410 | mmc_remove_host(mmc); | |
1411 | ||
1412 | sdhci_reset(host, SDHCI_RESET_ALL); | |
1413 | ||
1414 | free_irq(host->irq, host); | |
1415 | ||
1416 | del_timer_sync(&host->timer); | |
1417 | ||
1418 | tasklet_kill(&host->card_tasklet); | |
1419 | tasklet_kill(&host->finish_tasklet); | |
1420 | ||
1421 | iounmap(host->ioaddr); | |
1422 | ||
1423 | pci_release_region(pdev, host->bar); | |
1424 | ||
1425 | mmc_free_host(mmc); | |
1426 | } | |
1427 | ||
1428 | static int __devinit sdhci_probe(struct pci_dev *pdev, | |
1429 | const struct pci_device_id *ent) | |
1430 | { | |
1431 | int ret, i; | |
51f82bc0 | 1432 | u8 slots, rev; |
d129bceb PO |
1433 | struct sdhci_chip *chip; |
1434 | ||
1435 | BUG_ON(pdev == NULL); | |
1436 | BUG_ON(ent == NULL); | |
1437 | ||
51f82bc0 PO |
1438 | pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev); |
1439 | ||
1440 | printk(KERN_INFO DRIVER_NAME | |
1441 | ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n", | |
1442 | pci_name(pdev), (int)pdev->vendor, (int)pdev->device, | |
1443 | (int)rev); | |
d129bceb PO |
1444 | |
1445 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); | |
1446 | if (ret) | |
1447 | return ret; | |
1448 | ||
1449 | slots = PCI_SLOT_INFO_SLOTS(slots) + 1; | |
1450 | DBG("found %d slot(s)\n", slots); | |
1451 | if (slots == 0) | |
1452 | return -ENODEV; | |
1453 | ||
1454 | ret = pci_enable_device(pdev); | |
1455 | if (ret) | |
1456 | return ret; | |
1457 | ||
1458 | chip = kzalloc(sizeof(struct sdhci_chip) + | |
1459 | sizeof(struct sdhci_host*) * slots, GFP_KERNEL); | |
1460 | if (!chip) { | |
1461 | ret = -ENOMEM; | |
1462 | goto err; | |
1463 | } | |
1464 | ||
1465 | chip->pdev = pdev; | |
df673b22 PO |
1466 | chip->quirks = ent->driver_data; |
1467 | ||
1468 | if (debug_quirks) | |
1469 | chip->quirks = debug_quirks; | |
d129bceb PO |
1470 | |
1471 | chip->num_slots = slots; | |
1472 | pci_set_drvdata(pdev, chip); | |
1473 | ||
1474 | for (i = 0;i < slots;i++) { | |
1475 | ret = sdhci_probe_slot(pdev, i); | |
1476 | if (ret) { | |
1477 | for (i--;i >= 0;i--) | |
1478 | sdhci_remove_slot(pdev, i); | |
1479 | goto free; | |
1480 | } | |
1481 | } | |
1482 | ||
1483 | return 0; | |
1484 | ||
1485 | free: | |
1486 | pci_set_drvdata(pdev, NULL); | |
1487 | kfree(chip); | |
1488 | ||
1489 | err: | |
1490 | pci_disable_device(pdev); | |
1491 | return ret; | |
1492 | } | |
1493 | ||
1494 | static void __devexit sdhci_remove(struct pci_dev *pdev) | |
1495 | { | |
1496 | int i; | |
1497 | struct sdhci_chip *chip; | |
1498 | ||
1499 | chip = pci_get_drvdata(pdev); | |
1500 | ||
1501 | if (chip) { | |
1502 | for (i = 0;i < chip->num_slots;i++) | |
1503 | sdhci_remove_slot(pdev, i); | |
1504 | ||
1505 | pci_set_drvdata(pdev, NULL); | |
1506 | ||
1507 | kfree(chip); | |
1508 | } | |
1509 | ||
1510 | pci_disable_device(pdev); | |
1511 | } | |
1512 | ||
1513 | static struct pci_driver sdhci_driver = { | |
1514 | .name = DRIVER_NAME, | |
1515 | .id_table = pci_ids, | |
1516 | .probe = sdhci_probe, | |
1517 | .remove = __devexit_p(sdhci_remove), | |
1518 | .suspend = sdhci_suspend, | |
1519 | .resume = sdhci_resume, | |
1520 | }; | |
1521 | ||
1522 | /*****************************************************************************\ | |
1523 | * * | |
1524 | * Driver init/exit * | |
1525 | * * | |
1526 | \*****************************************************************************/ | |
1527 | ||
1528 | static int __init sdhci_drv_init(void) | |
1529 | { | |
1530 | printk(KERN_INFO DRIVER_NAME | |
1531 | ": Secure Digital Host Controller Interface driver, " | |
1532 | DRIVER_VERSION "\n"); | |
1533 | printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); | |
1534 | ||
1535 | return pci_register_driver(&sdhci_driver); | |
1536 | } | |
1537 | ||
1538 | static void __exit sdhci_drv_exit(void) | |
1539 | { | |
1540 | DBG("Exiting\n"); | |
1541 | ||
1542 | pci_unregister_driver(&sdhci_driver); | |
1543 | } | |
1544 | ||
1545 | module_init(sdhci_drv_init); | |
1546 | module_exit(sdhci_drv_exit); | |
1547 | ||
67435274 PO |
1548 | module_param(debug_nodma, uint, 0444); |
1549 | module_param(debug_forcedma, uint, 0444); | |
df673b22 | 1550 | module_param(debug_quirks, uint, 0444); |
67435274 | 1551 | |
d129bceb PO |
1552 | MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>"); |
1553 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver"); | |
1554 | MODULE_VERSION(DRIVER_VERSION); | |
1555 | MODULE_LICENSE("GPL"); | |
67435274 PO |
1556 | |
1557 | MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)"); | |
1558 | MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)"); | |
df673b22 | 1559 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |