Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/mmc/mmci.c - ARM PrimeCell MMCI PL180/1 driver | |
3 | * | |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #include <linux/config.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/highmem.h> | |
20 | #include <linux/mmc/host.h> | |
21 | #include <linux/mmc/protocol.h> | |
22 | ||
23 | #include <asm/io.h> | |
24 | #include <asm/irq.h> | |
25 | #include <asm/scatterlist.h> | |
26 | #include <asm/hardware/amba.h> | |
27 | #include <asm/hardware/clock.h> | |
28 | #include <asm/mach/mmc.h> | |
29 | ||
30 | #include "mmci.h" | |
31 | ||
32 | #define DRIVER_NAME "mmci-pl18x" | |
33 | ||
34 | #ifdef CONFIG_MMC_DEBUG | |
35 | #define DBG(host,fmt,args...) \ | |
36 | pr_debug("%s: %s: " fmt, host->mmc->host_name, __func__ , args) | |
37 | #else | |
38 | #define DBG(host,fmt,args...) do { } while (0) | |
39 | #endif | |
40 | ||
41 | static unsigned int fmax = 515633; | |
42 | ||
43 | static void | |
44 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
45 | { | |
46 | writel(0, host->base + MMCICOMMAND); | |
47 | ||
48 | host->mrq = NULL; | |
49 | host->cmd = NULL; | |
50 | ||
51 | if (mrq->data) | |
52 | mrq->data->bytes_xfered = host->data_xfered; | |
53 | ||
54 | /* | |
55 | * Need to drop the host lock here; mmc_request_done may call | |
56 | * back into the driver... | |
57 | */ | |
58 | spin_unlock(&host->lock); | |
59 | mmc_request_done(host->mmc, mrq); | |
60 | spin_lock(&host->lock); | |
61 | } | |
62 | ||
63 | static void mmci_stop_data(struct mmci_host *host) | |
64 | { | |
65 | writel(0, host->base + MMCIDATACTRL); | |
66 | writel(0, host->base + MMCIMASK1); | |
67 | host->data = NULL; | |
68 | } | |
69 | ||
70 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) | |
71 | { | |
72 | unsigned int datactrl, timeout, irqmask; | |
73 | void __iomem *base; | |
74 | ||
75 | DBG(host, "blksz %04x blks %04x flags %08x\n", | |
76 | 1 << data->blksz_bits, data->blocks, data->flags); | |
77 | ||
78 | host->data = data; | |
79 | host->size = data->blocks << data->blksz_bits; | |
80 | host->data_xfered = 0; | |
81 | ||
82 | mmci_init_sg(host, data); | |
83 | ||
84 | timeout = data->timeout_clks + | |
85 | ((unsigned long long)data->timeout_ns * host->cclk) / | |
86 | 1000000000ULL; | |
87 | ||
88 | base = host->base; | |
89 | writel(timeout, base + MMCIDATATIMER); | |
90 | writel(host->size, base + MMCIDATALENGTH); | |
91 | ||
92 | datactrl = MCI_DPSM_ENABLE | data->blksz_bits << 4; | |
93 | if (data->flags & MMC_DATA_READ) { | |
94 | datactrl |= MCI_DPSM_DIRECTION; | |
95 | irqmask = MCI_RXFIFOHALFFULLMASK; | |
96 | } else { | |
97 | /* | |
98 | * We don't actually need to include "FIFO empty" here | |
99 | * since its implicit in "FIFO half empty". | |
100 | */ | |
101 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
102 | } | |
103 | ||
104 | writel(datactrl, base + MMCIDATACTRL); | |
105 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
106 | writel(irqmask, base + MMCIMASK1); | |
107 | } | |
108 | ||
109 | static void | |
110 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
111 | { | |
112 | void __iomem *base = host->base; | |
113 | ||
114 | DBG(host, "op %02x arg %08x flags %08x\n", | |
115 | cmd->opcode, cmd->arg, cmd->flags); | |
116 | ||
117 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
118 | writel(0, base + MMCICOMMAND); | |
119 | udelay(1); | |
120 | } | |
121 | ||
122 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
123 | switch (cmd->flags & MMC_RSP_MASK) { | |
124 | case MMC_RSP_NONE: | |
125 | default: | |
126 | break; | |
127 | case MMC_RSP_LONG: | |
128 | c |= MCI_CPSM_LONGRSP; | |
129 | case MMC_RSP_SHORT: | |
130 | c |= MCI_CPSM_RESPONSE; | |
131 | break; | |
132 | } | |
133 | if (/*interrupt*/0) | |
134 | c |= MCI_CPSM_INTERRUPT; | |
135 | ||
136 | host->cmd = cmd; | |
137 | ||
138 | writel(cmd->arg, base + MMCIARGUMENT); | |
139 | writel(c, base + MMCICOMMAND); | |
140 | } | |
141 | ||
142 | static void | |
143 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
144 | unsigned int status) | |
145 | { | |
146 | if (status & MCI_DATABLOCKEND) { | |
147 | host->data_xfered += 1 << data->blksz_bits; | |
148 | } | |
149 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
150 | if (status & MCI_DATACRCFAIL) | |
151 | data->error = MMC_ERR_BADCRC; | |
152 | else if (status & MCI_DATATIMEOUT) | |
153 | data->error = MMC_ERR_TIMEOUT; | |
154 | else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) | |
155 | data->error = MMC_ERR_FIFO; | |
156 | status |= MCI_DATAEND; | |
157 | } | |
158 | if (status & MCI_DATAEND) { | |
159 | mmci_stop_data(host); | |
160 | ||
161 | if (!data->stop) { | |
162 | mmci_request_end(host, data->mrq); | |
163 | } else { | |
164 | mmci_start_command(host, data->stop, 0); | |
165 | } | |
166 | } | |
167 | } | |
168 | ||
169 | static void | |
170 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
171 | unsigned int status) | |
172 | { | |
173 | void __iomem *base = host->base; | |
174 | ||
175 | host->cmd = NULL; | |
176 | ||
177 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
178 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
179 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
180 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
181 | ||
182 | if (status & MCI_CMDTIMEOUT) { | |
183 | cmd->error = MMC_ERR_TIMEOUT; | |
184 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { | |
185 | cmd->error = MMC_ERR_BADCRC; | |
186 | } | |
187 | ||
188 | if (!cmd->data || cmd->error != MMC_ERR_NONE) { | |
189 | mmci_request_end(host, cmd->mrq); | |
190 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
191 | mmci_start_data(host, cmd->data); | |
192 | } | |
193 | } | |
194 | ||
195 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
196 | { | |
197 | void __iomem *base = host->base; | |
198 | char *ptr = buffer; | |
199 | u32 status; | |
200 | ||
201 | do { | |
202 | int count = host->size - (readl(base + MMCIFIFOCNT) << 2); | |
203 | ||
204 | if (count > remain) | |
205 | count = remain; | |
206 | ||
207 | if (count <= 0) | |
208 | break; | |
209 | ||
210 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
211 | ||
212 | ptr += count; | |
213 | remain -= count; | |
214 | ||
215 | if (remain == 0) | |
216 | break; | |
217 | ||
218 | status = readl(base + MMCISTATUS); | |
219 | } while (status & MCI_RXDATAAVLBL); | |
220 | ||
221 | return ptr - buffer; | |
222 | } | |
223 | ||
224 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
225 | { | |
226 | void __iomem *base = host->base; | |
227 | char *ptr = buffer; | |
228 | ||
229 | do { | |
230 | unsigned int count, maxcnt; | |
231 | ||
232 | maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE; | |
233 | count = min(remain, maxcnt); | |
234 | ||
235 | writesl(base + MMCIFIFO, ptr, count >> 2); | |
236 | ||
237 | ptr += count; | |
238 | remain -= count; | |
239 | ||
240 | if (remain == 0) | |
241 | break; | |
242 | ||
243 | status = readl(base + MMCISTATUS); | |
244 | } while (status & MCI_TXFIFOHALFEMPTY); | |
245 | ||
246 | return ptr - buffer; | |
247 | } | |
248 | ||
249 | /* | |
250 | * PIO data transfer IRQ handler. | |
251 | */ | |
252 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id, struct pt_regs *regs) | |
253 | { | |
254 | struct mmci_host *host = dev_id; | |
255 | void __iomem *base = host->base; | |
256 | u32 status; | |
257 | ||
258 | status = readl(base + MMCISTATUS); | |
259 | ||
260 | DBG(host, "irq1 %08x\n", status); | |
261 | ||
262 | do { | |
263 | unsigned long flags; | |
264 | unsigned int remain, len; | |
265 | char *buffer; | |
266 | ||
267 | /* | |
268 | * For write, we only need to test the half-empty flag | |
269 | * here - if the FIFO is completely empty, then by | |
270 | * definition it is more than half empty. | |
271 | * | |
272 | * For read, check for data available. | |
273 | */ | |
274 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
275 | break; | |
276 | ||
277 | /* | |
278 | * Map the current scatter buffer. | |
279 | */ | |
280 | buffer = mmci_kmap_atomic(host, &flags) + host->sg_off; | |
281 | remain = host->sg_ptr->length - host->sg_off; | |
282 | ||
283 | len = 0; | |
284 | if (status & MCI_RXACTIVE) | |
285 | len = mmci_pio_read(host, buffer, remain); | |
286 | if (status & MCI_TXACTIVE) | |
287 | len = mmci_pio_write(host, buffer, remain, status); | |
288 | ||
289 | /* | |
290 | * Unmap the buffer. | |
291 | */ | |
292 | mmci_kunmap_atomic(host, &flags); | |
293 | ||
294 | host->sg_off += len; | |
295 | host->size -= len; | |
296 | remain -= len; | |
297 | ||
298 | if (remain) | |
299 | break; | |
300 | ||
301 | if (!mmci_next_sg(host)) | |
302 | break; | |
303 | ||
304 | status = readl(base + MMCISTATUS); | |
305 | } while (1); | |
306 | ||
307 | /* | |
308 | * If we're nearing the end of the read, switch to | |
309 | * "any data available" mode. | |
310 | */ | |
311 | if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE) | |
312 | writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1); | |
313 | ||
314 | /* | |
315 | * If we run out of data, disable the data IRQs; this | |
316 | * prevents a race where the FIFO becomes empty before | |
317 | * the chip itself has disabled the data path, and | |
318 | * stops us racing with our data end IRQ. | |
319 | */ | |
320 | if (host->size == 0) { | |
321 | writel(0, base + MMCIMASK1); | |
322 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); | |
323 | } | |
324 | ||
325 | return IRQ_HANDLED; | |
326 | } | |
327 | ||
328 | /* | |
329 | * Handle completion of command and data transfers. | |
330 | */ | |
331 | static irqreturn_t mmci_irq(int irq, void *dev_id, struct pt_regs *regs) | |
332 | { | |
333 | struct mmci_host *host = dev_id; | |
334 | u32 status; | |
335 | int ret = 0; | |
336 | ||
337 | spin_lock(&host->lock); | |
338 | ||
339 | do { | |
340 | struct mmc_command *cmd; | |
341 | struct mmc_data *data; | |
342 | ||
343 | status = readl(host->base + MMCISTATUS); | |
344 | status &= readl(host->base + MMCIMASK0); | |
345 | writel(status, host->base + MMCICLEAR); | |
346 | ||
347 | DBG(host, "irq0 %08x\n", status); | |
348 | ||
349 | data = host->data; | |
350 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| | |
351 | MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) | |
352 | mmci_data_irq(host, data, status); | |
353 | ||
354 | cmd = host->cmd; | |
355 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
356 | mmci_cmd_irq(host, cmd, status); | |
357 | ||
358 | ret = 1; | |
359 | } while (status); | |
360 | ||
361 | spin_unlock(&host->lock); | |
362 | ||
363 | return IRQ_RETVAL(ret); | |
364 | } | |
365 | ||
366 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
367 | { | |
368 | struct mmci_host *host = mmc_priv(mmc); | |
369 | ||
370 | WARN_ON(host->mrq != NULL); | |
371 | ||
372 | spin_lock_irq(&host->lock); | |
373 | ||
374 | host->mrq = mrq; | |
375 | ||
376 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) | |
377 | mmci_start_data(host, mrq->data); | |
378 | ||
379 | mmci_start_command(host, mrq->cmd, 0); | |
380 | ||
381 | spin_unlock_irq(&host->lock); | |
382 | } | |
383 | ||
384 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
385 | { | |
386 | struct mmci_host *host = mmc_priv(mmc); | |
387 | u32 clk = 0, pwr = 0; | |
388 | ||
389 | DBG(host, "clock %uHz busmode %u powermode %u Vdd %u\n", | |
390 | ios->clock, ios->bus_mode, ios->power_mode, ios->vdd); | |
391 | ||
392 | if (ios->clock) { | |
393 | if (ios->clock >= host->mclk) { | |
394 | clk = MCI_CLK_BYPASS; | |
395 | host->cclk = host->mclk; | |
396 | } else { | |
397 | clk = host->mclk / (2 * ios->clock) - 1; | |
398 | if (clk > 256) | |
399 | clk = 255; | |
400 | host->cclk = host->mclk / (2 * (clk + 1)); | |
401 | } | |
402 | clk |= MCI_CLK_ENABLE; | |
403 | } | |
404 | ||
405 | if (host->plat->translate_vdd) | |
406 | pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd); | |
407 | ||
408 | switch (ios->power_mode) { | |
409 | case MMC_POWER_OFF: | |
410 | break; | |
411 | case MMC_POWER_UP: | |
412 | pwr |= MCI_PWR_UP; | |
413 | break; | |
414 | case MMC_POWER_ON: | |
415 | pwr |= MCI_PWR_ON; | |
416 | break; | |
417 | } | |
418 | ||
419 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
420 | pwr |= MCI_ROD; | |
421 | ||
422 | writel(clk, host->base + MMCICLOCK); | |
423 | ||
424 | if (host->pwr != pwr) { | |
425 | host->pwr = pwr; | |
426 | writel(pwr, host->base + MMCIPOWER); | |
427 | } | |
428 | } | |
429 | ||
430 | static struct mmc_host_ops mmci_ops = { | |
431 | .request = mmci_request, | |
432 | .set_ios = mmci_set_ios, | |
433 | }; | |
434 | ||
435 | static void mmci_check_status(unsigned long data) | |
436 | { | |
437 | struct mmci_host *host = (struct mmci_host *)data; | |
438 | unsigned int status; | |
439 | ||
440 | status = host->plat->status(mmc_dev(host->mmc)); | |
441 | if (status ^ host->oldstat) | |
442 | mmc_detect_change(host->mmc); | |
443 | ||
444 | host->oldstat = status; | |
445 | mod_timer(&host->timer, jiffies + HZ); | |
446 | } | |
447 | ||
448 | static int mmci_probe(struct amba_device *dev, void *id) | |
449 | { | |
450 | struct mmc_platform_data *plat = dev->dev.platform_data; | |
451 | struct mmci_host *host; | |
452 | struct mmc_host *mmc; | |
453 | int ret; | |
454 | ||
455 | /* must have platform data */ | |
456 | if (!plat) { | |
457 | ret = -EINVAL; | |
458 | goto out; | |
459 | } | |
460 | ||
461 | ret = amba_request_regions(dev, DRIVER_NAME); | |
462 | if (ret) | |
463 | goto out; | |
464 | ||
465 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
466 | if (!mmc) { | |
467 | ret = -ENOMEM; | |
468 | goto rel_regions; | |
469 | } | |
470 | ||
471 | host = mmc_priv(mmc); | |
472 | host->clk = clk_get(&dev->dev, "MCLK"); | |
473 | if (IS_ERR(host->clk)) { | |
474 | ret = PTR_ERR(host->clk); | |
475 | host->clk = NULL; | |
476 | goto host_free; | |
477 | } | |
478 | ||
479 | ret = clk_use(host->clk); | |
480 | if (ret) | |
481 | goto clk_free; | |
482 | ||
483 | ret = clk_enable(host->clk); | |
484 | if (ret) | |
485 | goto clk_unuse; | |
486 | ||
487 | host->plat = plat; | |
488 | host->mclk = clk_get_rate(host->clk); | |
489 | host->mmc = mmc; | |
490 | host->base = ioremap(dev->res.start, SZ_4K); | |
491 | if (!host->base) { | |
492 | ret = -ENOMEM; | |
493 | goto clk_disable; | |
494 | } | |
495 | ||
496 | mmc->ops = &mmci_ops; | |
497 | mmc->f_min = (host->mclk + 511) / 512; | |
498 | mmc->f_max = min(host->mclk, fmax); | |
499 | mmc->ocr_avail = plat->ocr_mask; | |
500 | ||
501 | /* | |
502 | * We can do SGIO | |
503 | */ | |
504 | mmc->max_hw_segs = 16; | |
505 | mmc->max_phys_segs = NR_SG; | |
506 | ||
507 | /* | |
508 | * Since we only have a 16-bit data length register, we must | |
509 | * ensure that we don't exceed 2^16-1 bytes in a single request. | |
510 | * Choose 64 (512-byte) sectors as the limit. | |
511 | */ | |
512 | mmc->max_sectors = 64; | |
513 | ||
514 | /* | |
515 | * Set the maximum segment size. Since we aren't doing DMA | |
516 | * (yet) we are only limited by the data length register. | |
517 | */ | |
518 | mmc->max_seg_size = mmc->max_sectors << 9; | |
519 | ||
520 | spin_lock_init(&host->lock); | |
521 | ||
522 | writel(0, host->base + MMCIMASK0); | |
523 | writel(0, host->base + MMCIMASK1); | |
524 | writel(0xfff, host->base + MMCICLEAR); | |
525 | ||
526 | ret = request_irq(dev->irq[0], mmci_irq, SA_SHIRQ, DRIVER_NAME " (cmd)", host); | |
527 | if (ret) | |
528 | goto unmap; | |
529 | ||
530 | ret = request_irq(dev->irq[1], mmci_pio_irq, SA_SHIRQ, DRIVER_NAME " (pio)", host); | |
531 | if (ret) | |
532 | goto irq0_free; | |
533 | ||
534 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
535 | ||
536 | amba_set_drvdata(dev, mmc); | |
537 | ||
538 | mmc_add_host(mmc); | |
539 | ||
540 | printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%08lx irq %d,%d\n", | |
541 | mmc->host_name, amba_rev(dev), amba_config(dev), | |
542 | dev->res.start, dev->irq[0], dev->irq[1]); | |
543 | ||
544 | init_timer(&host->timer); | |
545 | host->timer.data = (unsigned long)host; | |
546 | host->timer.function = mmci_check_status; | |
547 | host->timer.expires = jiffies + HZ; | |
548 | add_timer(&host->timer); | |
549 | ||
550 | return 0; | |
551 | ||
552 | irq0_free: | |
553 | free_irq(dev->irq[0], host); | |
554 | unmap: | |
555 | iounmap(host->base); | |
556 | clk_disable: | |
557 | clk_disable(host->clk); | |
558 | clk_unuse: | |
559 | clk_unuse(host->clk); | |
560 | clk_free: | |
561 | clk_put(host->clk); | |
562 | host_free: | |
563 | mmc_free_host(mmc); | |
564 | rel_regions: | |
565 | amba_release_regions(dev); | |
566 | out: | |
567 | return ret; | |
568 | } | |
569 | ||
570 | static int mmci_remove(struct amba_device *dev) | |
571 | { | |
572 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
573 | ||
574 | amba_set_drvdata(dev, NULL); | |
575 | ||
576 | if (mmc) { | |
577 | struct mmci_host *host = mmc_priv(mmc); | |
578 | ||
579 | del_timer_sync(&host->timer); | |
580 | ||
581 | mmc_remove_host(mmc); | |
582 | ||
583 | writel(0, host->base + MMCIMASK0); | |
584 | writel(0, host->base + MMCIMASK1); | |
585 | ||
586 | writel(0, host->base + MMCICOMMAND); | |
587 | writel(0, host->base + MMCIDATACTRL); | |
588 | ||
589 | free_irq(dev->irq[0], host); | |
590 | free_irq(dev->irq[1], host); | |
591 | ||
592 | iounmap(host->base); | |
593 | clk_disable(host->clk); | |
594 | clk_unuse(host->clk); | |
595 | clk_put(host->clk); | |
596 | ||
597 | mmc_free_host(mmc); | |
598 | ||
599 | amba_release_regions(dev); | |
600 | } | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | #ifdef CONFIG_PM | |
606 | static int mmci_suspend(struct amba_device *dev, u32 state) | |
607 | { | |
608 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
609 | int ret = 0; | |
610 | ||
611 | if (mmc) { | |
612 | struct mmci_host *host = mmc_priv(mmc); | |
613 | ||
614 | ret = mmc_suspend_host(mmc, state); | |
615 | if (ret == 0) | |
616 | writel(0, host->base + MMCIMASK0); | |
617 | } | |
618 | ||
619 | return ret; | |
620 | } | |
621 | ||
622 | static int mmci_resume(struct amba_device *dev) | |
623 | { | |
624 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
625 | int ret = 0; | |
626 | ||
627 | if (mmc) { | |
628 | struct mmci_host *host = mmc_priv(mmc); | |
629 | ||
630 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
631 | ||
632 | ret = mmc_resume_host(mmc); | |
633 | } | |
634 | ||
635 | return ret; | |
636 | } | |
637 | #else | |
638 | #define mmci_suspend NULL | |
639 | #define mmci_resume NULL | |
640 | #endif | |
641 | ||
642 | static struct amba_id mmci_ids[] = { | |
643 | { | |
644 | .id = 0x00041180, | |
645 | .mask = 0x000fffff, | |
646 | }, | |
647 | { | |
648 | .id = 0x00041181, | |
649 | .mask = 0x000fffff, | |
650 | }, | |
651 | { 0, 0 }, | |
652 | }; | |
653 | ||
654 | static struct amba_driver mmci_driver = { | |
655 | .drv = { | |
656 | .name = DRIVER_NAME, | |
657 | }, | |
658 | .probe = mmci_probe, | |
659 | .remove = mmci_remove, | |
660 | .suspend = mmci_suspend, | |
661 | .resume = mmci_resume, | |
662 | .id_table = mmci_ids, | |
663 | }; | |
664 | ||
665 | static int __init mmci_init(void) | |
666 | { | |
667 | return amba_driver_register(&mmci_driver); | |
668 | } | |
669 | ||
670 | static void __exit mmci_exit(void) | |
671 | { | |
672 | amba_driver_unregister(&mmci_driver); | |
673 | } | |
674 | ||
675 | module_init(mmci_init); | |
676 | module_exit(mmci_exit); | |
677 | module_param(fmax, uint, 0444); | |
678 | ||
679 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
680 | MODULE_LICENSE("GPL"); |