[linux-2.6-block.git] / drivers / mmc / mmci.c

/*
 *  linux/drivers/mmc/mmci.c - ARM PrimeCell MMCI PL180/1 driver
 *
 *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/highmem.h>
#include <linux/mmc/host.h>
#include <linux/mmc/protocol.h>
#include <linux/amba/bus.h>
#include <linux/clk.h>

#include <asm/cacheflush.h>
#include <asm/div64.h>
#include <asm/io.h>
#include <asm/scatterlist.h>
#include <asm/sizes.h>
#include <asm/mach/mmc.h>

#include "mmci.h"

#define DRIVER_NAME "mmci-pl18x"

#define DBG(host,fmt,args...)	\
	pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)

static unsigned int fmax = 515633;

static void
mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
{
	writel(0, host->base + MMCICOMMAND);

	host->mrq = NULL;
	host->cmd = NULL;

	if (mrq->data)
		mrq->data->bytes_xfered = host->data_xfered;

	/*
	 * Need to drop the host lock here; mmc_request_done may call
	 * back into the driver...
	 */
	spin_unlock(&host->lock);
	mmc_request_done(host->mmc, mrq);
	spin_lock(&host->lock);
}

static void mmci_stop_data(struct mmci_host *host)
{
	writel(0, host->base + MMCIDATACTRL);
	writel(0, host->base + MMCIMASK1);
	host->data = NULL;
}

static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
{
	unsigned int datactrl, timeout, irqmask;
	unsigned long long clks;
	void __iomem *base;

	DBG(host, "blksz %04x blks %04x flags %08x\n",
	    1 << data->blksz_bits, data->blocks, data->flags);

	host->data = data;
	host->size = data->blocks << data->blksz_bits;
	host->data_xfered = 0;

	mmci_init_sg(host, data);

	clks = (unsigned long long)data->timeout_ns * host->cclk;
	do_div(clks, 1000000000UL);

	timeout = data->timeout_clks + (unsigned int)clks;

	base = host->base;
	writel(timeout, base + MMCIDATATIMER);
	writel(host->size, base + MMCIDATALENGTH);

	datactrl = MCI_DPSM_ENABLE | data->blksz_bits << 4;
	if (data->flags & MMC_DATA_READ) {
		datactrl |= MCI_DPSM_DIRECTION;
		irqmask = MCI_RXFIFOHALFFULLMASK;

		/*
		 * If we have less than a FIFOSIZE of bytes to transfer,
		 * trigger a PIO interrupt as soon as any data is available.
		 */
		if (host->size < MCI_FIFOSIZE)
			irqmask |= MCI_RXDATAAVLBLMASK;
	} else {
		/*
		 * We don't actually need to include "FIFO empty" here
		 * since its implicit in "FIFO half empty".
		 */
		irqmask = MCI_TXFIFOHALFEMPTYMASK;
	}

	writel(datactrl, base + MMCIDATACTRL);
	writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
	writel(irqmask, base + MMCIMASK1);
}

static void
mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
{
	void __iomem *base = host->base;

	DBG(host, "op %02x arg %08x flags %08x\n",
	    cmd->opcode, cmd->arg, cmd->flags);

	if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
		writel(0, base + MMCICOMMAND);
		udelay(1);
	}

	c |= cmd->opcode | MCI_CPSM_ENABLE;
	if (cmd->flags & MMC_RSP_PRESENT) {
		if (cmd->flags & MMC_RSP_136)
			c |= MCI_CPSM_LONGRSP;
		c |= MCI_CPSM_RESPONSE;
	}
	if (/*interrupt*/0)
		c |= MCI_CPSM_INTERRUPT;

	host->cmd = cmd;

	writel(cmd->arg, base + MMCIARGUMENT);
	writel(c, base + MMCICOMMAND);
}

static void
mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
	      unsigned int status)
{
	if (status & MCI_DATABLOCKEND) {
		host->data_xfered += 1 << data->blksz_bits;
	}
	if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
		if (status & MCI_DATACRCFAIL)
			data->error = MMC_ERR_BADCRC;
		else if (status & MCI_DATATIMEOUT)
			data->error = MMC_ERR_TIMEOUT;
		else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
			data->error = MMC_ERR_FIFO;
		status |= MCI_DATAEND;

		/*
		 * We hit an error condition.  Ensure that any data
		 * partially written to a page is properly coherent.
		 */
		if (host->sg_len && data->flags & MMC_DATA_READ)
			flush_dcache_page(host->sg_ptr->page);
	}
	if (status & MCI_DATAEND) {
		mmci_stop_data(host);

		if (!data->stop) {
			mmci_request_end(host, data->mrq);
		} else {
			mmci_start_command(host, data->stop, 0);
		}
	}
}

static void
mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
	     unsigned int status)
{
	void __iomem *base = host->base;

	host->cmd = NULL;

	cmd->resp[0] = readl(base + MMCIRESPONSE0);
	cmd->resp[1] = readl(base + MMCIRESPONSE1);
	cmd->resp[2] = readl(base + MMCIRESPONSE2);
	cmd->resp[3] = readl(base + MMCIRESPONSE3);

	if (status & MCI_CMDTIMEOUT) {
		cmd->error = MMC_ERR_TIMEOUT;
	} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
		cmd->error = MMC_ERR_BADCRC;
	}

	if (!cmd->data || cmd->error != MMC_ERR_NONE) {
		mmci_request_end(host, cmd->mrq);
	} else if (!(cmd->data->flags & MMC_DATA_READ)) {
		mmci_start_data(host, cmd->data);
	}
}

static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
{
	void __iomem *base = host->base;
	char *ptr = buffer;
	u32 status;

	do {
		int count = host->size - (readl(base + MMCIFIFOCNT) << 2);

		if (count > remain)
			count = remain;

		if (count <= 0)
			break;

		readsl(base + MMCIFIFO, ptr, count >> 2);

		ptr += count;
		remain -= count;

		if (remain == 0)
			break;

		status = readl(base + MMCISTATUS);
	} while (status & MCI_RXDATAAVLBL);

	return ptr - buffer;
}

static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
{
	void __iomem *base = host->base;
	char *ptr = buffer;

	do {
		unsigned int count, maxcnt;

		maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
		count = min(remain, maxcnt);

		writesl(base + MMCIFIFO, ptr, count >> 2);

		ptr += count;
		remain -= count;

		if (remain == 0)
			break;

		status = readl(base + MMCISTATUS);
	} while (status & MCI_TXFIFOHALFEMPTY);

	return ptr - buffer;
}

/*
 * PIO data transfer IRQ handler.
 */
static irqreturn_t mmci_pio_irq(int irq, void *dev_id, struct pt_regs *regs)
{
	struct mmci_host *host = dev_id;
	void __iomem *base = host->base;
	u32 status;

	status = readl(base + MMCISTATUS);

	DBG(host, "irq1 %08x\n", status);

	do {
		unsigned long flags;
		unsigned int remain, len;
		char *buffer;

		/*
		 * For write, we only need to test the half-empty flag
		 * here - if the FIFO is completely empty, then by
		 * definition it is more than half empty.
		 *
		 * For read, check for data available.
		 */
		if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
			break;

		/*
		 * Map the current scatter buffer.
		 */
		buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
		remain = host->sg_ptr->length - host->sg_off;

		len = 0;
		if (status & MCI_RXACTIVE)
			len = mmci_pio_read(host, buffer, remain);
		if (status & MCI_TXACTIVE)
			len = mmci_pio_write(host, buffer, remain, status);

		/*
		 * Unmap the buffer.
		 */
		mmci_kunmap_atomic(host, buffer, &flags);

		host->sg_off += len;
		host->size -= len;
		remain -= len;

		if (remain)
			break;

		/*
		 * If we were reading, and we have completed this
		 * page, ensure that the data cache is coherent.
		 */
		if (status & MCI_RXACTIVE)
			flush_dcache_page(host->sg_ptr->page);

		if (!mmci_next_sg(host))
			break;

		status = readl(base + MMCISTATUS);
	} while (1);

	/*
	 * If we're nearing the end of the read, switch to
	 * "any data available" mode.
	 */
	if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
		writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);

	/*
	 * If we run out of data, disable the data IRQs; this
	 * prevents a race where the FIFO becomes empty before
	 * the chip itself has disabled the data path, and
	 * stops us racing with our data end IRQ.
	 */
	if (host->size == 0) {
		writel(0, base + MMCIMASK1);
		writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
	}

	return IRQ_HANDLED;
}

/*
 * Handle completion of command and data transfers.
 */
static irqreturn_t mmci_irq(int irq, void *dev_id, struct pt_regs *regs)
{
	struct mmci_host *host = dev_id;
	u32 status;
	int ret = 0;

	spin_lock(&host->lock);

	do {
		struct mmc_command *cmd;
		struct mmc_data *data;

		status = readl(host->base + MMCISTATUS);
		status &= readl(host->base + MMCIMASK0);
		writel(status, host->base + MMCICLEAR);

		DBG(host, "irq0 %08x\n", status);

		data = host->data;
		if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
			      MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
			mmci_data_irq(host, data, status);

		cmd = host->cmd;
		if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
			mmci_cmd_irq(host, cmd, status);

		ret = 1;
	} while (status);

	spin_unlock(&host->lock);

	return IRQ_RETVAL(ret);
}

static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
	struct mmci_host *host = mmc_priv(mmc);

	WARN_ON(host->mrq != NULL);

	spin_lock_irq(&host->lock);

	host->mrq = mrq;

	if (mrq->data && mrq->data->flags & MMC_DATA_READ)
		mmci_start_data(host, mrq->data);

	mmci_start_command(host, mrq->cmd, 0);

	spin_unlock_irq(&host->lock);
}

static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct mmci_host *host = mmc_priv(mmc);
	u32 clk = 0, pwr = 0;

	if (ios->clock) {
		if (ios->clock >= host->mclk) {
			clk = MCI_CLK_BYPASS;
			host->cclk = host->mclk;
		} else {
			clk = host->mclk / (2 * ios->clock) - 1;
			if (clk > 256)
				clk = 255;
			host->cclk = host->mclk / (2 * (clk + 1));
		}
		clk |= MCI_CLK_ENABLE;
	}

	if (host->plat->translate_vdd)
		pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);

	switch (ios->power_mode) {
	case MMC_POWER_OFF:
		break;
	case MMC_POWER_UP:
		pwr |= MCI_PWR_UP;
		break;
	case MMC_POWER_ON:
		pwr |= MCI_PWR_ON;
		break;
	}

	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
		pwr |= MCI_ROD;

	writel(clk, host->base + MMCICLOCK);

	if (host->pwr != pwr) {
		host->pwr = pwr;
		writel(pwr, host->base + MMCIPOWER);
	}
}

static struct mmc_host_ops mmci_ops = {
	.request	= mmci_request,
	.set_ios	= mmci_set_ios,
};

static void mmci_check_status(unsigned long data)
{
	struct mmci_host *host = (struct mmci_host *)data;
	unsigned int status;

	status = host->plat->status(mmc_dev(host->mmc));
	if (status ^ host->oldstat)
		mmc_detect_change(host->mmc, 0);

	host->oldstat = status;
	mod_timer(&host->timer, jiffies + HZ);
}

static int mmci_probe(struct amba_device *dev, void *id)
{
	struct mmc_platform_data *plat = dev->dev.platform_data;
	struct mmci_host *host;
	struct mmc_host *mmc;
	int ret;

	/* must have platform data */
	if (!plat) {
		ret = -EINVAL;
		goto out;
	}

	ret = amba_request_regions(dev, DRIVER_NAME);
	if (ret)
		goto out;

	mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
	if (!mmc) {
		ret = -ENOMEM;
		goto rel_regions;
	}

	host = mmc_priv(mmc);
	host->clk = clk_get(&dev->dev, "MCLK");
	if (IS_ERR(host->clk)) {
		ret = PTR_ERR(host->clk);
		host->clk = NULL;
		goto host_free;
	}

	ret = clk_enable(host->clk);
	if (ret)
		goto clk_free;

	host->plat = plat;
	host->mclk = clk_get_rate(host->clk);
	host->mmc = mmc;
	host->base = ioremap(dev->res.start, SZ_4K);
	if (!host->base) {
		ret = -ENOMEM;
		goto clk_disable;
	}

	mmc->ops = &mmci_ops;
	mmc->f_min = (host->mclk + 511) / 512;
	mmc->f_max = min(host->mclk, fmax);
	mmc->ocr_avail = plat->ocr_mask;

	/*
	 * We can do SGIO
	 */
	mmc->max_hw_segs = 16;
	mmc->max_phys_segs = NR_SG;

	/*
	 * Since we only have a 16-bit data length register, we must
	 * ensure that we don't exceed 2^16-1 bytes in a single request.
	 * Choose 64 (512-byte) sectors as the limit.
	 */
	mmc->max_sectors = 64;

	/*
	 * Set the maximum segment size.  Since we aren't doing DMA
	 * (yet) we are only limited by the data length register.
	 */
	mmc->max_seg_size = mmc->max_sectors << 9;

	spin_lock_init(&host->lock);

	writel(0, host->base + MMCIMASK0);
	writel(0, host->base + MMCIMASK1);
	writel(0xfff, host->base + MMCICLEAR);

	ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
	if (ret)
		goto unmap;

	ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host);
	if (ret)
		goto irq0_free;

	writel(MCI_IRQENABLE, host->base + MMCIMASK0);

	amba_set_drvdata(dev, mmc);

	mmc_add_host(mmc);

	printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
		mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
		(unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);

	init_timer(&host->timer);
	host->timer.data = (unsigned long)host;
	host->timer.function = mmci_check_status;
	host->timer.expires = jiffies + HZ;
	add_timer(&host->timer);

	return 0;

 irq0_free:
	free_irq(dev->irq[0], host);
 unmap:
	iounmap(host->base);
 clk_disable:
	clk_disable(host->clk);
 clk_free:
	clk_put(host->clk);
 host_free:
	mmc_free_host(mmc);
 rel_regions:
	amba_release_regions(dev);
 out:
	return ret;
}

static int mmci_remove(struct amba_device *dev)
{
	struct mmc_host *mmc = amba_get_drvdata(dev);

	amba_set_drvdata(dev, NULL);

	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);

		del_timer_sync(&host->timer);

		mmc_remove_host(mmc);

		writel(0, host->base + MMCIMASK0);
		writel(0, host->base + MMCIMASK1);

		writel(0, host->base + MMCICOMMAND);
		writel(0, host->base + MMCIDATACTRL);

		free_irq(dev->irq[0], host);
		free_irq(dev->irq[1], host);

		iounmap(host->base);
		clk_disable(host->clk);
		clk_put(host->clk);

		mmc_free_host(mmc);

		amba_release_regions(dev);
	}

	return 0;
}

#ifdef CONFIG_PM
static int mmci_suspend(struct amba_device *dev, pm_message_t state)
{
	struct mmc_host *mmc = amba_get_drvdata(dev);
	int ret = 0;

	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);

		ret = mmc_suspend_host(mmc, state);
		if (ret == 0)
			writel(0, host->base + MMCIMASK0);
	}

	return ret;
}

static int mmci_resume(struct amba_device *dev)
{
	struct mmc_host *mmc = amba_get_drvdata(dev);
	int ret = 0;

	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);

		writel(MCI_IRQENABLE, host->base + MMCIMASK0);

		ret = mmc_resume_host(mmc);
	}

	return ret;
}
#else
#define mmci_suspend	NULL
#define mmci_resume	NULL
#endif

static struct amba_id mmci_ids[] = {
	{
		.id	= 0x00041180,
		.mask	= 0x000fffff,
	},
	{
		.id	= 0x00041181,
		.mask	= 0x000fffff,
	},
	{ 0, 0 },
};

static struct amba_driver mmci_driver = {
	.drv		= {
		.name	= DRIVER_NAME,
	},
	.probe		= mmci_probe,
	.remove		= mmci_remove,
	.suspend	= mmci_suspend,
	.resume		= mmci_resume,
	.id_table	= mmci_ids,
};

static int __init mmci_init(void)
{
	return amba_driver_register(&mmci_driver);
}

static void __exit mmci_exit(void)
{
	amba_driver_unregister(&mmci_driver);
}

module_init(mmci_init);
module_exit(mmci_exit);
module_param(fmax, uint, 0444);

MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/mmc/mmci.c - ARM PrimeCell MMCI PL180/1 driver
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/moduleparam.h>
	12	#include <linux/init.h>
	13	#include <linux/ioport.h>
	14	#include <linux/device.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/delay.h>
	17	#include <linux/err.h>
	18	#include <linux/highmem.h>
	19	#include <linux/mmc/host.h>
	20	#include <linux/mmc/protocol.h>
a62c80e5	21	#include <linux/amba/bus.h>
f8ce2547	22	#include <linux/clk.h>
1da177e4	23
e9c091b4	24	#include <asm/cacheflush.h>
7b09cdac	25	#include <asm/div64.h>
1da177e4	26	#include <asm/io.h>
1da177e4	27	#include <asm/scatterlist.h>
c6b8fdad	28	#include <asm/sizes.h>
1da177e4 LT	29	#include <asm/mach/mmc.h>
	30
	31	#include "mmci.h"
	32
	33	#define DRIVER_NAME "mmci-pl18x"
	34
1da177e4	35	#define DBG(host,fmt,args...) \
d366b643	36	pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
1da177e4 LT	37
	38	static unsigned int fmax = 515633;
	39
	40	static void
	41	mmci_request_end(struct mmci_host host, struct mmc_request mrq)
	42	{
	43	writel(0, host->base + MMCICOMMAND);
	44
	45	host->mrq = NULL;
	46	host->cmd = NULL;
	47
	48	if (mrq->data)
	49	mrq->data->bytes_xfered = host->data_xfered;
	50
	51	/*
	52	* Need to drop the host lock here; mmc_request_done may call
	53	* back into the driver...
	54	*/
	55	spin_unlock(&host->lock);
	56	mmc_request_done(host->mmc, mrq);
	57	spin_lock(&host->lock);
	58	}
	59
	60	static void mmci_stop_data(struct mmci_host *host)
	61	{
	62	writel(0, host->base + MMCIDATACTRL);
	63	writel(0, host->base + MMCIMASK1);
	64	host->data = NULL;
	65	}
	66
	67	static void mmci_start_data(struct mmci_host host, struct mmc_data data)
	68	{
	69	unsigned int datactrl, timeout, irqmask;
7b09cdac	70	unsigned long long clks;
1da177e4 LT	71	void __iomem *base;
	72
	73	DBG(host, "blksz %04x blks %04x flags %08x\n",
	74	1 << data->blksz_bits, data->blocks, data->flags);
	75
	76	host->data = data;
	77	host->size = data->blocks << data->blksz_bits;
	78	host->data_xfered = 0;
	79
	80	mmci_init_sg(host, data);
	81
7b09cdac RK	82	clks = (unsigned long long)data->timeout_ns * host->cclk;
	83	do_div(clks, 1000000000UL);
	84
	85	timeout = data->timeout_clks + (unsigned int)clks;
1da177e4 LT	86
	87	base = host->base;
	88	writel(timeout, base + MMCIDATATIMER);
	89	writel(host->size, base + MMCIDATALENGTH);
	90
	91	datactrl = MCI_DPSM_ENABLE \| data->blksz_bits << 4;
	92	if (data->flags & MMC_DATA_READ) {
	93	datactrl \|= MCI_DPSM_DIRECTION;
	94	irqmask = MCI_RXFIFOHALFFULLMASK;
0425a142 RK	95
	96	/*
	97	* If we have less than a FIFOSIZE of bytes to transfer,
	98	* trigger a PIO interrupt as soon as any data is available.
	99	*/
	100	if (host->size < MCI_FIFOSIZE)
	101	irqmask \|= MCI_RXDATAAVLBLMASK;
1da177e4 LT	102	} else {
	103	/*
	104	* We don't actually need to include "FIFO empty" here
	105	* since its implicit in "FIFO half empty".
	106	*/
	107	irqmask = MCI_TXFIFOHALFEMPTYMASK;
	108	}
	109
	110	writel(datactrl, base + MMCIDATACTRL);
	111	writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
	112	writel(irqmask, base + MMCIMASK1);
	113	}
	114
	115	static void
	116	mmci_start_command(struct mmci_host host, struct mmc_command cmd, u32 c)
	117	{
	118	void __iomem *base = host->base;
	119
	120	DBG(host, "op %02x arg %08x flags %08x\n",
	121	cmd->opcode, cmd->arg, cmd->flags);
	122
	123	if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
	124	writel(0, base + MMCICOMMAND);
	125	udelay(1);
	126	}
	127
	128	c \|= cmd->opcode \| MCI_CPSM_ENABLE;
e9225176 RK	129	if (cmd->flags & MMC_RSP_PRESENT) {
	130	if (cmd->flags & MMC_RSP_136)
	131	c \|= MCI_CPSM_LONGRSP;
1da177e4	132	c \|= MCI_CPSM_RESPONSE;
1da177e4 LT	133	}
	134	if (/interrupt/0)
	135	c \|= MCI_CPSM_INTERRUPT;
	136
	137	host->cmd = cmd;
	138
	139	writel(cmd->arg, base + MMCIARGUMENT);
	140	writel(c, base + MMCICOMMAND);
	141	}
	142
	143	static void
	144	mmci_data_irq(struct mmci_host host, struct mmc_data data,
	145	unsigned int status)
	146	{
	147	if (status & MCI_DATABLOCKEND) {
	148	host->data_xfered += 1 << data->blksz_bits;
	149	}
	150	if (status & (MCI_DATACRCFAIL\|MCI_DATATIMEOUT\|MCI_TXUNDERRUN\|MCI_RXOVERRUN)) {
	151	if (status & MCI_DATACRCFAIL)
	152	data->error = MMC_ERR_BADCRC;
	153	else if (status & MCI_DATATIMEOUT)
	154	data->error = MMC_ERR_TIMEOUT;
	155	else if (status & (MCI_TXUNDERRUN\|MCI_RXOVERRUN))
	156	data->error = MMC_ERR_FIFO;
	157	status \|= MCI_DATAEND;
e9c091b4 RK	158
	159	/*
	160	* We hit an error condition. Ensure that any data
	161	* partially written to a page is properly coherent.
	162	*/
	163	if (host->sg_len && data->flags & MMC_DATA_READ)
	164	flush_dcache_page(host->sg_ptr->page);
1da177e4 LT	165	}
	166	if (status & MCI_DATAEND) {
	167	mmci_stop_data(host);
	168
	169	if (!data->stop) {
	170	mmci_request_end(host, data->mrq);
	171	} else {
	172	mmci_start_command(host, data->stop, 0);
	173	}
	174	}
	175	}
	176
	177	static void
	178	mmci_cmd_irq(struct mmci_host host, struct mmc_command cmd,
	179	unsigned int status)
	180	{
	181	void __iomem *base = host->base;
	182
	183	host->cmd = NULL;
	184
	185	cmd->resp[0] = readl(base + MMCIRESPONSE0);
	186	cmd->resp[1] = readl(base + MMCIRESPONSE1);
	187	cmd->resp[2] = readl(base + MMCIRESPONSE2);
	188	cmd->resp[3] = readl(base + MMCIRESPONSE3);
	189
	190	if (status & MCI_CMDTIMEOUT) {
	191	cmd->error = MMC_ERR_TIMEOUT;
	192	} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
	193	cmd->error = MMC_ERR_BADCRC;
	194	}
	195
	196	if (!cmd->data \|\| cmd->error != MMC_ERR_NONE) {
	197	mmci_request_end(host, cmd->mrq);
	198	} else if (!(cmd->data->flags & MMC_DATA_READ)) {
	199	mmci_start_data(host, cmd->data);
	200	}
	201	}
	202
	203	static int mmci_pio_read(struct mmci_host host, char buffer, unsigned int remain)
	204	{
	205	void __iomem *base = host->base;
	206	char *ptr = buffer;
	207	u32 status;
	208
	209	do {
	210	int count = host->size - (readl(base + MMCIFIFOCNT) << 2);
	211
	212	if (count > remain)
	213	count = remain;
	214
	215	if (count <= 0)
	216	break;
	217
	218	readsl(base + MMCIFIFO, ptr, count >> 2);
	219
	220	ptr += count;
	221	remain -= count;
	222
	223	if (remain == 0)
	224	break;
	225
	226	status = readl(base + MMCISTATUS);
	227	} while (status & MCI_RXDATAAVLBL);
	228
229	return ptr - buffer;
230	}
231
232	static int mmci_pio_write(struct mmci_host host, char buffer, unsigned int remain, u32 status)
233	{
234	void __iomem *base = host->base;
235	char *ptr = buffer;
236
237	do {
238	unsigned int count, maxcnt;
239
240	maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
241	count = min(remain, maxcnt);
242
243	writesl(base + MMCIFIFO, ptr, count >> 2);
244
245	ptr += count;
246	remain -= count;
247
248	if (remain == 0)
249	break;
250
251	status = readl(base + MMCISTATUS);
252	} while (status & MCI_TXFIFOHALFEMPTY);
253
254	return ptr - buffer;
255	}
256
257	/*
258	* PIO data transfer IRQ handler.
259	*/
260	static irqreturn_t mmci_pio_irq(int irq, void dev_id, struct pt_regs regs)
261	{
262	struct mmci_host *host = dev_id;
263	void __iomem *base = host->base;
264	u32 status;
265
266	status = readl(base + MMCISTATUS);
267
268	DBG(host, "irq1 %08x\n", status);
269
270	do {
271	unsigned long flags;
272	unsigned int remain, len;
273	char *buffer;
274
275	/*
276	* For write, we only need to test the half-empty flag
277	* here - if the FIFO is completely empty, then by
278	* definition it is more than half empty.
279	*
280	* For read, check for data available.
281	*/
282	if (!(status & (MCI_TXFIFOHALFEMPTY\|MCI_RXDATAAVLBL)))
283	break;
284
285	/*
286	* Map the current scatter buffer.
287	*/
288	buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
289	remain = host->sg_ptr->length - host->sg_off;
290
291	len = 0;
292	if (status & MCI_RXACTIVE)
293	len = mmci_pio_read(host, buffer, remain);
294	if (status & MCI_TXACTIVE)
295	len = mmci_pio_write(host, buffer, remain, status);
296
297	/*
298	* Unmap the buffer.
299	*/
f3e2628b	300	mmci_kunmap_atomic(host, buffer, &flags);
1da177e4 LT	301
	302	host->sg_off += len;
	303	host->size -= len;
	304	remain -= len;
	305
	306	if (remain)
	307	break;
	308
e9c091b4 RK	309	/*
	310	* If we were reading, and we have completed this
	311	* page, ensure that the data cache is coherent.
	312	*/
	313	if (status & MCI_RXACTIVE)
	314	flush_dcache_page(host->sg_ptr->page);
	315
1da177e4 LT	316	if (!mmci_next_sg(host))
	317	break;
	318
	319	status = readl(base + MMCISTATUS);
	320	} while (1);
	321
	322	/*
	323	* If we're nearing the end of the read, switch to
	324	* "any data available" mode.
	325	*/
	326	if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
	327	writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
	328
	329	/*
	330	* If we run out of data, disable the data IRQs; this
	331	* prevents a race where the FIFO becomes empty before
	332	* the chip itself has disabled the data path, and
	333	* stops us racing with our data end IRQ.
	334	*/
	335	if (host->size == 0) {
	336	writel(0, base + MMCIMASK1);
	337	writel(readl(base + MMCIMASK0) \| MCI_DATAENDMASK, base + MMCIMASK0);
	338	}
	339
	340	return IRQ_HANDLED;
	341	}
	342
	343	/*
	344	* Handle completion of command and data transfers.
	345	*/
	346	static irqreturn_t mmci_irq(int irq, void dev_id, struct pt_regs regs)
	347	{
	348	struct mmci_host *host = dev_id;
	349	u32 status;
	350	int ret = 0;
	351
	352	spin_lock(&host->lock);
	353
	354	do {
	355	struct mmc_command *cmd;
	356	struct mmc_data *data;
	357
	358	status = readl(host->base + MMCISTATUS);
	359	status &= readl(host->base + MMCIMASK0);
	360	writel(status, host->base + MMCICLEAR);
	361
	362	DBG(host, "irq0 %08x\n", status);
	363
	364	data = host->data;
	365	if (status & (MCI_DATACRCFAIL\|MCI_DATATIMEOUT\|MCI_TXUNDERRUN\|
	366	MCI_RXOVERRUN\|MCI_DATAEND\|MCI_DATABLOCKEND) && data)
	367	mmci_data_irq(host, data, status);
	368
	369	cmd = host->cmd;
	370	if (status & (MCI_CMDCRCFAIL\|MCI_CMDTIMEOUT\|MCI_CMDSENT\|MCI_CMDRESPEND) && cmd)
	371	mmci_cmd_irq(host, cmd, status);
	372
	373	ret = 1;
	374	} while (status);
	375
	376	spin_unlock(&host->lock);
	377
	378	return IRQ_RETVAL(ret);
	379	}
380
381	static void mmci_request(struct mmc_host mmc, struct mmc_request mrq)
382	{
383	struct mmci_host *host = mmc_priv(mmc);
384
385	WARN_ON(host->mrq != NULL);
386
387	spin_lock_irq(&host->lock);
388
389	host->mrq = mrq;
390
391	if (mrq->data && mrq->data->flags & MMC_DATA_READ)
392	mmci_start_data(host, mrq->data);
393
394	mmci_start_command(host, mrq->cmd, 0);
395
396	spin_unlock_irq(&host->lock);
397	}
398
399	static void mmci_set_ios(struct mmc_host mmc, struct mmc_ios ios)
400	{
401	struct mmci_host *host = mmc_priv(mmc);
402	u32 clk = 0, pwr = 0;
403
1da177e4 LT	404	if (ios->clock) {
	405	if (ios->clock >= host->mclk) {
	406	clk = MCI_CLK_BYPASS;
	407	host->cclk = host->mclk;
	408	} else {
	409	clk = host->mclk / (2 * ios->clock) - 1;
	410	if (clk > 256)
	411	clk = 255;
	412	host->cclk = host->mclk / (2 * (clk + 1));
	413	}
	414	clk \|= MCI_CLK_ENABLE;
	415	}
	416
	417	if (host->plat->translate_vdd)
	418	pwr \|= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
	419
	420	switch (ios->power_mode) {
	421	case MMC_POWER_OFF:
	422	break;
	423	case MMC_POWER_UP:
	424	pwr \|= MCI_PWR_UP;
	425	break;
	426	case MMC_POWER_ON:
	427	pwr \|= MCI_PWR_ON;
	428	break;
	429	}
	430
	431	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
	432	pwr \|= MCI_ROD;
	433
	434	writel(clk, host->base + MMCICLOCK);
	435
	436	if (host->pwr != pwr) {
	437	host->pwr = pwr;
	438	writel(pwr, host->base + MMCIPOWER);
	439	}
	440	}
	441
	442	static struct mmc_host_ops mmci_ops = {
	443	.request = mmci_request,
	444	.set_ios = mmci_set_ios,
	445	};
	446
	447	static void mmci_check_status(unsigned long data)
	448	{
	449	struct mmci_host host = (struct mmci_host )data;
	450	unsigned int status;
	451
	452	status = host->plat->status(mmc_dev(host->mmc));
	453	if (status ^ host->oldstat)
8dc00335	454	mmc_detect_change(host->mmc, 0);
1da177e4 LT	455
	456	host->oldstat = status;
	457	mod_timer(&host->timer, jiffies + HZ);
	458	}
	459
	460	static int mmci_probe(struct amba_device dev, void id)
	461	{
	462	struct mmc_platform_data *plat = dev->dev.platform_data;
	463	struct mmci_host *host;
	464	struct mmc_host *mmc;
	465	int ret;
	466
	467	/* must have platform data */
	468	if (!plat) {
	469	ret = -EINVAL;
	470	goto out;
	471	}
	472
	473	ret = amba_request_regions(dev, DRIVER_NAME);
	474	if (ret)
	475	goto out;
	476
	477	mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
	478	if (!mmc) {
	479	ret = -ENOMEM;
	480	goto rel_regions;
	481	}
	482
	483	host = mmc_priv(mmc);
	484	host->clk = clk_get(&dev->dev, "MCLK");
	485	if (IS_ERR(host->clk)) {
	486	ret = PTR_ERR(host->clk);
	487	host->clk = NULL;
	488	goto host_free;
	489	}
	490
1da177e4 LT	491	ret = clk_enable(host->clk);
1da177e4 LT	492	if (ret)
a8d3584a	493	goto clk_free;
1da177e4 LT	494
	495	host->plat = plat;
	496	host->mclk = clk_get_rate(host->clk);
	497	host->mmc = mmc;
	498	host->base = ioremap(dev->res.start, SZ_4K);
	499	if (!host->base) {
	500	ret = -ENOMEM;
	501	goto clk_disable;
	502	}
	503
	504	mmc->ops = &mmci_ops;
	505	mmc->f_min = (host->mclk + 511) / 512;
	506	mmc->f_max = min(host->mclk, fmax);
	507	mmc->ocr_avail = plat->ocr_mask;
	508
	509	/*
	510	* We can do SGIO
	511	*/
	512	mmc->max_hw_segs = 16;
	513	mmc->max_phys_segs = NR_SG;
	514
	515	/*
	516	* Since we only have a 16-bit data length register, we must
	517	* ensure that we don't exceed 2^16-1 bytes in a single request.
	518	* Choose 64 (512-byte) sectors as the limit.
	519	*/
	520	mmc->max_sectors = 64;
	521
	522	/*
	523	* Set the maximum segment size. Since we aren't doing DMA
	524	* (yet) we are only limited by the data length register.
	525	*/
	526	mmc->max_seg_size = mmc->max_sectors << 9;
	527
	528	spin_lock_init(&host->lock);
	529
	530	writel(0, host->base + MMCIMASK0);
	531	writel(0, host->base + MMCIMASK1);
	532	writel(0xfff, host->base + MMCICLEAR);
	533
dace1453	534	ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
1da177e4 LT	535	if (ret)
	536	goto unmap;
	537
dace1453	538	ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host);
1da177e4 LT	539	if (ret)
	540	goto irq0_free;
	541
	542	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
	543
	544	amba_set_drvdata(dev, mmc);
	545
	546	mmc_add_host(mmc);
	547
e29419ff	548	printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
d366b643	549	mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
e29419ff	550	(unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
1da177e4 LT	551
	552	init_timer(&host->timer);
	553	host->timer.data = (unsigned long)host;
	554	host->timer.function = mmci_check_status;
	555	host->timer.expires = jiffies + HZ;
	556	add_timer(&host->timer);
	557
	558	return 0;
	559
	560	irq0_free:
	561	free_irq(dev->irq[0], host);
	562	unmap:
	563	iounmap(host->base);
	564	clk_disable:
	565	clk_disable(host->clk);
1da177e4 LT	566	clk_free:
	567	clk_put(host->clk);
	568	host_free:
	569	mmc_free_host(mmc);
	570	rel_regions:
	571	amba_release_regions(dev);
	572	out:
	573	return ret;
	574	}
	575
	576	static int mmci_remove(struct amba_device *dev)
	577	{
	578	struct mmc_host *mmc = amba_get_drvdata(dev);
	579
	580	amba_set_drvdata(dev, NULL);
	581
	582	if (mmc) {
	583	struct mmci_host *host = mmc_priv(mmc);
	584
	585	del_timer_sync(&host->timer);
	586
	587	mmc_remove_host(mmc);
	588
	589	writel(0, host->base + MMCIMASK0);
	590	writel(0, host->base + MMCIMASK1);
	591
	592	writel(0, host->base + MMCICOMMAND);
	593	writel(0, host->base + MMCIDATACTRL);
	594
	595	free_irq(dev->irq[0], host);
	596	free_irq(dev->irq[1], host);
	597
	598	iounmap(host->base);
	599	clk_disable(host->clk);
1da177e4 LT	600	clk_put(host->clk);
	601
	602	mmc_free_host(mmc);
	603
	604	amba_release_regions(dev);
	605	}
	606
	607	return 0;
	608	}
	609
	610	#ifdef CONFIG_PM
e5378ca8	611	static int mmci_suspend(struct amba_device *dev, pm_message_t state)
1da177e4 LT	612	{
	613	struct mmc_host *mmc = amba_get_drvdata(dev);
	614	int ret = 0;
	615
	616	if (mmc) {
	617	struct mmci_host *host = mmc_priv(mmc);
	618
	619	ret = mmc_suspend_host(mmc, state);
	620	if (ret == 0)
	621	writel(0, host->base + MMCIMASK0);
	622	}
	623
	624	return ret;
	625	}
	626
	627	static int mmci_resume(struct amba_device *dev)
	628	{
	629	struct mmc_host *mmc = amba_get_drvdata(dev);
	630	int ret = 0;
	631
	632	if (mmc) {
	633	struct mmci_host *host = mmc_priv(mmc);
	634
	635	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
	636
	637	ret = mmc_resume_host(mmc);
	638	}
	639
	640	return ret;
	641	}
	642	#else
	643	#define mmci_suspend NULL
	644	#define mmci_resume NULL
	645	#endif
	646
	647	static struct amba_id mmci_ids[] = {
	648	{
	649	.id = 0x00041180,
	650	.mask = 0x000fffff,
	651	},
	652	{
	653	.id = 0x00041181,
	654	.mask = 0x000fffff,
	655	},
	656	{ 0, 0 },
	657	};
	658
	659	static struct amba_driver mmci_driver = {
	660	.drv = {
	661	.name = DRIVER_NAME,
	662	},
	663	.probe = mmci_probe,
	664	.remove = mmci_remove,
	665	.suspend = mmci_suspend,
	666	.resume = mmci_resume,
	667	.id_table = mmci_ids,
	668	};
	669
	670	static int __init mmci_init(void)
	671	{
	672	return amba_driver_register(&mmci_driver);
	673	}
	674
	675	static void __exit mmci_exit(void)
676	{
677	amba_driver_unregister(&mmci_driver);
678	}
679
680	module_init(mmci_init);
681	module_exit(mmci_exit);
682	module_param(fmax, uint, 0444);
683
684	MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
685	MODULE_LICENSE("GPL");