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mmc: rtsx_usb: use new macro for R1 without CRC
[linux-2.6-block.git] / drivers / mmc / host / tmio_mmc_pio.c
CommitLineData
b6147490
GL		 1/*
2 * linux/drivers/mmc/host/tmio_mmc_pio.c
3 *
bf96208f
WS		 4 * Copyright (C) 2016 Sang Engineering, Wolfram Sang
5 * Copyright (C) 2015-16 Renesas Electronics Corporation
b6147490
GL		 6 * Copyright (C) 2011 Guennadi Liakhovetski
7 * Copyright (C) 2007 Ian Molton
8 * Copyright (C) 2004 Ian Molton
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Driver for the MMC / SD / SDIO IP found in:
15 *
16 * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
17 *
18 * This driver draws mainly on scattered spec sheets, Reverse engineering
19 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
20 * support). (Further 4 bit support from a later datasheet).
21 *
22 * TODO:
23 * Investigate using a workqueue for PIO transfers
24 * Eliminate FIXMEs
25 * SDIO support
26 * Better Power management
27 * Handle MMC errors better
28 * double buffer support
29 *
30 */
31
32#include <linux/delay.h>
33#include <linux/device.h>
34#include <linux/highmem.h>
35#include <linux/interrupt.h>
36#include <linux/io.h>
37#include <linux/irq.h>
38#include <linux/mfd/tmio.h>
39#include <linux/mmc/host.h>
0f506a96 40#include <linux/mmc/mmc.h>
fd0ea65d 41#include <linux/mmc/slot-gpio.h>
b6147490
GL		 42#include <linux/module.h>
43#include <linux/pagemap.h>
44#include <linux/platform_device.h>
c419e611 45#include <linux/pm_qos.h>
e6ee7182 46#include <linux/pm_runtime.h>
619b08d4 47#include <linux/regulator/consumer.h>
b8d11962 48#include <linux/mmc/sdio.h>
b6147490 49#include <linux/scatterlist.h>
b6147490 50#include <linux/spinlock.h>
e3de2be7 51#include <linux/workqueue.h>
b6147490
GL		 52
53#include "tmio_mmc.h"
54
b6147490
GL		 55void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
56{
54680fe7 57 host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ);
2c54506b 58 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 59}
60
61void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
62{
54680fe7 63 host->sdcard_irq_mask |= (i & TMIO_MASK_IRQ);
2c54506b 64 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 65}
66
67static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)
68{
2c54506b 69 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, ~i);
b6147490
GL		 70}
71
72static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
73{
74 host->sg_len = data->sg_len;
75 host->sg_ptr = data->sg;
76 host->sg_orig = data->sg;
77 host->sg_off = 0;
78}
79
80static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
81{
82 host->sg_ptr = sg_next(host->sg_ptr);
83 host->sg_off = 0;
84 return --host->sg_len;
85}
86
0df9d2ea
TK		 87#define CMDREQ_TIMEOUT 5000
88
b6147490
GL		 89#ifdef CONFIG_MMC_DEBUG
90
91#define STATUS_TO_TEXT(a, status, i) \
92 do { \
93 if (status & TMIO_STAT_##a) { \
94 if (i++) \
95 printk(" | "); \
96 printk(#a); \
97 } \
98 } while (0)
99
100static void pr_debug_status(u32 status)
101{
102 int i = 0;
a3c76eb9 103 pr_debug("status: %08x = ", status);
b6147490
GL		 104 STATUS_TO_TEXT(CARD_REMOVE, status, i);
105 STATUS_TO_TEXT(CARD_INSERT, status, i);
106 STATUS_TO_TEXT(SIGSTATE, status, i);
107 STATUS_TO_TEXT(WRPROTECT, status, i);
108 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
109 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
110 STATUS_TO_TEXT(SIGSTATE_A, status, i);
111 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
112 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
113 STATUS_TO_TEXT(ILL_FUNC, status, i);
114 STATUS_TO_TEXT(CMD_BUSY, status, i);
115 STATUS_TO_TEXT(CMDRESPEND, status, i);
116 STATUS_TO_TEXT(DATAEND, status, i);
117 STATUS_TO_TEXT(CRCFAIL, status, i);
118 STATUS_TO_TEXT(DATATIMEOUT, status, i);
119 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
120 STATUS_TO_TEXT(RXOVERFLOW, status, i);
121 STATUS_TO_TEXT(TXUNDERRUN, status, i);
122 STATUS_TO_TEXT(RXRDY, status, i);
123 STATUS_TO_TEXT(TXRQ, status, i);
124 STATUS_TO_TEXT(ILL_ACCESS, status, i);
125 printk("\n");
126}
127
128#else
129#define pr_debug_status(s) do { } while (0)
130#endif
131
132static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
133{
134 struct tmio_mmc_host *host = mmc_priv(mmc);
135
7501c431
UH		 136 if (enable && !host->sdio_irq_enabled) {
137 /* Keep device active while SDIO irq is enabled */
138 pm_runtime_get_sync(mmc_dev(mmc));
139 host->sdio_irq_enabled = true;
140
54680fe7
SH		 141 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL &
142 ~TMIO_SDIO_STAT_IOIRQ;
b6147490 143 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
54680fe7 144 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
7501c431 145 } else if (!enable && host->sdio_irq_enabled) {
54680fe7
SH		 146 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
147 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
b6147490 148 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
7501c431
UH		 149
150 host->sdio_irq_enabled = false;
0369483e
UH		 151 pm_runtime_mark_last_busy(mmc_dev(mmc));
152 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 153 }
154}
155
7fbc030d
WS		 156static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
157{
158 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
159 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
3d376fb2 160 msleep(host->pdata->flags & TMIO_MMC_MIN_RCAR2 ? 1 : 10);
7fbc030d
WS		 161
162 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
163 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
164 msleep(10);
165 }
166}
167
148634d2
WS		 168static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
169{
170 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
171 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
172 msleep(10);
173 }
174
175 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
176 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
3d376fb2 177 msleep(host->pdata->flags & TMIO_MMC_MIN_RCAR2 ? 5 : 10);
148634d2
WS		 178}
179
ae12d250
UH		 180static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
181 unsigned int new_clock)
b6147490
GL		 182{
183 u32 clk = 0, clock;
184
148634d2
WS		 185 if (new_clock == 0) {
186 tmio_mmc_clk_stop(host);
187 return;
188 }
2fb55956 189
148634d2
WS		 190 if (host->clk_update)
191 clock = host->clk_update(host, new_clock) / 512;
192 else
193 clock = host->mmc->f_min;
da29fe2b 194
148634d2
WS		 195 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
196 clock <<= 1;
197
198 /* 1/1 clock is option */
199 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1))
200 clk |= 0xff;
b6147490
GL		 201
202 if (host->set_clk_div)
bf96208f 203 host->set_clk_div(host->pdev, (clk >> 22) & 1);
b6147490 204
14d5828f
WS		 205 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
206 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
bf96208f 207 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
3d376fb2 208 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
04e24b80 209 msleep(10);
7fbc030d
WS		 210
211 tmio_mmc_clk_start(host);
b6147490
GL		 212}
213
b6147490
GL		 214static void tmio_mmc_reset(struct tmio_mmc_host *host)
215{
216 /* FIXME - should we set stop clock reg here */
217 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
5d60e500 218 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 219 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
b6147490
GL		 220 msleep(10);
221 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
5d60e500 222 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 223 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
b6147490
GL		 224 msleep(10);
225}
226
227static void tmio_mmc_reset_work(struct work_struct *work)
228{
229 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
230 delayed_reset_work.work);
231 struct mmc_request *mrq;
232 unsigned long flags;
233
234 spin_lock_irqsave(&host->lock, flags);
235 mrq = host->mrq;
236
df3ef2d3
GL		 237 /*
238 * is request already finished? Since we use a non-blocking
239 * cancel_delayed_work(), it can happen, that a .set_ios() call preempts
240 * us, so, have to check for IS_ERR(host->mrq)
241 */
242 if (IS_ERR_OR_NULL(mrq)
b6147490 243 || time_is_after_jiffies(host->last_req_ts +
0df9d2ea 244 msecs_to_jiffies(CMDREQ_TIMEOUT))) {
b6147490
GL		 245 spin_unlock_irqrestore(&host->lock, flags);
246 return;
247 }
248
249 dev_warn(&host->pdev->dev,
250 "timeout waiting for hardware interrupt (CMD%u)\n",
251 mrq->cmd->opcode);
252
253 if (host->data)
254 host->data->error = -ETIMEDOUT;
255 else if (host->cmd)
256 host->cmd->error = -ETIMEDOUT;
257 else
258 mrq->cmd->error = -ETIMEDOUT;
259
260 host->cmd = NULL;
261 host->data = NULL;
b6147490
GL		 262 host->force_pio = false;
263
264 spin_unlock_irqrestore(&host->lock, flags);
265
266 tmio_mmc_reset(host);
267
df3ef2d3
GL		 268 /* Ready for new calls */
269 host->mrq = NULL;
270
e3de2be7 271 tmio_mmc_abort_dma(host);
b6147490
GL		 272 mmc_request_done(host->mmc, mrq);
273}
274
df3ef2d3 275/* called with host->lock held, interrupts disabled */
b6147490
GL		 276static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
277{
b9269fdd
GL		 278 struct mmc_request *mrq;
279 unsigned long flags;
b6147490 280
b9269fdd
GL		 281 spin_lock_irqsave(&host->lock, flags);
282
283 mrq = host->mrq;
284 if (IS_ERR_OR_NULL(mrq)) {
285 spin_unlock_irqrestore(&host->lock, flags);
b6147490 286 return;
b9269fdd 287 }
b6147490 288
b6147490
GL		 289 host->cmd = NULL;
290 host->data = NULL;
291 host->force_pio = false;
292
293 cancel_delayed_work(&host->delayed_reset_work);
294
df3ef2d3 295 host->mrq = NULL;
b9269fdd 296 spin_unlock_irqrestore(&host->lock, flags);
df3ef2d3 297
e3de2be7
GL		 298 if (mrq->cmd->error || (mrq->data && mrq->data->error))
299 tmio_mmc_abort_dma(host);
300
b6147490
GL		 301 mmc_request_done(host->mmc, mrq);
302}
303
b9269fdd
GL		 304static void tmio_mmc_done_work(struct work_struct *work)
305{
306 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
307 done);
308 tmio_mmc_finish_request(host);
309}
310
b6147490
GL		 311/* These are the bitmasks the tmio chip requires to implement the MMC response
312 * types. Note that R1 and R6 are the same in this scheme. */
313#define APP_CMD 0x0040
314#define RESP_NONE 0x0300
315#define RESP_R1 0x0400
316#define RESP_R1B 0x0500
317#define RESP_R2 0x0600
318#define RESP_R3 0x0700
319#define DATA_PRESENT 0x0800
320#define TRANSFER_READ 0x1000
321#define TRANSFER_MULTI 0x2000
322#define SECURITY_CMD 0x4000
b8d11962 323#define NO_CMD12_ISSUE 0x4000 /* TMIO_MMC_HAVE_CMD12_CTRL */
b6147490
GL		 324
325static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
326{
327 struct mmc_data *data = host->data;
328 int c = cmd->opcode;
e23cd53c 329 u32 irq_mask = TMIO_MASK_CMD;
b6147490 330
0f506a96
GL		 331 /* CMD12 is handled by hardware */
332 if (cmd->opcode == MMC_STOP_TRANSMISSION && !cmd->arg) {
b6147490
GL		 333 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
334 return 0;
335 }
336
337 switch (mmc_resp_type(cmd)) {
338 case MMC_RSP_NONE: c |= RESP_NONE; break;
339 case MMC_RSP_R1: c |= RESP_R1; break;
340 case MMC_RSP_R1B: c |= RESP_R1B; break;
341 case MMC_RSP_R2: c |= RESP_R2; break;
342 case MMC_RSP_R3: c |= RESP_R3; break;
343 default:
344 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
345 return -EINVAL;
346 }
347
348 host->cmd = cmd;
349
350/* FIXME - this seems to be ok commented out but the spec suggest this bit
351 * should be set when issuing app commands.
352 * if(cmd->flags & MMC_FLAG_ACMD)
353 * c |= APP_CMD;
354 */
355 if (data) {
356 c |= DATA_PRESENT;
357 if (data->blocks > 1) {
358 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
359 c |= TRANSFER_MULTI;
b8d11962
SU		 360
361 /*
362 * Disable auto CMD12 at IO_RW_EXTENDED when
363 * multiple block transfer
364 */
365 if ((host->pdata->flags & TMIO_MMC_HAVE_CMD12_CTRL) &&
366 (cmd->opcode == SD_IO_RW_EXTENDED))
367 c |= NO_CMD12_ISSUE;
b6147490
GL		 368 }
369 if (data->flags & MMC_DATA_READ)
370 c |= TRANSFER_READ;
371 }
372
e23cd53c
GL		 373 if (!host->native_hotplug)
374 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
375 tmio_mmc_enable_mmc_irqs(host, irq_mask);
b6147490
GL		 376
377 /* Fire off the command */
2c54506b 378 sd_ctrl_write32_as_16_and_16(host, CTL_ARG_REG, cmd->arg);
b6147490
GL		 379 sd_ctrl_write16(host, CTL_SD_CMD, c);
380
381 return 0;
382}
383
b9bd7ff8
KM		 384static void tmio_mmc_transfer_data(struct tmio_mmc_host *host,
385 unsigned short *buf,
386 unsigned int count)
387{
388 int is_read = host->data->flags & MMC_DATA_READ;
389 u8 *buf8;
390
391 /*
392 * Transfer the data
393 */
394 if (is_read)
395 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
396 else
397 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
398
399 /* if count was even number */
400 if (!(count & 0x1))
401 return;
402
403 /* if count was odd number */
404 buf8 = (u8 *)(buf + (count >> 1));
405
406 /*
407 * FIXME
408 *
409 * driver and this function are assuming that
410 * it is used as little endian
411 */
412 if (is_read)
413 *buf8 = sd_ctrl_read16(host, CTL_SD_DATA_PORT) & 0xff;
414 else
415 sd_ctrl_write16(host, CTL_SD_DATA_PORT, *buf8);
416}
417
b6147490
GL		 418/*
419 * This chip always returns (at least?) as much data as you ask for.
420 * I'm unsure what happens if you ask for less than a block. This should be
25985edc 421 * looked into to ensure that a funny length read doesn't hose the controller.
b6147490
GL		 422 */
423static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
424{
425 struct mmc_data *data = host->data;
426 void *sg_virt;
427 unsigned short *buf;
428 unsigned int count;
429 unsigned long flags;
430
431 if ((host->chan_tx || host->chan_rx) && !host->force_pio) {
432 pr_err("PIO IRQ in DMA mode!\n");
433 return;
434 } else if (!data) {
435 pr_debug("Spurious PIO IRQ\n");
436 return;
437 }
438
439 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
440 buf = (unsigned short *)(sg_virt + host->sg_off);
441
442 count = host->sg_ptr->length - host->sg_off;
443 if (count > data->blksz)
444 count = data->blksz;
445
446 pr_debug("count: %08x offset: %08x flags %08x\n",
447 count, host->sg_off, data->flags);
448
449 /* Transfer the data */
b9bd7ff8 450 tmio_mmc_transfer_data(host, buf, count);
b6147490
GL		 451
452 host->sg_off += count;
453
454 tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
455
456 if (host->sg_off == host->sg_ptr->length)
457 tmio_mmc_next_sg(host);
458
459 return;
460}
461
462static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host)
463{
464 if (host->sg_ptr == &host->bounce_sg) {
465 unsigned long flags;
466 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
467 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
468 tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
469 }
470}
471
472/* needs to be called with host->lock held */
473void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
474{
475 struct mmc_data *data = host->data;
476 struct mmc_command *stop;
477
478 host->data = NULL;
479
480 if (!data) {
481 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
482 return;
483 }
484 stop = data->stop;
485
486 /* FIXME - return correct transfer count on errors */
487 if (!data->error)
488 data->bytes_xfered = data->blocks * data->blksz;
489 else
490 data->bytes_xfered = 0;
491
492 pr_debug("Completed data request\n");
493
494 /*
495 * FIXME: other drivers allow an optional stop command of any given type
496 * which we dont do, as the chip can auto generate them.
497 * Perhaps we can be smarter about when to use auto CMD12 and
498 * only issue the auto request when we know this is the desired
499 * stop command, allowing fallback to the stop command the
500 * upper layers expect. For now, we do what works.
501 */
502
503 if (data->flags & MMC_DATA_READ) {
504 if (host->chan_rx && !host->force_pio)
505 tmio_mmc_check_bounce_buffer(host);
506 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
507 host->mrq);
508 } else {
509 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
510 host->mrq);
511 }
512
513 if (stop) {
0f506a96 514 if (stop->opcode == MMC_STOP_TRANSMISSION && !stop->arg)
b6147490
GL		 515 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
516 else
517 BUG();
518 }
519
b9269fdd 520 schedule_work(&host->done);
b6147490
GL		 521}
522
523static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
524{
525 struct mmc_data *data;
526 spin_lock(&host->lock);
527 data = host->data;
528
529 if (!data)
530 goto out;
531
532 if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
2c54506b 533 u32 status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);
81e888da
SU		 534 bool done = false;
535
b6147490
GL		 536 /*
537 * Has all data been written out yet? Testing on SuperH showed,
538 * that in most cases the first interrupt comes already with the
539 * BUSY status bit clear, but on some operations, like mount or
540 * in the beginning of a write / sync / umount, there is one
541 * DATAEND interrupt with the BUSY bit set, in this cases
542 * waiting for one more interrupt fixes the problem.
543 */
81e888da 544 if (host->pdata->flags & TMIO_MMC_HAS_IDLE_WAIT) {
a21553c9 545 if (status & TMIO_STAT_SCLKDIVEN)
81e888da
SU		 546 done = true;
547 } else {
548 if (!(status & TMIO_STAT_CMD_BUSY))
549 done = true;
550 }
551
552 if (done) {
b6147490
GL		 553 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
554 tasklet_schedule(&host->dma_complete);
555 }
556 } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
557 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
558 tasklet_schedule(&host->dma_complete);
559 } else {
560 tmio_mmc_do_data_irq(host);
561 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
562 }
563out:
564 spin_unlock(&host->lock);
565}
566
567static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
568 unsigned int stat)
569{
570 struct mmc_command *cmd = host->cmd;
571 int i, addr;
572
573 spin_lock(&host->lock);
574
575 if (!host->cmd) {
576 pr_debug("Spurious CMD irq\n");
577 goto out;
578 }
579
580 host->cmd = NULL;
581
582 /* This controller is sicker than the PXA one. Not only do we need to
583 * drop the top 8 bits of the first response word, we also need to
584 * modify the order of the response for short response command types.
585 */
586
587 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
2c54506b 588 cmd->resp[i] = sd_ctrl_read16_and_16_as_32(host, addr);
b6147490
GL		 589
590 if (cmd->flags & MMC_RSP_136) {
591 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
592 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
593 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
594 cmd->resp[3] <<= 8;
595 } else if (cmd->flags & MMC_RSP_R3) {
596 cmd->resp[0] = cmd->resp[3];
597 }
598
599 if (stat & TMIO_STAT_CMDTIMEOUT)
600 cmd->error = -ETIMEDOUT;
601 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
602 cmd->error = -EILSEQ;
603
604 /* If there is data to handle we enable data IRQs here, and
605 * we will ultimatley finish the request in the data_end handler.
606 * If theres no data or we encountered an error, finish now.
607 */
608 if (host->data && !cmd->error) {
609 if (host->data->flags & MMC_DATA_READ) {
610 if (host->force_pio || !host->chan_rx)
611 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
612 else
613 tasklet_schedule(&host->dma_issue);
614 } else {
615 if (host->force_pio || !host->chan_tx)
616 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
617 else
618 tasklet_schedule(&host->dma_issue);
619 }
620 } else {
b9269fdd 621 schedule_work(&host->done);
b6147490
GL		 622 }
623
624out:
625 spin_unlock(&host->lock);
626}
627
7729c7a2
SH		 628static bool __tmio_mmc_card_detect_irq(struct tmio_mmc_host *host,
629 int ireg, int status)
630{
631 struct mmc_host *mmc = host->mmc;
b6147490 632
e312eb1e
PP		 633 /* Card insert / remove attempts */
634 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
635 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
636 TMIO_STAT_CARD_REMOVE);
71d111cd
GL		 637 if ((((ireg & TMIO_STAT_CARD_REMOVE) && mmc->card) ||
638 ((ireg & TMIO_STAT_CARD_INSERT) && !mmc->card)) &&
639 !work_pending(&mmc->detect.work))
b9269fdd 640 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
7729c7a2 641 return true;
b6147490
GL		 642 }
643
7729c7a2
SH		 644 return false;
645}
646
7729c7a2
SH		 647static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host,
648 int ireg, int status)
649{
e312eb1e
PP		 650 /* Command completion */
651 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
652 tmio_mmc_ack_mmc_irqs(host,
653 TMIO_STAT_CMDRESPEND |
654 TMIO_STAT_CMDTIMEOUT);
655 tmio_mmc_cmd_irq(host, status);
7729c7a2 656 return true;
e312eb1e 657 }
b6147490 658
e312eb1e
PP		 659 /* Data transfer */
660 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
661 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
662 tmio_mmc_pio_irq(host);
7729c7a2 663 return true;
e312eb1e 664 }
b6147490 665
e312eb1e
PP		 666 /* Data transfer completion */
667 if (ireg & TMIO_STAT_DATAEND) {
668 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
669 tmio_mmc_data_irq(host);
7729c7a2 670 return true;
b6147490 671 }
e312eb1e 672
7729c7a2
SH		 673 return false;
674}
675
4da98670 676static void tmio_mmc_sdio_irq(int irq, void *devid)
7729c7a2
SH		 677{
678 struct tmio_mmc_host *host = devid;
679 struct mmc_host *mmc = host->mmc;
680 struct tmio_mmc_data *pdata = host->pdata;
681 unsigned int ireg, status;
6b98757e 682 unsigned int sdio_status;
7729c7a2
SH		 683
684 if (!(pdata->flags & TMIO_MMC_SDIO_IRQ))
4da98670 685 return;
7729c7a2
SH		 686
687 status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
688 ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdcard_irq_mask;
689
6b98757e
SU		 690 sdio_status = status & ~TMIO_SDIO_MASK_ALL;
691 if (pdata->flags & TMIO_MMC_SDIO_STATUS_QUIRK)
692 sdio_status |= 6;
693
694 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status);
7729c7a2
SH		 695
696 if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ)
697 mmc_signal_sdio_irq(mmc);
7729c7a2 698}
7729c7a2
SH		 699
700irqreturn_t tmio_mmc_irq(int irq, void *devid)
701{
702 struct tmio_mmc_host *host = devid;
703 unsigned int ireg, status;
704
2c54506b 705 status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);
95840126
WS		 706 ireg = status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask;
707
708 pr_debug_status(status);
709 pr_debug_status(ireg);
710
711 /* Clear the status except the interrupt status */
2c54506b 712 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, TMIO_MASK_IRQ);
7729c7a2 713
7729c7a2
SH		 714 if (__tmio_mmc_card_detect_irq(host, ireg, status))
715 return IRQ_HANDLED;
716 if (__tmio_mmc_sdcard_irq(host, ireg, status))
717 return IRQ_HANDLED;
718
719 tmio_mmc_sdio_irq(irq, devid);
b6147490 720
b6147490
GL		 721 return IRQ_HANDLED;
722}
8e7bfdb3 723EXPORT_SYMBOL(tmio_mmc_irq);
b6147490
GL		 724
725static int tmio_mmc_start_data(struct tmio_mmc_host *host,
726 struct mmc_data *data)
727{
728 struct tmio_mmc_data *pdata = host->pdata;
729
730 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
731 data->blksz, data->blocks);
732
733 /* Some hardware cannot perform 2 byte requests in 4 bit mode */
734 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
735 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
736
737 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
738 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
739 mmc_hostname(host->mmc), data->blksz);
740 return -EINVAL;
741 }
742 }
743
744 tmio_mmc_init_sg(host, data);
745 host->data = data;
746
747 /* Set transfer length / blocksize */
748 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
749 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
750
751 tmio_mmc_start_dma(host, data);
752
753 return 0;
754}
755
756/* Process requests from the MMC layer */
757static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
758{
759 struct tmio_mmc_host *host = mmc_priv(mmc);
df3ef2d3 760 unsigned long flags;
b6147490
GL		 761 int ret;
762
df3ef2d3
GL		 763 spin_lock_irqsave(&host->lock, flags);
764
765 if (host->mrq) {
b6147490 766 pr_debug("request not null\n");
df3ef2d3
GL		 767 if (IS_ERR(host->mrq)) {
768 spin_unlock_irqrestore(&host->lock, flags);
769 mrq->cmd->error = -EAGAIN;
770 mmc_request_done(mmc, mrq);
771 return;
772 }
773 }
b6147490
GL		 774
775 host->last_req_ts = jiffies;
776 wmb();
777 host->mrq = mrq;
778
df3ef2d3
GL		 779 spin_unlock_irqrestore(&host->lock, flags);
780
b6147490
GL		 781 if (mrq->data) {
782 ret = tmio_mmc_start_data(host, mrq->data);
783 if (ret)
784 goto fail;
785 }
786
787 ret = tmio_mmc_start_command(host, mrq->cmd);
788 if (!ret) {
789 schedule_delayed_work(&host->delayed_reset_work,
0df9d2ea 790 msecs_to_jiffies(CMDREQ_TIMEOUT));
b6147490
GL		 791 return;
792 }
793
794fail:
b6147490 795 host->force_pio = false;
df3ef2d3 796 host->mrq = NULL;
b6147490
GL		 797 mrq->cmd->error = ret;
798 mmc_request_done(mmc, mrq);
799}
800
2fb55956 801static int tmio_mmc_clk_enable(struct tmio_mmc_host *host)
8c102a96 802{
4fe2ec57 803 if (!host->clk_enable)
8c102a96
GL		 804 return -ENOTSUPP;
805
2fb55956 806 return host->clk_enable(host);
8c102a96
GL		 807}
808
619b08d4 809static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd)
b958a67c
GL		 810{
811 struct mmc_host *mmc = host->mmc;
619b08d4
GL		 812 int ret = 0;
813
814 /* .set_ios() is returning void, so, no chance to report an error */
b958a67c 815
9d731e75
CB		 816 if (host->set_pwr)
817 host->set_pwr(host->pdev, 1);
818
619b08d4
GL		 819 if (!IS_ERR(mmc->supply.vmmc)) {
820 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
821 /*
822 * Attention: empiric value. With a b43 WiFi SDIO card this
823 * delay proved necessary for reliable card-insertion probing.
824 * 100us were not enough. Is this the same 140us delay, as in
825 * tmio_mmc_set_ios()?
826 */
827 udelay(200);
828 }
829 /*
830 * It seems, VccQ should be switched on after Vcc, this is also what the
831 * omap_hsmmc.c driver does.
832 */
833 if (!IS_ERR(mmc->supply.vqmmc) && !ret) {
6d1d6b47 834 ret = regulator_enable(mmc->supply.vqmmc);
619b08d4
GL		 835 udelay(200);
836 }
6d1d6b47
GL		 837
838 if (ret < 0)
839 dev_dbg(&host->pdev->dev, "Regulators failed to power up: %d\n",
840 ret);
619b08d4
GL		 841}
842
843static void tmio_mmc_power_off(struct tmio_mmc_host *host)
844{
845 struct mmc_host *mmc = host->mmc;
846
847 if (!IS_ERR(mmc->supply.vqmmc))
848 regulator_disable(mmc->supply.vqmmc);
849
b958a67c 850 if (!IS_ERR(mmc->supply.vmmc))
619b08d4 851 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
9d731e75
CB		 852
853 if (host->set_pwr)
854 host->set_pwr(host->pdev, 0);
b958a67c
GL		 855}
856
9ae4ed7d
UH		 857static void tmio_mmc_set_bus_width(struct tmio_mmc_host *host,
858 unsigned char bus_width)
859{
860 switch (bus_width) {
861 case MMC_BUS_WIDTH_1:
862 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
863 break;
864 case MMC_BUS_WIDTH_4:
865 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
866 break;
867 }
868}
869
b6147490
GL		 870/* Set MMC clock / power.
871 * Note: This controller uses a simple divider scheme therefore it cannot
872 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
873 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
874 * slowest setting.
875 */
876static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
877{
878 struct tmio_mmc_host *host = mmc_priv(mmc);
4932bd64 879 struct device *dev = &host->pdev->dev;
df3ef2d3
GL		 880 unsigned long flags;
881
b9269fdd
GL		 882 mutex_lock(&host->ios_lock);
883
df3ef2d3
GL		 884 spin_lock_irqsave(&host->lock, flags);
885 if (host->mrq) {
886 if (IS_ERR(host->mrq)) {
4932bd64 887 dev_dbg(dev,
df3ef2d3
GL		 888 "%s.%d: concurrent .set_ios(), clk %u, mode %u\n",
889 current->comm, task_pid_nr(current),
890 ios->clock, ios->power_mode);
891 host->mrq = ERR_PTR(-EINTR);
892 } else {
4932bd64 893 dev_dbg(dev,
df3ef2d3
GL		 894 "%s.%d: CMD%u active since %lu, now %lu!\n",
895 current->comm, task_pid_nr(current),
896 host->mrq->cmd->opcode, host->last_req_ts, jiffies);
897 }
898 spin_unlock_irqrestore(&host->lock, flags);
b9269fdd
GL		 899
900 mutex_unlock(&host->ios_lock);
df3ef2d3
GL		 901 return;
902 }
903
904 host->mrq = ERR_PTR(-EBUSY);
905
906 spin_unlock_irqrestore(&host->lock, flags);
b6147490 907
3b292bb0
UH		 908 switch (ios->power_mode) {
909 case MMC_POWER_OFF:
910 tmio_mmc_power_off(host);
911 tmio_mmc_clk_stop(host);
912 break;
913 case MMC_POWER_UP:
3b292bb0 914 tmio_mmc_power_on(host, ios->vdd);
7fbc030d 915 tmio_mmc_set_clock(host, ios->clock);
9ae4ed7d 916 tmio_mmc_set_bus_width(host, ios->bus_width);
3b292bb0
UH		 917 break;
918 case MMC_POWER_ON:
919 tmio_mmc_set_clock(host, ios->clock);
3b292bb0
UH		 920 tmio_mmc_set_bus_width(host, ios->bus_width);
921 break;
922 }
b6147490
GL		 923
924 /* Let things settle. delay taken from winCE driver */
925 udelay(140);
df3ef2d3
GL		 926 if (PTR_ERR(host->mrq) == -EINTR)
927 dev_dbg(&host->pdev->dev,
928 "%s.%d: IOS interrupted: clk %u, mode %u",
929 current->comm, task_pid_nr(current),
930 ios->clock, ios->power_mode);
931 host->mrq = NULL;
b9269fdd 932
ae12d250
UH		 933 host->clk_cache = ios->clock;
934
b9269fdd 935 mutex_unlock(&host->ios_lock);
b6147490
GL		 936}
937
938static int tmio_mmc_get_ro(struct mmc_host *mmc)
939{
940 struct tmio_mmc_host *host = mmc_priv(mmc);
941 struct tmio_mmc_data *pdata = host->pdata;
3071cafb
GL		 942 int ret = mmc_gpio_get_ro(mmc);
943 if (ret >= 0)
944 return ret;
b6147490 945
0369483e 946 ret = !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
2c54506b 947 (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
0369483e
UH		 948
949 return ret;
b6147490
GL		 950}
951
bbf0208d
KM		 952static int tmio_multi_io_quirk(struct mmc_card *card,
953 unsigned int direction, int blk_size)
954{
955 struct tmio_mmc_host *host = mmc_priv(card->host);
bbf0208d 956
85c02ddd
KM		 957 if (host->multi_io_quirk)
958 return host->multi_io_quirk(card, direction, blk_size);
bbf0208d
KM		 959
960 return blk_size;
961}
962
452e5eef 963static struct mmc_host_ops tmio_mmc_ops = {
b6147490
GL		 964 .request = tmio_mmc_request,
965 .set_ios = tmio_mmc_set_ios,
966 .get_ro = tmio_mmc_get_ro,
2b63b341 967 .get_cd = mmc_gpio_get_cd,
b6147490 968 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
bbf0208d 969 .multi_io_quirk = tmio_multi_io_quirk,
b6147490
GL		 970};
971
05fae4a7 972static int tmio_mmc_init_ocr(struct tmio_mmc_host *host)
b958a67c
GL		 973{
974 struct tmio_mmc_data *pdata = host->pdata;
975 struct mmc_host *mmc = host->mmc;
976
977 mmc_regulator_get_supply(mmc);
978
05fae4a7 979 /* use ocr_mask if no regulator */
b958a67c 980 if (!mmc->ocr_avail)
05fae4a7
KM		 981 mmc->ocr_avail = pdata->ocr_mask;
982
983 /*
984 * try again.
985 * There is possibility that regulator has not been probed
986 */
987 if (!mmc->ocr_avail)
988 return -EPROBE_DEFER;
989
990 return 0;
b958a67c
GL		 991}
992
5a00a971
GL		 993static void tmio_mmc_of_parse(struct platform_device *pdev,
994 struct tmio_mmc_data *pdata)
995{
996 const struct device_node *np = pdev->dev.of_node;
997 if (!np)
998 return;
999
1000 if (of_get_property(np, "toshiba,mmc-wrprotect-disable", NULL))
1001 pdata->flags |= TMIO_MMC_WRPROTECT_DISABLE;
1002}
1003
94b110af
KM		 1004struct tmio_mmc_host*
1005tmio_mmc_host_alloc(struct platform_device *pdev)
b6147490 1006{
94b110af 1007 struct tmio_mmc_host *host;
b6147490 1008 struct mmc_host *mmc;
94b110af
KM		 1009
1010 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
1011 if (!mmc)
1012 return NULL;
1013
1014 host = mmc_priv(mmc);
1015 host->mmc = mmc;
1016 host->pdev = pdev;
1017
1018 return host;
1019}
1020EXPORT_SYMBOL(tmio_mmc_host_alloc);
1021
1022void tmio_mmc_host_free(struct tmio_mmc_host *host)
1023{
1024 mmc_free_host(host->mmc);
94b110af
KM		 1025}
1026EXPORT_SYMBOL(tmio_mmc_host_free);
1027
1028int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
1029 struct tmio_mmc_data *pdata)
1030{
1031 struct platform_device *pdev = _host->pdev;
1032 struct mmc_host *mmc = _host->mmc;
b6147490
GL		 1033 struct resource *res_ctl;
1034 int ret;
1035 u32 irq_mask = TMIO_MASK_CMD;
1036
5a00a971
GL		 1037 tmio_mmc_of_parse(pdev, pdata);
1038
7b952137 1039 if (!(pdata->flags & TMIO_MMC_HAS_IDLE_WAIT))
dfe9a229 1040 _host->write16_hook = NULL;
7b952137 1041
b6147490
GL		 1042 res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1043 if (!res_ctl)
1044 return -EINVAL;
1045
274a752b
SB		 1046 ret = mmc_of_parse(mmc);
1047 if (ret < 0)
1048 goto host_free;
5a00a971 1049
b6147490 1050 _host->pdata = pdata;
b6147490
GL		 1051 platform_set_drvdata(pdev, mmc);
1052
9d731e75 1053 _host->set_pwr = pdata->set_pwr;
b6147490
GL		 1054 _host->set_clk_div = pdata->set_clk_div;
1055
05fae4a7
KM		 1056 ret = tmio_mmc_init_ocr(_host);
1057 if (ret < 0)
1058 goto host_free;
1059
7df56bbb
IM		 1060 _host->ctl = devm_ioremap(&pdev->dev,
1061 res_ctl->start, resource_size(res_ctl));
b6147490
GL		 1062 if (!_host->ctl) {
1063 ret = -ENOMEM;
1064 goto host_free;
1065 }
1066
6a4679f3 1067 tmio_mmc_ops.card_busy = _host->card_busy;
452e5eef 1068 tmio_mmc_ops.start_signal_voltage_switch = _host->start_signal_voltage_switch;
b6147490 1069 mmc->ops = &tmio_mmc_ops;
452e5eef 1070
5a00a971 1071 mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
dd006b30 1072 mmc->caps2 |= pdata->capabilities2;
b6147490
GL		 1073 mmc->max_segs = 32;
1074 mmc->max_blk_size = 512;
09cbfeaf 1075 mmc->max_blk_count = (PAGE_SIZE / mmc->max_blk_size) *
b6147490
GL		 1076 mmc->max_segs;
1077 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1078 mmc->max_seg_size = mmc->max_req_size;
b6147490 1079
c8be24c2 1080 _host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD ||
2b1ac5c2 1081 mmc->caps & MMC_CAP_NEEDS_POLL ||
860951c5 1082 !mmc_card_is_removable(mmc) ||
5a00a971 1083 mmc->slot.cd_irq >= 0);
2b1ac5c2 1084
2fb55956 1085 if (tmio_mmc_clk_enable(_host) < 0) {
8c102a96
GL		 1086 mmc->f_max = pdata->hclk;
1087 mmc->f_min = mmc->f_max / 512;
1088 }
1089
bb98d9d1
SS		 1090 /*
1091 * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from
1092 * looping forever...
1093 */
1094 if (mmc->f_min == 0) {
1095 ret = -EINVAL;
1096 goto host_free;
1097 }
1098
cbb18b30 1099 /*
0369483e
UH		 1100 * While using internal tmio hardware logic for card detection, we need
1101 * to ensure it stays powered for it to work.
cbb18b30 1102 */
2b1ac5c2 1103 if (_host->native_hotplug)
cbb18b30
BH		 1104 pm_runtime_get_noresume(&pdev->dev);
1105
b6147490
GL		 1106 tmio_mmc_clk_stop(_host);
1107 tmio_mmc_reset(_host);
1108
2c54506b 1109 _host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK);
b6147490 1110 tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
e0337cc8
GL		 1111
1112 /* Unmask the IRQs we want to know about */
1113 if (!_host->chan_rx)
1114 irq_mask |= TMIO_MASK_READOP;
1115 if (!_host->chan_tx)
1116 irq_mask |= TMIO_MASK_WRITEOP;
1117 if (!_host->native_hotplug)
1118 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
1119
1120 _host->sdcard_irq_mask &= ~irq_mask;
1121
7501c431
UH		 1122 _host->sdio_irq_enabled = false;
1123 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
1124 _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
1125 sd_ctrl_write16(_host, CTL_SDIO_IRQ_MASK, _host->sdio_irq_mask);
1126 sd_ctrl_write16(_host, CTL_TRANSACTION_CTL, 0x0000);
1127 }
b6147490 1128
b6147490 1129 spin_lock_init(&_host->lock);
b9269fdd 1130 mutex_init(&_host->ios_lock);
b6147490
GL		 1131
1132 /* Init delayed work for request timeouts */
1133 INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work);
b9269fdd 1134 INIT_WORK(&_host->done, tmio_mmc_done_work);
b6147490
GL		 1135
1136 /* See if we also get DMA */
1137 tmio_mmc_request_dma(_host, pdata);
1138
0369483e
UH		 1139 pm_runtime_set_active(&pdev->dev);
1140 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1141 pm_runtime_use_autosuspend(&pdev->dev);
1142 pm_runtime_enable(&pdev->dev);
1143
8c102a96 1144 ret = mmc_add_host(mmc);
8c102a96
GL		 1145 if (ret < 0) {
1146 tmio_mmc_host_remove(_host);
1147 return ret;
1148 }
b6147490 1149
c419e611
RW		 1150 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1151
c8be24c2 1152 if (pdata->flags & TMIO_MMC_USE_GPIO_CD) {
214fc309 1153 ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0);
c8be24c2
GL		 1154 if (ret < 0) {
1155 tmio_mmc_host_remove(_host);
1156 return ret;
1157 }
d4d11449 1158 mmc_gpiod_request_cd_irq(mmc);
c8be24c2
GL		 1159 }
1160
b6147490
GL		 1161 return 0;
1162
b6147490 1163host_free:
b6147490
GL		 1164
1165 return ret;
1166}
1167EXPORT_SYMBOL(tmio_mmc_host_probe);
1168
1169void tmio_mmc_host_remove(struct tmio_mmc_host *host)
1170{
e6ee7182 1171 struct platform_device *pdev = host->pdev;
c8be24c2
GL		 1172 struct mmc_host *mmc = host->mmc;
1173
2b1ac5c2 1174 if (!host->native_hotplug)
7311bef0
GL		 1175 pm_runtime_get_sync(&pdev->dev);
1176
c419e611
RW		 1177 dev_pm_qos_hide_latency_limit(&pdev->dev);
1178
c8be24c2 1179 mmc_remove_host(mmc);
b9269fdd 1180 cancel_work_sync(&host->done);
b6147490
GL		 1181 cancel_delayed_work_sync(&host->delayed_reset_work);
1182 tmio_mmc_release_dma(host);
e6ee7182 1183
e6ee7182
GL		 1184 pm_runtime_put_sync(&pdev->dev);
1185 pm_runtime_disable(&pdev->dev);
b6147490
GL		 1186}
1187EXPORT_SYMBOL(tmio_mmc_host_remove);
1188
9ade7dbf 1189#ifdef CONFIG_PM
7311bef0
GL		 1190int tmio_mmc_host_runtime_suspend(struct device *dev)
1191{
ae12d250
UH		 1192 struct mmc_host *mmc = dev_get_drvdata(dev);
1193 struct tmio_mmc_host *host = mmc_priv(mmc);
1194
20e955c3
UH		 1195 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
1196
ae12d250
UH		 1197 if (host->clk_cache)
1198 tmio_mmc_clk_stop(host);
1199
00452c11 1200 if (host->clk_disable)
0ea28210 1201 host->clk_disable(host);
ae12d250 1202
7311bef0
GL		 1203 return 0;
1204}
1205EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend);
1206
1207int tmio_mmc_host_runtime_resume(struct device *dev)
1208{
1209 struct mmc_host *mmc = dev_get_drvdata(dev);
1210 struct tmio_mmc_host *host = mmc_priv(mmc);
7311bef0 1211
ae12d250 1212 tmio_mmc_reset(host);
2fb55956 1213 tmio_mmc_clk_enable(host);
ae12d250 1214
7fbc030d 1215 if (host->clk_cache)
ae12d250 1216 tmio_mmc_set_clock(host, host->clk_cache);
ae12d250 1217
162f43e3 1218 tmio_mmc_enable_dma(host, true);
7311bef0 1219
7311bef0
GL		 1220 return 0;
1221}
1222EXPORT_SYMBOL(tmio_mmc_host_runtime_resume);
710dec95 1223#endif
7311bef0 1224
b6147490 1225MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)