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mmc: sh_mobile_sdhi: add ocr_mask option
[linux-2.6-block.git] / drivers / mmc / host / tmio_mmc_pio.c
CommitLineData
b6147490
GL		 1/*
2 * linux/drivers/mmc/host/tmio_mmc_pio.c
3 *
bf96208f
WS		 4 * Copyright (C) 2016 Sang Engineering, Wolfram Sang
5 * Copyright (C) 2015-16 Renesas Electronics Corporation
b6147490
GL		 6 * Copyright (C) 2011 Guennadi Liakhovetski
7 * Copyright (C) 2007 Ian Molton
8 * Copyright (C) 2004 Ian Molton
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Driver for the MMC / SD / SDIO IP found in:
15 *
16 * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
17 *
18 * This driver draws mainly on scattered spec sheets, Reverse engineering
19 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
20 * support). (Further 4 bit support from a later datasheet).
21 *
22 * TODO:
23 * Investigate using a workqueue for PIO transfers
24 * Eliminate FIXMEs
25 * SDIO support
26 * Better Power management
27 * Handle MMC errors better
28 * double buffer support
29 *
30 */
31
32#include <linux/delay.h>
33#include <linux/device.h>
34#include <linux/highmem.h>
35#include <linux/interrupt.h>
36#include <linux/io.h>
37#include <linux/irq.h>
38#include <linux/mfd/tmio.h>
39#include <linux/mmc/host.h>
0f506a96 40#include <linux/mmc/mmc.h>
fd0ea65d 41#include <linux/mmc/slot-gpio.h>
b6147490
GL		 42#include <linux/module.h>
43#include <linux/pagemap.h>
44#include <linux/platform_device.h>
c419e611 45#include <linux/pm_qos.h>
e6ee7182 46#include <linux/pm_runtime.h>
619b08d4 47#include <linux/regulator/consumer.h>
b8d11962 48#include <linux/mmc/sdio.h>
b6147490 49#include <linux/scatterlist.h>
b6147490 50#include <linux/spinlock.h>
e3de2be7 51#include <linux/workqueue.h>
b6147490
GL		 52
53#include "tmio_mmc.h"
54
b6147490
GL		 55void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
56{
54680fe7 57 host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ);
2c54506b 58 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 59}
60
61void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
62{
54680fe7 63 host->sdcard_irq_mask |= (i & TMIO_MASK_IRQ);
2c54506b 64 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 65}
66
67static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)
68{
2c54506b 69 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, ~i);
b6147490
GL		 70}
71
72static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
73{
74 host->sg_len = data->sg_len;
75 host->sg_ptr = data->sg;
76 host->sg_orig = data->sg;
77 host->sg_off = 0;
78}
79
80static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
81{
82 host->sg_ptr = sg_next(host->sg_ptr);
83 host->sg_off = 0;
84 return --host->sg_len;
85}
86
0df9d2ea
TK		 87#define CMDREQ_TIMEOUT 5000
88
b6147490
GL		 89#ifdef CONFIG_MMC_DEBUG
90
91#define STATUS_TO_TEXT(a, status, i) \
92 do { \
93 if (status & TMIO_STAT_##a) { \
94 if (i++) \
95 printk(" | "); \
96 printk(#a); \
97 } \
98 } while (0)
99
100static void pr_debug_status(u32 status)
101{
102 int i = 0;
a3c76eb9 103 pr_debug("status: %08x = ", status);
b6147490
GL		 104 STATUS_TO_TEXT(CARD_REMOVE, status, i);
105 STATUS_TO_TEXT(CARD_INSERT, status, i);
106 STATUS_TO_TEXT(SIGSTATE, status, i);
107 STATUS_TO_TEXT(WRPROTECT, status, i);
108 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
109 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
110 STATUS_TO_TEXT(SIGSTATE_A, status, i);
111 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
112 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
113 STATUS_TO_TEXT(ILL_FUNC, status, i);
114 STATUS_TO_TEXT(CMD_BUSY, status, i);
115 STATUS_TO_TEXT(CMDRESPEND, status, i);
116 STATUS_TO_TEXT(DATAEND, status, i);
117 STATUS_TO_TEXT(CRCFAIL, status, i);
118 STATUS_TO_TEXT(DATATIMEOUT, status, i);
119 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
120 STATUS_TO_TEXT(RXOVERFLOW, status, i);
121 STATUS_TO_TEXT(TXUNDERRUN, status, i);
122 STATUS_TO_TEXT(RXRDY, status, i);
123 STATUS_TO_TEXT(TXRQ, status, i);
124 STATUS_TO_TEXT(ILL_ACCESS, status, i);
125 printk("\n");
126}
127
128#else
129#define pr_debug_status(s) do { } while (0)
130#endif
131
132static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
133{
134 struct tmio_mmc_host *host = mmc_priv(mmc);
135
7501c431
UH		 136 if (enable && !host->sdio_irq_enabled) {
137 /* Keep device active while SDIO irq is enabled */
138 pm_runtime_get_sync(mmc_dev(mmc));
139 host->sdio_irq_enabled = true;
140
54680fe7
SH		 141 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL &
142 ~TMIO_SDIO_STAT_IOIRQ;
b6147490 143 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
54680fe7 144 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
7501c431 145 } else if (!enable && host->sdio_irq_enabled) {
54680fe7
SH		 146 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
147 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
b6147490 148 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
7501c431
UH		 149
150 host->sdio_irq_enabled = false;
0369483e
UH		 151 pm_runtime_mark_last_busy(mmc_dev(mmc));
152 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 153 }
154}
155
7fbc030d
WS		 156static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
157{
158 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
159 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
3d376fb2 160 msleep(host->pdata->flags & TMIO_MMC_MIN_RCAR2 ? 1 : 10);
7fbc030d
WS		 161
162 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
163 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
164 msleep(10);
165 }
166}
167
148634d2
WS		 168static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
169{
170 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
171 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
172 msleep(10);
173 }
174
175 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
176 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
3d376fb2 177 msleep(host->pdata->flags & TMIO_MMC_MIN_RCAR2 ? 5 : 10);
148634d2
WS		 178}
179
ae12d250
UH		 180static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
181 unsigned int new_clock)
b6147490
GL		 182{
183 u32 clk = 0, clock;
184
148634d2
WS		 185 if (new_clock == 0) {
186 tmio_mmc_clk_stop(host);
187 return;
188 }
2fb55956 189
148634d2
WS		 190 if (host->clk_update)
191 clock = host->clk_update(host, new_clock) / 512;
192 else
193 clock = host->mmc->f_min;
da29fe2b 194
148634d2
WS		 195 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
196 clock <<= 1;
197
198 /* 1/1 clock is option */
199 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1))
200 clk |= 0xff;
b6147490
GL		 201
202 if (host->set_clk_div)
bf96208f 203 host->set_clk_div(host->pdev, (clk >> 22) & 1);
b6147490 204
14d5828f
WS		 205 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
206 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
bf96208f 207 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
3d376fb2 208 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
04e24b80 209 msleep(10);
7fbc030d
WS		 210
211 tmio_mmc_clk_start(host);
b6147490
GL		 212}
213
b6147490
GL		 214static void tmio_mmc_reset(struct tmio_mmc_host *host)
215{
216 /* FIXME - should we set stop clock reg here */
217 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
5d60e500 218 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 219 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
b6147490
GL		 220 msleep(10);
221 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
5d60e500 222 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 223 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
b6147490
GL		 224 msleep(10);
225}
226
227static void tmio_mmc_reset_work(struct work_struct *work)
228{
229 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
230 delayed_reset_work.work);
231 struct mmc_request *mrq;
232 unsigned long flags;
233
234 spin_lock_irqsave(&host->lock, flags);
235 mrq = host->mrq;
236
df3ef2d3
GL		 237 /*
238 * is request already finished? Since we use a non-blocking
239 * cancel_delayed_work(), it can happen, that a .set_ios() call preempts
240 * us, so, have to check for IS_ERR(host->mrq)
241 */
242 if (IS_ERR_OR_NULL(mrq)
b6147490 243 || time_is_after_jiffies(host->last_req_ts +
0df9d2ea 244 msecs_to_jiffies(CMDREQ_TIMEOUT))) {
b6147490
GL		 245 spin_unlock_irqrestore(&host->lock, flags);
246 return;
247 }
248
249 dev_warn(&host->pdev->dev,
250 "timeout waiting for hardware interrupt (CMD%u)\n",
251 mrq->cmd->opcode);
252
253 if (host->data)
254 host->data->error = -ETIMEDOUT;
255 else if (host->cmd)
256 host->cmd->error = -ETIMEDOUT;
257 else
258 mrq->cmd->error = -ETIMEDOUT;
259
260 host->cmd = NULL;
261 host->data = NULL;
b6147490
GL		 262 host->force_pio = false;
263
264 spin_unlock_irqrestore(&host->lock, flags);
265
266 tmio_mmc_reset(host);
267
df3ef2d3
GL		 268 /* Ready for new calls */
269 host->mrq = NULL;
270
e3de2be7 271 tmio_mmc_abort_dma(host);
b6147490
GL		 272 mmc_request_done(host->mmc, mrq);
273}
274
df3ef2d3 275/* called with host->lock held, interrupts disabled */
b6147490
GL		 276static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
277{
b9269fdd
GL		 278 struct mmc_request *mrq;
279 unsigned long flags;
b6147490 280
b9269fdd
GL		 281 spin_lock_irqsave(&host->lock, flags);
282
283 mrq = host->mrq;
284 if (IS_ERR_OR_NULL(mrq)) {
285 spin_unlock_irqrestore(&host->lock, flags);
b6147490 286 return;
b9269fdd 287 }
b6147490 288
b6147490
GL		 289 host->cmd = NULL;
290 host->data = NULL;
291 host->force_pio = false;
292
293 cancel_delayed_work(&host->delayed_reset_work);
294
df3ef2d3 295 host->mrq = NULL;
b9269fdd 296 spin_unlock_irqrestore(&host->lock, flags);
df3ef2d3 297
e3de2be7
GL		 298 if (mrq->cmd->error || (mrq->data && mrq->data->error))
299 tmio_mmc_abort_dma(host);
300
b6147490
GL		 301 mmc_request_done(host->mmc, mrq);
302}
303
b9269fdd
GL		 304static void tmio_mmc_done_work(struct work_struct *work)
305{
306 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
307 done);
308 tmio_mmc_finish_request(host);
309}
310
b6147490
GL		 311/* These are the bitmasks the tmio chip requires to implement the MMC response
312 * types. Note that R1 and R6 are the same in this scheme. */
313#define APP_CMD 0x0040
314#define RESP_NONE 0x0300
315#define RESP_R1 0x0400
316#define RESP_R1B 0x0500
317#define RESP_R2 0x0600
318#define RESP_R3 0x0700
319#define DATA_PRESENT 0x0800
320#define TRANSFER_READ 0x1000
321#define TRANSFER_MULTI 0x2000
322#define SECURITY_CMD 0x4000
b8d11962 323#define NO_CMD12_ISSUE 0x4000 /* TMIO_MMC_HAVE_CMD12_CTRL */
b6147490
GL		 324
325static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
326{
327 struct mmc_data *data = host->data;
328 int c = cmd->opcode;
e23cd53c 329 u32 irq_mask = TMIO_MASK_CMD;
b6147490 330
0f506a96
GL		 331 /* CMD12 is handled by hardware */
332 if (cmd->opcode == MMC_STOP_TRANSMISSION && !cmd->arg) {
b6147490
GL		 333 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
334 return 0;
335 }
336
337 switch (mmc_resp_type(cmd)) {
338 case MMC_RSP_NONE: c |= RESP_NONE; break;
0bc0b6e8
WS		 339 case MMC_RSP_R1:
340 case MMC_RSP_R1_NO_CRC:
341 c |= RESP_R1; break;
b6147490
GL		 342 case MMC_RSP_R1B: c |= RESP_R1B; break;
343 case MMC_RSP_R2: c |= RESP_R2; break;
344 case MMC_RSP_R3: c |= RESP_R3; break;
345 default:
346 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
347 return -EINVAL;
348 }
349
350 host->cmd = cmd;
351
352/* FIXME - this seems to be ok commented out but the spec suggest this bit
353 * should be set when issuing app commands.
354 * if(cmd->flags & MMC_FLAG_ACMD)
355 * c |= APP_CMD;
356 */
357 if (data) {
358 c |= DATA_PRESENT;
359 if (data->blocks > 1) {
360 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
361 c |= TRANSFER_MULTI;
b8d11962
SU		 362
363 /*
364 * Disable auto CMD12 at IO_RW_EXTENDED when
365 * multiple block transfer
366 */
367 if ((host->pdata->flags & TMIO_MMC_HAVE_CMD12_CTRL) &&
368 (cmd->opcode == SD_IO_RW_EXTENDED))
369 c |= NO_CMD12_ISSUE;
b6147490
GL		 370 }
371 if (data->flags & MMC_DATA_READ)
372 c |= TRANSFER_READ;
373 }
374
e23cd53c
GL		 375 if (!host->native_hotplug)
376 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
377 tmio_mmc_enable_mmc_irqs(host, irq_mask);
b6147490
GL		 378
379 /* Fire off the command */
2c54506b 380 sd_ctrl_write32_as_16_and_16(host, CTL_ARG_REG, cmd->arg);
b6147490
GL		 381 sd_ctrl_write16(host, CTL_SD_CMD, c);
382
383 return 0;
384}
385
b9bd7ff8
KM		 386static void tmio_mmc_transfer_data(struct tmio_mmc_host *host,
387 unsigned short *buf,
388 unsigned int count)
389{
390 int is_read = host->data->flags & MMC_DATA_READ;
391 u8 *buf8;
392
393 /*
394 * Transfer the data
395 */
396 if (is_read)
397 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
398 else
399 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
400
401 /* if count was even number */
402 if (!(count & 0x1))
403 return;
404
405 /* if count was odd number */
406 buf8 = (u8 *)(buf + (count >> 1));
407
408 /*
409 * FIXME
410 *
411 * driver and this function are assuming that
412 * it is used as little endian
413 */
414 if (is_read)
415 *buf8 = sd_ctrl_read16(host, CTL_SD_DATA_PORT) & 0xff;
416 else
417 sd_ctrl_write16(host, CTL_SD_DATA_PORT, *buf8);
418}
419
b6147490
GL		 420/*
421 * This chip always returns (at least?) as much data as you ask for.
422 * I'm unsure what happens if you ask for less than a block. This should be
25985edc 423 * looked into to ensure that a funny length read doesn't hose the controller.
b6147490
GL		 424 */
425static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
426{
427 struct mmc_data *data = host->data;
428 void *sg_virt;
429 unsigned short *buf;
430 unsigned int count;
431 unsigned long flags;
432
433 if ((host->chan_tx || host->chan_rx) && !host->force_pio) {
434 pr_err("PIO IRQ in DMA mode!\n");
435 return;
436 } else if (!data) {
437 pr_debug("Spurious PIO IRQ\n");
438 return;
439 }
440
441 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
442 buf = (unsigned short *)(sg_virt + host->sg_off);
443
444 count = host->sg_ptr->length - host->sg_off;
445 if (count > data->blksz)
446 count = data->blksz;
447
448 pr_debug("count: %08x offset: %08x flags %08x\n",
449 count, host->sg_off, data->flags);
450
451 /* Transfer the data */
b9bd7ff8 452 tmio_mmc_transfer_data(host, buf, count);
b6147490
GL		 453
454 host->sg_off += count;
455
456 tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
457
458 if (host->sg_off == host->sg_ptr->length)
459 tmio_mmc_next_sg(host);
460
461 return;
462}
463
464static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host)
465{
466 if (host->sg_ptr == &host->bounce_sg) {
467 unsigned long flags;
468 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
469 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
470 tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
471 }
472}
473
474/* needs to be called with host->lock held */
475void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
476{
477 struct mmc_data *data = host->data;
478 struct mmc_command *stop;
479
480 host->data = NULL;
481
482 if (!data) {
483 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
484 return;
485 }
486 stop = data->stop;
487
488 /* FIXME - return correct transfer count on errors */
489 if (!data->error)
490 data->bytes_xfered = data->blocks * data->blksz;
491 else
492 data->bytes_xfered = 0;
493
494 pr_debug("Completed data request\n");
495
496 /*
497 * FIXME: other drivers allow an optional stop command of any given type
498 * which we dont do, as the chip can auto generate them.
499 * Perhaps we can be smarter about when to use auto CMD12 and
500 * only issue the auto request when we know this is the desired
501 * stop command, allowing fallback to the stop command the
502 * upper layers expect. For now, we do what works.
503 */
504
505 if (data->flags & MMC_DATA_READ) {
506 if (host->chan_rx && !host->force_pio)
507 tmio_mmc_check_bounce_buffer(host);
508 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
509 host->mrq);
510 } else {
511 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
512 host->mrq);
513 }
514
515 if (stop) {
0f506a96 516 if (stop->opcode == MMC_STOP_TRANSMISSION && !stop->arg)
b6147490
GL		 517 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
518 else
519 BUG();
520 }
521
b9269fdd 522 schedule_work(&host->done);
b6147490
GL		 523}
524
525static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
526{
527 struct mmc_data *data;
528 spin_lock(&host->lock);
529 data = host->data;
530
531 if (!data)
532 goto out;
533
534 if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
2c54506b 535 u32 status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);
81e888da
SU		 536 bool done = false;
537
b6147490
GL		 538 /*
539 * Has all data been written out yet? Testing on SuperH showed,
540 * that in most cases the first interrupt comes already with the
541 * BUSY status bit clear, but on some operations, like mount or
542 * in the beginning of a write / sync / umount, there is one
543 * DATAEND interrupt with the BUSY bit set, in this cases
544 * waiting for one more interrupt fixes the problem.
545 */
81e888da 546 if (host->pdata->flags & TMIO_MMC_HAS_IDLE_WAIT) {
a21553c9 547 if (status & TMIO_STAT_SCLKDIVEN)
81e888da
SU		 548 done = true;
549 } else {
550 if (!(status & TMIO_STAT_CMD_BUSY))
551 done = true;
552 }
553
554 if (done) {
b6147490
GL		 555 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
556 tasklet_schedule(&host->dma_complete);
557 }
558 } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
559 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
560 tasklet_schedule(&host->dma_complete);
561 } else {
562 tmio_mmc_do_data_irq(host);
563 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
564 }
565out:
566 spin_unlock(&host->lock);
567}
568
569static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
570 unsigned int stat)
571{
572 struct mmc_command *cmd = host->cmd;
573 int i, addr;
574
575 spin_lock(&host->lock);
576
577 if (!host->cmd) {
578 pr_debug("Spurious CMD irq\n");
579 goto out;
580 }
581
582 host->cmd = NULL;
583
584 /* This controller is sicker than the PXA one. Not only do we need to
585 * drop the top 8 bits of the first response word, we also need to
586 * modify the order of the response for short response command types.
587 */
588
589 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
2c54506b 590 cmd->resp[i] = sd_ctrl_read16_and_16_as_32(host, addr);
b6147490
GL		 591
592 if (cmd->flags & MMC_RSP_136) {
593 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
594 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
595 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
596 cmd->resp[3] <<= 8;
597 } else if (cmd->flags & MMC_RSP_R3) {
598 cmd->resp[0] = cmd->resp[3];
599 }
600
601 if (stat & TMIO_STAT_CMDTIMEOUT)
602 cmd->error = -ETIMEDOUT;
603 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
604 cmd->error = -EILSEQ;
605
606 /* If there is data to handle we enable data IRQs here, and
607 * we will ultimatley finish the request in the data_end handler.
608 * If theres no data or we encountered an error, finish now.
609 */
610 if (host->data && !cmd->error) {
611 if (host->data->flags & MMC_DATA_READ) {
612 if (host->force_pio || !host->chan_rx)
613 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
614 else
615 tasklet_schedule(&host->dma_issue);
616 } else {
617 if (host->force_pio || !host->chan_tx)
618 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
619 else
620 tasklet_schedule(&host->dma_issue);
621 }
622 } else {
b9269fdd 623 schedule_work(&host->done);
b6147490
GL		 624 }
625
626out:
627 spin_unlock(&host->lock);
628}
629
7729c7a2
SH		 630static bool __tmio_mmc_card_detect_irq(struct tmio_mmc_host *host,
631 int ireg, int status)
632{
633 struct mmc_host *mmc = host->mmc;
b6147490 634
e312eb1e
PP		 635 /* Card insert / remove attempts */
636 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
637 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
638 TMIO_STAT_CARD_REMOVE);
71d111cd
GL		 639 if ((((ireg & TMIO_STAT_CARD_REMOVE) && mmc->card) ||
640 ((ireg & TMIO_STAT_CARD_INSERT) && !mmc->card)) &&
641 !work_pending(&mmc->detect.work))
b9269fdd 642 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
7729c7a2 643 return true;
b6147490
GL		 644 }
645
7729c7a2
SH		 646 return false;
647}
648
7729c7a2
SH		 649static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host,
650 int ireg, int status)
651{
e312eb1e
PP		 652 /* Command completion */
653 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
654 tmio_mmc_ack_mmc_irqs(host,
655 TMIO_STAT_CMDRESPEND |
656 TMIO_STAT_CMDTIMEOUT);
657 tmio_mmc_cmd_irq(host, status);
7729c7a2 658 return true;
e312eb1e 659 }
b6147490 660
e312eb1e
PP		 661 /* Data transfer */
662 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
663 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
664 tmio_mmc_pio_irq(host);
7729c7a2 665 return true;
e312eb1e 666 }
b6147490 667
e312eb1e
PP		 668 /* Data transfer completion */
669 if (ireg & TMIO_STAT_DATAEND) {
670 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
671 tmio_mmc_data_irq(host);
7729c7a2 672 return true;
b6147490 673 }
e312eb1e 674
7729c7a2
SH		 675 return false;
676}
677
4da98670 678static void tmio_mmc_sdio_irq(int irq, void *devid)
7729c7a2
SH		 679{
680 struct tmio_mmc_host *host = devid;
681 struct mmc_host *mmc = host->mmc;
682 struct tmio_mmc_data *pdata = host->pdata;
683 unsigned int ireg, status;
6b98757e 684 unsigned int sdio_status;
7729c7a2
SH		 685
686 if (!(pdata->flags & TMIO_MMC_SDIO_IRQ))
4da98670 687 return;
7729c7a2
SH		 688
689 status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
690 ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdcard_irq_mask;
691
6b98757e
SU		 692 sdio_status = status & ~TMIO_SDIO_MASK_ALL;
693 if (pdata->flags & TMIO_MMC_SDIO_STATUS_QUIRK)
694 sdio_status |= 6;
695
696 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status);
7729c7a2
SH		 697
698 if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ)
699 mmc_signal_sdio_irq(mmc);
7729c7a2 700}
7729c7a2
SH		 701
702irqreturn_t tmio_mmc_irq(int irq, void *devid)
703{
704 struct tmio_mmc_host *host = devid;
705 unsigned int ireg, status;
706
2c54506b 707 status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);
95840126
WS		 708 ireg = status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask;
709
710 pr_debug_status(status);
711 pr_debug_status(ireg);
712
713 /* Clear the status except the interrupt status */
2c54506b 714 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, TMIO_MASK_IRQ);
7729c7a2 715
7729c7a2
SH		 716 if (__tmio_mmc_card_detect_irq(host, ireg, status))
717 return IRQ_HANDLED;
718 if (__tmio_mmc_sdcard_irq(host, ireg, status))
719 return IRQ_HANDLED;
720
721 tmio_mmc_sdio_irq(irq, devid);
b6147490 722
b6147490
GL		 723 return IRQ_HANDLED;
724}
8e7bfdb3 725EXPORT_SYMBOL(tmio_mmc_irq);
b6147490
GL		 726
727static int tmio_mmc_start_data(struct tmio_mmc_host *host,
728 struct mmc_data *data)
729{
730 struct tmio_mmc_data *pdata = host->pdata;
731
732 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
733 data->blksz, data->blocks);
734
0bc0b6e8
WS		 735 /* Some hardware cannot perform 2 byte requests in 4/8 bit mode */
736 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4 ||
737 host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
b6147490
GL		 738 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
739
740 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
0bc0b6e8 741 pr_err("%s: %d byte block unsupported in 4/8 bit mode\n",
b6147490
GL		 742 mmc_hostname(host->mmc), data->blksz);
743 return -EINVAL;
744 }
745 }
746
747 tmio_mmc_init_sg(host, data);
748 host->data = data;
749
750 /* Set transfer length / blocksize */
751 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
752 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
753
754 tmio_mmc_start_dma(host, data);
755
756 return 0;
757}
758
759/* Process requests from the MMC layer */
760static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
761{
762 struct tmio_mmc_host *host = mmc_priv(mmc);
df3ef2d3 763 unsigned long flags;
b6147490
GL		 764 int ret;
765
df3ef2d3
GL		 766 spin_lock_irqsave(&host->lock, flags);
767
768 if (host->mrq) {
b6147490 769 pr_debug("request not null\n");
df3ef2d3
GL		 770 if (IS_ERR(host->mrq)) {
771 spin_unlock_irqrestore(&host->lock, flags);
772 mrq->cmd->error = -EAGAIN;
773 mmc_request_done(mmc, mrq);
774 return;
775 }
776 }
b6147490
GL		 777
778 host->last_req_ts = jiffies;
779 wmb();
780 host->mrq = mrq;
781
df3ef2d3
GL		 782 spin_unlock_irqrestore(&host->lock, flags);
783
b6147490
GL		 784 if (mrq->data) {
785 ret = tmio_mmc_start_data(host, mrq->data);
786 if (ret)
787 goto fail;
788 }
789
790 ret = tmio_mmc_start_command(host, mrq->cmd);
791 if (!ret) {
792 schedule_delayed_work(&host->delayed_reset_work,
0df9d2ea 793 msecs_to_jiffies(CMDREQ_TIMEOUT));
b6147490
GL		 794 return;
795 }
796
797fail:
b6147490 798 host->force_pio = false;
df3ef2d3 799 host->mrq = NULL;
b6147490
GL		 800 mrq->cmd->error = ret;
801 mmc_request_done(mmc, mrq);
802}
803
2fb55956 804static int tmio_mmc_clk_enable(struct tmio_mmc_host *host)
8c102a96 805{
4fe2ec57 806 if (!host->clk_enable)
8c102a96
GL		 807 return -ENOTSUPP;
808
2fb55956 809 return host->clk_enable(host);
8c102a96
GL		 810}
811
619b08d4 812static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd)
b958a67c
GL		 813{
814 struct mmc_host *mmc = host->mmc;
619b08d4
GL		 815 int ret = 0;
816
817 /* .set_ios() is returning void, so, no chance to report an error */
b958a67c 818
9d731e75
CB		 819 if (host->set_pwr)
820 host->set_pwr(host->pdev, 1);
821
619b08d4
GL		 822 if (!IS_ERR(mmc->supply.vmmc)) {
823 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
824 /*
825 * Attention: empiric value. With a b43 WiFi SDIO card this
826 * delay proved necessary for reliable card-insertion probing.
827 * 100us were not enough. Is this the same 140us delay, as in
828 * tmio_mmc_set_ios()?
829 */
830 udelay(200);
831 }
832 /*
833 * It seems, VccQ should be switched on after Vcc, this is also what the
834 * omap_hsmmc.c driver does.
835 */
836 if (!IS_ERR(mmc->supply.vqmmc) && !ret) {
6d1d6b47 837 ret = regulator_enable(mmc->supply.vqmmc);
619b08d4
GL		 838 udelay(200);
839 }
6d1d6b47
GL		 840
841 if (ret < 0)
842 dev_dbg(&host->pdev->dev, "Regulators failed to power up: %d\n",
843 ret);
619b08d4
GL		 844}
845
846static void tmio_mmc_power_off(struct tmio_mmc_host *host)
847{
848 struct mmc_host *mmc = host->mmc;
849
850 if (!IS_ERR(mmc->supply.vqmmc))
851 regulator_disable(mmc->supply.vqmmc);
852
b958a67c 853 if (!IS_ERR(mmc->supply.vmmc))
619b08d4 854 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
9d731e75
CB		 855
856 if (host->set_pwr)
857 host->set_pwr(host->pdev, 0);
b958a67c
GL		 858}
859
9ae4ed7d
UH		 860static void tmio_mmc_set_bus_width(struct tmio_mmc_host *host,
861 unsigned char bus_width)
862{
0bc0b6e8
WS		 863 u16 reg = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT)
864 & ~(CARD_OPT_WIDTH | CARD_OPT_WIDTH8);
865
866 /* reg now applies to MMC_BUS_WIDTH_4 */
867 if (bus_width == MMC_BUS_WIDTH_1)
868 reg |= CARD_OPT_WIDTH;
869 else if (bus_width == MMC_BUS_WIDTH_8)
870 reg |= CARD_OPT_WIDTH8;
871
872 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, reg);
9ae4ed7d
UH		 873}
874
b6147490
GL		 875/* Set MMC clock / power.
876 * Note: This controller uses a simple divider scheme therefore it cannot
877 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
878 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
879 * slowest setting.
880 */
881static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
882{
883 struct tmio_mmc_host *host = mmc_priv(mmc);
4932bd64 884 struct device *dev = &host->pdev->dev;
df3ef2d3
GL		 885 unsigned long flags;
886
b9269fdd
GL		 887 mutex_lock(&host->ios_lock);
888
df3ef2d3
GL		 889 spin_lock_irqsave(&host->lock, flags);
890 if (host->mrq) {
891 if (IS_ERR(host->mrq)) {
4932bd64 892 dev_dbg(dev,
df3ef2d3
GL		 893 "%s.%d: concurrent .set_ios(), clk %u, mode %u\n",
894 current->comm, task_pid_nr(current),
895 ios->clock, ios->power_mode);
896 host->mrq = ERR_PTR(-EINTR);
897 } else {
4932bd64 898 dev_dbg(dev,
df3ef2d3
GL		 899 "%s.%d: CMD%u active since %lu, now %lu!\n",
900 current->comm, task_pid_nr(current),
901 host->mrq->cmd->opcode, host->last_req_ts, jiffies);
902 }
903 spin_unlock_irqrestore(&host->lock, flags);
b9269fdd
GL		 904
905 mutex_unlock(&host->ios_lock);
df3ef2d3
GL		 906 return;
907 }
908
909 host->mrq = ERR_PTR(-EBUSY);
910
911 spin_unlock_irqrestore(&host->lock, flags);
b6147490 912
3b292bb0
UH		 913 switch (ios->power_mode) {
914 case MMC_POWER_OFF:
915 tmio_mmc_power_off(host);
916 tmio_mmc_clk_stop(host);
917 break;
918 case MMC_POWER_UP:
3b292bb0 919 tmio_mmc_power_on(host, ios->vdd);
7fbc030d 920 tmio_mmc_set_clock(host, ios->clock);
9ae4ed7d 921 tmio_mmc_set_bus_width(host, ios->bus_width);
3b292bb0
UH		 922 break;
923 case MMC_POWER_ON:
924 tmio_mmc_set_clock(host, ios->clock);
3b292bb0
UH		 925 tmio_mmc_set_bus_width(host, ios->bus_width);
926 break;
927 }
b6147490
GL		 928
929 /* Let things settle. delay taken from winCE driver */
930 udelay(140);
df3ef2d3
GL		 931 if (PTR_ERR(host->mrq) == -EINTR)
932 dev_dbg(&host->pdev->dev,
933 "%s.%d: IOS interrupted: clk %u, mode %u",
934 current->comm, task_pid_nr(current),
935 ios->clock, ios->power_mode);
936 host->mrq = NULL;
b9269fdd 937
ae12d250
UH		 938 host->clk_cache = ios->clock;
939
b9269fdd 940 mutex_unlock(&host->ios_lock);
b6147490
GL		 941}
942
943static int tmio_mmc_get_ro(struct mmc_host *mmc)
944{
945 struct tmio_mmc_host *host = mmc_priv(mmc);
946 struct tmio_mmc_data *pdata = host->pdata;
3071cafb
GL		 947 int ret = mmc_gpio_get_ro(mmc);
948 if (ret >= 0)
949 return ret;
b6147490 950
0369483e 951 ret = !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
2c54506b 952 (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
0369483e
UH		 953
954 return ret;
b6147490
GL		 955}
956
bbf0208d
KM		 957static int tmio_multi_io_quirk(struct mmc_card *card,
958 unsigned int direction, int blk_size)
959{
960 struct tmio_mmc_host *host = mmc_priv(card->host);
bbf0208d 961
85c02ddd
KM		 962 if (host->multi_io_quirk)
963 return host->multi_io_quirk(card, direction, blk_size);
bbf0208d
KM		 964
965 return blk_size;
966}
967
452e5eef 968static struct mmc_host_ops tmio_mmc_ops = {
b6147490
GL		 969 .request = tmio_mmc_request,
970 .set_ios = tmio_mmc_set_ios,
971 .get_ro = tmio_mmc_get_ro,
2b63b341 972 .get_cd = mmc_gpio_get_cd,
b6147490 973 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
bbf0208d 974 .multi_io_quirk = tmio_multi_io_quirk,
b6147490
GL		 975};
976
05fae4a7 977static int tmio_mmc_init_ocr(struct tmio_mmc_host *host)
b958a67c
GL		 978{
979 struct tmio_mmc_data *pdata = host->pdata;
980 struct mmc_host *mmc = host->mmc;
981
982 mmc_regulator_get_supply(mmc);
983
05fae4a7 984 /* use ocr_mask if no regulator */
b958a67c 985 if (!mmc->ocr_avail)
05fae4a7
KM		 986 mmc->ocr_avail = pdata->ocr_mask;
987
988 /*
989 * try again.
990 * There is possibility that regulator has not been probed
991 */
992 if (!mmc->ocr_avail)
993 return -EPROBE_DEFER;
994
995 return 0;
b958a67c
GL		 996}
997
5a00a971
GL		 998static void tmio_mmc_of_parse(struct platform_device *pdev,
999 struct tmio_mmc_data *pdata)
1000{
1001 const struct device_node *np = pdev->dev.of_node;
1002 if (!np)
1003 return;
1004
1005 if (of_get_property(np, "toshiba,mmc-wrprotect-disable", NULL))
1006 pdata->flags |= TMIO_MMC_WRPROTECT_DISABLE;
1007}
1008
94b110af
KM		 1009struct tmio_mmc_host*
1010tmio_mmc_host_alloc(struct platform_device *pdev)
b6147490 1011{
94b110af 1012 struct tmio_mmc_host *host;
b6147490 1013 struct mmc_host *mmc;
94b110af
KM		 1014
1015 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
1016 if (!mmc)
1017 return NULL;
1018
1019 host = mmc_priv(mmc);
1020 host->mmc = mmc;
1021 host->pdev = pdev;
1022
1023 return host;
1024}
1025EXPORT_SYMBOL(tmio_mmc_host_alloc);
1026
1027void tmio_mmc_host_free(struct tmio_mmc_host *host)
1028{
1029 mmc_free_host(host->mmc);
94b110af
KM		 1030}
1031EXPORT_SYMBOL(tmio_mmc_host_free);
1032
1033int tmio_mmc_host_probe(struct tmio_mmc_host *_host,
1034 struct tmio_mmc_data *pdata)
1035{
1036 struct platform_device *pdev = _host->pdev;
1037 struct mmc_host *mmc = _host->mmc;
b6147490
GL		 1038 struct resource *res_ctl;
1039 int ret;
1040 u32 irq_mask = TMIO_MASK_CMD;
1041
5a00a971
GL		 1042 tmio_mmc_of_parse(pdev, pdata);
1043
7b952137 1044 if (!(pdata->flags & TMIO_MMC_HAS_IDLE_WAIT))
dfe9a229 1045 _host->write16_hook = NULL;
7b952137 1046
b6147490
GL		 1047 res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1048 if (!res_ctl)
1049 return -EINVAL;
1050
274a752b
SB		 1051 ret = mmc_of_parse(mmc);
1052 if (ret < 0)
1053 goto host_free;
5a00a971 1054
b6147490 1055 _host->pdata = pdata;
b6147490
GL		 1056 platform_set_drvdata(pdev, mmc);
1057
9d731e75 1058 _host->set_pwr = pdata->set_pwr;
b6147490
GL		 1059 _host->set_clk_div = pdata->set_clk_div;
1060
05fae4a7
KM		 1061 ret = tmio_mmc_init_ocr(_host);
1062 if (ret < 0)
1063 goto host_free;
1064
7df56bbb
IM		 1065 _host->ctl = devm_ioremap(&pdev->dev,
1066 res_ctl->start, resource_size(res_ctl));
b6147490
GL		 1067 if (!_host->ctl) {
1068 ret = -ENOMEM;
1069 goto host_free;
1070 }
1071
6a4679f3 1072 tmio_mmc_ops.card_busy = _host->card_busy;
452e5eef 1073 tmio_mmc_ops.start_signal_voltage_switch = _host->start_signal_voltage_switch;
b6147490 1074 mmc->ops = &tmio_mmc_ops;
452e5eef 1075
5a00a971 1076 mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
dd006b30 1077 mmc->caps2 |= pdata->capabilities2;
b6147490
GL		 1078 mmc->max_segs = 32;
1079 mmc->max_blk_size = 512;
09cbfeaf 1080 mmc->max_blk_count = (PAGE_SIZE / mmc->max_blk_size) *
b6147490
GL		 1081 mmc->max_segs;
1082 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1083 mmc->max_seg_size = mmc->max_req_size;
b6147490 1084
c8be24c2 1085 _host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD ||
2b1ac5c2 1086 mmc->caps & MMC_CAP_NEEDS_POLL ||
860951c5 1087 !mmc_card_is_removable(mmc) ||
5a00a971 1088 mmc->slot.cd_irq >= 0);
2b1ac5c2 1089
0bc0b6e8
WS		 1090 /*
1091 * On Gen2+, eMMC with NONREMOVABLE currently fails because native
1092 * hotplug gets disabled. It seems RuntimePM related yet we need further
1093 * research. Since we are planning a PM overhaul anyway, let's enforce
1094 * for now the device being active by enabling native hotplug always.
1095 */
1096 if (pdata->flags & TMIO_MMC_MIN_RCAR2)
1097 _host->native_hotplug = true;
1098
2fb55956 1099 if (tmio_mmc_clk_enable(_host) < 0) {
8c102a96
GL		 1100 mmc->f_max = pdata->hclk;
1101 mmc->f_min = mmc->f_max / 512;
1102 }
1103
bb98d9d1
SS		 1104 /*
1105 * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from
1106 * looping forever...
1107 */
1108 if (mmc->f_min == 0) {
1109 ret = -EINVAL;
1110 goto host_free;
1111 }
1112
cbb18b30 1113 /*
0369483e
UH		 1114 * While using internal tmio hardware logic for card detection, we need
1115 * to ensure it stays powered for it to work.
cbb18b30 1116 */
2b1ac5c2 1117 if (_host->native_hotplug)
cbb18b30
BH		 1118 pm_runtime_get_noresume(&pdev->dev);
1119
b6147490
GL		 1120 tmio_mmc_clk_stop(_host);
1121 tmio_mmc_reset(_host);
1122
2c54506b 1123 _host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK);
b6147490 1124 tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
e0337cc8
GL		 1125
1126 /* Unmask the IRQs we want to know about */
1127 if (!_host->chan_rx)
1128 irq_mask |= TMIO_MASK_READOP;
1129 if (!_host->chan_tx)
1130 irq_mask |= TMIO_MASK_WRITEOP;
1131 if (!_host->native_hotplug)
1132 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
1133
1134 _host->sdcard_irq_mask &= ~irq_mask;
1135
7501c431
UH		 1136 _host->sdio_irq_enabled = false;
1137 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
1138 _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
1139 sd_ctrl_write16(_host, CTL_SDIO_IRQ_MASK, _host->sdio_irq_mask);
1140 sd_ctrl_write16(_host, CTL_TRANSACTION_CTL, 0x0000);
1141 }
b6147490 1142
b6147490 1143 spin_lock_init(&_host->lock);
b9269fdd 1144 mutex_init(&_host->ios_lock);
b6147490
GL		 1145
1146 /* Init delayed work for request timeouts */
1147 INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work);
b9269fdd 1148 INIT_WORK(&_host->done, tmio_mmc_done_work);
b6147490
GL		 1149
1150 /* See if we also get DMA */
1151 tmio_mmc_request_dma(_host, pdata);
1152
0369483e
UH		 1153 pm_runtime_set_active(&pdev->dev);
1154 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1155 pm_runtime_use_autosuspend(&pdev->dev);
1156 pm_runtime_enable(&pdev->dev);
1157
8c102a96 1158 ret = mmc_add_host(mmc);
8c102a96
GL		 1159 if (ret < 0) {
1160 tmio_mmc_host_remove(_host);
1161 return ret;
1162 }
b6147490 1163
c419e611
RW		 1164 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1165
c8be24c2 1166 if (pdata->flags & TMIO_MMC_USE_GPIO_CD) {
214fc309 1167 ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0);
c8be24c2
GL		 1168 if (ret < 0) {
1169 tmio_mmc_host_remove(_host);
1170 return ret;
1171 }
d4d11449 1172 mmc_gpiod_request_cd_irq(mmc);
c8be24c2
GL		 1173 }
1174
b6147490
GL		 1175 return 0;
1176
b6147490 1177host_free:
b6147490
GL		 1178
1179 return ret;
1180}
1181EXPORT_SYMBOL(tmio_mmc_host_probe);
1182
1183void tmio_mmc_host_remove(struct tmio_mmc_host *host)
1184{
e6ee7182 1185 struct platform_device *pdev = host->pdev;
c8be24c2
GL		 1186 struct mmc_host *mmc = host->mmc;
1187
2b1ac5c2 1188 if (!host->native_hotplug)
7311bef0
GL		 1189 pm_runtime_get_sync(&pdev->dev);
1190
c419e611
RW		 1191 dev_pm_qos_hide_latency_limit(&pdev->dev);
1192
c8be24c2 1193 mmc_remove_host(mmc);
b9269fdd 1194 cancel_work_sync(&host->done);
b6147490
GL		 1195 cancel_delayed_work_sync(&host->delayed_reset_work);
1196 tmio_mmc_release_dma(host);
e6ee7182 1197
e6ee7182
GL		 1198 pm_runtime_put_sync(&pdev->dev);
1199 pm_runtime_disable(&pdev->dev);
b6147490
GL		 1200}
1201EXPORT_SYMBOL(tmio_mmc_host_remove);
1202
9ade7dbf 1203#ifdef CONFIG_PM
7311bef0
GL		 1204int tmio_mmc_host_runtime_suspend(struct device *dev)
1205{
ae12d250
UH		 1206 struct mmc_host *mmc = dev_get_drvdata(dev);
1207 struct tmio_mmc_host *host = mmc_priv(mmc);
1208
20e955c3
UH		 1209 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
1210
ae12d250
UH		 1211 if (host->clk_cache)
1212 tmio_mmc_clk_stop(host);
1213
00452c11 1214 if (host->clk_disable)
0ea28210 1215 host->clk_disable(host);
ae12d250 1216
7311bef0
GL		 1217 return 0;
1218}
1219EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend);
1220
1221int tmio_mmc_host_runtime_resume(struct device *dev)
1222{
1223 struct mmc_host *mmc = dev_get_drvdata(dev);
1224 struct tmio_mmc_host *host = mmc_priv(mmc);
7311bef0 1225
ae12d250 1226 tmio_mmc_reset(host);
2fb55956 1227 tmio_mmc_clk_enable(host);
ae12d250 1228
7fbc030d 1229 if (host->clk_cache)
ae12d250 1230 tmio_mmc_set_clock(host, host->clk_cache);
ae12d250 1231
162f43e3 1232 tmio_mmc_enable_dma(host, true);
7311bef0 1233
7311bef0
GL		 1234 return 0;
1235}
1236EXPORT_SYMBOL(tmio_mmc_host_runtime_resume);
710dec95 1237#endif
7311bef0 1238
b6147490 1239MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)