projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: tmio: control multiple block transfer mode
[linux-2.6-block.git] / drivers / mmc / host / tmio_mmc_pio.c
CommitLineData
b6147490
GL		 1/*
2 * linux/drivers/mmc/host/tmio_mmc_pio.c
3 *
4 * Copyright (C) 2011 Guennadi Liakhovetski
5 * Copyright (C) 2007 Ian Molton
6 * Copyright (C) 2004 Ian Molton
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Driver for the MMC / SD / SDIO IP found in:
13 *
14 * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
15 *
16 * This driver draws mainly on scattered spec sheets, Reverse engineering
17 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
18 * support). (Further 4 bit support from a later datasheet).
19 *
20 * TODO:
21 * Investigate using a workqueue for PIO transfers
22 * Eliminate FIXMEs
23 * SDIO support
24 * Better Power management
25 * Handle MMC errors better
26 * double buffer support
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <linux/highmem.h>
33#include <linux/interrupt.h>
34#include <linux/io.h>
35#include <linux/irq.h>
36#include <linux/mfd/tmio.h>
37#include <linux/mmc/host.h>
0f506a96 38#include <linux/mmc/mmc.h>
fd0ea65d 39#include <linux/mmc/slot-gpio.h>
cba179ae 40#include <linux/mmc/tmio.h>
b6147490
GL		 41#include <linux/module.h>
42#include <linux/pagemap.h>
43#include <linux/platform_device.h>
c419e611 44#include <linux/pm_qos.h>
e6ee7182 45#include <linux/pm_runtime.h>
619b08d4 46#include <linux/regulator/consumer.h>
b8d11962 47#include <linux/mmc/sdio.h>
b6147490 48#include <linux/scatterlist.h>
b6147490 49#include <linux/spinlock.h>
e3de2be7 50#include <linux/workqueue.h>
b6147490
GL		 51
52#include "tmio_mmc.h"
53
b6147490
GL		 54void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
55{
54680fe7
SH		 56 host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ);
57 sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 58}
59
60void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
61{
54680fe7
SH		 62 host->sdcard_irq_mask |= (i & TMIO_MASK_IRQ);
63 sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
b6147490
GL		 64}
65
66static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)
67{
68 sd_ctrl_write32(host, CTL_STATUS, ~i);
69}
70
71static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
72{
73 host->sg_len = data->sg_len;
74 host->sg_ptr = data->sg;
75 host->sg_orig = data->sg;
76 host->sg_off = 0;
77}
78
79static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
80{
81 host->sg_ptr = sg_next(host->sg_ptr);
82 host->sg_off = 0;
83 return --host->sg_len;
84}
85
86#ifdef CONFIG_MMC_DEBUG
87
88#define STATUS_TO_TEXT(a, status, i) \
89 do { \
90 if (status & TMIO_STAT_##a) { \
91 if (i++) \
92 printk(" | "); \
93 printk(#a); \
94 } \
95 } while (0)
96
97static void pr_debug_status(u32 status)
98{
99 int i = 0;
a3c76eb9 100 pr_debug("status: %08x = ", status);
b6147490
GL		 101 STATUS_TO_TEXT(CARD_REMOVE, status, i);
102 STATUS_TO_TEXT(CARD_INSERT, status, i);
103 STATUS_TO_TEXT(SIGSTATE, status, i);
104 STATUS_TO_TEXT(WRPROTECT, status, i);
105 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
106 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
107 STATUS_TO_TEXT(SIGSTATE_A, status, i);
108 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
109 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
110 STATUS_TO_TEXT(ILL_FUNC, status, i);
111 STATUS_TO_TEXT(CMD_BUSY, status, i);
112 STATUS_TO_TEXT(CMDRESPEND, status, i);
113 STATUS_TO_TEXT(DATAEND, status, i);
114 STATUS_TO_TEXT(CRCFAIL, status, i);
115 STATUS_TO_TEXT(DATATIMEOUT, status, i);
116 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
117 STATUS_TO_TEXT(RXOVERFLOW, status, i);
118 STATUS_TO_TEXT(TXUNDERRUN, status, i);
119 STATUS_TO_TEXT(RXRDY, status, i);
120 STATUS_TO_TEXT(TXRQ, status, i);
121 STATUS_TO_TEXT(ILL_ACCESS, status, i);
122 printk("\n");
123}
124
125#else
126#define pr_debug_status(s) do { } while (0)
127#endif
128
129static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
130{
131 struct tmio_mmc_host *host = mmc_priv(mmc);
132
7501c431
UH		 133 if (enable && !host->sdio_irq_enabled) {
134 /* Keep device active while SDIO irq is enabled */
135 pm_runtime_get_sync(mmc_dev(mmc));
136 host->sdio_irq_enabled = true;
137
54680fe7
SH		 138 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL &
139 ~TMIO_SDIO_STAT_IOIRQ;
b6147490 140 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
54680fe7 141 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
7501c431 142 } else if (!enable && host->sdio_irq_enabled) {
54680fe7
SH		 143 host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
144 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
b6147490 145 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
7501c431
UH		 146
147 host->sdio_irq_enabled = false;
0369483e
UH		 148 pm_runtime_mark_last_busy(mmc_dev(mmc));
149 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 150 }
151}
152
ae12d250
UH		 153static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
154 unsigned int new_clock)
b6147490
GL		 155{
156 u32 clk = 0, clock;
157
158 if (new_clock) {
159 for (clock = host->mmc->f_min, clk = 0x80000080;
160 new_clock >= (clock<<1); clk >>= 1)
161 clock <<= 1;
162 clk |= 0x100;
163 }
164
165 if (host->set_clk_div)
166 host->set_clk_div(host->pdev, (clk>>22) & 1);
167
168 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
619b08d4 169 msleep(10);
b6147490
GL		 170}
171
172static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
173{
69d1fe18 174 /* implicit BUG_ON(!res) */
5d60e500 175 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
69d1fe18
GL		 176 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
177 msleep(10);
178 }
d9b03421 179
b6147490
GL		 180 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
181 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
182 msleep(10);
183}
184
185static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
186{
b6147490
GL		 187 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
188 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
189 msleep(10);
d9b03421 190
69d1fe18 191 /* implicit BUG_ON(!res) */
5d60e500 192 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
69d1fe18
GL		 193 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
194 msleep(10);
195 }
b6147490
GL		 196}
197
198static void tmio_mmc_reset(struct tmio_mmc_host *host)
199{
200 /* FIXME - should we set stop clock reg here */
201 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
69d1fe18 202 /* implicit BUG_ON(!res) */
5d60e500 203 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 204 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
b6147490
GL		 205 msleep(10);
206 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
5d60e500 207 if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG)
69d1fe18 208 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
b6147490
GL		 209 msleep(10);
210}
211
212static void tmio_mmc_reset_work(struct work_struct *work)
213{
214 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
215 delayed_reset_work.work);
216 struct mmc_request *mrq;
217 unsigned long flags;
218
219 spin_lock_irqsave(&host->lock, flags);
220 mrq = host->mrq;
221
df3ef2d3
GL		 222 /*
223 * is request already finished? Since we use a non-blocking
224 * cancel_delayed_work(), it can happen, that a .set_ios() call preempts
225 * us, so, have to check for IS_ERR(host->mrq)
226 */
227 if (IS_ERR_OR_NULL(mrq)
b6147490
GL		 228 || time_is_after_jiffies(host->last_req_ts +
229 msecs_to_jiffies(2000))) {
230 spin_unlock_irqrestore(&host->lock, flags);
231 return;
232 }
233
234 dev_warn(&host->pdev->dev,
235 "timeout waiting for hardware interrupt (CMD%u)\n",
236 mrq->cmd->opcode);
237
238 if (host->data)
239 host->data->error = -ETIMEDOUT;
240 else if (host->cmd)
241 host->cmd->error = -ETIMEDOUT;
242 else
243 mrq->cmd->error = -ETIMEDOUT;
244
245 host->cmd = NULL;
246 host->data = NULL;
b6147490
GL		 247 host->force_pio = false;
248
249 spin_unlock_irqrestore(&host->lock, flags);
250
251 tmio_mmc_reset(host);
252
df3ef2d3
GL		 253 /* Ready for new calls */
254 host->mrq = NULL;
255
e3de2be7 256 tmio_mmc_abort_dma(host);
b6147490 257 mmc_request_done(host->mmc, mrq);
0369483e
UH		 258
259 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
260 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
b6147490
GL		 261}
262
df3ef2d3 263/* called with host->lock held, interrupts disabled */
b6147490
GL		 264static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
265{
b9269fdd
GL		 266 struct mmc_request *mrq;
267 unsigned long flags;
b6147490 268
b9269fdd
GL		 269 spin_lock_irqsave(&host->lock, flags);
270
271 mrq = host->mrq;
272 if (IS_ERR_OR_NULL(mrq)) {
273 spin_unlock_irqrestore(&host->lock, flags);
b6147490 274 return;
b9269fdd 275 }
b6147490 276
b6147490
GL		 277 host->cmd = NULL;
278 host->data = NULL;
279 host->force_pio = false;
280
281 cancel_delayed_work(&host->delayed_reset_work);
282
df3ef2d3 283 host->mrq = NULL;
b9269fdd 284 spin_unlock_irqrestore(&host->lock, flags);
df3ef2d3 285
e3de2be7
GL		 286 if (mrq->cmd->error || (mrq->data && mrq->data->error))
287 tmio_mmc_abort_dma(host);
288
b6147490 289 mmc_request_done(host->mmc, mrq);
0369483e
UH		 290
291 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
292 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
b6147490
GL		 293}
294
b9269fdd
GL		 295static void tmio_mmc_done_work(struct work_struct *work)
296{
297 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
298 done);
299 tmio_mmc_finish_request(host);
300}
301
b6147490
GL		 302/* These are the bitmasks the tmio chip requires to implement the MMC response
303 * types. Note that R1 and R6 are the same in this scheme. */
304#define APP_CMD 0x0040
305#define RESP_NONE 0x0300
306#define RESP_R1 0x0400
307#define RESP_R1B 0x0500
308#define RESP_R2 0x0600
309#define RESP_R3 0x0700
310#define DATA_PRESENT 0x0800
311#define TRANSFER_READ 0x1000
312#define TRANSFER_MULTI 0x2000
313#define SECURITY_CMD 0x4000
b8d11962 314#define NO_CMD12_ISSUE 0x4000 /* TMIO_MMC_HAVE_CMD12_CTRL */
b6147490
GL		 315
316static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
317{
318 struct mmc_data *data = host->data;
319 int c = cmd->opcode;
e23cd53c 320 u32 irq_mask = TMIO_MASK_CMD;
b6147490 321
0f506a96
GL		 322 /* CMD12 is handled by hardware */
323 if (cmd->opcode == MMC_STOP_TRANSMISSION && !cmd->arg) {
b6147490
GL		 324 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
325 return 0;
326 }
327
328 switch (mmc_resp_type(cmd)) {
329 case MMC_RSP_NONE: c |= RESP_NONE; break;
330 case MMC_RSP_R1: c |= RESP_R1; break;
331 case MMC_RSP_R1B: c |= RESP_R1B; break;
332 case MMC_RSP_R2: c |= RESP_R2; break;
333 case MMC_RSP_R3: c |= RESP_R3; break;
334 default:
335 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
336 return -EINVAL;
337 }
338
339 host->cmd = cmd;
340
341/* FIXME - this seems to be ok commented out but the spec suggest this bit
342 * should be set when issuing app commands.
343 * if(cmd->flags & MMC_FLAG_ACMD)
344 * c |= APP_CMD;
345 */
346 if (data) {
347 c |= DATA_PRESENT;
348 if (data->blocks > 1) {
349 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
350 c |= TRANSFER_MULTI;
b8d11962
SU		 351
352 /*
353 * Disable auto CMD12 at IO_RW_EXTENDED when
354 * multiple block transfer
355 */
356 if ((host->pdata->flags & TMIO_MMC_HAVE_CMD12_CTRL) &&
357 (cmd->opcode == SD_IO_RW_EXTENDED))
358 c |= NO_CMD12_ISSUE;
b6147490
GL		 359 }
360 if (data->flags & MMC_DATA_READ)
361 c |= TRANSFER_READ;
362 }
363
e23cd53c
GL		 364 if (!host->native_hotplug)
365 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
366 tmio_mmc_enable_mmc_irqs(host, irq_mask);
b6147490
GL		 367
368 /* Fire off the command */
369 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
370 sd_ctrl_write16(host, CTL_SD_CMD, c);
371
372 return 0;
373}
374
375/*
376 * This chip always returns (at least?) as much data as you ask for.
377 * I'm unsure what happens if you ask for less than a block. This should be
25985edc 378 * looked into to ensure that a funny length read doesn't hose the controller.
b6147490
GL		 379 */
380static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
381{
382 struct mmc_data *data = host->data;
383 void *sg_virt;
384 unsigned short *buf;
385 unsigned int count;
386 unsigned long flags;
387
388 if ((host->chan_tx || host->chan_rx) && !host->force_pio) {
389 pr_err("PIO IRQ in DMA mode!\n");
390 return;
391 } else if (!data) {
392 pr_debug("Spurious PIO IRQ\n");
393 return;
394 }
395
396 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
397 buf = (unsigned short *)(sg_virt + host->sg_off);
398
399 count = host->sg_ptr->length - host->sg_off;
400 if (count > data->blksz)
401 count = data->blksz;
402
403 pr_debug("count: %08x offset: %08x flags %08x\n",
404 count, host->sg_off, data->flags);
405
406 /* Transfer the data */
407 if (data->flags & MMC_DATA_READ)
408 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
409 else
410 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
411
412 host->sg_off += count;
413
414 tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
415
416 if (host->sg_off == host->sg_ptr->length)
417 tmio_mmc_next_sg(host);
418
419 return;
420}
421
422static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host)
423{
424 if (host->sg_ptr == &host->bounce_sg) {
425 unsigned long flags;
426 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
427 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
428 tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
429 }
430}
431
432/* needs to be called with host->lock held */
433void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
434{
435 struct mmc_data *data = host->data;
436 struct mmc_command *stop;
437
438 host->data = NULL;
439
440 if (!data) {
441 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
442 return;
443 }
444 stop = data->stop;
445
446 /* FIXME - return correct transfer count on errors */
447 if (!data->error)
448 data->bytes_xfered = data->blocks * data->blksz;
449 else
450 data->bytes_xfered = 0;
451
452 pr_debug("Completed data request\n");
453
454 /*
455 * FIXME: other drivers allow an optional stop command of any given type
456 * which we dont do, as the chip can auto generate them.
457 * Perhaps we can be smarter about when to use auto CMD12 and
458 * only issue the auto request when we know this is the desired
459 * stop command, allowing fallback to the stop command the
460 * upper layers expect. For now, we do what works.
461 */
462
463 if (data->flags & MMC_DATA_READ) {
464 if (host->chan_rx && !host->force_pio)
465 tmio_mmc_check_bounce_buffer(host);
466 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
467 host->mrq);
468 } else {
469 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
470 host->mrq);
471 }
472
473 if (stop) {
0f506a96 474 if (stop->opcode == MMC_STOP_TRANSMISSION && !stop->arg)
b6147490
GL		 475 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
476 else
477 BUG();
478 }
479
b9269fdd 480 schedule_work(&host->done);
b6147490
GL		 481}
482
483static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
484{
485 struct mmc_data *data;
486 spin_lock(&host->lock);
487 data = host->data;
488
489 if (!data)
490 goto out;
491
492 if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
493 /*
494 * Has all data been written out yet? Testing on SuperH showed,
495 * that in most cases the first interrupt comes already with the
496 * BUSY status bit clear, but on some operations, like mount or
497 * in the beginning of a write / sync / umount, there is one
498 * DATAEND interrupt with the BUSY bit set, in this cases
499 * waiting for one more interrupt fixes the problem.
500 */
501 if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) {
502 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
503 tasklet_schedule(&host->dma_complete);
504 }
505 } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
506 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
507 tasklet_schedule(&host->dma_complete);
508 } else {
509 tmio_mmc_do_data_irq(host);
510 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
511 }
512out:
513 spin_unlock(&host->lock);
514}
515
516static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
517 unsigned int stat)
518{
519 struct mmc_command *cmd = host->cmd;
520 int i, addr;
521
522 spin_lock(&host->lock);
523
524 if (!host->cmd) {
525 pr_debug("Spurious CMD irq\n");
526 goto out;
527 }
528
529 host->cmd = NULL;
530
531 /* This controller is sicker than the PXA one. Not only do we need to
532 * drop the top 8 bits of the first response word, we also need to
533 * modify the order of the response for short response command types.
534 */
535
536 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
537 cmd->resp[i] = sd_ctrl_read32(host, addr);
538
539 if (cmd->flags & MMC_RSP_136) {
540 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
541 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
542 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
543 cmd->resp[3] <<= 8;
544 } else if (cmd->flags & MMC_RSP_R3) {
545 cmd->resp[0] = cmd->resp[3];
546 }
547
548 if (stat & TMIO_STAT_CMDTIMEOUT)
549 cmd->error = -ETIMEDOUT;
550 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
551 cmd->error = -EILSEQ;
552
553 /* If there is data to handle we enable data IRQs here, and
554 * we will ultimatley finish the request in the data_end handler.
555 * If theres no data or we encountered an error, finish now.
556 */
557 if (host->data && !cmd->error) {
558 if (host->data->flags & MMC_DATA_READ) {
559 if (host->force_pio || !host->chan_rx)
560 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
561 else
562 tasklet_schedule(&host->dma_issue);
563 } else {
564 if (host->force_pio || !host->chan_tx)
565 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
566 else
567 tasklet_schedule(&host->dma_issue);
568 }
569 } else {
b9269fdd 570 schedule_work(&host->done);
b6147490
GL		 571 }
572
573out:
574 spin_unlock(&host->lock);
575}
576
7729c7a2
SH		 577static void tmio_mmc_card_irq_status(struct tmio_mmc_host *host,
578 int *ireg, int *status)
b6147490 579{
7729c7a2
SH		 580 *status = sd_ctrl_read32(host, CTL_STATUS);
581 *ireg = *status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask;
b6147490 582
7729c7a2
SH		 583 pr_debug_status(*status);
584 pr_debug_status(*ireg);
f83bfa75
SU		 585
586 /* Clear the status except the interrupt status */
587 sd_ctrl_write32(host, CTL_STATUS, TMIO_MASK_IRQ);
7729c7a2 588}
b6147490 589
7729c7a2
SH		 590static bool __tmio_mmc_card_detect_irq(struct tmio_mmc_host *host,
591 int ireg, int status)
592{
593 struct mmc_host *mmc = host->mmc;
b6147490 594
e312eb1e
PP		 595 /* Card insert / remove attempts */
596 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
597 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
598 TMIO_STAT_CARD_REMOVE);
71d111cd
GL		 599 if ((((ireg & TMIO_STAT_CARD_REMOVE) && mmc->card) ||
600 ((ireg & TMIO_STAT_CARD_INSERT) && !mmc->card)) &&
601 !work_pending(&mmc->detect.work))
b9269fdd 602 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
7729c7a2 603 return true;
b6147490
GL		 604 }
605
7729c7a2
SH		 606 return false;
607}
608
609irqreturn_t tmio_mmc_card_detect_irq(int irq, void *devid)
610{
611 unsigned int ireg, status;
612 struct tmio_mmc_host *host = devid;
b6147490 613
7729c7a2
SH		 614 tmio_mmc_card_irq_status(host, &ireg, &status);
615 __tmio_mmc_card_detect_irq(host, ireg, status);
616
617 return IRQ_HANDLED;
618}
619EXPORT_SYMBOL(tmio_mmc_card_detect_irq);
620
621static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host,
622 int ireg, int status)
623{
e312eb1e
PP		 624 /* Command completion */
625 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
626 tmio_mmc_ack_mmc_irqs(host,
627 TMIO_STAT_CMDRESPEND |
628 TMIO_STAT_CMDTIMEOUT);
629 tmio_mmc_cmd_irq(host, status);
7729c7a2 630 return true;
e312eb1e 631 }
b6147490 632
e312eb1e
PP		 633 /* Data transfer */
634 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
635 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
636 tmio_mmc_pio_irq(host);
7729c7a2 637 return true;
e312eb1e 638 }
b6147490 639
e312eb1e
PP		 640 /* Data transfer completion */
641 if (ireg & TMIO_STAT_DATAEND) {
642 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
643 tmio_mmc_data_irq(host);
7729c7a2 644 return true;
b6147490 645 }
e312eb1e 646
7729c7a2
SH		 647 return false;
648}
649
650irqreturn_t tmio_mmc_sdcard_irq(int irq, void *devid)
651{
652 unsigned int ireg, status;
653 struct tmio_mmc_host *host = devid;
654
655 tmio_mmc_card_irq_status(host, &ireg, &status);
656 __tmio_mmc_sdcard_irq(host, ireg, status);
657
658 return IRQ_HANDLED;
659}
660EXPORT_SYMBOL(tmio_mmc_sdcard_irq);
661
662irqreturn_t tmio_mmc_sdio_irq(int irq, void *devid)
663{
664 struct tmio_mmc_host *host = devid;
665 struct mmc_host *mmc = host->mmc;
666 struct tmio_mmc_data *pdata = host->pdata;
667 unsigned int ireg, status;
668
669 if (!(pdata->flags & TMIO_MMC_SDIO_IRQ))
670 return IRQ_HANDLED;
671
672 status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
673 ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdcard_irq_mask;
674
675 sd_ctrl_write16(host, CTL_SDIO_STATUS, status & ~TMIO_SDIO_MASK_ALL);
676
677 if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ)
678 mmc_signal_sdio_irq(mmc);
679
680 return IRQ_HANDLED;
681}
682EXPORT_SYMBOL(tmio_mmc_sdio_irq);
683
684irqreturn_t tmio_mmc_irq(int irq, void *devid)
685{
686 struct tmio_mmc_host *host = devid;
687 unsigned int ireg, status;
688
689 pr_debug("MMC IRQ begin\n");
690
691 tmio_mmc_card_irq_status(host, &ireg, &status);
692 if (__tmio_mmc_card_detect_irq(host, ireg, status))
693 return IRQ_HANDLED;
694 if (__tmio_mmc_sdcard_irq(host, ireg, status))
695 return IRQ_HANDLED;
696
697 tmio_mmc_sdio_irq(irq, devid);
b6147490 698
b6147490
GL		 699 return IRQ_HANDLED;
700}
8e7bfdb3 701EXPORT_SYMBOL(tmio_mmc_irq);
b6147490
GL		 702
703static int tmio_mmc_start_data(struct tmio_mmc_host *host,
704 struct mmc_data *data)
705{
706 struct tmio_mmc_data *pdata = host->pdata;
707
708 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
709 data->blksz, data->blocks);
710
711 /* Some hardware cannot perform 2 byte requests in 4 bit mode */
712 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
713 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
714
715 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
716 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
717 mmc_hostname(host->mmc), data->blksz);
718 return -EINVAL;
719 }
720 }
721
722 tmio_mmc_init_sg(host, data);
723 host->data = data;
724
725 /* Set transfer length / blocksize */
726 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
727 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
728
729 tmio_mmc_start_dma(host, data);
730
731 return 0;
732}
733
734/* Process requests from the MMC layer */
735static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
736{
737 struct tmio_mmc_host *host = mmc_priv(mmc);
df3ef2d3 738 unsigned long flags;
b6147490
GL		 739 int ret;
740
df3ef2d3
GL		 741 spin_lock_irqsave(&host->lock, flags);
742
743 if (host->mrq) {
b6147490 744 pr_debug("request not null\n");
df3ef2d3
GL		 745 if (IS_ERR(host->mrq)) {
746 spin_unlock_irqrestore(&host->lock, flags);
747 mrq->cmd->error = -EAGAIN;
748 mmc_request_done(mmc, mrq);
749 return;
750 }
751 }
b6147490
GL		 752
753 host->last_req_ts = jiffies;
754 wmb();
755 host->mrq = mrq;
756
df3ef2d3
GL		 757 spin_unlock_irqrestore(&host->lock, flags);
758
0369483e
UH		 759 pm_runtime_get_sync(mmc_dev(mmc));
760
b6147490
GL		 761 if (mrq->data) {
762 ret = tmio_mmc_start_data(host, mrq->data);
763 if (ret)
764 goto fail;
765 }
766
767 ret = tmio_mmc_start_command(host, mrq->cmd);
768 if (!ret) {
769 schedule_delayed_work(&host->delayed_reset_work,
770 msecs_to_jiffies(2000));
771 return;
772 }
773
774fail:
b6147490 775 host->force_pio = false;
df3ef2d3 776 host->mrq = NULL;
b6147490
GL		 777 mrq->cmd->error = ret;
778 mmc_request_done(mmc, mrq);
0369483e
UH		 779
780 pm_runtime_mark_last_busy(mmc_dev(mmc));
781 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 782}
783
ae12d250 784static int tmio_mmc_clk_update(struct tmio_mmc_host *host)
8c102a96 785{
ae12d250 786 struct mmc_host *mmc = host->mmc;
8c102a96
GL		 787 struct tmio_mmc_data *pdata = host->pdata;
788 int ret;
789
790 if (!pdata->clk_enable)
791 return -ENOTSUPP;
792
793 ret = pdata->clk_enable(host->pdev, &mmc->f_max);
794 if (!ret)
795 mmc->f_min = mmc->f_max / 512;
796
797 return ret;
798}
799
619b08d4 800static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd)
b958a67c
GL		 801{
802 struct mmc_host *mmc = host->mmc;
619b08d4
GL		 803 int ret = 0;
804
805 /* .set_ios() is returning void, so, no chance to report an error */
b958a67c 806
9d731e75
CB		 807 if (host->set_pwr)
808 host->set_pwr(host->pdev, 1);
809
619b08d4
GL		 810 if (!IS_ERR(mmc->supply.vmmc)) {
811 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
812 /*
813 * Attention: empiric value. With a b43 WiFi SDIO card this
814 * delay proved necessary for reliable card-insertion probing.
815 * 100us were not enough. Is this the same 140us delay, as in
816 * tmio_mmc_set_ios()?
817 */
818 udelay(200);
819 }
820 /*
821 * It seems, VccQ should be switched on after Vcc, this is also what the
822 * omap_hsmmc.c driver does.
823 */
824 if (!IS_ERR(mmc->supply.vqmmc) && !ret) {
6d1d6b47 825 ret = regulator_enable(mmc->supply.vqmmc);
619b08d4
GL		 826 udelay(200);
827 }
6d1d6b47
GL		 828
829 if (ret < 0)
830 dev_dbg(&host->pdev->dev, "Regulators failed to power up: %d\n",
831 ret);
619b08d4
GL		 832}
833
834static void tmio_mmc_power_off(struct tmio_mmc_host *host)
835{
836 struct mmc_host *mmc = host->mmc;
837
838 if (!IS_ERR(mmc->supply.vqmmc))
839 regulator_disable(mmc->supply.vqmmc);
840
b958a67c 841 if (!IS_ERR(mmc->supply.vmmc))
619b08d4 842 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
9d731e75
CB		 843
844 if (host->set_pwr)
845 host->set_pwr(host->pdev, 0);
b958a67c
GL		 846}
847
9ae4ed7d
UH		 848static void tmio_mmc_set_bus_width(struct tmio_mmc_host *host,
849 unsigned char bus_width)
850{
851 switch (bus_width) {
852 case MMC_BUS_WIDTH_1:
853 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
854 break;
855 case MMC_BUS_WIDTH_4:
856 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
857 break;
858 }
859}
860
b6147490
GL		 861/* Set MMC clock / power.
862 * Note: This controller uses a simple divider scheme therefore it cannot
863 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
864 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
865 * slowest setting.
866 */
867static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
868{
869 struct tmio_mmc_host *host = mmc_priv(mmc);
4932bd64 870 struct device *dev = &host->pdev->dev;
df3ef2d3
GL		 871 unsigned long flags;
872
0369483e
UH		 873 pm_runtime_get_sync(mmc_dev(mmc));
874
b9269fdd
GL		 875 mutex_lock(&host->ios_lock);
876
df3ef2d3
GL		 877 spin_lock_irqsave(&host->lock, flags);
878 if (host->mrq) {
879 if (IS_ERR(host->mrq)) {
4932bd64 880 dev_dbg(dev,
df3ef2d3
GL		 881 "%s.%d: concurrent .set_ios(), clk %u, mode %u\n",
882 current->comm, task_pid_nr(current),
883 ios->clock, ios->power_mode);
884 host->mrq = ERR_PTR(-EINTR);
885 } else {
4932bd64 886 dev_dbg(dev,
df3ef2d3
GL		 887 "%s.%d: CMD%u active since %lu, now %lu!\n",
888 current->comm, task_pid_nr(current),
889 host->mrq->cmd->opcode, host->last_req_ts, jiffies);
890 }
891 spin_unlock_irqrestore(&host->lock, flags);
b9269fdd
GL		 892
893 mutex_unlock(&host->ios_lock);
df3ef2d3
GL		 894 return;
895 }
896
897 host->mrq = ERR_PTR(-EBUSY);
898
899 spin_unlock_irqrestore(&host->lock, flags);
b6147490 900
3b292bb0
UH		 901 switch (ios->power_mode) {
902 case MMC_POWER_OFF:
903 tmio_mmc_power_off(host);
904 tmio_mmc_clk_stop(host);
905 break;
906 case MMC_POWER_UP:
71d111cd 907 tmio_mmc_set_clock(host, ios->clock);
3b292bb0 908 tmio_mmc_power_on(host, ios->vdd);
5fd01579 909 tmio_mmc_clk_start(host);
9ae4ed7d 910 tmio_mmc_set_bus_width(host, ios->bus_width);
3b292bb0
UH		 911 break;
912 case MMC_POWER_ON:
913 tmio_mmc_set_clock(host, ios->clock);
914 tmio_mmc_clk_start(host);
915 tmio_mmc_set_bus_width(host, ios->bus_width);
916 break;
917 }
b6147490
GL		 918
919 /* Let things settle. delay taken from winCE driver */
920 udelay(140);
df3ef2d3
GL		 921 if (PTR_ERR(host->mrq) == -EINTR)
922 dev_dbg(&host->pdev->dev,
923 "%s.%d: IOS interrupted: clk %u, mode %u",
924 current->comm, task_pid_nr(current),
925 ios->clock, ios->power_mode);
926 host->mrq = NULL;
b9269fdd 927
ae12d250
UH		 928 host->clk_cache = ios->clock;
929
b9269fdd 930 mutex_unlock(&host->ios_lock);
0369483e
UH		 931
932 pm_runtime_mark_last_busy(mmc_dev(mmc));
933 pm_runtime_put_autosuspend(mmc_dev(mmc));
b6147490
GL		 934}
935
936static int tmio_mmc_get_ro(struct mmc_host *mmc)
937{
938 struct tmio_mmc_host *host = mmc_priv(mmc);
939 struct tmio_mmc_data *pdata = host->pdata;
3071cafb
GL		 940 int ret = mmc_gpio_get_ro(mmc);
941 if (ret >= 0)
942 return ret;
b6147490 943
0369483e
UH		 944 pm_runtime_get_sync(mmc_dev(mmc));
945 ret = !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
946 (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
947 pm_runtime_mark_last_busy(mmc_dev(mmc));
948 pm_runtime_put_autosuspend(mmc_dev(mmc));
949
950 return ret;
b6147490
GL		 951}
952
b6147490
GL		 953static const struct mmc_host_ops tmio_mmc_ops = {
954 .request = tmio_mmc_request,
955 .set_ios = tmio_mmc_set_ios,
956 .get_ro = tmio_mmc_get_ro,
2b63b341 957 .get_cd = mmc_gpio_get_cd,
b6147490
GL		 958 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
959};
960
05fae4a7 961static int tmio_mmc_init_ocr(struct tmio_mmc_host *host)
b958a67c
GL		 962{
963 struct tmio_mmc_data *pdata = host->pdata;
964 struct mmc_host *mmc = host->mmc;
965
966 mmc_regulator_get_supply(mmc);
967
05fae4a7 968 /* use ocr_mask if no regulator */
b958a67c 969 if (!mmc->ocr_avail)
05fae4a7
KM		 970 mmc->ocr_avail = pdata->ocr_mask;
971
972 /*
973 * try again.
974 * There is possibility that regulator has not been probed
975 */
976 if (!mmc->ocr_avail)
977 return -EPROBE_DEFER;
978
979 return 0;
b958a67c
GL		 980}
981
5a00a971
GL		 982static void tmio_mmc_of_parse(struct platform_device *pdev,
983 struct tmio_mmc_data *pdata)
984{
985 const struct device_node *np = pdev->dev.of_node;
986 if (!np)
987 return;
988
989 if (of_get_property(np, "toshiba,mmc-wrprotect-disable", NULL))
990 pdata->flags |= TMIO_MMC_WRPROTECT_DISABLE;
991}
992
c3be1efd 993int tmio_mmc_host_probe(struct tmio_mmc_host **host,
b6147490
GL		 994 struct platform_device *pdev,
995 struct tmio_mmc_data *pdata)
996{
997 struct tmio_mmc_host *_host;
998 struct mmc_host *mmc;
999 struct resource *res_ctl;
1000 int ret;
1001 u32 irq_mask = TMIO_MASK_CMD;
1002
5a00a971
GL		 1003 tmio_mmc_of_parse(pdev, pdata);
1004
7b952137
GL		 1005 if (!(pdata->flags & TMIO_MMC_HAS_IDLE_WAIT))
1006 pdata->write16_hook = NULL;
1007
b6147490
GL		 1008 res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1009 if (!res_ctl)
1010 return -EINVAL;
1011
1012 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
1013 if (!mmc)
1014 return -ENOMEM;
1015
274a752b
SB		 1016 ret = mmc_of_parse(mmc);
1017 if (ret < 0)
1018 goto host_free;
5a00a971 1019
7311bef0 1020 pdata->dev = &pdev->dev;
b6147490
GL		 1021 _host = mmc_priv(mmc);
1022 _host->pdata = pdata;
1023 _host->mmc = mmc;
1024 _host->pdev = pdev;
1025 platform_set_drvdata(pdev, mmc);
1026
9d731e75 1027 _host->set_pwr = pdata->set_pwr;
b6147490
GL		 1028 _host->set_clk_div = pdata->set_clk_div;
1029
05fae4a7
KM		 1030 ret = tmio_mmc_init_ocr(_host);
1031 if (ret < 0)
1032 goto host_free;
1033
b6147490
GL		 1034 _host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
1035 if (!_host->ctl) {
1036 ret = -ENOMEM;
1037 goto host_free;
1038 }
1039
1040 mmc->ops = &tmio_mmc_ops;
5a00a971 1041 mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
dd006b30 1042 mmc->caps2 |= pdata->capabilities2;
b6147490
GL		 1043 mmc->max_segs = 32;
1044 mmc->max_blk_size = 512;
1045 mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
1046 mmc->max_segs;
1047 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1048 mmc->max_seg_size = mmc->max_req_size;
b6147490 1049
c8be24c2 1050 _host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD ||
2b1ac5c2 1051 mmc->caps & MMC_CAP_NEEDS_POLL ||
5a00a971
GL		 1052 mmc->caps & MMC_CAP_NONREMOVABLE ||
1053 mmc->slot.cd_irq >= 0);
2b1ac5c2 1054
ae12d250 1055 if (tmio_mmc_clk_update(_host) < 0) {
8c102a96
GL		 1056 mmc->f_max = pdata->hclk;
1057 mmc->f_min = mmc->f_max / 512;
1058 }
1059
cbb18b30 1060 /*
0369483e
UH		 1061 * While using internal tmio hardware logic for card detection, we need
1062 * to ensure it stays powered for it to work.
cbb18b30 1063 */
2b1ac5c2 1064 if (_host->native_hotplug)
cbb18b30
BH		 1065 pm_runtime_get_noresume(&pdev->dev);
1066
b6147490
GL		 1067 tmio_mmc_clk_stop(_host);
1068 tmio_mmc_reset(_host);
1069
54680fe7 1070 _host->sdcard_irq_mask = sd_ctrl_read32(_host, CTL_IRQ_MASK);
b6147490 1071 tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
e0337cc8
GL		 1072
1073 /* Unmask the IRQs we want to know about */
1074 if (!_host->chan_rx)
1075 irq_mask |= TMIO_MASK_READOP;
1076 if (!_host->chan_tx)
1077 irq_mask |= TMIO_MASK_WRITEOP;
1078 if (!_host->native_hotplug)
1079 irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
1080
1081 _host->sdcard_irq_mask &= ~irq_mask;
1082
7501c431
UH		 1083 _host->sdio_irq_enabled = false;
1084 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
1085 _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
1086 sd_ctrl_write16(_host, CTL_SDIO_IRQ_MASK, _host->sdio_irq_mask);
1087 sd_ctrl_write16(_host, CTL_TRANSACTION_CTL, 0x0000);
1088 }
b6147490 1089
b6147490 1090 spin_lock_init(&_host->lock);
b9269fdd 1091 mutex_init(&_host->ios_lock);
b6147490
GL		 1092
1093 /* Init delayed work for request timeouts */
1094 INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work);
b9269fdd 1095 INIT_WORK(&_host->done, tmio_mmc_done_work);
b6147490
GL		 1096
1097 /* See if we also get DMA */
1098 tmio_mmc_request_dma(_host, pdata);
1099
0369483e
UH		 1100 pm_runtime_set_active(&pdev->dev);
1101 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1102 pm_runtime_use_autosuspend(&pdev->dev);
1103 pm_runtime_enable(&pdev->dev);
1104
8c102a96 1105 ret = mmc_add_host(mmc);
8c102a96
GL		 1106 if (ret < 0) {
1107 tmio_mmc_host_remove(_host);
1108 return ret;
1109 }
b6147490 1110
c419e611
RW		 1111 dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1112
c8be24c2 1113 if (pdata->flags & TMIO_MMC_USE_GPIO_CD) {
214fc309 1114 ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0);
c8be24c2
GL		 1115 if (ret < 0) {
1116 tmio_mmc_host_remove(_host);
1117 return ret;
1118 }
1119 }
1120
b6147490
GL		 1121 *host = _host;
1122
1123 return 0;
1124
b6147490
GL		 1125host_free:
1126 mmc_free_host(mmc);
1127
1128 return ret;
1129}
1130EXPORT_SYMBOL(tmio_mmc_host_probe);
1131
1132void tmio_mmc_host_remove(struct tmio_mmc_host *host)
1133{
e6ee7182 1134 struct platform_device *pdev = host->pdev;
c8be24c2
GL		 1135 struct mmc_host *mmc = host->mmc;
1136
2b1ac5c2 1137 if (!host->native_hotplug)
7311bef0
GL		 1138 pm_runtime_get_sync(&pdev->dev);
1139
c419e611
RW		 1140 dev_pm_qos_hide_latency_limit(&pdev->dev);
1141
c8be24c2 1142 mmc_remove_host(mmc);
b9269fdd 1143 cancel_work_sync(&host->done);
b6147490
GL		 1144 cancel_delayed_work_sync(&host->delayed_reset_work);
1145 tmio_mmc_release_dma(host);
e6ee7182 1146
e6ee7182
GL		 1147 pm_runtime_put_sync(&pdev->dev);
1148 pm_runtime_disable(&pdev->dev);
7311bef0
GL		 1149
1150 iounmap(host->ctl);
c8be24c2 1151 mmc_free_host(mmc);
b6147490
GL		 1152}
1153EXPORT_SYMBOL(tmio_mmc_host_remove);
1154
9ade7dbf 1155#ifdef CONFIG_PM
7311bef0
GL		 1156int tmio_mmc_host_runtime_suspend(struct device *dev)
1157{
ae12d250
UH		 1158 struct mmc_host *mmc = dev_get_drvdata(dev);
1159 struct tmio_mmc_host *host = mmc_priv(mmc);
1160
20e955c3
UH		 1161 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
1162
ae12d250
UH		 1163 if (host->clk_cache)
1164 tmio_mmc_clk_stop(host);
1165
1166 if (host->pdata->clk_disable)
1167 host->pdata->clk_disable(host->pdev);
1168
7311bef0
GL		 1169 return 0;
1170}
1171EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend);
1172
1173int tmio_mmc_host_runtime_resume(struct device *dev)
1174{
1175 struct mmc_host *mmc = dev_get_drvdata(dev);
1176 struct tmio_mmc_host *host = mmc_priv(mmc);
7311bef0 1177
ae12d250
UH		 1178 tmio_mmc_reset(host);
1179 tmio_mmc_clk_update(host);
1180
1181 if (host->clk_cache) {
1182 tmio_mmc_set_clock(host, host->clk_cache);
1183 tmio_mmc_clk_start(host);
1184 }
1185
162f43e3 1186 tmio_mmc_enable_dma(host, true);
7311bef0 1187
7311bef0
GL		 1188 return 0;
1189}
1190EXPORT_SYMBOL(tmio_mmc_host_runtime_resume);
710dec95 1191#endif
7311bef0 1192
b6147490 1193MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)