Commit | Line | Data |
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b6147490 GL |
1 | /* |
2 | * linux/drivers/mmc/host/tmio_mmc_pio.c | |
3 | * | |
bf96208f WS |
4 | * Copyright (C) 2016 Sang Engineering, Wolfram Sang |
5 | * Copyright (C) 2015-16 Renesas Electronics Corporation | |
b6147490 GL |
6 | * Copyright (C) 2011 Guennadi Liakhovetski |
7 | * Copyright (C) 2007 Ian Molton | |
8 | * Copyright (C) 2004 Ian Molton | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * Driver for the MMC / SD / SDIO IP found in: | |
15 | * | |
16 | * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs | |
17 | * | |
18 | * This driver draws mainly on scattered spec sheets, Reverse engineering | |
19 | * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit | |
20 | * support). (Further 4 bit support from a later datasheet). | |
21 | * | |
22 | * TODO: | |
23 | * Investigate using a workqueue for PIO transfers | |
24 | * Eliminate FIXMEs | |
b6147490 GL |
25 | * Better Power management |
26 | * Handle MMC errors better | |
27 | * double buffer support | |
28 | * | |
29 | */ | |
30 | ||
31 | #include <linux/delay.h> | |
32 | #include <linux/device.h> | |
33 | #include <linux/highmem.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/io.h> | |
36 | #include <linux/irq.h> | |
37 | #include <linux/mfd/tmio.h> | |
4f119977 | 38 | #include <linux/mmc/card.h> |
b6147490 | 39 | #include <linux/mmc/host.h> |
0f506a96 | 40 | #include <linux/mmc/mmc.h> |
fd0ea65d | 41 | #include <linux/mmc/slot-gpio.h> |
b6147490 GL |
42 | #include <linux/module.h> |
43 | #include <linux/pagemap.h> | |
44 | #include <linux/platform_device.h> | |
c419e611 | 45 | #include <linux/pm_qos.h> |
e6ee7182 | 46 | #include <linux/pm_runtime.h> |
619b08d4 | 47 | #include <linux/regulator/consumer.h> |
b8d11962 | 48 | #include <linux/mmc/sdio.h> |
b6147490 | 49 | #include <linux/scatterlist.h> |
b6147490 | 50 | #include <linux/spinlock.h> |
e3de2be7 | 51 | #include <linux/workqueue.h> |
b6147490 GL |
52 | |
53 | #include "tmio_mmc.h" | |
54 | ||
b6147490 GL |
55 | void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i) |
56 | { | |
54680fe7 | 57 | host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ); |
2c54506b | 58 | sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask); |
b6147490 GL |
59 | } |
60 | ||
61 | void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i) | |
62 | { | |
54680fe7 | 63 | host->sdcard_irq_mask |= (i & TMIO_MASK_IRQ); |
2c54506b | 64 | sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask); |
b6147490 GL |
65 | } |
66 | ||
67 | static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i) | |
68 | { | |
2c54506b | 69 | sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, ~i); |
b6147490 GL |
70 | } |
71 | ||
72 | static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data) | |
73 | { | |
74 | host->sg_len = data->sg_len; | |
75 | host->sg_ptr = data->sg; | |
76 | host->sg_orig = data->sg; | |
77 | host->sg_off = 0; | |
78 | } | |
79 | ||
80 | static int tmio_mmc_next_sg(struct tmio_mmc_host *host) | |
81 | { | |
82 | host->sg_ptr = sg_next(host->sg_ptr); | |
83 | host->sg_off = 0; | |
84 | return --host->sg_len; | |
85 | } | |
86 | ||
0df9d2ea TK |
87 | #define CMDREQ_TIMEOUT 5000 |
88 | ||
b6147490 GL |
89 | #ifdef CONFIG_MMC_DEBUG |
90 | ||
91 | #define STATUS_TO_TEXT(a, status, i) \ | |
92 | do { \ | |
93 | if (status & TMIO_STAT_##a) { \ | |
94 | if (i++) \ | |
95 | printk(" | "); \ | |
96 | printk(#a); \ | |
97 | } \ | |
98 | } while (0) | |
99 | ||
100 | static void pr_debug_status(u32 status) | |
101 | { | |
102 | int i = 0; | |
a3c76eb9 | 103 | pr_debug("status: %08x = ", status); |
b6147490 GL |
104 | STATUS_TO_TEXT(CARD_REMOVE, status, i); |
105 | STATUS_TO_TEXT(CARD_INSERT, status, i); | |
106 | STATUS_TO_TEXT(SIGSTATE, status, i); | |
107 | STATUS_TO_TEXT(WRPROTECT, status, i); | |
108 | STATUS_TO_TEXT(CARD_REMOVE_A, status, i); | |
109 | STATUS_TO_TEXT(CARD_INSERT_A, status, i); | |
110 | STATUS_TO_TEXT(SIGSTATE_A, status, i); | |
111 | STATUS_TO_TEXT(CMD_IDX_ERR, status, i); | |
112 | STATUS_TO_TEXT(STOPBIT_ERR, status, i); | |
113 | STATUS_TO_TEXT(ILL_FUNC, status, i); | |
114 | STATUS_TO_TEXT(CMD_BUSY, status, i); | |
115 | STATUS_TO_TEXT(CMDRESPEND, status, i); | |
116 | STATUS_TO_TEXT(DATAEND, status, i); | |
117 | STATUS_TO_TEXT(CRCFAIL, status, i); | |
118 | STATUS_TO_TEXT(DATATIMEOUT, status, i); | |
119 | STATUS_TO_TEXT(CMDTIMEOUT, status, i); | |
120 | STATUS_TO_TEXT(RXOVERFLOW, status, i); | |
121 | STATUS_TO_TEXT(TXUNDERRUN, status, i); | |
122 | STATUS_TO_TEXT(RXRDY, status, i); | |
123 | STATUS_TO_TEXT(TXRQ, status, i); | |
124 | STATUS_TO_TEXT(ILL_ACCESS, status, i); | |
125 | printk("\n"); | |
126 | } | |
127 | ||
128 | #else | |
129 | #define pr_debug_status(s) do { } while (0) | |
130 | #endif | |
131 | ||
132 | static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) | |
133 | { | |
134 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
135 | ||
7501c431 | 136 | if (enable && !host->sdio_irq_enabled) { |
ee289815 WS |
137 | u16 sdio_status; |
138 | ||
7501c431 UH |
139 | /* Keep device active while SDIO irq is enabled */ |
140 | pm_runtime_get_sync(mmc_dev(mmc)); | |
7501c431 | 141 | |
ee289815 | 142 | host->sdio_irq_enabled = true; |
54680fe7 SH |
143 | host->sdio_irq_mask = TMIO_SDIO_MASK_ALL & |
144 | ~TMIO_SDIO_STAT_IOIRQ; | |
ee289815 WS |
145 | |
146 | /* Clear obsolete interrupts before enabling */ | |
147 | sdio_status = sd_ctrl_read16(host, CTL_SDIO_STATUS) & ~TMIO_SDIO_MASK_ALL; | |
148 | if (host->pdata->flags & TMIO_MMC_SDIO_STATUS_SETBITS) | |
149 | sdio_status |= TMIO_SDIO_SETBITS_MASK; | |
150 | sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status); | |
151 | ||
54680fe7 | 152 | sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask); |
7501c431 | 153 | } else if (!enable && host->sdio_irq_enabled) { |
54680fe7 SH |
154 | host->sdio_irq_mask = TMIO_SDIO_MASK_ALL; |
155 | sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask); | |
7501c431 UH |
156 | |
157 | host->sdio_irq_enabled = false; | |
0369483e UH |
158 | pm_runtime_mark_last_busy(mmc_dev(mmc)); |
159 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
b6147490 GL |
160 | } |
161 | } | |
162 | ||
7fbc030d WS |
163 | static void tmio_mmc_clk_start(struct tmio_mmc_host *host) |
164 | { | |
165 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | | |
166 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
3d376fb2 | 167 | msleep(host->pdata->flags & TMIO_MMC_MIN_RCAR2 ? 1 : 10); |
7fbc030d WS |
168 | |
169 | if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) { | |
170 | sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100); | |
171 | msleep(10); | |
172 | } | |
173 | } | |
174 | ||
148634d2 WS |
175 | static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) |
176 | { | |
177 | if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) { | |
178 | sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000); | |
179 | msleep(10); | |
180 | } | |
181 | ||
182 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & | |
183 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
3d376fb2 | 184 | msleep(host->pdata->flags & TMIO_MMC_MIN_RCAR2 ? 5 : 10); |
148634d2 WS |
185 | } |
186 | ||
ae12d250 UH |
187 | static void tmio_mmc_set_clock(struct tmio_mmc_host *host, |
188 | unsigned int new_clock) | |
b6147490 GL |
189 | { |
190 | u32 clk = 0, clock; | |
191 | ||
148634d2 WS |
192 | if (new_clock == 0) { |
193 | tmio_mmc_clk_stop(host); | |
194 | return; | |
195 | } | |
2fb55956 | 196 | |
148634d2 WS |
197 | if (host->clk_update) |
198 | clock = host->clk_update(host, new_clock) / 512; | |
199 | else | |
200 | clock = host->mmc->f_min; | |
da29fe2b | 201 | |
148634d2 WS |
202 | for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) |
203 | clock <<= 1; | |
204 | ||
205 | /* 1/1 clock is option */ | |
206 | if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) | |
207 | clk |= 0xff; | |
b6147490 GL |
208 | |
209 | if (host->set_clk_div) | |
bf96208f | 210 | host->set_clk_div(host->pdev, (clk >> 22) & 1); |
b6147490 | 211 | |
14d5828f WS |
212 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & |
213 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
bf96208f | 214 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); |
3d376fb2 | 215 | if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) |
04e24b80 | 216 | msleep(10); |
7fbc030d WS |
217 | |
218 | tmio_mmc_clk_start(host); | |
b6147490 GL |
219 | } |
220 | ||
b6147490 GL |
221 | static void tmio_mmc_reset(struct tmio_mmc_host *host) |
222 | { | |
223 | /* FIXME - should we set stop clock reg here */ | |
224 | sd_ctrl_write16(host, CTL_RESET_SD, 0x0000); | |
5d60e500 | 225 | if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) |
69d1fe18 | 226 | sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000); |
b6147490 GL |
227 | msleep(10); |
228 | sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); | |
5d60e500 | 229 | if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) |
69d1fe18 | 230 | sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001); |
b6147490 GL |
231 | msleep(10); |
232 | } | |
233 | ||
234 | static void tmio_mmc_reset_work(struct work_struct *work) | |
235 | { | |
236 | struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host, | |
237 | delayed_reset_work.work); | |
238 | struct mmc_request *mrq; | |
239 | unsigned long flags; | |
240 | ||
241 | spin_lock_irqsave(&host->lock, flags); | |
242 | mrq = host->mrq; | |
243 | ||
df3ef2d3 GL |
244 | /* |
245 | * is request already finished? Since we use a non-blocking | |
246 | * cancel_delayed_work(), it can happen, that a .set_ios() call preempts | |
247 | * us, so, have to check for IS_ERR(host->mrq) | |
248 | */ | |
249 | if (IS_ERR_OR_NULL(mrq) | |
b6147490 | 250 | || time_is_after_jiffies(host->last_req_ts + |
0df9d2ea | 251 | msecs_to_jiffies(CMDREQ_TIMEOUT))) { |
b6147490 GL |
252 | spin_unlock_irqrestore(&host->lock, flags); |
253 | return; | |
254 | } | |
255 | ||
256 | dev_warn(&host->pdev->dev, | |
257 | "timeout waiting for hardware interrupt (CMD%u)\n", | |
258 | mrq->cmd->opcode); | |
259 | ||
260 | if (host->data) | |
261 | host->data->error = -ETIMEDOUT; | |
262 | else if (host->cmd) | |
263 | host->cmd->error = -ETIMEDOUT; | |
264 | else | |
265 | mrq->cmd->error = -ETIMEDOUT; | |
266 | ||
267 | host->cmd = NULL; | |
268 | host->data = NULL; | |
b6147490 GL |
269 | host->force_pio = false; |
270 | ||
271 | spin_unlock_irqrestore(&host->lock, flags); | |
272 | ||
273 | tmio_mmc_reset(host); | |
274 | ||
df3ef2d3 GL |
275 | /* Ready for new calls */ |
276 | host->mrq = NULL; | |
277 | ||
e3de2be7 | 278 | tmio_mmc_abort_dma(host); |
b6147490 GL |
279 | mmc_request_done(host->mmc, mrq); |
280 | } | |
281 | ||
df3ef2d3 | 282 | /* called with host->lock held, interrupts disabled */ |
b6147490 GL |
283 | static void tmio_mmc_finish_request(struct tmio_mmc_host *host) |
284 | { | |
b9269fdd GL |
285 | struct mmc_request *mrq; |
286 | unsigned long flags; | |
b6147490 | 287 | |
b9269fdd GL |
288 | spin_lock_irqsave(&host->lock, flags); |
289 | ||
290 | mrq = host->mrq; | |
291 | if (IS_ERR_OR_NULL(mrq)) { | |
292 | spin_unlock_irqrestore(&host->lock, flags); | |
b6147490 | 293 | return; |
b9269fdd | 294 | } |
b6147490 | 295 | |
b6147490 GL |
296 | host->cmd = NULL; |
297 | host->data = NULL; | |
298 | host->force_pio = false; | |
299 | ||
300 | cancel_delayed_work(&host->delayed_reset_work); | |
301 | ||
df3ef2d3 | 302 | host->mrq = NULL; |
b9269fdd | 303 | spin_unlock_irqrestore(&host->lock, flags); |
df3ef2d3 | 304 | |
e3de2be7 GL |
305 | if (mrq->cmd->error || (mrq->data && mrq->data->error)) |
306 | tmio_mmc_abort_dma(host); | |
307 | ||
4f119977 AK |
308 | if (host->check_scc_error) |
309 | host->check_scc_error(host); | |
310 | ||
b6147490 GL |
311 | mmc_request_done(host->mmc, mrq); |
312 | } | |
313 | ||
b9269fdd GL |
314 | static void tmio_mmc_done_work(struct work_struct *work) |
315 | { | |
316 | struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host, | |
317 | done); | |
318 | tmio_mmc_finish_request(host); | |
319 | } | |
320 | ||
b6147490 GL |
321 | /* These are the bitmasks the tmio chip requires to implement the MMC response |
322 | * types. Note that R1 and R6 are the same in this scheme. */ | |
323 | #define APP_CMD 0x0040 | |
324 | #define RESP_NONE 0x0300 | |
325 | #define RESP_R1 0x0400 | |
326 | #define RESP_R1B 0x0500 | |
327 | #define RESP_R2 0x0600 | |
328 | #define RESP_R3 0x0700 | |
329 | #define DATA_PRESENT 0x0800 | |
330 | #define TRANSFER_READ 0x1000 | |
331 | #define TRANSFER_MULTI 0x2000 | |
332 | #define SECURITY_CMD 0x4000 | |
b8d11962 | 333 | #define NO_CMD12_ISSUE 0x4000 /* TMIO_MMC_HAVE_CMD12_CTRL */ |
b6147490 GL |
334 | |
335 | static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd) | |
336 | { | |
337 | struct mmc_data *data = host->data; | |
338 | int c = cmd->opcode; | |
e23cd53c | 339 | u32 irq_mask = TMIO_MASK_CMD; |
b6147490 | 340 | |
0f506a96 GL |
341 | /* CMD12 is handled by hardware */ |
342 | if (cmd->opcode == MMC_STOP_TRANSMISSION && !cmd->arg) { | |
9afcbf4a | 343 | sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, TMIO_STOP_STP); |
b6147490 GL |
344 | return 0; |
345 | } | |
346 | ||
347 | switch (mmc_resp_type(cmd)) { | |
348 | case MMC_RSP_NONE: c |= RESP_NONE; break; | |
0bc0b6e8 WS |
349 | case MMC_RSP_R1: |
350 | case MMC_RSP_R1_NO_CRC: | |
351 | c |= RESP_R1; break; | |
b6147490 GL |
352 | case MMC_RSP_R1B: c |= RESP_R1B; break; |
353 | case MMC_RSP_R2: c |= RESP_R2; break; | |
354 | case MMC_RSP_R3: c |= RESP_R3; break; | |
355 | default: | |
356 | pr_debug("Unknown response type %d\n", mmc_resp_type(cmd)); | |
357 | return -EINVAL; | |
358 | } | |
359 | ||
360 | host->cmd = cmd; | |
361 | ||
362 | /* FIXME - this seems to be ok commented out but the spec suggest this bit | |
363 | * should be set when issuing app commands. | |
364 | * if(cmd->flags & MMC_FLAG_ACMD) | |
365 | * c |= APP_CMD; | |
366 | */ | |
367 | if (data) { | |
368 | c |= DATA_PRESENT; | |
369 | if (data->blocks > 1) { | |
9afcbf4a | 370 | sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, TMIO_STOP_SEC); |
b6147490 | 371 | c |= TRANSFER_MULTI; |
b8d11962 SU |
372 | |
373 | /* | |
374 | * Disable auto CMD12 at IO_RW_EXTENDED when | |
375 | * multiple block transfer | |
376 | */ | |
377 | if ((host->pdata->flags & TMIO_MMC_HAVE_CMD12_CTRL) && | |
378 | (cmd->opcode == SD_IO_RW_EXTENDED)) | |
379 | c |= NO_CMD12_ISSUE; | |
b6147490 GL |
380 | } |
381 | if (data->flags & MMC_DATA_READ) | |
382 | c |= TRANSFER_READ; | |
383 | } | |
384 | ||
e23cd53c GL |
385 | if (!host->native_hotplug) |
386 | irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT); | |
387 | tmio_mmc_enable_mmc_irqs(host, irq_mask); | |
b6147490 GL |
388 | |
389 | /* Fire off the command */ | |
2c54506b | 390 | sd_ctrl_write32_as_16_and_16(host, CTL_ARG_REG, cmd->arg); |
b6147490 GL |
391 | sd_ctrl_write16(host, CTL_SD_CMD, c); |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
b9bd7ff8 KM |
396 | static void tmio_mmc_transfer_data(struct tmio_mmc_host *host, |
397 | unsigned short *buf, | |
398 | unsigned int count) | |
399 | { | |
400 | int is_read = host->data->flags & MMC_DATA_READ; | |
401 | u8 *buf8; | |
402 | ||
403 | /* | |
404 | * Transfer the data | |
405 | */ | |
8185e51f CB |
406 | if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) { |
407 | u8 data[4] = { }; | |
408 | ||
409 | if (is_read) | |
410 | sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf, | |
411 | count >> 2); | |
412 | else | |
413 | sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf, | |
414 | count >> 2); | |
415 | ||
416 | /* if count was multiple of 4 */ | |
417 | if (!(count & 0x3)) | |
418 | return; | |
419 | ||
420 | buf8 = (u8 *)(buf + (count >> 2)); | |
421 | count %= 4; | |
422 | ||
423 | if (is_read) { | |
424 | sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, | |
425 | (u32 *)data, 1); | |
426 | memcpy(buf8, data, count); | |
427 | } else { | |
428 | memcpy(data, buf8, count); | |
429 | sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, | |
430 | (u32 *)data, 1); | |
431 | } | |
432 | ||
433 | return; | |
434 | } | |
435 | ||
b9bd7ff8 KM |
436 | if (is_read) |
437 | sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1); | |
438 | else | |
439 | sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1); | |
440 | ||
441 | /* if count was even number */ | |
442 | if (!(count & 0x1)) | |
443 | return; | |
444 | ||
445 | /* if count was odd number */ | |
446 | buf8 = (u8 *)(buf + (count >> 1)); | |
447 | ||
448 | /* | |
449 | * FIXME | |
450 | * | |
451 | * driver and this function are assuming that | |
452 | * it is used as little endian | |
453 | */ | |
454 | if (is_read) | |
455 | *buf8 = sd_ctrl_read16(host, CTL_SD_DATA_PORT) & 0xff; | |
456 | else | |
457 | sd_ctrl_write16(host, CTL_SD_DATA_PORT, *buf8); | |
458 | } | |
459 | ||
b6147490 GL |
460 | /* |
461 | * This chip always returns (at least?) as much data as you ask for. | |
462 | * I'm unsure what happens if you ask for less than a block. This should be | |
25985edc | 463 | * looked into to ensure that a funny length read doesn't hose the controller. |
b6147490 GL |
464 | */ |
465 | static void tmio_mmc_pio_irq(struct tmio_mmc_host *host) | |
466 | { | |
467 | struct mmc_data *data = host->data; | |
468 | void *sg_virt; | |
469 | unsigned short *buf; | |
470 | unsigned int count; | |
471 | unsigned long flags; | |
472 | ||
473 | if ((host->chan_tx || host->chan_rx) && !host->force_pio) { | |
474 | pr_err("PIO IRQ in DMA mode!\n"); | |
475 | return; | |
476 | } else if (!data) { | |
477 | pr_debug("Spurious PIO IRQ\n"); | |
478 | return; | |
479 | } | |
480 | ||
481 | sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags); | |
482 | buf = (unsigned short *)(sg_virt + host->sg_off); | |
483 | ||
484 | count = host->sg_ptr->length - host->sg_off; | |
485 | if (count > data->blksz) | |
486 | count = data->blksz; | |
487 | ||
488 | pr_debug("count: %08x offset: %08x flags %08x\n", | |
489 | count, host->sg_off, data->flags); | |
490 | ||
491 | /* Transfer the data */ | |
b9bd7ff8 | 492 | tmio_mmc_transfer_data(host, buf, count); |
b6147490 GL |
493 | |
494 | host->sg_off += count; | |
495 | ||
496 | tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt); | |
497 | ||
498 | if (host->sg_off == host->sg_ptr->length) | |
499 | tmio_mmc_next_sg(host); | |
500 | ||
501 | return; | |
502 | } | |
503 | ||
504 | static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host) | |
505 | { | |
506 | if (host->sg_ptr == &host->bounce_sg) { | |
507 | unsigned long flags; | |
508 | void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags); | |
509 | memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length); | |
510 | tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr); | |
511 | } | |
512 | } | |
513 | ||
514 | /* needs to be called with host->lock held */ | |
515 | void tmio_mmc_do_data_irq(struct tmio_mmc_host *host) | |
516 | { | |
517 | struct mmc_data *data = host->data; | |
518 | struct mmc_command *stop; | |
519 | ||
520 | host->data = NULL; | |
521 | ||
522 | if (!data) { | |
523 | dev_warn(&host->pdev->dev, "Spurious data end IRQ\n"); | |
524 | return; | |
525 | } | |
526 | stop = data->stop; | |
527 | ||
528 | /* FIXME - return correct transfer count on errors */ | |
529 | if (!data->error) | |
530 | data->bytes_xfered = data->blocks * data->blksz; | |
531 | else | |
532 | data->bytes_xfered = 0; | |
533 | ||
534 | pr_debug("Completed data request\n"); | |
535 | ||
536 | /* | |
537 | * FIXME: other drivers allow an optional stop command of any given type | |
538 | * which we dont do, as the chip can auto generate them. | |
539 | * Perhaps we can be smarter about when to use auto CMD12 and | |
540 | * only issue the auto request when we know this is the desired | |
541 | * stop command, allowing fallback to the stop command the | |
542 | * upper layers expect. For now, we do what works. | |
543 | */ | |
544 | ||
545 | if (data->flags & MMC_DATA_READ) { | |
546 | if (host->chan_rx && !host->force_pio) | |
547 | tmio_mmc_check_bounce_buffer(host); | |
548 | dev_dbg(&host->pdev->dev, "Complete Rx request %p\n", | |
549 | host->mrq); | |
550 | } else { | |
551 | dev_dbg(&host->pdev->dev, "Complete Tx request %p\n", | |
552 | host->mrq); | |
553 | } | |
554 | ||
555 | if (stop) { | |
022f731e WS |
556 | if (stop->opcode != MMC_STOP_TRANSMISSION || stop->arg) |
557 | dev_err(&host->pdev->dev, "unsupported stop: CMD%u,0x%x. We did CMD12,0\n", | |
558 | stop->opcode, stop->arg); | |
559 | ||
eb7c00e1 WS |
560 | /* fill in response from auto CMD12 */ |
561 | stop->resp[0] = sd_ctrl_read16_and_16_as_32(host, CTL_RESPONSE); | |
562 | ||
022f731e | 563 | sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0); |
b6147490 GL |
564 | } |
565 | ||
b9269fdd | 566 | schedule_work(&host->done); |
b6147490 GL |
567 | } |
568 | ||
96e0b2ba | 569 | static void tmio_mmc_data_irq(struct tmio_mmc_host *host, unsigned int stat) |
b6147490 GL |
570 | { |
571 | struct mmc_data *data; | |
572 | spin_lock(&host->lock); | |
573 | data = host->data; | |
574 | ||
575 | if (!data) | |
576 | goto out; | |
577 | ||
96e0b2ba AK |
578 | if (stat & TMIO_STAT_CRCFAIL || stat & TMIO_STAT_STOPBIT_ERR || |
579 | stat & TMIO_STAT_TXUNDERRUN) | |
580 | data->error = -EILSEQ; | |
b6147490 | 581 | if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) { |
2c54506b | 582 | u32 status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS); |
81e888da SU |
583 | bool done = false; |
584 | ||
b6147490 GL |
585 | /* |
586 | * Has all data been written out yet? Testing on SuperH showed, | |
587 | * that in most cases the first interrupt comes already with the | |
588 | * BUSY status bit clear, but on some operations, like mount or | |
589 | * in the beginning of a write / sync / umount, there is one | |
590 | * DATAEND interrupt with the BUSY bit set, in this cases | |
591 | * waiting for one more interrupt fixes the problem. | |
592 | */ | |
81e888da | 593 | if (host->pdata->flags & TMIO_MMC_HAS_IDLE_WAIT) { |
a21553c9 | 594 | if (status & TMIO_STAT_SCLKDIVEN) |
81e888da SU |
595 | done = true; |
596 | } else { | |
597 | if (!(status & TMIO_STAT_CMD_BUSY)) | |
598 | done = true; | |
599 | } | |
600 | ||
601 | if (done) { | |
b6147490 | 602 | tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND); |
52ad9a8e | 603 | complete(&host->dma_dataend); |
b6147490 GL |
604 | } |
605 | } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) { | |
606 | tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND); | |
52ad9a8e | 607 | complete(&host->dma_dataend); |
b6147490 GL |
608 | } else { |
609 | tmio_mmc_do_data_irq(host); | |
610 | tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP); | |
611 | } | |
612 | out: | |
613 | spin_unlock(&host->lock); | |
614 | } | |
615 | ||
616 | static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host, | |
617 | unsigned int stat) | |
618 | { | |
619 | struct mmc_command *cmd = host->cmd; | |
620 | int i, addr; | |
621 | ||
622 | spin_lock(&host->lock); | |
623 | ||
624 | if (!host->cmd) { | |
625 | pr_debug("Spurious CMD irq\n"); | |
626 | goto out; | |
627 | } | |
628 | ||
b6147490 GL |
629 | /* This controller is sicker than the PXA one. Not only do we need to |
630 | * drop the top 8 bits of the first response word, we also need to | |
631 | * modify the order of the response for short response command types. | |
632 | */ | |
633 | ||
634 | for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4) | |
2c54506b | 635 | cmd->resp[i] = sd_ctrl_read16_and_16_as_32(host, addr); |
b6147490 GL |
636 | |
637 | if (cmd->flags & MMC_RSP_136) { | |
638 | cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24); | |
639 | cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24); | |
640 | cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24); | |
641 | cmd->resp[3] <<= 8; | |
642 | } else if (cmd->flags & MMC_RSP_R3) { | |
643 | cmd->resp[0] = cmd->resp[3]; | |
644 | } | |
645 | ||
646 | if (stat & TMIO_STAT_CMDTIMEOUT) | |
647 | cmd->error = -ETIMEDOUT; | |
96e0b2ba AK |
648 | else if ((stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC) || |
649 | stat & TMIO_STAT_STOPBIT_ERR || | |
650 | stat & TMIO_STAT_CMD_IDX_ERR) | |
b6147490 GL |
651 | cmd->error = -EILSEQ; |
652 | ||
653 | /* If there is data to handle we enable data IRQs here, and | |
654 | * we will ultimatley finish the request in the data_end handler. | |
655 | * If theres no data or we encountered an error, finish now. | |
656 | */ | |
96e0b2ba | 657 | if (host->data && (!cmd->error || cmd->error == -EILSEQ)) { |
b6147490 GL |
658 | if (host->data->flags & MMC_DATA_READ) { |
659 | if (host->force_pio || !host->chan_rx) | |
660 | tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP); | |
661 | else | |
662 | tasklet_schedule(&host->dma_issue); | |
663 | } else { | |
664 | if (host->force_pio || !host->chan_tx) | |
665 | tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP); | |
666 | else | |
667 | tasklet_schedule(&host->dma_issue); | |
668 | } | |
669 | } else { | |
b9269fdd | 670 | schedule_work(&host->done); |
b6147490 GL |
671 | } |
672 | ||
673 | out: | |
674 | spin_unlock(&host->lock); | |
675 | } | |
676 | ||
7729c7a2 SH |
677 | static bool __tmio_mmc_card_detect_irq(struct tmio_mmc_host *host, |
678 | int ireg, int status) | |
679 | { | |
680 | struct mmc_host *mmc = host->mmc; | |
b6147490 | 681 | |
e312eb1e PP |
682 | /* Card insert / remove attempts */ |
683 | if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) { | |
684 | tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT | | |
685 | TMIO_STAT_CARD_REMOVE); | |
71d111cd GL |
686 | if ((((ireg & TMIO_STAT_CARD_REMOVE) && mmc->card) || |
687 | ((ireg & TMIO_STAT_CARD_INSERT) && !mmc->card)) && | |
688 | !work_pending(&mmc->detect.work)) | |
b9269fdd | 689 | mmc_detect_change(host->mmc, msecs_to_jiffies(100)); |
7729c7a2 | 690 | return true; |
b6147490 GL |
691 | } |
692 | ||
7729c7a2 SH |
693 | return false; |
694 | } | |
695 | ||
7729c7a2 SH |
696 | static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host, |
697 | int ireg, int status) | |
698 | { | |
e312eb1e PP |
699 | /* Command completion */ |
700 | if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) { | |
701 | tmio_mmc_ack_mmc_irqs(host, | |
702 | TMIO_STAT_CMDRESPEND | | |
703 | TMIO_STAT_CMDTIMEOUT); | |
704 | tmio_mmc_cmd_irq(host, status); | |
7729c7a2 | 705 | return true; |
e312eb1e | 706 | } |
b6147490 | 707 | |
e312eb1e PP |
708 | /* Data transfer */ |
709 | if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) { | |
710 | tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ); | |
711 | tmio_mmc_pio_irq(host); | |
7729c7a2 | 712 | return true; |
e312eb1e | 713 | } |
b6147490 | 714 | |
e312eb1e PP |
715 | /* Data transfer completion */ |
716 | if (ireg & TMIO_STAT_DATAEND) { | |
717 | tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND); | |
96e0b2ba | 718 | tmio_mmc_data_irq(host, status); |
7729c7a2 | 719 | return true; |
b6147490 | 720 | } |
e312eb1e | 721 | |
7729c7a2 SH |
722 | return false; |
723 | } | |
724 | ||
e4f38eb1 | 725 | static void __tmio_mmc_sdio_irq(struct tmio_mmc_host *host) |
7729c7a2 | 726 | { |
7729c7a2 SH |
727 | struct mmc_host *mmc = host->mmc; |
728 | struct tmio_mmc_data *pdata = host->pdata; | |
729 | unsigned int ireg, status; | |
6b98757e | 730 | unsigned int sdio_status; |
7729c7a2 SH |
731 | |
732 | if (!(pdata->flags & TMIO_MMC_SDIO_IRQ)) | |
4da98670 | 733 | return; |
7729c7a2 SH |
734 | |
735 | status = sd_ctrl_read16(host, CTL_SDIO_STATUS); | |
0c4bf5be | 736 | ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdio_irq_mask; |
7729c7a2 | 737 | |
6b98757e | 738 | sdio_status = status & ~TMIO_SDIO_MASK_ALL; |
20dd0373 | 739 | if (pdata->flags & TMIO_MMC_SDIO_STATUS_SETBITS) |
ee289815 | 740 | sdio_status |= TMIO_SDIO_SETBITS_MASK; |
6b98757e SU |
741 | |
742 | sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status); | |
7729c7a2 SH |
743 | |
744 | if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ) | |
745 | mmc_signal_sdio_irq(mmc); | |
7729c7a2 | 746 | } |
7729c7a2 SH |
747 | |
748 | irqreturn_t tmio_mmc_irq(int irq, void *devid) | |
749 | { | |
750 | struct tmio_mmc_host *host = devid; | |
751 | unsigned int ireg, status; | |
752 | ||
2c54506b | 753 | status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS); |
95840126 WS |
754 | ireg = status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask; |
755 | ||
756 | pr_debug_status(status); | |
757 | pr_debug_status(ireg); | |
758 | ||
759 | /* Clear the status except the interrupt status */ | |
2c54506b | 760 | sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, TMIO_MASK_IRQ); |
7729c7a2 | 761 | |
7729c7a2 SH |
762 | if (__tmio_mmc_card_detect_irq(host, ireg, status)) |
763 | return IRQ_HANDLED; | |
764 | if (__tmio_mmc_sdcard_irq(host, ireg, status)) | |
765 | return IRQ_HANDLED; | |
766 | ||
e4f38eb1 | 767 | __tmio_mmc_sdio_irq(host); |
b6147490 | 768 | |
b6147490 GL |
769 | return IRQ_HANDLED; |
770 | } | |
8e7bfdb3 | 771 | EXPORT_SYMBOL(tmio_mmc_irq); |
b6147490 GL |
772 | |
773 | static int tmio_mmc_start_data(struct tmio_mmc_host *host, | |
774 | struct mmc_data *data) | |
775 | { | |
776 | struct tmio_mmc_data *pdata = host->pdata; | |
777 | ||
778 | pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n", | |
779 | data->blksz, data->blocks); | |
780 | ||
0bc0b6e8 WS |
781 | /* Some hardware cannot perform 2 byte requests in 4/8 bit mode */ |
782 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4 || | |
783 | host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) { | |
b6147490 GL |
784 | int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES; |
785 | ||
786 | if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) { | |
0bc0b6e8 | 787 | pr_err("%s: %d byte block unsupported in 4/8 bit mode\n", |
b6147490 GL |
788 | mmc_hostname(host->mmc), data->blksz); |
789 | return -EINVAL; | |
790 | } | |
791 | } | |
792 | ||
793 | tmio_mmc_init_sg(host, data); | |
794 | host->data = data; | |
795 | ||
796 | /* Set transfer length / blocksize */ | |
797 | sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz); | |
798 | sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks); | |
799 | ||
800 | tmio_mmc_start_dma(host, data); | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
e8f36b5d AK |
805 | static void tmio_mmc_hw_reset(struct mmc_host *mmc) |
806 | { | |
807 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
808 | ||
809 | if (host->hw_reset) | |
810 | host->hw_reset(host); | |
811 | } | |
812 | ||
4f119977 AK |
813 | static int tmio_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode) |
814 | { | |
815 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
816 | int i, ret = 0; | |
817 | ||
43b0b361 MH |
818 | if (!host->init_tuning || !host->select_tuning) |
819 | /* Tuning is not supported */ | |
820 | goto out; | |
4f119977 | 821 | |
43b0b361 MH |
822 | host->tap_num = host->init_tuning(host); |
823 | if (!host->tap_num) | |
824 | /* Tuning is not supported */ | |
825 | goto out; | |
4f119977 AK |
826 | |
827 | if (host->tap_num * 2 >= sizeof(host->taps) * BITS_PER_BYTE) { | |
828 | dev_warn_once(&host->pdev->dev, | |
829 | "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n"); | |
830 | goto out; | |
831 | } | |
832 | ||
833 | bitmap_zero(host->taps, host->tap_num * 2); | |
834 | ||
835 | /* Issue CMD19 twice for each tap */ | |
836 | for (i = 0; i < 2 * host->tap_num; i++) { | |
837 | if (host->prepare_tuning) | |
838 | host->prepare_tuning(host, i % host->tap_num); | |
839 | ||
840 | ret = mmc_send_tuning(mmc, opcode, NULL); | |
841 | if (ret && ret != -EILSEQ) | |
842 | goto out; | |
843 | if (ret == 0) | |
844 | set_bit(i, host->taps); | |
845 | ||
846 | mdelay(1); | |
847 | } | |
848 | ||
849 | ret = host->select_tuning(host); | |
850 | ||
851 | out: | |
852 | if (ret < 0) { | |
853 | dev_warn(&host->pdev->dev, "Tuning procedure failed\n"); | |
854 | tmio_mmc_hw_reset(mmc); | |
855 | } | |
856 | ||
857 | return ret; | |
858 | } | |
859 | ||
b6147490 GL |
860 | /* Process requests from the MMC layer */ |
861 | static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
862 | { | |
863 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
df3ef2d3 | 864 | unsigned long flags; |
b6147490 GL |
865 | int ret; |
866 | ||
df3ef2d3 GL |
867 | spin_lock_irqsave(&host->lock, flags); |
868 | ||
869 | if (host->mrq) { | |
b6147490 | 870 | pr_debug("request not null\n"); |
df3ef2d3 GL |
871 | if (IS_ERR(host->mrq)) { |
872 | spin_unlock_irqrestore(&host->lock, flags); | |
873 | mrq->cmd->error = -EAGAIN; | |
874 | mmc_request_done(mmc, mrq); | |
875 | return; | |
876 | } | |
877 | } | |
b6147490 GL |
878 | |
879 | host->last_req_ts = jiffies; | |
880 | wmb(); | |
881 | host->mrq = mrq; | |
882 | ||
df3ef2d3 GL |
883 | spin_unlock_irqrestore(&host->lock, flags); |
884 | ||
b6147490 GL |
885 | if (mrq->data) { |
886 | ret = tmio_mmc_start_data(host, mrq->data); | |
887 | if (ret) | |
888 | goto fail; | |
889 | } | |
890 | ||
891 | ret = tmio_mmc_start_command(host, mrq->cmd); | |
892 | if (!ret) { | |
893 | schedule_delayed_work(&host->delayed_reset_work, | |
0df9d2ea | 894 | msecs_to_jiffies(CMDREQ_TIMEOUT)); |
b6147490 GL |
895 | return; |
896 | } | |
897 | ||
898 | fail: | |
b6147490 | 899 | host->force_pio = false; |
df3ef2d3 | 900 | host->mrq = NULL; |
b6147490 GL |
901 | mrq->cmd->error = ret; |
902 | mmc_request_done(mmc, mrq); | |
903 | } | |
904 | ||
2fb55956 | 905 | static int tmio_mmc_clk_enable(struct tmio_mmc_host *host) |
8c102a96 | 906 | { |
4fe2ec57 | 907 | if (!host->clk_enable) |
8c102a96 GL |
908 | return -ENOTSUPP; |
909 | ||
2fb55956 | 910 | return host->clk_enable(host); |
8c102a96 GL |
911 | } |
912 | ||
dfcba5ff WS |
913 | static void tmio_mmc_clk_disable(struct tmio_mmc_host *host) |
914 | { | |
915 | if (host->clk_disable) | |
916 | host->clk_disable(host); | |
917 | } | |
918 | ||
619b08d4 | 919 | static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd) |
b958a67c GL |
920 | { |
921 | struct mmc_host *mmc = host->mmc; | |
619b08d4 GL |
922 | int ret = 0; |
923 | ||
924 | /* .set_ios() is returning void, so, no chance to report an error */ | |
b958a67c | 925 | |
9d731e75 CB |
926 | if (host->set_pwr) |
927 | host->set_pwr(host->pdev, 1); | |
928 | ||
619b08d4 GL |
929 | if (!IS_ERR(mmc->supply.vmmc)) { |
930 | ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); | |
931 | /* | |
932 | * Attention: empiric value. With a b43 WiFi SDIO card this | |
933 | * delay proved necessary for reliable card-insertion probing. | |
934 | * 100us were not enough. Is this the same 140us delay, as in | |
935 | * tmio_mmc_set_ios()? | |
936 | */ | |
937 | udelay(200); | |
938 | } | |
939 | /* | |
940 | * It seems, VccQ should be switched on after Vcc, this is also what the | |
941 | * omap_hsmmc.c driver does. | |
942 | */ | |
943 | if (!IS_ERR(mmc->supply.vqmmc) && !ret) { | |
6d1d6b47 | 944 | ret = regulator_enable(mmc->supply.vqmmc); |
619b08d4 GL |
945 | udelay(200); |
946 | } | |
6d1d6b47 GL |
947 | |
948 | if (ret < 0) | |
949 | dev_dbg(&host->pdev->dev, "Regulators failed to power up: %d\n", | |
950 | ret); | |
619b08d4 GL |
951 | } |
952 | ||
953 | static void tmio_mmc_power_off(struct tmio_mmc_host *host) | |
954 | { | |
955 | struct mmc_host *mmc = host->mmc; | |
956 | ||
957 | if (!IS_ERR(mmc->supply.vqmmc)) | |
958 | regulator_disable(mmc->supply.vqmmc); | |
959 | ||
b958a67c | 960 | if (!IS_ERR(mmc->supply.vmmc)) |
619b08d4 | 961 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
9d731e75 CB |
962 | |
963 | if (host->set_pwr) | |
964 | host->set_pwr(host->pdev, 0); | |
b958a67c GL |
965 | } |
966 | ||
9ae4ed7d UH |
967 | static void tmio_mmc_set_bus_width(struct tmio_mmc_host *host, |
968 | unsigned char bus_width) | |
969 | { | |
0bc0b6e8 WS |
970 | u16 reg = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT) |
971 | & ~(CARD_OPT_WIDTH | CARD_OPT_WIDTH8); | |
972 | ||
973 | /* reg now applies to MMC_BUS_WIDTH_4 */ | |
974 | if (bus_width == MMC_BUS_WIDTH_1) | |
975 | reg |= CARD_OPT_WIDTH; | |
976 | else if (bus_width == MMC_BUS_WIDTH_8) | |
977 | reg |= CARD_OPT_WIDTH8; | |
978 | ||
979 | sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, reg); | |
9ae4ed7d UH |
980 | } |
981 | ||
b6147490 GL |
982 | /* Set MMC clock / power. |
983 | * Note: This controller uses a simple divider scheme therefore it cannot | |
984 | * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as | |
985 | * MMC wont run that fast, it has to be clocked at 12MHz which is the next | |
986 | * slowest setting. | |
987 | */ | |
988 | static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
989 | { | |
990 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
4932bd64 | 991 | struct device *dev = &host->pdev->dev; |
df3ef2d3 GL |
992 | unsigned long flags; |
993 | ||
b9269fdd GL |
994 | mutex_lock(&host->ios_lock); |
995 | ||
df3ef2d3 GL |
996 | spin_lock_irqsave(&host->lock, flags); |
997 | if (host->mrq) { | |
998 | if (IS_ERR(host->mrq)) { | |
4932bd64 | 999 | dev_dbg(dev, |
df3ef2d3 GL |
1000 | "%s.%d: concurrent .set_ios(), clk %u, mode %u\n", |
1001 | current->comm, task_pid_nr(current), | |
1002 | ios->clock, ios->power_mode); | |
1003 | host->mrq = ERR_PTR(-EINTR); | |
1004 | } else { | |
4932bd64 | 1005 | dev_dbg(dev, |
df3ef2d3 GL |
1006 | "%s.%d: CMD%u active since %lu, now %lu!\n", |
1007 | current->comm, task_pid_nr(current), | |
1008 | host->mrq->cmd->opcode, host->last_req_ts, jiffies); | |
1009 | } | |
1010 | spin_unlock_irqrestore(&host->lock, flags); | |
b9269fdd GL |
1011 | |
1012 | mutex_unlock(&host->ios_lock); | |
df3ef2d3 GL |
1013 | return; |
1014 | } | |
1015 | ||
1016 | host->mrq = ERR_PTR(-EBUSY); | |
1017 | ||
1018 | spin_unlock_irqrestore(&host->lock, flags); | |
b6147490 | 1019 | |
3b292bb0 UH |
1020 | switch (ios->power_mode) { |
1021 | case MMC_POWER_OFF: | |
1022 | tmio_mmc_power_off(host); | |
1023 | tmio_mmc_clk_stop(host); | |
1024 | break; | |
1025 | case MMC_POWER_UP: | |
3b292bb0 | 1026 | tmio_mmc_power_on(host, ios->vdd); |
7fbc030d | 1027 | tmio_mmc_set_clock(host, ios->clock); |
9ae4ed7d | 1028 | tmio_mmc_set_bus_width(host, ios->bus_width); |
3b292bb0 UH |
1029 | break; |
1030 | case MMC_POWER_ON: | |
1031 | tmio_mmc_set_clock(host, ios->clock); | |
3b292bb0 UH |
1032 | tmio_mmc_set_bus_width(host, ios->bus_width); |
1033 | break; | |
1034 | } | |
b6147490 GL |
1035 | |
1036 | /* Let things settle. delay taken from winCE driver */ | |
1037 | udelay(140); | |
df3ef2d3 GL |
1038 | if (PTR_ERR(host->mrq) == -EINTR) |
1039 | dev_dbg(&host->pdev->dev, | |
1040 | "%s.%d: IOS interrupted: clk %u, mode %u", | |
1041 | current->comm, task_pid_nr(current), | |
1042 | ios->clock, ios->power_mode); | |
1043 | host->mrq = NULL; | |
b9269fdd | 1044 | |
ae12d250 UH |
1045 | host->clk_cache = ios->clock; |
1046 | ||
b9269fdd | 1047 | mutex_unlock(&host->ios_lock); |
b6147490 GL |
1048 | } |
1049 | ||
1050 | static int tmio_mmc_get_ro(struct mmc_host *mmc) | |
1051 | { | |
1052 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
1053 | struct tmio_mmc_data *pdata = host->pdata; | |
3071cafb GL |
1054 | int ret = mmc_gpio_get_ro(mmc); |
1055 | if (ret >= 0) | |
1056 | return ret; | |
b6147490 | 1057 | |
0369483e | 1058 | ret = !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) || |
2c54506b | 1059 | (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT)); |
0369483e UH |
1060 | |
1061 | return ret; | |
b6147490 GL |
1062 | } |
1063 | ||
bbf0208d KM |
1064 | static int tmio_multi_io_quirk(struct mmc_card *card, |
1065 | unsigned int direction, int blk_size) | |
1066 | { | |
1067 | struct tmio_mmc_host *host = mmc_priv(card->host); | |
bbf0208d | 1068 | |
85c02ddd KM |
1069 | if (host->multi_io_quirk) |
1070 | return host->multi_io_quirk(card, direction, blk_size); | |
bbf0208d KM |
1071 | |
1072 | return blk_size; | |
1073 | } | |
1074 | ||
452e5eef | 1075 | static struct mmc_host_ops tmio_mmc_ops = { |
b6147490 GL |
1076 | .request = tmio_mmc_request, |
1077 | .set_ios = tmio_mmc_set_ios, | |
1078 | .get_ro = tmio_mmc_get_ro, | |
2b63b341 | 1079 | .get_cd = mmc_gpio_get_cd, |
b6147490 | 1080 | .enable_sdio_irq = tmio_mmc_enable_sdio_irq, |
bbf0208d | 1081 | .multi_io_quirk = tmio_multi_io_quirk, |
e8f36b5d | 1082 | .hw_reset = tmio_mmc_hw_reset, |
4f119977 | 1083 | .execute_tuning = tmio_mmc_execute_tuning, |
b6147490 GL |
1084 | }; |
1085 | ||
05fae4a7 | 1086 | static int tmio_mmc_init_ocr(struct tmio_mmc_host *host) |
b958a67c GL |
1087 | { |
1088 | struct tmio_mmc_data *pdata = host->pdata; | |
1089 | struct mmc_host *mmc = host->mmc; | |
1090 | ||
1091 | mmc_regulator_get_supply(mmc); | |
1092 | ||
05fae4a7 | 1093 | /* use ocr_mask if no regulator */ |
b958a67c | 1094 | if (!mmc->ocr_avail) |
05fae4a7 KM |
1095 | mmc->ocr_avail = pdata->ocr_mask; |
1096 | ||
1097 | /* | |
1098 | * try again. | |
1099 | * There is possibility that regulator has not been probed | |
1100 | */ | |
1101 | if (!mmc->ocr_avail) | |
1102 | return -EPROBE_DEFER; | |
1103 | ||
1104 | return 0; | |
b958a67c GL |
1105 | } |
1106 | ||
5a00a971 GL |
1107 | static void tmio_mmc_of_parse(struct platform_device *pdev, |
1108 | struct tmio_mmc_data *pdata) | |
1109 | { | |
1110 | const struct device_node *np = pdev->dev.of_node; | |
1111 | if (!np) | |
1112 | return; | |
1113 | ||
1114 | if (of_get_property(np, "toshiba,mmc-wrprotect-disable", NULL)) | |
1115 | pdata->flags |= TMIO_MMC_WRPROTECT_DISABLE; | |
1116 | } | |
1117 | ||
94b110af KM |
1118 | struct tmio_mmc_host* |
1119 | tmio_mmc_host_alloc(struct platform_device *pdev) | |
b6147490 | 1120 | { |
94b110af | 1121 | struct tmio_mmc_host *host; |
b6147490 | 1122 | struct mmc_host *mmc; |
94b110af KM |
1123 | |
1124 | mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev); | |
1125 | if (!mmc) | |
1126 | return NULL; | |
1127 | ||
1128 | host = mmc_priv(mmc); | |
1129 | host->mmc = mmc; | |
1130 | host->pdev = pdev; | |
1131 | ||
1132 | return host; | |
1133 | } | |
1134 | EXPORT_SYMBOL(tmio_mmc_host_alloc); | |
1135 | ||
1136 | void tmio_mmc_host_free(struct tmio_mmc_host *host) | |
1137 | { | |
1138 | mmc_free_host(host->mmc); | |
94b110af KM |
1139 | } |
1140 | EXPORT_SYMBOL(tmio_mmc_host_free); | |
1141 | ||
1142 | int tmio_mmc_host_probe(struct tmio_mmc_host *_host, | |
1143 | struct tmio_mmc_data *pdata) | |
1144 | { | |
1145 | struct platform_device *pdev = _host->pdev; | |
1146 | struct mmc_host *mmc = _host->mmc; | |
b6147490 GL |
1147 | struct resource *res_ctl; |
1148 | int ret; | |
1149 | u32 irq_mask = TMIO_MASK_CMD; | |
1150 | ||
5a00a971 GL |
1151 | tmio_mmc_of_parse(pdev, pdata); |
1152 | ||
7b952137 | 1153 | if (!(pdata->flags & TMIO_MMC_HAS_IDLE_WAIT)) |
dfe9a229 | 1154 | _host->write16_hook = NULL; |
7b952137 | 1155 | |
b6147490 GL |
1156 | res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1157 | if (!res_ctl) | |
1158 | return -EINVAL; | |
1159 | ||
274a752b SB |
1160 | ret = mmc_of_parse(mmc); |
1161 | if (ret < 0) | |
ad7014b3 | 1162 | return ret; |
5a00a971 | 1163 | |
b6147490 | 1164 | _host->pdata = pdata; |
b6147490 GL |
1165 | platform_set_drvdata(pdev, mmc); |
1166 | ||
9d731e75 | 1167 | _host->set_pwr = pdata->set_pwr; |
b6147490 GL |
1168 | _host->set_clk_div = pdata->set_clk_div; |
1169 | ||
05fae4a7 KM |
1170 | ret = tmio_mmc_init_ocr(_host); |
1171 | if (ret < 0) | |
ad7014b3 | 1172 | return ret; |
05fae4a7 | 1173 | |
7df56bbb IM |
1174 | _host->ctl = devm_ioremap(&pdev->dev, |
1175 | res_ctl->start, resource_size(res_ctl)); | |
ad7014b3 WS |
1176 | if (!_host->ctl) |
1177 | return -ENOMEM; | |
b6147490 | 1178 | |
6a4679f3 | 1179 | tmio_mmc_ops.card_busy = _host->card_busy; |
452e5eef | 1180 | tmio_mmc_ops.start_signal_voltage_switch = _host->start_signal_voltage_switch; |
b6147490 | 1181 | mmc->ops = &tmio_mmc_ops; |
452e5eef | 1182 | |
5a00a971 | 1183 | mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities; |
dd006b30 | 1184 | mmc->caps2 |= pdata->capabilities2; |
b6147490 GL |
1185 | mmc->max_segs = 32; |
1186 | mmc->max_blk_size = 512; | |
09cbfeaf | 1187 | mmc->max_blk_count = (PAGE_SIZE / mmc->max_blk_size) * |
b6147490 GL |
1188 | mmc->max_segs; |
1189 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1190 | mmc->max_seg_size = mmc->max_req_size; | |
b6147490 | 1191 | |
c8be24c2 | 1192 | _host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD || |
2b1ac5c2 | 1193 | mmc->caps & MMC_CAP_NEEDS_POLL || |
efd7be7b | 1194 | !mmc_card_is_removable(mmc)); |
2b1ac5c2 | 1195 | |
0bc0b6e8 WS |
1196 | /* |
1197 | * On Gen2+, eMMC with NONREMOVABLE currently fails because native | |
1198 | * hotplug gets disabled. It seems RuntimePM related yet we need further | |
1199 | * research. Since we are planning a PM overhaul anyway, let's enforce | |
1200 | * for now the device being active by enabling native hotplug always. | |
1201 | */ | |
1202 | if (pdata->flags & TMIO_MMC_MIN_RCAR2) | |
1203 | _host->native_hotplug = true; | |
1204 | ||
2fb55956 | 1205 | if (tmio_mmc_clk_enable(_host) < 0) { |
8c102a96 GL |
1206 | mmc->f_max = pdata->hclk; |
1207 | mmc->f_min = mmc->f_max / 512; | |
1208 | } | |
1209 | ||
bb98d9d1 SS |
1210 | /* |
1211 | * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from | |
1212 | * looping forever... | |
1213 | */ | |
ad7014b3 WS |
1214 | if (mmc->f_min == 0) |
1215 | return -EINVAL; | |
bb98d9d1 | 1216 | |
cbb18b30 | 1217 | /* |
0369483e UH |
1218 | * While using internal tmio hardware logic for card detection, we need |
1219 | * to ensure it stays powered for it to work. | |
cbb18b30 | 1220 | */ |
2b1ac5c2 | 1221 | if (_host->native_hotplug) |
cbb18b30 BH |
1222 | pm_runtime_get_noresume(&pdev->dev); |
1223 | ||
b6147490 GL |
1224 | tmio_mmc_clk_stop(_host); |
1225 | tmio_mmc_reset(_host); | |
1226 | ||
2c54506b | 1227 | _host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK); |
b6147490 | 1228 | tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL); |
e0337cc8 GL |
1229 | |
1230 | /* Unmask the IRQs we want to know about */ | |
1231 | if (!_host->chan_rx) | |
1232 | irq_mask |= TMIO_MASK_READOP; | |
1233 | if (!_host->chan_tx) | |
1234 | irq_mask |= TMIO_MASK_WRITEOP; | |
1235 | if (!_host->native_hotplug) | |
1236 | irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT); | |
1237 | ||
1238 | _host->sdcard_irq_mask &= ~irq_mask; | |
1239 | ||
7501c431 UH |
1240 | _host->sdio_irq_enabled = false; |
1241 | if (pdata->flags & TMIO_MMC_SDIO_IRQ) { | |
1242 | _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL; | |
1243 | sd_ctrl_write16(_host, CTL_SDIO_IRQ_MASK, _host->sdio_irq_mask); | |
c51ff6c6 | 1244 | sd_ctrl_write16(_host, CTL_TRANSACTION_CTL, 0x0001); |
7501c431 | 1245 | } |
b6147490 | 1246 | |
b6147490 | 1247 | spin_lock_init(&_host->lock); |
b9269fdd | 1248 | mutex_init(&_host->ios_lock); |
b6147490 GL |
1249 | |
1250 | /* Init delayed work for request timeouts */ | |
1251 | INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work); | |
b9269fdd | 1252 | INIT_WORK(&_host->done, tmio_mmc_done_work); |
b6147490 GL |
1253 | |
1254 | /* See if we also get DMA */ | |
1255 | tmio_mmc_request_dma(_host, pdata); | |
1256 | ||
0369483e UH |
1257 | pm_runtime_set_active(&pdev->dev); |
1258 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); | |
1259 | pm_runtime_use_autosuspend(&pdev->dev); | |
1260 | pm_runtime_enable(&pdev->dev); | |
1261 | ||
8c102a96 | 1262 | ret = mmc_add_host(mmc); |
8c102a96 GL |
1263 | if (ret < 0) { |
1264 | tmio_mmc_host_remove(_host); | |
1265 | return ret; | |
1266 | } | |
b6147490 | 1267 | |
c419e611 RW |
1268 | dev_pm_qos_expose_latency_limit(&pdev->dev, 100); |
1269 | ||
c8be24c2 | 1270 | if (pdata->flags & TMIO_MMC_USE_GPIO_CD) { |
214fc309 | 1271 | ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0); |
c8be24c2 GL |
1272 | if (ret < 0) { |
1273 | tmio_mmc_host_remove(_host); | |
1274 | return ret; | |
1275 | } | |
d4d11449 | 1276 | mmc_gpiod_request_cd_irq(mmc); |
c8be24c2 GL |
1277 | } |
1278 | ||
b6147490 | 1279 | return 0; |
b6147490 GL |
1280 | } |
1281 | EXPORT_SYMBOL(tmio_mmc_host_probe); | |
1282 | ||
1283 | void tmio_mmc_host_remove(struct tmio_mmc_host *host) | |
1284 | { | |
e6ee7182 | 1285 | struct platform_device *pdev = host->pdev; |
c8be24c2 GL |
1286 | struct mmc_host *mmc = host->mmc; |
1287 | ||
c51ff6c6 WS |
1288 | if (host->pdata->flags & TMIO_MMC_SDIO_IRQ) |
1289 | sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000); | |
1290 | ||
2b1ac5c2 | 1291 | if (!host->native_hotplug) |
7311bef0 GL |
1292 | pm_runtime_get_sync(&pdev->dev); |
1293 | ||
c419e611 RW |
1294 | dev_pm_qos_hide_latency_limit(&pdev->dev); |
1295 | ||
c8be24c2 | 1296 | mmc_remove_host(mmc); |
b9269fdd | 1297 | cancel_work_sync(&host->done); |
b6147490 GL |
1298 | cancel_delayed_work_sync(&host->delayed_reset_work); |
1299 | tmio_mmc_release_dma(host); | |
e6ee7182 | 1300 | |
e6ee7182 GL |
1301 | pm_runtime_put_sync(&pdev->dev); |
1302 | pm_runtime_disable(&pdev->dev); | |
dfcba5ff WS |
1303 | |
1304 | tmio_mmc_clk_disable(host); | |
b6147490 GL |
1305 | } |
1306 | EXPORT_SYMBOL(tmio_mmc_host_remove); | |
1307 | ||
9ade7dbf | 1308 | #ifdef CONFIG_PM |
7311bef0 GL |
1309 | int tmio_mmc_host_runtime_suspend(struct device *dev) |
1310 | { | |
ae12d250 UH |
1311 | struct mmc_host *mmc = dev_get_drvdata(dev); |
1312 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
1313 | ||
20e955c3 UH |
1314 | tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL); |
1315 | ||
ae12d250 UH |
1316 | if (host->clk_cache) |
1317 | tmio_mmc_clk_stop(host); | |
1318 | ||
dfcba5ff | 1319 | tmio_mmc_clk_disable(host); |
ae12d250 | 1320 | |
7311bef0 GL |
1321 | return 0; |
1322 | } | |
1323 | EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend); | |
1324 | ||
4f119977 AK |
1325 | static bool tmio_mmc_can_retune(struct tmio_mmc_host *host) |
1326 | { | |
1327 | return host->tap_num && mmc_can_retune(host->mmc); | |
1328 | } | |
1329 | ||
7311bef0 GL |
1330 | int tmio_mmc_host_runtime_resume(struct device *dev) |
1331 | { | |
1332 | struct mmc_host *mmc = dev_get_drvdata(dev); | |
1333 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
7311bef0 | 1334 | |
ae12d250 | 1335 | tmio_mmc_reset(host); |
2fb55956 | 1336 | tmio_mmc_clk_enable(host); |
ae12d250 | 1337 | |
7fbc030d | 1338 | if (host->clk_cache) |
ae12d250 | 1339 | tmio_mmc_set_clock(host, host->clk_cache); |
ae12d250 | 1340 | |
162f43e3 | 1341 | tmio_mmc_enable_dma(host, true); |
7311bef0 | 1342 | |
4f119977 AK |
1343 | if (tmio_mmc_can_retune(host) && host->select_tuning(host)) |
1344 | dev_warn(&host->pdev->dev, "Tuning selection failed\n"); | |
1345 | ||
7311bef0 GL |
1346 | return 0; |
1347 | } | |
1348 | EXPORT_SYMBOL(tmio_mmc_host_runtime_resume); | |
710dec95 | 1349 | #endif |
7311bef0 | 1350 | |
b6147490 | 1351 | MODULE_LICENSE("GPL v2"); |