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4a48998f IM |
1 | /* Definitons for use with the tmio_mmc.c |
2 | * | |
3 | * (c) 2004 Ian Molton <spyro@f2s.com> | |
4 | * (c) 2007 Ian Molton <spyro@f2s.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
4cb32906 AB |
11 | |
12 | #include <linux/highmem.h> | |
13 | ||
4a48998f IM |
14 | #define CNF_CMD 0x04 |
15 | #define CNF_CTL_BASE 0x10 | |
16 | #define CNF_INT_PIN 0x3d | |
17 | #define CNF_STOP_CLK_CTL 0x40 | |
18 | #define CNF_GCLK_CTL 0x41 | |
19 | #define CNF_SD_CLK_MODE 0x42 | |
20 | #define CNF_PIN_STATUS 0x44 | |
21 | #define CNF_PWR_CTL_1 0x48 | |
22 | #define CNF_PWR_CTL_2 0x49 | |
23 | #define CNF_PWR_CTL_3 0x4a | |
24 | #define CNF_CARD_DETECT_MODE 0x4c | |
25 | #define CNF_SD_SLOT 0x50 | |
26 | #define CNF_EXT_GCLK_CTL_1 0xf0 | |
27 | #define CNF_EXT_GCLK_CTL_2 0xf1 | |
28 | #define CNF_EXT_GCLK_CTL_3 0xf9 | |
29 | #define CNF_SD_LED_EN_1 0xfa | |
30 | #define CNF_SD_LED_EN_2 0xfe | |
31 | ||
32 | #define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/ | |
33 | ||
34 | #define CTL_SD_CMD 0x00 | |
35 | #define CTL_ARG_REG 0x04 | |
36 | #define CTL_STOP_INTERNAL_ACTION 0x08 | |
37 | #define CTL_XFER_BLK_COUNT 0xa | |
38 | #define CTL_RESPONSE 0x0c | |
39 | #define CTL_STATUS 0x1c | |
40 | #define CTL_IRQ_MASK 0x20 | |
41 | #define CTL_SD_CARD_CLK_CTL 0x24 | |
42 | #define CTL_SD_XFER_LEN 0x26 | |
43 | #define CTL_SD_MEM_CARD_OPT 0x28 | |
44 | #define CTL_SD_ERROR_DETAIL_STATUS 0x2c | |
45 | #define CTL_SD_DATA_PORT 0x30 | |
46 | #define CTL_TRANSACTION_CTL 0x34 | |
47 | #define CTL_RESET_SD 0xe0 | |
48 | #define CTL_SDIO_REGS 0x100 | |
49 | #define CTL_CLK_AND_WAIT_CTL 0x138 | |
50 | #define CTL_RESET_SDIO 0x1e0 | |
51 | ||
52 | /* Definitions for values the CTRL_STATUS register can take. */ | |
53 | #define TMIO_STAT_CMDRESPEND 0x00000001 | |
54 | #define TMIO_STAT_DATAEND 0x00000004 | |
55 | #define TMIO_STAT_CARD_REMOVE 0x00000008 | |
56 | #define TMIO_STAT_CARD_INSERT 0x00000010 | |
57 | #define TMIO_STAT_SIGSTATE 0x00000020 | |
58 | #define TMIO_STAT_WRPROTECT 0x00000080 | |
59 | #define TMIO_STAT_CARD_REMOVE_A 0x00000100 | |
60 | #define TMIO_STAT_CARD_INSERT_A 0x00000200 | |
61 | #define TMIO_STAT_SIGSTATE_A 0x00000400 | |
62 | #define TMIO_STAT_CMD_IDX_ERR 0x00010000 | |
63 | #define TMIO_STAT_CRCFAIL 0x00020000 | |
64 | #define TMIO_STAT_STOPBIT_ERR 0x00040000 | |
65 | #define TMIO_STAT_DATATIMEOUT 0x00080000 | |
66 | #define TMIO_STAT_RXOVERFLOW 0x00100000 | |
67 | #define TMIO_STAT_TXUNDERRUN 0x00200000 | |
68 | #define TMIO_STAT_CMDTIMEOUT 0x00400000 | |
69 | #define TMIO_STAT_RXRDY 0x01000000 | |
70 | #define TMIO_STAT_TXRQ 0x02000000 | |
71 | #define TMIO_STAT_ILL_FUNC 0x20000000 | |
72 | #define TMIO_STAT_CMD_BUSY 0x40000000 | |
73 | #define TMIO_STAT_ILL_ACCESS 0x80000000 | |
74 | ||
75 | /* Define some IRQ masks */ | |
76 | /* This is the mask used at reset by the chip */ | |
77 | #define TMIO_MASK_ALL 0x837f031d | |
78 | #define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND | \ | |
79 | TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) | |
80 | #define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND | \ | |
81 | TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) | |
82 | #define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \ | |
83 | TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) | |
84 | #define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD) | |
85 | ||
5e74672c PZ |
86 | |
87 | #define enable_mmc_irqs(host, i) \ | |
4a48998f IM |
88 | do { \ |
89 | u32 mask;\ | |
5e74672c | 90 | mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \ |
4a48998f | 91 | mask &= ~((i) & TMIO_MASK_IRQ); \ |
5e74672c | 92 | sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \ |
4a48998f IM |
93 | } while (0) |
94 | ||
5e74672c | 95 | #define disable_mmc_irqs(host, i) \ |
4a48998f IM |
96 | do { \ |
97 | u32 mask;\ | |
5e74672c | 98 | mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \ |
4a48998f | 99 | mask |= ((i) & TMIO_MASK_IRQ); \ |
5e74672c | 100 | sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \ |
4a48998f IM |
101 | } while (0) |
102 | ||
5e74672c | 103 | #define ack_mmc_irqs(host, i) \ |
4a48998f IM |
104 | do { \ |
105 | u32 mask;\ | |
5e74672c | 106 | mask = sd_ctrl_read32((host), CTL_STATUS); \ |
4a48998f | 107 | mask &= ~((i) & TMIO_MASK_IRQ); \ |
5e74672c | 108 | sd_ctrl_write32((host), CTL_STATUS, mask); \ |
4a48998f IM |
109 | } while (0) |
110 | ||
111 | ||
112 | struct tmio_mmc_host { | |
113 | void __iomem *cnf; | |
114 | void __iomem *ctl; | |
5e74672c | 115 | unsigned long bus_shift; |
4a48998f IM |
116 | struct mmc_command *cmd; |
117 | struct mmc_request *mrq; | |
118 | struct mmc_data *data; | |
119 | struct mmc_host *mmc; | |
120 | int irq; | |
121 | ||
122 | /* pio related stuff */ | |
123 | struct scatterlist *sg_ptr; | |
124 | unsigned int sg_len; | |
125 | unsigned int sg_off; | |
126 | }; | |
127 | ||
5e74672c PZ |
128 | #include <linux/io.h> |
129 | ||
130 | static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr) | |
131 | { | |
132 | return readw(host->ctl + (addr << host->bus_shift)); | |
133 | } | |
134 | ||
135 | static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr, | |
136 | u16 *buf, int count) | |
137 | { | |
138 | readsw(host->ctl + (addr << host->bus_shift), buf, count); | |
139 | } | |
140 | ||
141 | static inline u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr) | |
142 | { | |
143 | return readw(host->ctl + (addr << host->bus_shift)) | | |
144 | readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16; | |
145 | } | |
146 | ||
147 | static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, | |
148 | u16 val) | |
149 | { | |
150 | writew(val, host->ctl + (addr << host->bus_shift)); | |
151 | } | |
152 | ||
153 | static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr, | |
154 | u16 *buf, int count) | |
155 | { | |
156 | writesw(host->ctl + (addr << host->bus_shift), buf, count); | |
157 | } | |
158 | ||
159 | static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, | |
160 | u32 val) | |
161 | { | |
162 | writew(val, host->ctl + (addr << host->bus_shift)); | |
163 | writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift)); | |
164 | } | |
165 | ||
166 | static inline void sd_config_write8(struct tmio_mmc_host *host, int addr, | |
167 | u8 val) | |
168 | { | |
169 | writeb(val, host->cnf + (addr << host->bus_shift)); | |
170 | } | |
171 | ||
172 | static inline void sd_config_write16(struct tmio_mmc_host *host, int addr, | |
173 | u16 val) | |
174 | { | |
175 | writew(val, host->cnf + (addr << host->bus_shift)); | |
176 | } | |
177 | ||
178 | static inline void sd_config_write32(struct tmio_mmc_host *host, int addr, | |
179 | u32 val) | |
180 | { | |
181 | writew(val, host->cnf + (addr << host->bus_shift)); | |
182 | writew(val >> 16, host->cnf + ((addr + 2) << host->bus_shift)); | |
183 | } | |
184 | ||
4a48998f IM |
185 | #include <linux/scatterlist.h> |
186 | #include <linux/blkdev.h> | |
187 | ||
188 | static inline void tmio_mmc_init_sg(struct tmio_mmc_host *host, | |
189 | struct mmc_data *data) | |
190 | { | |
191 | host->sg_len = data->sg_len; | |
192 | host->sg_ptr = data->sg; | |
193 | host->sg_off = 0; | |
194 | } | |
195 | ||
196 | static inline int tmio_mmc_next_sg(struct tmio_mmc_host *host) | |
197 | { | |
198 | host->sg_ptr = sg_next(host->sg_ptr); | |
199 | host->sg_off = 0; | |
200 | return --host->sg_len; | |
201 | } | |
202 | ||
203 | static inline char *tmio_mmc_kmap_atomic(struct tmio_mmc_host *host, | |
204 | unsigned long *flags) | |
205 | { | |
206 | struct scatterlist *sg = host->sg_ptr; | |
207 | ||
208 | local_irq_save(*flags); | |
209 | return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; | |
210 | } | |
211 | ||
212 | static inline void tmio_mmc_kunmap_atomic(struct tmio_mmc_host *host, | |
213 | unsigned long *flags) | |
214 | { | |
215 | kunmap_atomic(sg_page(host->sg_ptr), KM_BIO_SRC_IRQ); | |
216 | local_irq_restore(*flags); | |
217 | } | |
218 | ||
219 | #ifdef CONFIG_MMC_DEBUG | |
220 | ||
221 | #define STATUS_TO_TEXT(a) \ | |
222 | do { \ | |
223 | if (status & TMIO_STAT_##a) \ | |
fe246eb0 | 224 | printk(#a); \ |
4a48998f IM |
225 | } while (0) |
226 | ||
fe246eb0 | 227 | void pr_debug_status(u32 status) |
4a48998f IM |
228 | { |
229 | printk(KERN_DEBUG "status: %08x = ", status); | |
230 | STATUS_TO_TEXT(CARD_REMOVE); | |
231 | STATUS_TO_TEXT(CARD_INSERT); | |
232 | STATUS_TO_TEXT(SIGSTATE); | |
233 | STATUS_TO_TEXT(WRPROTECT); | |
234 | STATUS_TO_TEXT(CARD_REMOVE_A); | |
235 | STATUS_TO_TEXT(CARD_INSERT_A); | |
236 | STATUS_TO_TEXT(SIGSTATE_A); | |
237 | STATUS_TO_TEXT(CMD_IDX_ERR); | |
238 | STATUS_TO_TEXT(STOPBIT_ERR); | |
239 | STATUS_TO_TEXT(ILL_FUNC); | |
240 | STATUS_TO_TEXT(CMD_BUSY); | |
241 | STATUS_TO_TEXT(CMDRESPEND); | |
242 | STATUS_TO_TEXT(DATAEND); | |
243 | STATUS_TO_TEXT(CRCFAIL); | |
244 | STATUS_TO_TEXT(DATATIMEOUT); | |
245 | STATUS_TO_TEXT(CMDTIMEOUT); | |
246 | STATUS_TO_TEXT(RXOVERFLOW); | |
247 | STATUS_TO_TEXT(TXUNDERRUN); | |
248 | STATUS_TO_TEXT(RXRDY); | |
249 | STATUS_TO_TEXT(TXRQ); | |
250 | STATUS_TO_TEXT(ILL_ACCESS); | |
251 | printk("\n"); | |
252 | } | |
253 | ||
254 | #else | |
255 | #define pr_debug_status(s) do { } while (0) | |
256 | #endif |