Commit | Line | Data |
---|---|---|
b6147490 | 1 | /* |
b21f13d8 SH |
2 | * Driver for the MMC / SD / SDIO cell found in: |
3 | * | |
4 | * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3 | |
b6147490 | 5 | * |
87317c4d SH |
6 | * Copyright (C) 2015-17 Renesas Electronics Corporation |
7 | * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang | |
8 | * Copyright (C) 2016-17 Horms Solutions, Simon Horman | |
b6147490 GL |
9 | * Copyright (C) 2007 Ian Molton |
10 | * Copyright (C) 2004 Ian Molton | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
b6147490 GL |
16 | */ |
17 | ||
18 | #ifndef TMIO_MMC_H | |
19 | #define TMIO_MMC_H | |
20 | ||
361936ef | 21 | #include <linux/dmaengine.h> |
b6147490 | 22 | #include <linux/highmem.h> |
b9269fdd | 23 | #include <linux/mutex.h> |
b6147490 | 24 | #include <linux/pagemap.h> |
6c0cbef6 | 25 | #include <linux/scatterlist.h> |
e3de2be7 | 26 | #include <linux/spinlock.h> |
b8789ec4 | 27 | #include <linux/interrupt.h> |
b6147490 | 28 | |
ac86045e WS |
29 | #define CTL_SD_CMD 0x00 |
30 | #define CTL_ARG_REG 0x04 | |
31 | #define CTL_STOP_INTERNAL_ACTION 0x08 | |
32 | #define CTL_XFER_BLK_COUNT 0xa | |
33 | #define CTL_RESPONSE 0x0c | |
184adf20 | 34 | /* driver merges STATUS and following STATUS2 */ |
ac86045e | 35 | #define CTL_STATUS 0x1c |
184adf20 | 36 | /* driver merges IRQ_MASK and following IRQ_MASK2 */ |
ac86045e WS |
37 | #define CTL_IRQ_MASK 0x20 |
38 | #define CTL_SD_CARD_CLK_CTL 0x24 | |
39 | #define CTL_SD_XFER_LEN 0x26 | |
40 | #define CTL_SD_MEM_CARD_OPT 0x28 | |
41 | #define CTL_SD_ERROR_DETAIL_STATUS 0x2c | |
42 | #define CTL_SD_DATA_PORT 0x30 | |
43 | #define CTL_TRANSACTION_CTL 0x34 | |
44 | #define CTL_SDIO_STATUS 0x36 | |
45 | #define CTL_SDIO_IRQ_MASK 0x38 | |
46 | #define CTL_DMA_ENABLE 0xd8 | |
47 | #define CTL_RESET_SD 0xe0 | |
48 | #define CTL_VERSION 0xe2 | |
49 | #define CTL_SDIO_REGS 0x100 | |
50 | #define CTL_CLK_AND_WAIT_CTL 0x138 | |
51 | #define CTL_RESET_SDIO 0x1e0 | |
52 | ||
9afcbf4a WS |
53 | /* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */ |
54 | #define TMIO_STOP_STP BIT(0) | |
55 | #define TMIO_STOP_SEC BIT(8) | |
56 | ||
d8acd16c | 57 | /* Definitions for values the CTL_STATUS register can take */ |
2cafc5cb WS |
58 | #define TMIO_STAT_CMDRESPEND BIT(0) |
59 | #define TMIO_STAT_DATAEND BIT(2) | |
60 | #define TMIO_STAT_CARD_REMOVE BIT(3) | |
61 | #define TMIO_STAT_CARD_INSERT BIT(4) | |
62 | #define TMIO_STAT_SIGSTATE BIT(5) | |
63 | #define TMIO_STAT_WRPROTECT BIT(7) | |
64 | #define TMIO_STAT_CARD_REMOVE_A BIT(8) | |
65 | #define TMIO_STAT_CARD_INSERT_A BIT(9) | |
66 | #define TMIO_STAT_SIGSTATE_A BIT(10) | |
67 | ||
d8acd16c | 68 | /* These belong technically to CTL_STATUS2, but the driver merges them */ |
2cafc5cb WS |
69 | #define TMIO_STAT_CMD_IDX_ERR BIT(16) |
70 | #define TMIO_STAT_CRCFAIL BIT(17) | |
71 | #define TMIO_STAT_STOPBIT_ERR BIT(18) | |
72 | #define TMIO_STAT_DATATIMEOUT BIT(19) | |
73 | #define TMIO_STAT_RXOVERFLOW BIT(20) | |
74 | #define TMIO_STAT_TXUNDERRUN BIT(21) | |
75 | #define TMIO_STAT_CMDTIMEOUT BIT(22) | |
83e95351 | 76 | #define TMIO_STAT_DAT0 BIT(23) /* only known on R-Car so far */ |
2cafc5cb WS |
77 | #define TMIO_STAT_RXRDY BIT(24) |
78 | #define TMIO_STAT_TXRQ BIT(25) | |
a21553c9 WS |
79 | #define TMIO_STAT_ILL_FUNC BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */ |
80 | #define TMIO_STAT_SCLKDIVEN BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */ | |
2cafc5cb WS |
81 | #define TMIO_STAT_CMD_BUSY BIT(30) |
82 | #define TMIO_STAT_ILL_ACCESS BIT(31) | |
ac86045e | 83 | |
ac86045e WS |
84 | #define CLK_CTL_DIV_MASK 0xff |
85 | #define CLK_CTL_SCLKEN BIT(8) | |
86 | ||
0bc0b6e8 WS |
87 | #define CARD_OPT_WIDTH8 BIT(13) |
88 | #define CARD_OPT_WIDTH BIT(15) | |
89 | ||
ac86045e WS |
90 | #define TMIO_BBS 512 /* Boot block size */ |
91 | ||
d8acd16c | 92 | /* Definitions for values the CTL_SDIO_STATUS register can take */ |
cba179ae | 93 | #define TMIO_SDIO_STAT_IOIRQ 0x0001 |
b6147490 | 94 | #define TMIO_SDIO_STAT_EXPUB52 0x4000 |
cba179ae SH |
95 | #define TMIO_SDIO_STAT_EXWT 0x8000 |
96 | #define TMIO_SDIO_MASK_ALL 0xc007 | |
b6147490 | 97 | |
ee289815 WS |
98 | #define TMIO_SDIO_SETBITS_MASK 0x0006 |
99 | ||
b6147490 GL |
100 | /* Define some IRQ masks */ |
101 | /* This is the mask used at reset by the chip */ | |
102 | #define TMIO_MASK_ALL 0x837f031d | |
103 | #define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND) | |
104 | #define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND) | |
105 | #define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \ | |
106 | TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) | |
107 | #define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD) | |
108 | ||
109 | struct tmio_mmc_data; | |
5add2aca | 110 | struct tmio_mmc_host; |
b6147490 | 111 | |
7ecc09ba | 112 | struct tmio_mmc_dma { |
361936ef | 113 | enum dma_slave_buswidth dma_buswidth; |
7ecc09ba | 114 | bool (*filter)(struct dma_chan *chan, void *arg); |
5add2aca | 115 | void (*enable)(struct tmio_mmc_host *host, bool enable); |
7ecc09ba KM |
116 | }; |
117 | ||
631fa73c SH |
118 | struct tmio_mmc_dma_ops { |
119 | void (*start)(struct tmio_mmc_host *host, struct mmc_data *data); | |
120 | void (*enable)(struct tmio_mmc_host *host, bool enable); | |
121 | void (*request)(struct tmio_mmc_host *host, | |
122 | struct tmio_mmc_data *pdata); | |
123 | void (*release)(struct tmio_mmc_host *host); | |
124 | void (*abort)(struct tmio_mmc_host *host); | |
125 | }; | |
126 | ||
b6147490 GL |
127 | struct tmio_mmc_host { |
128 | void __iomem *ctl; | |
b6147490 GL |
129 | struct mmc_command *cmd; |
130 | struct mmc_request *mrq; | |
131 | struct mmc_data *data; | |
132 | struct mmc_host *mmc; | |
b6147490 GL |
133 | |
134 | /* Callbacks for clock / power control */ | |
135 | void (*set_pwr)(struct platform_device *host, int state); | |
136 | void (*set_clk_div)(struct platform_device *host, int state); | |
137 | ||
138 | /* pio related stuff */ | |
139 | struct scatterlist *sg_ptr; | |
140 | struct scatterlist *sg_orig; | |
141 | unsigned int sg_len; | |
142 | unsigned int sg_off; | |
7445bf9e | 143 | unsigned long bus_shift; |
b6147490 GL |
144 | |
145 | struct platform_device *pdev; | |
146 | struct tmio_mmc_data *pdata; | |
7ecc09ba | 147 | struct tmio_mmc_dma *dma; |
b6147490 GL |
148 | |
149 | /* DMA support */ | |
150 | bool force_pio; | |
151 | struct dma_chan *chan_rx; | |
152 | struct dma_chan *chan_tx; | |
52ad9a8e | 153 | struct completion dma_dataend; |
b6147490 GL |
154 | struct tasklet_struct dma_issue; |
155 | struct scatterlist bounce_sg; | |
156 | u8 *bounce_buf; | |
157 | ||
158 | /* Track lost interrupts */ | |
159 | struct delayed_work delayed_reset_work; | |
b9269fdd GL |
160 | struct work_struct done; |
161 | ||
ae12d250 | 162 | /* Cache */ |
54680fe7 SH |
163 | u32 sdcard_irq_mask; |
164 | u32 sdio_irq_mask; | |
ae12d250 | 165 | unsigned int clk_cache; |
54680fe7 | 166 | |
b9269fdd | 167 | spinlock_t lock; /* protect host private data */ |
b6147490 | 168 | unsigned long last_req_ts; |
b9269fdd | 169 | struct mutex ios_lock; /* protect set_ios() context */ |
2b1ac5c2 | 170 | bool native_hotplug; |
7501c431 | 171 | bool sdio_irq_enabled; |
4f119977 | 172 | u32 scc_tappos; |
dfe9a229 | 173 | |
2f87365f | 174 | /* Mandatory callback */ |
0ea28210 | 175 | int (*clk_enable)(struct tmio_mmc_host *host); |
2f87365f SH |
176 | |
177 | /* Optional callbacks */ | |
2fb55956 BH |
178 | unsigned int (*clk_update)(struct tmio_mmc_host *host, |
179 | unsigned int new_clock); | |
0ea28210 | 180 | void (*clk_disable)(struct tmio_mmc_host *host); |
85c02ddd KM |
181 | int (*multi_io_quirk)(struct mmc_card *card, |
182 | unsigned int direction, int blk_size); | |
6a4679f3 | 183 | int (*card_busy)(struct mmc_host *mmc); |
452e5eef WS |
184 | int (*start_signal_voltage_switch)(struct mmc_host *mmc, |
185 | struct mmc_ios *ios); | |
2f87365f | 186 | int (*write16_hook)(struct tmio_mmc_host *host, int addr); |
e8f36b5d | 187 | void (*hw_reset)(struct tmio_mmc_host *host); |
4f119977 AK |
188 | void (*prepare_tuning)(struct tmio_mmc_host *host, unsigned long tap); |
189 | bool (*check_scc_error)(struct tmio_mmc_host *host); | |
190 | ||
191 | /* | |
192 | * Mandatory callback for tuning to occur which is optional for SDR50 | |
193 | * and mandatory for SDR104. | |
194 | */ | |
195 | unsigned int (*init_tuning)(struct tmio_mmc_host *host); | |
196 | int (*select_tuning)(struct tmio_mmc_host *host); | |
197 | ||
198 | /* Tuning values: 1 for success, 0 for failure */ | |
199 | DECLARE_BITMAP(taps, BITS_PER_BYTE * sizeof(long)); | |
200 | unsigned int tap_num; | |
631fa73c SH |
201 | |
202 | const struct tmio_mmc_dma_ops *dma_ops; | |
b6147490 GL |
203 | }; |
204 | ||
94b110af KM |
205 | struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev); |
206 | void tmio_mmc_host_free(struct tmio_mmc_host *host); | |
207 | int tmio_mmc_host_probe(struct tmio_mmc_host *host, | |
631fa73c SH |
208 | struct tmio_mmc_data *pdata, |
209 | const struct tmio_mmc_dma_ops *dma_ops); | |
b6147490 GL |
210 | void tmio_mmc_host_remove(struct tmio_mmc_host *host); |
211 | void tmio_mmc_do_data_irq(struct tmio_mmc_host *host); | |
212 | ||
213 | void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i); | |
214 | void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i); | |
8e7bfdb3 | 215 | irqreturn_t tmio_mmc_irq(int irq, void *devid); |
b6147490 GL |
216 | |
217 | static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg, | |
218 | unsigned long *flags) | |
219 | { | |
220 | local_irq_save(*flags); | |
482fce99 | 221 | return kmap_atomic(sg_page(sg)) + sg->offset; |
b6147490 GL |
222 | } |
223 | ||
224 | static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg, | |
225 | unsigned long *flags, void *virt) | |
226 | { | |
482fce99 | 227 | kunmap_atomic(virt - sg->offset); |
b6147490 GL |
228 | local_irq_restore(*flags); |
229 | } | |
230 | ||
9ade7dbf | 231 | #ifdef CONFIG_PM |
7311bef0 GL |
232 | int tmio_mmc_host_runtime_suspend(struct device *dev); |
233 | int tmio_mmc_host_runtime_resume(struct device *dev); | |
710dec95 | 234 | #endif |
7311bef0 | 235 | |
a11862d3 SH |
236 | static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr) |
237 | { | |
7445bf9e | 238 | return readw(host->ctl + (addr << host->bus_shift)); |
a11862d3 SH |
239 | } |
240 | ||
241 | static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr, | |
242 | u16 *buf, int count) | |
243 | { | |
7445bf9e | 244 | readsw(host->ctl + (addr << host->bus_shift), buf, count); |
a11862d3 SH |
245 | } |
246 | ||
2c54506b | 247 | static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host, int addr) |
a11862d3 | 248 | { |
7445bf9e KM |
249 | return readw(host->ctl + (addr << host->bus_shift)) | |
250 | readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16; | |
a11862d3 SH |
251 | } |
252 | ||
8185e51f CB |
253 | static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr, |
254 | u32 *buf, int count) | |
255 | { | |
256 | readsl(host->ctl + (addr << host->bus_shift), buf, count); | |
257 | } | |
258 | ||
a11862d3 SH |
259 | static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val) |
260 | { | |
973ed3af SH |
261 | /* If there is a hook and it returns non-zero then there |
262 | * is an error and the write should be skipped | |
263 | */ | |
dfe9a229 | 264 | if (host->write16_hook && host->write16_hook(host, addr)) |
973ed3af | 265 | return; |
7445bf9e | 266 | writew(val, host->ctl + (addr << host->bus_shift)); |
a11862d3 SH |
267 | } |
268 | ||
269 | static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr, | |
270 | u16 *buf, int count) | |
271 | { | |
7445bf9e | 272 | writesw(host->ctl + (addr << host->bus_shift), buf, count); |
a11862d3 SH |
273 | } |
274 | ||
2c54506b | 275 | static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host, int addr, u32 val) |
a11862d3 | 276 | { |
7c42dbf3 | 277 | writew(val & 0xffff, host->ctl + (addr << host->bus_shift)); |
7445bf9e | 278 | writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift)); |
a11862d3 SH |
279 | } |
280 | ||
8185e51f CB |
281 | static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr, |
282 | const u32 *buf, int count) | |
283 | { | |
284 | writesl(host->ctl + (addr << host->bus_shift), buf, count); | |
285 | } | |
286 | ||
b6147490 | 287 | #endif |