Commit | Line | Data |
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f707079d | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
b6147490 | 2 | /* |
b21f13d8 SH |
3 | * Driver for the MMC / SD / SDIO cell found in: |
4 | * | |
5 | * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3 | |
b6147490 | 6 | * |
f49bdcde WS |
7 | * Copyright (C) 2015-19 Renesas Electronics Corporation |
8 | * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang | |
87317c4d | 9 | * Copyright (C) 2016-17 Horms Solutions, Simon Horman |
b6147490 GL |
10 | * Copyright (C) 2007 Ian Molton |
11 | * Copyright (C) 2004 Ian Molton | |
b6147490 GL |
12 | */ |
13 | ||
14 | #ifndef TMIO_MMC_H | |
15 | #define TMIO_MMC_H | |
16 | ||
361936ef | 17 | #include <linux/dmaengine.h> |
b6147490 | 18 | #include <linux/highmem.h> |
b9269fdd | 19 | #include <linux/mutex.h> |
b6147490 | 20 | #include <linux/pagemap.h> |
6c0cbef6 | 21 | #include <linux/scatterlist.h> |
e3de2be7 | 22 | #include <linux/spinlock.h> |
b8789ec4 | 23 | #include <linux/interrupt.h> |
b6147490 | 24 | |
ac86045e WS |
25 | #define CTL_SD_CMD 0x00 |
26 | #define CTL_ARG_REG 0x04 | |
27 | #define CTL_STOP_INTERNAL_ACTION 0x08 | |
28 | #define CTL_XFER_BLK_COUNT 0xa | |
29 | #define CTL_RESPONSE 0x0c | |
184adf20 | 30 | /* driver merges STATUS and following STATUS2 */ |
ac86045e | 31 | #define CTL_STATUS 0x1c |
184adf20 | 32 | /* driver merges IRQ_MASK and following IRQ_MASK2 */ |
ac86045e WS |
33 | #define CTL_IRQ_MASK 0x20 |
34 | #define CTL_SD_CARD_CLK_CTL 0x24 | |
35 | #define CTL_SD_XFER_LEN 0x26 | |
36 | #define CTL_SD_MEM_CARD_OPT 0x28 | |
37 | #define CTL_SD_ERROR_DETAIL_STATUS 0x2c | |
38 | #define CTL_SD_DATA_PORT 0x30 | |
39 | #define CTL_TRANSACTION_CTL 0x34 | |
40 | #define CTL_SDIO_STATUS 0x36 | |
41 | #define CTL_SDIO_IRQ_MASK 0x38 | |
42 | #define CTL_DMA_ENABLE 0xd8 | |
43 | #define CTL_RESET_SD 0xe0 | |
44 | #define CTL_VERSION 0xe2 | |
db924bba | 45 | #define CTL_SDIF_MODE 0xe6 |
ac86045e | 46 | |
9afcbf4a WS |
47 | /* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */ |
48 | #define TMIO_STOP_STP BIT(0) | |
49 | #define TMIO_STOP_SEC BIT(8) | |
50 | ||
d8acd16c | 51 | /* Definitions for values the CTL_STATUS register can take */ |
2cafc5cb WS |
52 | #define TMIO_STAT_CMDRESPEND BIT(0) |
53 | #define TMIO_STAT_DATAEND BIT(2) | |
54 | #define TMIO_STAT_CARD_REMOVE BIT(3) | |
55 | #define TMIO_STAT_CARD_INSERT BIT(4) | |
56 | #define TMIO_STAT_SIGSTATE BIT(5) | |
57 | #define TMIO_STAT_WRPROTECT BIT(7) | |
58 | #define TMIO_STAT_CARD_REMOVE_A BIT(8) | |
59 | #define TMIO_STAT_CARD_INSERT_A BIT(9) | |
60 | #define TMIO_STAT_SIGSTATE_A BIT(10) | |
61 | ||
d8acd16c | 62 | /* These belong technically to CTL_STATUS2, but the driver merges them */ |
2cafc5cb WS |
63 | #define TMIO_STAT_CMD_IDX_ERR BIT(16) |
64 | #define TMIO_STAT_CRCFAIL BIT(17) | |
65 | #define TMIO_STAT_STOPBIT_ERR BIT(18) | |
66 | #define TMIO_STAT_DATATIMEOUT BIT(19) | |
67 | #define TMIO_STAT_RXOVERFLOW BIT(20) | |
68 | #define TMIO_STAT_TXUNDERRUN BIT(21) | |
69 | #define TMIO_STAT_CMDTIMEOUT BIT(22) | |
83e95351 | 70 | #define TMIO_STAT_DAT0 BIT(23) /* only known on R-Car so far */ |
2cafc5cb WS |
71 | #define TMIO_STAT_RXRDY BIT(24) |
72 | #define TMIO_STAT_TXRQ BIT(25) | |
1970701f | 73 | #define TMIO_STAT_ALWAYS_SET_27 BIT(27) /* only known on R-Car 2+ so far */ |
a21553c9 WS |
74 | #define TMIO_STAT_ILL_FUNC BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */ |
75 | #define TMIO_STAT_SCLKDIVEN BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */ | |
2cafc5cb WS |
76 | #define TMIO_STAT_CMD_BUSY BIT(30) |
77 | #define TMIO_STAT_ILL_ACCESS BIT(31) | |
ac86045e | 78 | |
c78e1694 | 79 | /* Definitions for values the CTL_SD_CARD_CLK_CTL register can take */ |
ac86045e WS |
80 | #define CLK_CTL_DIV_MASK 0xff |
81 | #define CLK_CTL_SCLKEN BIT(8) | |
82 | ||
c78e1694 | 83 | /* Definitions for values the CTL_SD_MEM_CARD_OPT register can take */ |
0bc0b6e8 WS |
84 | #define CARD_OPT_WIDTH8 BIT(13) |
85 | #define CARD_OPT_WIDTH BIT(15) | |
86 | ||
d8acd16c | 87 | /* Definitions for values the CTL_SDIO_STATUS register can take */ |
cba179ae | 88 | #define TMIO_SDIO_STAT_IOIRQ 0x0001 |
b6147490 | 89 | #define TMIO_SDIO_STAT_EXPUB52 0x4000 |
cba179ae SH |
90 | #define TMIO_SDIO_STAT_EXWT 0x8000 |
91 | #define TMIO_SDIO_MASK_ALL 0xc007 | |
b6147490 | 92 | |
ee289815 WS |
93 | #define TMIO_SDIO_SETBITS_MASK 0x0006 |
94 | ||
5af02d32 WS |
95 | /* Definitions for values the CTL_DMA_ENABLE register can take */ |
96 | #define DMA_ENABLE_DMASDRW BIT(1) | |
97 | ||
b6147490 GL |
98 | /* Define some IRQ masks */ |
99 | /* This is the mask used at reset by the chip */ | |
202367cb | 100 | #define TMIO_MASK_INIT_RCAR2 0x8b7f031d /* Initial value for R-Car Gen2+ */ |
b6147490 GL |
101 | #define TMIO_MASK_ALL 0x837f031d |
102 | #define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND) | |
103 | #define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND) | |
104 | #define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \ | |
105 | TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) | |
106 | #define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD) | |
107 | ||
609e5fba WS |
108 | #define TMIO_MAX_BLK_SIZE 512 |
109 | ||
b6147490 | 110 | struct tmio_mmc_data; |
5add2aca | 111 | struct tmio_mmc_host; |
b6147490 | 112 | |
631fa73c SH |
113 | struct tmio_mmc_dma_ops { |
114 | void (*start)(struct tmio_mmc_host *host, struct mmc_data *data); | |
115 | void (*enable)(struct tmio_mmc_host *host, bool enable); | |
116 | void (*request)(struct tmio_mmc_host *host, | |
117 | struct tmio_mmc_data *pdata); | |
118 | void (*release)(struct tmio_mmc_host *host); | |
119 | void (*abort)(struct tmio_mmc_host *host); | |
92d0f925 | 120 | void (*dataend)(struct tmio_mmc_host *host); |
631fa73c SH |
121 | }; |
122 | ||
b6147490 GL |
123 | struct tmio_mmc_host { |
124 | void __iomem *ctl; | |
b6147490 GL |
125 | struct mmc_command *cmd; |
126 | struct mmc_request *mrq; | |
127 | struct mmc_data *data; | |
128 | struct mmc_host *mmc; | |
c055fc75 | 129 | struct mmc_host_ops ops; |
b6147490 GL |
130 | |
131 | /* Callbacks for clock / power control */ | |
132 | void (*set_pwr)(struct platform_device *host, int state); | |
b6147490 GL |
133 | |
134 | /* pio related stuff */ | |
135 | struct scatterlist *sg_ptr; | |
136 | struct scatterlist *sg_orig; | |
137 | unsigned int sg_len; | |
138 | unsigned int sg_off; | |
c4ba0e4a | 139 | unsigned int bus_shift; |
b6147490 GL |
140 | |
141 | struct platform_device *pdev; | |
142 | struct tmio_mmc_data *pdata; | |
143 | ||
144 | /* DMA support */ | |
d3dd5db0 | 145 | bool dma_on; |
b6147490 GL |
146 | struct dma_chan *chan_rx; |
147 | struct dma_chan *chan_tx; | |
b6147490 GL |
148 | struct tasklet_struct dma_issue; |
149 | struct scatterlist bounce_sg; | |
150 | u8 *bounce_buf; | |
151 | ||
152 | /* Track lost interrupts */ | |
153 | struct delayed_work delayed_reset_work; | |
b9269fdd GL |
154 | struct work_struct done; |
155 | ||
ae12d250 | 156 | /* Cache */ |
54680fe7 SH |
157 | u32 sdcard_irq_mask; |
158 | u32 sdio_irq_mask; | |
ae12d250 | 159 | unsigned int clk_cache; |
1970701f | 160 | u32 sdcard_irq_setbit_mask; |
54680fe7 | 161 | |
b9269fdd | 162 | spinlock_t lock; /* protect host private data */ |
b6147490 | 163 | unsigned long last_req_ts; |
b9269fdd | 164 | struct mutex ios_lock; /* protect set_ios() context */ |
2b1ac5c2 | 165 | bool native_hotplug; |
7501c431 | 166 | bool sdio_irq_enabled; |
dfe9a229 | 167 | |
2f87365f | 168 | /* Mandatory callback */ |
0ea28210 | 169 | int (*clk_enable)(struct tmio_mmc_host *host); |
0196c8db | 170 | void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock); |
2f87365f SH |
171 | |
172 | /* Optional callbacks */ | |
0ea28210 | 173 | void (*clk_disable)(struct tmio_mmc_host *host); |
85c02ddd KM |
174 | int (*multi_io_quirk)(struct mmc_card *card, |
175 | unsigned int direction, int blk_size); | |
2f87365f | 176 | int (*write16_hook)(struct tmio_mmc_host *host, int addr); |
acb9fce7 | 177 | void (*reset)(struct tmio_mmc_host *host); |
e8f36b5d | 178 | void (*hw_reset)(struct tmio_mmc_host *host); |
4f119977 AK |
179 | void (*prepare_tuning)(struct tmio_mmc_host *host, unsigned long tap); |
180 | bool (*check_scc_error)(struct tmio_mmc_host *host); | |
181 | ||
182 | /* | |
183 | * Mandatory callback for tuning to occur which is optional for SDR50 | |
184 | * and mandatory for SDR104. | |
185 | */ | |
186 | unsigned int (*init_tuning)(struct tmio_mmc_host *host); | |
187 | int (*select_tuning)(struct tmio_mmc_host *host); | |
188 | ||
189 | /* Tuning values: 1 for success, 0 for failure */ | |
190 | DECLARE_BITMAP(taps, BITS_PER_BYTE * sizeof(long)); | |
191 | unsigned int tap_num; | |
db924bba MH |
192 | unsigned long tap_set; |
193 | ||
194 | void (*prepare_hs400_tuning)(struct tmio_mmc_host *host); | |
195 | void (*hs400_downgrade)(struct tmio_mmc_host *host); | |
196 | void (*hs400_complete)(struct tmio_mmc_host *host); | |
631fa73c SH |
197 | |
198 | const struct tmio_mmc_dma_ops *dma_ops; | |
b6147490 GL |
199 | }; |
200 | ||
b21fc294 MY |
201 | struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev, |
202 | struct tmio_mmc_data *pdata); | |
94b110af | 203 | void tmio_mmc_host_free(struct tmio_mmc_host *host); |
bc45719c | 204 | int tmio_mmc_host_probe(struct tmio_mmc_host *host); |
b6147490 GL |
205 | void tmio_mmc_host_remove(struct tmio_mmc_host *host); |
206 | void tmio_mmc_do_data_irq(struct tmio_mmc_host *host); | |
207 | ||
208 | void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i); | |
209 | void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i); | |
8e7bfdb3 | 210 | irqreturn_t tmio_mmc_irq(int irq, void *devid); |
b6147490 GL |
211 | |
212 | static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg, | |
213 | unsigned long *flags) | |
214 | { | |
215 | local_irq_save(*flags); | |
482fce99 | 216 | return kmap_atomic(sg_page(sg)) + sg->offset; |
b6147490 GL |
217 | } |
218 | ||
219 | static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg, | |
220 | unsigned long *flags, void *virt) | |
221 | { | |
482fce99 | 222 | kunmap_atomic(virt - sg->offset); |
b6147490 GL |
223 | local_irq_restore(*flags); |
224 | } | |
225 | ||
9ade7dbf | 226 | #ifdef CONFIG_PM |
7311bef0 GL |
227 | int tmio_mmc_host_runtime_suspend(struct device *dev); |
228 | int tmio_mmc_host_runtime_resume(struct device *dev); | |
710dec95 | 229 | #endif |
7311bef0 | 230 | |
a11862d3 SH |
231 | static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr) |
232 | { | |
d63da8c6 | 233 | return ioread16(host->ctl + (addr << host->bus_shift)); |
a11862d3 SH |
234 | } |
235 | ||
236 | static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr, | |
f2218db8 | 237 | u16 *buf, int count) |
a11862d3 | 238 | { |
0c36fc0d | 239 | ioread16_rep(host->ctl + (addr << host->bus_shift), buf, count); |
a11862d3 SH |
240 | } |
241 | ||
f2218db8 SH |
242 | static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host, |
243 | int addr) | |
a11862d3 | 244 | { |
d63da8c6 WS |
245 | return ioread16(host->ctl + (addr << host->bus_shift)) | |
246 | ioread16(host->ctl + ((addr + 2) << host->bus_shift)) << 16; | |
a11862d3 SH |
247 | } |
248 | ||
8185e51f | 249 | static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr, |
f2218db8 | 250 | u32 *buf, int count) |
8185e51f | 251 | { |
0c36fc0d | 252 | ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count); |
8185e51f CB |
253 | } |
254 | ||
f2218db8 SH |
255 | static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, |
256 | u16 val) | |
a11862d3 | 257 | { |
973ed3af SH |
258 | /* If there is a hook and it returns non-zero then there |
259 | * is an error and the write should be skipped | |
260 | */ | |
dfe9a229 | 261 | if (host->write16_hook && host->write16_hook(host, addr)) |
973ed3af | 262 | return; |
d63da8c6 | 263 | iowrite16(val, host->ctl + (addr << host->bus_shift)); |
a11862d3 SH |
264 | } |
265 | ||
266 | static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr, | |
f2218db8 | 267 | u16 *buf, int count) |
a11862d3 | 268 | { |
0c36fc0d | 269 | iowrite16_rep(host->ctl + (addr << host->bus_shift), buf, count); |
a11862d3 SH |
270 | } |
271 | ||
f2218db8 SH |
272 | static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host, |
273 | int addr, u32 val) | |
a11862d3 | 274 | { |
1970701f WS |
275 | if (addr == CTL_IRQ_MASK || addr == CTL_STATUS) |
276 | val |= host->sdcard_irq_setbit_mask; | |
277 | ||
d63da8c6 WS |
278 | iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift)); |
279 | iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift)); | |
a11862d3 SH |
280 | } |
281 | ||
5603731a TS |
282 | static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val) |
283 | { | |
284 | iowrite32(val, host->ctl + (addr << host->bus_shift)); | |
285 | } | |
286 | ||
8185e51f | 287 | static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr, |
f2218db8 | 288 | const u32 *buf, int count) |
8185e51f | 289 | { |
0c36fc0d | 290 | iowrite32_rep(host->ctl + (addr << host->bus_shift), buf, count); |
8185e51f CB |
291 | } |
292 | ||
b6147490 | 293 | #endif |