[linux-2.6-block.git] / drivers / mmc / host / tmio_mmc.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Driver for the MMC / SD / SDIO cell found in:
 *
 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
 *
 * Copyright (C) 2015-17 Renesas Electronics Corporation
 * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
 * Copyright (C) 2007 Ian Molton
 * Copyright (C) 2004 Ian Molton
 */

#ifndef TMIO_MMC_H
#define TMIO_MMC_H

#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/mutex.h>
#include <linux/pagemap.h>
#include <linux/scatterlist.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>

#define CTL_SD_CMD 0x00
#define CTL_ARG_REG 0x04
#define CTL_STOP_INTERNAL_ACTION 0x08
#define CTL_XFER_BLK_COUNT 0xa
#define CTL_RESPONSE 0x0c
/* driver merges STATUS and following STATUS2 */
#define CTL_STATUS 0x1c
/* driver merges IRQ_MASK and following IRQ_MASK2 */
#define CTL_IRQ_MASK 0x20
#define CTL_SD_CARD_CLK_CTL 0x24
#define CTL_SD_XFER_LEN 0x26
#define CTL_SD_MEM_CARD_OPT 0x28
#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
#define CTL_SD_DATA_PORT 0x30
#define CTL_TRANSACTION_CTL 0x34
#define CTL_SDIO_STATUS 0x36
#define CTL_SDIO_IRQ_MASK 0x38
#define CTL_DMA_ENABLE 0xd8
#define CTL_RESET_SD 0xe0
#define CTL_VERSION 0xe2
#define CTL_SDIF_MODE 0xe6

/* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */
#define TMIO_STOP_STP		BIT(0)
#define TMIO_STOP_SEC		BIT(8)

/* Definitions for values the CTL_STATUS register can take */
#define TMIO_STAT_CMDRESPEND    BIT(0)
#define TMIO_STAT_DATAEND       BIT(2)
#define TMIO_STAT_CARD_REMOVE   BIT(3)
#define TMIO_STAT_CARD_INSERT   BIT(4)
#define TMIO_STAT_SIGSTATE      BIT(5)
#define TMIO_STAT_WRPROTECT     BIT(7)
#define TMIO_STAT_CARD_REMOVE_A BIT(8)
#define TMIO_STAT_CARD_INSERT_A BIT(9)
#define TMIO_STAT_SIGSTATE_A    BIT(10)

/* These belong technically to CTL_STATUS2, but the driver merges them */
#define TMIO_STAT_CMD_IDX_ERR   BIT(16)
#define TMIO_STAT_CRCFAIL       BIT(17)
#define TMIO_STAT_STOPBIT_ERR   BIT(18)
#define TMIO_STAT_DATATIMEOUT   BIT(19)
#define TMIO_STAT_RXOVERFLOW    BIT(20)
#define TMIO_STAT_TXUNDERRUN    BIT(21)
#define TMIO_STAT_CMDTIMEOUT    BIT(22)
#define TMIO_STAT_DAT0		BIT(23)	/* only known on R-Car so far */
#define TMIO_STAT_RXRDY         BIT(24)
#define TMIO_STAT_TXRQ          BIT(25)
#define TMIO_STAT_ILL_FUNC      BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */
#define TMIO_STAT_SCLKDIVEN     BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */
#define TMIO_STAT_CMD_BUSY      BIT(30)
#define TMIO_STAT_ILL_ACCESS    BIT(31)

/* Definitions for values the CTL_SD_CARD_CLK_CTL register can take */
#define	CLK_CTL_DIV_MASK	0xff
#define	CLK_CTL_SCLKEN		BIT(8)

/* Definitions for values the CTL_SD_MEM_CARD_OPT register can take */
#define CARD_OPT_WIDTH8		BIT(13)
#define CARD_OPT_WIDTH		BIT(15)

/* Definitions for values the CTL_SDIO_STATUS register can take */
#define TMIO_SDIO_STAT_IOIRQ	0x0001
#define TMIO_SDIO_STAT_EXPUB52	0x4000
#define TMIO_SDIO_STAT_EXWT	0x8000
#define TMIO_SDIO_MASK_ALL	0xc007

#define TMIO_SDIO_SETBITS_MASK	0x0006

/* Definitions for values the CTL_DMA_ENABLE register can take */
#define DMA_ENABLE_DMASDRW	BIT(1)

/* Define some IRQ masks */
/* This is the mask used at reset by the chip */
#define TMIO_MASK_ALL           0x837f031d
#define TMIO_MASK_READOP  (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
#define TMIO_MASK_CMD     (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
		TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
#define TMIO_MASK_IRQ     (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)

struct tmio_mmc_data;
struct tmio_mmc_host;

struct tmio_mmc_dma_ops {
	void (*start)(struct tmio_mmc_host *host, struct mmc_data *data);
	void (*enable)(struct tmio_mmc_host *host, bool enable);
	void (*request)(struct tmio_mmc_host *host,
			struct tmio_mmc_data *pdata);
	void (*release)(struct tmio_mmc_host *host);
	void (*abort)(struct tmio_mmc_host *host);
	void (*dataend)(struct tmio_mmc_host *host);
};

struct tmio_mmc_host {
	void __iomem *ctl;
	struct mmc_command      *cmd;
	struct mmc_request      *mrq;
	struct mmc_data         *data;
	struct mmc_host         *mmc;
	struct mmc_host_ops     ops;

	/* Callbacks for clock / power control */
	void (*set_pwr)(struct platform_device *host, int state);

	/* pio related stuff */
	struct scatterlist      *sg_ptr;
	struct scatterlist      *sg_orig;
	unsigned int            sg_len;
	unsigned int            sg_off;
	unsigned int		bus_shift;

	struct platform_device *pdev;
	struct tmio_mmc_data *pdata;

	/* DMA support */
	bool			dma_on;
	struct dma_chan		*chan_rx;
	struct dma_chan		*chan_tx;
	struct tasklet_struct	dma_issue;
	struct scatterlist	bounce_sg;
	u8			*bounce_buf;

	/* Track lost interrupts */
	struct delayed_work	delayed_reset_work;
	struct work_struct	done;

	/* Cache */
	u32			sdcard_irq_mask;
	u32			sdio_irq_mask;
	unsigned int		clk_cache;

	spinlock_t		lock;		/* protect host private data */
	unsigned long		last_req_ts;
	struct mutex		ios_lock;	/* protect set_ios() context */
	bool			native_hotplug;
	bool			sdio_irq_enabled;

	/* Mandatory callback */
	int (*clk_enable)(struct tmio_mmc_host *host);
	void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock);

	/* Optional callbacks */
	void (*clk_disable)(struct tmio_mmc_host *host);
	int (*multi_io_quirk)(struct mmc_card *card,
			      unsigned int direction, int blk_size);
	int (*write16_hook)(struct tmio_mmc_host *host, int addr);
	void (*reset)(struct tmio_mmc_host *host);
	void (*hw_reset)(struct tmio_mmc_host *host);
	void (*prepare_tuning)(struct tmio_mmc_host *host, unsigned long tap);
	bool (*check_scc_error)(struct tmio_mmc_host *host);

	/*
	 * Mandatory callback for tuning to occur which is optional for SDR50
	 * and mandatory for SDR104.
	 */
	unsigned int (*init_tuning)(struct tmio_mmc_host *host);
	int (*select_tuning)(struct tmio_mmc_host *host);

	/* Tuning values: 1 for success, 0 for failure */
	DECLARE_BITMAP(taps, BITS_PER_BYTE * sizeof(long));
	unsigned int tap_num;
	unsigned long tap_set;

	void (*prepare_hs400_tuning)(struct tmio_mmc_host *host);
	void (*hs400_downgrade)(struct tmio_mmc_host *host);
	void (*hs400_complete)(struct tmio_mmc_host *host);

	const struct tmio_mmc_dma_ops *dma_ops;
};

struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
					  struct tmio_mmc_data *pdata);
void tmio_mmc_host_free(struct tmio_mmc_host *host);
int tmio_mmc_host_probe(struct tmio_mmc_host *host);
void tmio_mmc_host_remove(struct tmio_mmc_host *host);
void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);

void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
irqreturn_t tmio_mmc_irq(int irq, void *devid);

static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg,
					 unsigned long *flags)
{
	local_irq_save(*flags);
	return kmap_atomic(sg_page(sg)) + sg->offset;
}

static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg,
					  unsigned long *flags, void *virt)
{
	kunmap_atomic(virt - sg->offset);
	local_irq_restore(*flags);
}

#ifdef CONFIG_PM
int tmio_mmc_host_runtime_suspend(struct device *dev);
int tmio_mmc_host_runtime_resume(struct device *dev);
#endif

static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
{
	return ioread16(host->ctl + (addr << host->bus_shift));
}

static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
				      u16 *buf, int count)
{
	ioread16_rep(host->ctl + (addr << host->bus_shift), buf, count);
}

static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
					      int addr)
{
	return ioread16(host->ctl + (addr << host->bus_shift)) |
	       ioread16(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
}

static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
				      u32 *buf, int count)
{
	ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count);
}

static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
				   u16 val)
{
	/* If there is a hook and it returns non-zero then there
	 * is an error and the write should be skipped
	 */
	if (host->write16_hook && host->write16_hook(host, addr))
		return;
	iowrite16(val, host->ctl + (addr << host->bus_shift));
}

static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
				       u16 *buf, int count)
{
	iowrite16_rep(host->ctl + (addr << host->bus_shift), buf, count);
}

static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
						int addr, u32 val)
{
	iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift));
	iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
}

static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
				       const u32 *buf, int count)
{
	iowrite32_rep(host->ctl + (addr << host->bus_shift), buf, count);
}

#endif
Commit	Line	Data
f707079d	1	/* SPDX-License-Identifier: GPL-2.0 */
b6147490	2	/*
b21f13d8 SH	3	* Driver for the MMC / SD / SDIO cell found in:
	4	*
	5	* TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
b6147490	6	*
87317c4d SH	7	* Copyright (C) 2015-17 Renesas Electronics Corporation
	8	* Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
	9	* Copyright (C) 2016-17 Horms Solutions, Simon Horman
b6147490 GL	10	* Copyright (C) 2007 Ian Molton
b6147490 GL	11	* Copyright (C) 2004 Ian Molton
b6147490 GL	12	*/
	13
	14	#ifndef TMIO_MMC_H
	15	#define TMIO_MMC_H
	16
361936ef	17	#include <linux/dmaengine.h>
b6147490	18	#include <linux/highmem.h>
b9269fdd	19	#include <linux/mutex.h>
b6147490	20	#include <linux/pagemap.h>
6c0cbef6	21	#include <linux/scatterlist.h>
e3de2be7	22	#include <linux/spinlock.h>
b8789ec4	23	#include <linux/interrupt.h>
b6147490	24
ac86045e WS	25	#define CTL_SD_CMD 0x00
	26	#define CTL_ARG_REG 0x04
	27	#define CTL_STOP_INTERNAL_ACTION 0x08
	28	#define CTL_XFER_BLK_COUNT 0xa
	29	#define CTL_RESPONSE 0x0c
184adf20	30	/* driver merges STATUS and following STATUS2 */
ac86045e	31	#define CTL_STATUS 0x1c
184adf20	32	/* driver merges IRQ_MASK and following IRQ_MASK2 */
ac86045e WS	33	#define CTL_IRQ_MASK 0x20
	34	#define CTL_SD_CARD_CLK_CTL 0x24
	35	#define CTL_SD_XFER_LEN 0x26
	36	#define CTL_SD_MEM_CARD_OPT 0x28
	37	#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
	38	#define CTL_SD_DATA_PORT 0x30
	39	#define CTL_TRANSACTION_CTL 0x34
	40	#define CTL_SDIO_STATUS 0x36
	41	#define CTL_SDIO_IRQ_MASK 0x38
	42	#define CTL_DMA_ENABLE 0xd8
	43	#define CTL_RESET_SD 0xe0
	44	#define CTL_VERSION 0xe2
db924bba	45	#define CTL_SDIF_MODE 0xe6
ac86045e	46
9afcbf4a WS	47	/* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */
	48	#define TMIO_STOP_STP BIT(0)
	49	#define TMIO_STOP_SEC BIT(8)
	50
d8acd16c	51	/* Definitions for values the CTL_STATUS register can take */
2cafc5cb WS	52	#define TMIO_STAT_CMDRESPEND BIT(0)
	53	#define TMIO_STAT_DATAEND BIT(2)
	54	#define TMIO_STAT_CARD_REMOVE BIT(3)
	55	#define TMIO_STAT_CARD_INSERT BIT(4)
	56	#define TMIO_STAT_SIGSTATE BIT(5)
	57	#define TMIO_STAT_WRPROTECT BIT(7)
	58	#define TMIO_STAT_CARD_REMOVE_A BIT(8)
	59	#define TMIO_STAT_CARD_INSERT_A BIT(9)
	60	#define TMIO_STAT_SIGSTATE_A BIT(10)
	61
d8acd16c	62	/* These belong technically to CTL_STATUS2, but the driver merges them */
2cafc5cb WS	63	#define TMIO_STAT_CMD_IDX_ERR BIT(16)
	64	#define TMIO_STAT_CRCFAIL BIT(17)
	65	#define TMIO_STAT_STOPBIT_ERR BIT(18)
	66	#define TMIO_STAT_DATATIMEOUT BIT(19)
	67	#define TMIO_STAT_RXOVERFLOW BIT(20)
	68	#define TMIO_STAT_TXUNDERRUN BIT(21)
	69	#define TMIO_STAT_CMDTIMEOUT BIT(22)
83e95351	70	#define TMIO_STAT_DAT0 BIT(23) /* only known on R-Car so far */
2cafc5cb WS	71	#define TMIO_STAT_RXRDY BIT(24)
2cafc5cb WS	72	#define TMIO_STAT_TXRQ BIT(25)
a21553c9 WS	73	#define TMIO_STAT_ILL_FUNC BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */
a21553c9 WS	74	#define TMIO_STAT_SCLKDIVEN BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */
2cafc5cb WS	75	#define TMIO_STAT_CMD_BUSY BIT(30)
2cafc5cb WS	76	#define TMIO_STAT_ILL_ACCESS BIT(31)
ac86045e	77
c78e1694	78	/* Definitions for values the CTL_SD_CARD_CLK_CTL register can take */
ac86045e WS	79	#define CLK_CTL_DIV_MASK 0xff
	80	#define CLK_CTL_SCLKEN BIT(8)
	81
c78e1694	82	/* Definitions for values the CTL_SD_MEM_CARD_OPT register can take */
0bc0b6e8 WS	83	#define CARD_OPT_WIDTH8 BIT(13)
	84	#define CARD_OPT_WIDTH BIT(15)
	85
d8acd16c	86	/* Definitions for values the CTL_SDIO_STATUS register can take */
cba179ae	87	#define TMIO_SDIO_STAT_IOIRQ 0x0001
b6147490	88	#define TMIO_SDIO_STAT_EXPUB52 0x4000
cba179ae SH	89	#define TMIO_SDIO_STAT_EXWT 0x8000
cba179ae SH	90	#define TMIO_SDIO_MASK_ALL 0xc007
b6147490	91
ee289815 WS	92	#define TMIO_SDIO_SETBITS_MASK 0x0006
ee289815 WS	93
5af02d32 WS	94	/* Definitions for values the CTL_DMA_ENABLE register can take */
	95	#define DMA_ENABLE_DMASDRW BIT(1)
	96
b6147490 GL	97	/* Define some IRQ masks */
	98	/* This is the mask used at reset by the chip */
	99	#define TMIO_MASK_ALL 0x837f031d
	100	#define TMIO_MASK_READOP (TMIO_STAT_RXRDY \| TMIO_STAT_DATAEND)
	101	#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ \| TMIO_STAT_DATAEND)
	102	#define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND \| TMIO_STAT_CMDTIMEOUT \| \
	103	TMIO_STAT_CARD_REMOVE \| TMIO_STAT_CARD_INSERT)
	104	#define TMIO_MASK_IRQ (TMIO_MASK_READOP \| TMIO_MASK_WRITEOP \| TMIO_MASK_CMD)
	105
	106	struct tmio_mmc_data;
5add2aca	107	struct tmio_mmc_host;
b6147490	108
631fa73c SH	109	struct tmio_mmc_dma_ops {
	110	void (start)(struct tmio_mmc_host host, struct mmc_data *data);
	111	void (enable)(struct tmio_mmc_host host, bool enable);
	112	void (request)(struct tmio_mmc_host host,
	113	struct tmio_mmc_data *pdata);
	114	void (release)(struct tmio_mmc_host host);
	115	void (abort)(struct tmio_mmc_host host);
92d0f925	116	void (dataend)(struct tmio_mmc_host host);
631fa73c SH	117	};
631fa73c SH	118
b6147490 GL	119	struct tmio_mmc_host {
b6147490 GL	120	void __iomem *ctl;
b6147490 GL	121	struct mmc_command *cmd;
	122	struct mmc_request *mrq;
	123	struct mmc_data *data;
	124	struct mmc_host *mmc;
c055fc75	125	struct mmc_host_ops ops;
b6147490 GL	126
	127	/* Callbacks for clock / power control */
	128	void (set_pwr)(struct platform_device host, int state);
b6147490 GL	129
	130	/* pio related stuff */
	131	struct scatterlist *sg_ptr;
	132	struct scatterlist *sg_orig;
	133	unsigned int sg_len;
	134	unsigned int sg_off;
c4ba0e4a	135	unsigned int bus_shift;
b6147490 GL	136
	137	struct platform_device *pdev;
	138	struct tmio_mmc_data *pdata;
	139
	140	/* DMA support */
d3dd5db0	141	bool dma_on;
b6147490 GL	142	struct dma_chan *chan_rx;
b6147490 GL	143	struct dma_chan *chan_tx;
b6147490 GL	144	struct tasklet_struct dma_issue;
	145	struct scatterlist bounce_sg;
	146	u8 *bounce_buf;
	147
	148	/* Track lost interrupts */
	149	struct delayed_work delayed_reset_work;
b9269fdd GL	150	struct work_struct done;
b9269fdd GL	151
ae12d250	152	/* Cache */
54680fe7 SH	153	u32 sdcard_irq_mask;
54680fe7 SH	154	u32 sdio_irq_mask;
ae12d250	155	unsigned int clk_cache;
54680fe7	156
b9269fdd	157	spinlock_t lock; /* protect host private data */
b6147490	158	unsigned long last_req_ts;
b9269fdd	159	struct mutex ios_lock; /* protect set_ios() context */
2b1ac5c2	160	bool native_hotplug;
7501c431	161	bool sdio_irq_enabled;
dfe9a229	162
2f87365f	163	/* Mandatory callback */
0ea28210	164	int (clk_enable)(struct tmio_mmc_host host);
0196c8db	165	void (set_clock)(struct tmio_mmc_host host, unsigned int clock);
2f87365f SH	166
2f87365f SH	167	/* Optional callbacks */
0ea28210	168	void (clk_disable)(struct tmio_mmc_host host);
85c02ddd KM	169	int (multi_io_quirk)(struct mmc_card card,
85c02ddd KM	170	unsigned int direction, int blk_size);
2f87365f	171	int (write16_hook)(struct tmio_mmc_host host, int addr);
acb9fce7	172	void (reset)(struct tmio_mmc_host host);
e8f36b5d	173	void (hw_reset)(struct tmio_mmc_host host);
4f119977 AK	174	void (prepare_tuning)(struct tmio_mmc_host host, unsigned long tap);
	175	bool (check_scc_error)(struct tmio_mmc_host host);
	176
	177	/*
	178	* Mandatory callback for tuning to occur which is optional for SDR50
	179	* and mandatory for SDR104.
	180	*/
	181	unsigned int (init_tuning)(struct tmio_mmc_host host);
	182	int (select_tuning)(struct tmio_mmc_host host);
	183
	184	/* Tuning values: 1 for success, 0 for failure */
	185	DECLARE_BITMAP(taps, BITS_PER_BYTE * sizeof(long));
	186	unsigned int tap_num;
db924bba MH	187	unsigned long tap_set;
	188
	189	void (prepare_hs400_tuning)(struct tmio_mmc_host host);
	190	void (hs400_downgrade)(struct tmio_mmc_host host);
	191	void (hs400_complete)(struct tmio_mmc_host host);
631fa73c SH	192
631fa73c SH	193	const struct tmio_mmc_dma_ops *dma_ops;
b6147490 GL	194	};
b6147490 GL	195
b21fc294 MY	196	struct tmio_mmc_host tmio_mmc_host_alloc(struct platform_device pdev,
b21fc294 MY	197	struct tmio_mmc_data *pdata);
94b110af	198	void tmio_mmc_host_free(struct tmio_mmc_host *host);
bc45719c	199	int tmio_mmc_host_probe(struct tmio_mmc_host *host);
b6147490 GL	200	void tmio_mmc_host_remove(struct tmio_mmc_host *host);
	201	void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);
	202
	203	void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
	204	void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
8e7bfdb3	205	irqreturn_t tmio_mmc_irq(int irq, void *devid);
b6147490 GL	206
	207	static inline char tmio_mmc_kmap_atomic(struct scatterlist sg,
	208	unsigned long *flags)
	209	{
	210	local_irq_save(*flags);
482fce99	211	return kmap_atomic(sg_page(sg)) + sg->offset;
b6147490 GL	212	}
	213
	214	static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg,
	215	unsigned long flags, void virt)
	216	{
482fce99	217	kunmap_atomic(virt - sg->offset);
b6147490 GL	218	local_irq_restore(*flags);
	219	}
	220
9ade7dbf	221	#ifdef CONFIG_PM
7311bef0 GL	222	int tmio_mmc_host_runtime_suspend(struct device *dev);
7311bef0 GL	223	int tmio_mmc_host_runtime_resume(struct device *dev);
710dec95	224	#endif
7311bef0	225
a11862d3 SH	226	static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
a11862d3 SH	227	{
d63da8c6	228	return ioread16(host->ctl + (addr << host->bus_shift));
a11862d3 SH	229	}
	230
	231	static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
f2218db8	232	u16 *buf, int count)
a11862d3	233	{
0c36fc0d	234	ioread16_rep(host->ctl + (addr << host->bus_shift), buf, count);
a11862d3 SH	235	}
a11862d3 SH	236
f2218db8 SH	237	static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
f2218db8 SH	238	int addr)
a11862d3	239	{
d63da8c6 WS	240	return ioread16(host->ctl + (addr << host->bus_shift)) \|
d63da8c6 WS	241	ioread16(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
a11862d3 SH	242	}
a11862d3 SH	243
8185e51f	244	static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
f2218db8	245	u32 *buf, int count)
8185e51f	246	{
0c36fc0d	247	ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count);
8185e51f CB	248	}
8185e51f CB	249
f2218db8 SH	250	static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
f2218db8 SH	251	u16 val)
a11862d3	252	{
973ed3af SH	253	/* If there is a hook and it returns non-zero then there
	254	* is an error and the write should be skipped
	255	*/
dfe9a229	256	if (host->write16_hook && host->write16_hook(host, addr))
973ed3af	257	return;
d63da8c6	258	iowrite16(val, host->ctl + (addr << host->bus_shift));
a11862d3 SH	259	}
	260
	261	static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
f2218db8	262	u16 *buf, int count)
a11862d3	263	{
0c36fc0d	264	iowrite16_rep(host->ctl + (addr << host->bus_shift), buf, count);
a11862d3 SH	265	}
a11862d3 SH	266
f2218db8 SH	267	static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
f2218db8 SH	268	int addr, u32 val)
a11862d3	269	{
d63da8c6 WS	270	iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift));
d63da8c6 WS	271	iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
a11862d3 SH	272	}
a11862d3 SH	273
8185e51f	274	static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
f2218db8	275	const u32 *buf, int count)
8185e51f	276	{
0c36fc0d	277	iowrite32_rep(host->ctl + (addr << host->bus_shift), buf, count);
8185e51f CB	278	}
8185e51f CB	279
b6147490	280	#endif