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Merge tag 'ovl-fixes-4.20-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/mszer...
[linux-2.6-block.git] / drivers / mmc / host / tifm_sd.c
CommitLineData
4020f2d7
AD		 1/*
2 * tifm_sd.c - TI FlashMedia driver
3 *
4 * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
91f8d011
AD		 10 * Special thanks to Brad Campbell for extensive testing of this driver.
11 *
4020f2d7
AD		 12 */
13
14
15#include <linux/tifm.h>
4020f2d7
AD		 16#include <linux/mmc/host.h>
17#include <linux/highmem.h>
13cdf48e 18#include <linux/scatterlist.h>
88b47679 19#include <linux/module.h>
2099c99e 20#include <asm/io.h>
4020f2d7
AD		 21
22#define DRIVER_NAME "tifm_sd"
4552f0cb 23#define DRIVER_VERSION "0.8"
4020f2d7 24
90ab5ee9
RR		 25static bool no_dma = 0;
26static bool fixed_timeout = 0;
4020f2d7
AD		 27module_param(no_dma, bool, 0644);
28module_param(fixed_timeout, bool, 0644);
29
30/* Constants here are mostly from OMAP5912 datasheet */
31#define TIFM_MMCSD_RESET 0x0002
32#define TIFM_MMCSD_CLKMASK 0x03ff
33#define TIFM_MMCSD_POWER 0x0800
34#define TIFM_MMCSD_4BBUS 0x8000
35#define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
36#define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
37#define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
38#define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
39#define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
40#define TIFM_MMCSD_READ 0x8000
41
12c83452 42#define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
4020f2d7 43#define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
91f8d011 44#define TIFM_MMCSD_CD 0x0002 /* card detect */
4020f2d7
AD		 45#define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
46#define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
47#define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
48#define TIFM_MMCSD_DTO 0x0020 /* data time-out */
49#define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
50#define TIFM_MMCSD_CTO 0x0080 /* command time-out */
51#define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
52#define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
53#define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
91f8d011
AD		 54#define TIFM_MMCSD_OCRB 0x1000 /* OCR busy */
55#define TIFM_MMCSD_CIRQ 0x2000 /* card irq (cmd40/sdio) */
4020f2d7
AD		 56#define TIFM_MMCSD_CERR 0x4000 /* card status error */
57
0007d483
AD		 58#define TIFM_MMCSD_ODTO 0x0040 /* open drain / extended timeout */
59#define TIFM_MMCSD_CARD_RO 0x0200 /* card is read-only */
60
4020f2d7
AD		 61#define TIFM_MMCSD_FIFO_SIZE 0x0020
62
63#define TIFM_MMCSD_RSP_R0 0x0000
64#define TIFM_MMCSD_RSP_R1 0x0100
65#define TIFM_MMCSD_RSP_R2 0x0200
66#define TIFM_MMCSD_RSP_R3 0x0300
67#define TIFM_MMCSD_RSP_R4 0x0400
68#define TIFM_MMCSD_RSP_R5 0x0500
69#define TIFM_MMCSD_RSP_R6 0x0600
70
71#define TIFM_MMCSD_RSP_BUSY 0x0800
72
73#define TIFM_MMCSD_CMD_BC 0x0000
74#define TIFM_MMCSD_CMD_BCR 0x1000
75#define TIFM_MMCSD_CMD_AC 0x2000
76#define TIFM_MMCSD_CMD_ADTC 0x3000
77
13cdf48e
AD		 78#define TIFM_MMCSD_MAX_BLOCK_SIZE 0x0800UL
79
4020f2d7 80enum {
72dc9d96
AD		 81 CMD_READY = 0x0001,
82 FIFO_READY = 0x0002,
83 BRS_READY = 0x0004,
84 SCMD_ACTIVE = 0x0008,
85 SCMD_READY = 0x0010,
86 CARD_BUSY = 0x0020,
87 DATA_CARRY = 0x0040
0007d483 88};
4020f2d7
AD		 89
90struct tifm_sd {
91f8d011 91 struct tifm_dev *dev;
4020f2d7 92
91f8d011
AD		 93 unsigned short eject:1,
94 open_drain:1,
95 no_dma:1;
96 unsigned short cmd_flags;
72dc9d96 97
91f8d011
AD		 98 unsigned int clk_freq;
99 unsigned int clk_div;
100 unsigned long timeout_jiffies;
4020f2d7 101
8e02f858 102 struct tasklet_struct finish_tasklet;
0803dd0c 103 struct timer_list timer;
4020f2d7 104 struct mmc_request *req;
4020f2d7 105
13cdf48e
AD		 106 int sg_len;
107 int sg_pos;
108 unsigned int block_pos;
109 struct scatterlist bounce_buf;
110 unsigned char bounce_buf_data[TIFM_MMCSD_MAX_BLOCK_SIZE];
4020f2d7
AD		 111};
112
13cdf48e
AD		 113/* for some reason, host won't respond correctly to readw/writew */
114static void tifm_sd_read_fifo(struct tifm_sd *host, struct page *pg,
115 unsigned int off, unsigned int cnt)
255ef22e 116{
13cdf48e
AD		 117 struct tifm_dev *sock = host->dev;
118 unsigned char *buf;
119 unsigned int pos = 0, val;
120
482fce99 121 buf = kmap_atomic(pg) + off;
13cdf48e
AD		 122 if (host->cmd_flags & DATA_CARRY) {
123 buf[pos++] = host->bounce_buf_data[0];
124 host->cmd_flags &= ~DATA_CARRY;
125 }
126
127 while (pos < cnt) {
128 val = readl(sock->addr + SOCK_MMCSD_DATA);
129 buf[pos++] = val & 0xff;
130 if (pos == cnt) {
131 host->bounce_buf_data[0] = (val >> 8) & 0xff;
132 host->cmd_flags |= DATA_CARRY;
133 break;
134 }
135 buf[pos++] = (val >> 8) & 0xff;
136 }
482fce99 137 kunmap_atomic(buf - off);
255ef22e
AD		 138}
139
13cdf48e
AD		 140static void tifm_sd_write_fifo(struct tifm_sd *host, struct page *pg,
141 unsigned int off, unsigned int cnt)
4020f2d7 142{
13cdf48e
AD		 143 struct tifm_dev *sock = host->dev;
144 unsigned char *buf;
145 unsigned int pos = 0, val;
146
482fce99 147 buf = kmap_atomic(pg) + off;
13cdf48e
AD		 148 if (host->cmd_flags & DATA_CARRY) {
149 val = host->bounce_buf_data[0] | ((buf[pos++] << 8) & 0xff00);
150 writel(val, sock->addr + SOCK_MMCSD_DATA);
151 host->cmd_flags &= ~DATA_CARRY;
152 }
153
154 while (pos < cnt) {
155 val = buf[pos++];
156 if (pos == cnt) {
157 host->bounce_buf_data[0] = val & 0xff;
158 host->cmd_flags |= DATA_CARRY;
159 break;
4020f2d7 160 }
13cdf48e
AD		 161 val |= (buf[pos++] << 8) & 0xff00;
162 writel(val, sock->addr + SOCK_MMCSD_DATA);
163 }
482fce99 164 kunmap_atomic(buf - off);
13cdf48e
AD		 165}
166
167static void tifm_sd_transfer_data(struct tifm_sd *host)
168{
169 struct mmc_data *r_data = host->req->cmd->data;
170 struct scatterlist *sg = r_data->sg;
171 unsigned int off, cnt, t_size = TIFM_MMCSD_FIFO_SIZE * 2;
172 unsigned int p_off, p_cnt;
173 struct page *pg;
174
175 if (host->sg_pos == host->sg_len)
176 return;
177 while (t_size) {
178 cnt = sg[host->sg_pos].length - host->block_pos;
179 if (!cnt) {
180 host->block_pos = 0;
181 host->sg_pos++;
182 if (host->sg_pos == host->sg_len) {
183 if ((r_data->flags & MMC_DATA_WRITE)
ce636452 184 && (host->cmd_flags & DATA_CARRY))
13cdf48e
AD		 185 writel(host->bounce_buf_data[0],
186 host->dev->addr
187 + SOCK_MMCSD_DATA);
188
189 return;
4020f2d7 190 }
13cdf48e 191 cnt = sg[host->sg_pos].length;
4020f2d7 192 }
13cdf48e
AD		 193 off = sg[host->sg_pos].offset + host->block_pos;
194
45711f1a 195 pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
13cdf48e
AD		 196 p_off = offset_in_page(off);
197 p_cnt = PAGE_SIZE - p_off;
198 p_cnt = min(p_cnt, cnt);
199 p_cnt = min(p_cnt, t_size);
200
201 if (r_data->flags & MMC_DATA_READ)
202 tifm_sd_read_fifo(host, pg, p_off, p_cnt);
203 else if (r_data->flags & MMC_DATA_WRITE)
204 tifm_sd_write_fifo(host, pg, p_off, p_cnt);
205
206 t_size -= p_cnt;
207 host->block_pos += p_cnt;
4020f2d7 208 }
13cdf48e
AD		 209}
210
211static void tifm_sd_copy_page(struct page *dst, unsigned int dst_off,
212 struct page *src, unsigned int src_off,
213 unsigned int count)
214{
482fce99
CW		 215 unsigned char *src_buf = kmap_atomic(src) + src_off;
216 unsigned char *dst_buf = kmap_atomic(dst) + dst_off;
13cdf48e
AD		 217
218 memcpy(dst_buf, src_buf, count);
219
482fce99
CW		 220 kunmap_atomic(dst_buf - dst_off);
221 kunmap_atomic(src_buf - src_off);
13cdf48e
AD		 222}
223
224static void tifm_sd_bounce_block(struct tifm_sd *host, struct mmc_data *r_data)
225{
226 struct scatterlist *sg = r_data->sg;
227 unsigned int t_size = r_data->blksz;
228 unsigned int off, cnt;
229 unsigned int p_off, p_cnt;
230 struct page *pg;
231
232 dev_dbg(&host->dev->dev, "bouncing block\n");
233 while (t_size) {
234 cnt = sg[host->sg_pos].length - host->block_pos;
235 if (!cnt) {
236 host->block_pos = 0;
237 host->sg_pos++;
238 if (host->sg_pos == host->sg_len)
239 return;
240 cnt = sg[host->sg_pos].length;
241 }
242 off = sg[host->sg_pos].offset + host->block_pos;
243
45711f1a 244 pg = nth_page(sg_page(&sg[host->sg_pos]), off >> PAGE_SHIFT);
13cdf48e
AD		 245 p_off = offset_in_page(off);
246 p_cnt = PAGE_SIZE - p_off;
247 p_cnt = min(p_cnt, cnt);
248 p_cnt = min(p_cnt, t_size);
249
250 if (r_data->flags & MMC_DATA_WRITE)
45711f1a 251 tifm_sd_copy_page(sg_page(&host->bounce_buf),
13cdf48e
AD		 252 r_data->blksz - t_size,
253 pg, p_off, p_cnt);
254 else if (r_data->flags & MMC_DATA_READ)
45711f1a 255 tifm_sd_copy_page(pg, p_off, sg_page(&host->bounce_buf),
13cdf48e
AD		 256 r_data->blksz - t_size, p_cnt);
257
258 t_size -= p_cnt;
259 host->block_pos += p_cnt;
260 }
261}
262
d97956f8 263static int tifm_sd_set_dma_data(struct tifm_sd *host, struct mmc_data *r_data)
13cdf48e
AD		 264{
265 struct tifm_dev *sock = host->dev;
266 unsigned int t_size = TIFM_DMA_TSIZE * r_data->blksz;
267 unsigned int dma_len, dma_blk_cnt, dma_off;
268 struct scatterlist *sg = NULL;
269 unsigned long flags;
270
271 if (host->sg_pos == host->sg_len)
272 return 1;
273
274 if (host->cmd_flags & DATA_CARRY) {
275 host->cmd_flags &= ~DATA_CARRY;
276 local_irq_save(flags);
277 tifm_sd_bounce_block(host, r_data);
278 local_irq_restore(flags);
279 if (host->sg_pos == host->sg_len)
280 return 1;
281 }
282
283 dma_len = sg_dma_len(&r_data->sg[host->sg_pos]) - host->block_pos;
284 if (!dma_len) {
285 host->block_pos = 0;
286 host->sg_pos++;
287 if (host->sg_pos == host->sg_len)
288 return 1;
289 dma_len = sg_dma_len(&r_data->sg[host->sg_pos]);
290 }
291
292 if (dma_len < t_size) {
293 dma_blk_cnt = dma_len / r_data->blksz;
294 dma_off = host->block_pos;
295 host->block_pos += dma_blk_cnt * r_data->blksz;
296 } else {
297 dma_blk_cnt = TIFM_DMA_TSIZE;
298 dma_off = host->block_pos;
299 host->block_pos += t_size;
300 }
301
302 if (dma_blk_cnt)
303 sg = &r_data->sg[host->sg_pos];
304 else if (dma_len) {
305 if (r_data->flags & MMC_DATA_WRITE) {
306 local_irq_save(flags);
307 tifm_sd_bounce_block(host, r_data);
308 local_irq_restore(flags);
309 } else
310 host->cmd_flags |= DATA_CARRY;
311
312 sg = &host->bounce_buf;
313 dma_off = 0;
314 dma_blk_cnt = 1;
315 } else
316 return 1;
317
318 dev_dbg(&sock->dev, "setting dma for %d blocks\n", dma_blk_cnt);
319 writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS);
320 if (r_data->flags & MMC_DATA_WRITE)
321 writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
322 sock->addr + SOCK_DMA_CONTROL);
323 else
324 writel((dma_blk_cnt << 8) | TIFM_DMA_EN,
325 sock->addr + SOCK_DMA_CONTROL);
326
4020f2d7
AD		 327 return 0;
328}
329
330static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
331{
332 unsigned int rc = 0;
333
334 switch (mmc_resp_type(cmd)) {
335 case MMC_RSP_NONE:
336 rc |= TIFM_MMCSD_RSP_R0;
337 break;
338 case MMC_RSP_R1B:
a5c83eb2
GS		 339 rc |= TIFM_MMCSD_RSP_BUSY;
340 /* fall-through */
4020f2d7
AD		 341 case MMC_RSP_R1:
342 rc |= TIFM_MMCSD_RSP_R1;
343 break;
344 case MMC_RSP_R2:
345 rc |= TIFM_MMCSD_RSP_R2;
346 break;
347 case MMC_RSP_R3:
348 rc |= TIFM_MMCSD_RSP_R3;
349 break;
4020f2d7
AD		 350 default:
351 BUG();
352 }
353
354 switch (mmc_cmd_type(cmd)) {
355 case MMC_CMD_BC:
356 rc |= TIFM_MMCSD_CMD_BC;
357 break;
358 case MMC_CMD_BCR:
359 rc |= TIFM_MMCSD_CMD_BCR;
360 break;
361 case MMC_CMD_AC:
362 rc |= TIFM_MMCSD_CMD_AC;
363 break;
364 case MMC_CMD_ADTC:
365 rc |= TIFM_MMCSD_CMD_ADTC;
366 break;
367 default:
368 BUG();
369 }
370 return rc;
371}
372
373static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
374{
375 struct tifm_dev *sock = host->dev;
0007d483
AD		 376 unsigned int cmd_mask = tifm_sd_op_flags(cmd);
377
378 if (host->open_drain)
379 cmd_mask |= TIFM_MMCSD_ODTO;
4020f2d7
AD		 380
381 if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
382 cmd_mask |= TIFM_MMCSD_READ;
383
384 dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
2e8ce5e7 385 cmd->opcode, cmd->arg, cmd_mask);
4020f2d7
AD		 386
387 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
388 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
389 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
390}
391
392static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
393{
394 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
395 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
396 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
397 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
398 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
399 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
400 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
401 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
402}
403
72dc9d96 404static void tifm_sd_check_status(struct tifm_sd *host)
4020f2d7 405{
72dc9d96 406 struct tifm_dev *sock = host->dev;
4020f2d7
AD		 407 struct mmc_command *cmd = host->req->cmd;
408
17b0429d 409 if (cmd->error)
72dc9d96
AD		 410 goto finish_request;
411
412 if (!(host->cmd_flags & CMD_READY))
4020f2d7 413 return;
72dc9d96
AD		 414
415 if (cmd->data) {
17b0429d 416 if (cmd->data->error) {
72dc9d96
AD		 417 if ((host->cmd_flags & SCMD_ACTIVE)
418 && !(host->cmd_flags & SCMD_READY))
419 return;
420
421 goto finish_request;
4020f2d7 422 }
72dc9d96
AD		 423
424 if (!(host->cmd_flags & BRS_READY))
425 return;
426
427 if (!(host->no_dma || (host->cmd_flags & FIFO_READY)))
428 return;
429
430 if (cmd->data->flags & MMC_DATA_WRITE) {
431 if (host->req->stop) {
432 if (!(host->cmd_flags & SCMD_ACTIVE)) {
433 host->cmd_flags |= SCMD_ACTIVE;
434 writel(TIFM_MMCSD_EOFB
435 | readl(sock->addr
436 + SOCK_MMCSD_INT_ENABLE),
437 sock->addr
438 + SOCK_MMCSD_INT_ENABLE);
1289335a 439 tifm_sd_exec(host, host->req->stop);
72dc9d96 440 return;
1289335a 441 } else {
72dc9d96
AD		 442 if (!(host->cmd_flags & SCMD_READY)
443 || (host->cmd_flags & CARD_BUSY))
444 return;
445 writel((~TIFM_MMCSD_EOFB)
446 & readl(sock->addr
447 + SOCK_MMCSD_INT_ENABLE),
448 sock->addr
449 + SOCK_MMCSD_INT_ENABLE);
1289335a
AD		 450 }
451 } else {
72dc9d96
AD		 452 if (host->cmd_flags & CARD_BUSY)
453 return;
454 writel((~TIFM_MMCSD_EOFB)
455 & readl(sock->addr
456 + SOCK_MMCSD_INT_ENABLE),
457 sock->addr + SOCK_MMCSD_INT_ENABLE);
1289335a 458 }
72dc9d96 459 } else {
1289335a 460 if (host->req->stop) {
72dc9d96
AD		 461 if (!(host->cmd_flags & SCMD_ACTIVE)) {
462 host->cmd_flags |= SCMD_ACTIVE;
463 tifm_sd_exec(host, host->req->stop);
464 return;
465 } else {
466 if (!(host->cmd_flags & SCMD_READY))
467 return;
468 }
1289335a 469 }
4020f2d7 470 }
4020f2d7 471 }
72dc9d96
AD		 472finish_request:
473 tasklet_schedule(&host->finish_tasklet);
4020f2d7
AD		 474}
475
476/* Called from interrupt handler */
4552f0cb 477static void tifm_sd_data_event(struct tifm_dev *sock)
4020f2d7
AD		 478{
479 struct tifm_sd *host;
4552f0cb 480 unsigned int fifo_status = 0;
72dc9d96 481 struct mmc_data *r_data = NULL;
4020f2d7
AD		 482
483 spin_lock(&sock->lock);
484 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
4552f0cb 485 fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
72dc9d96
AD		 486 dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n",
487 fifo_status, host->cmd_flags);
4552f0cb 488
72dc9d96
AD		 489 if (host->req) {
490 r_data = host->req->cmd->data;
4552f0cb 491
72dc9d96 492 if (r_data && (fifo_status & TIFM_FIFO_READY)) {
13cdf48e
AD		 493 if (tifm_sd_set_dma_data(host, r_data)) {
494 host->cmd_flags |= FIFO_READY;
495 tifm_sd_check_status(host);
496 }
72dc9d96
AD		 497 }
498 }
4552f0cb 499
72dc9d96 500 writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
4552f0cb 501 spin_unlock(&sock->lock);
4552f0cb
AD		 502}
503
504/* Called from interrupt handler */
505static void tifm_sd_card_event(struct tifm_dev *sock)
506{
507 struct tifm_sd *host;
508 unsigned int host_status = 0;
17b0429d 509 int cmd_error = 0;
72dc9d96
AD		 510 struct mmc_command *cmd = NULL;
511 unsigned long flags;
4552f0cb
AD		 512
513 spin_lock(&sock->lock);
514 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
72dc9d96
AD		 515 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
516 dev_dbg(&sock->dev, "host event: host_status %x, flags %x\n",
517 host_status, host->cmd_flags);
4020f2d7 518
72dc9d96
AD		 519 if (host->req) {
520 cmd = host->req->cmd;
4020f2d7
AD		 521
522 if (host_status & TIFM_MMCSD_ERRMASK) {
72dc9d96
AD		 523 writel(host_status & TIFM_MMCSD_ERRMASK,
524 sock->addr + SOCK_MMCSD_STATUS);
525 if (host_status & TIFM_MMCSD_CTO)
17b0429d 526 cmd_error = -ETIMEDOUT;
72dc9d96 527 else if (host_status & TIFM_MMCSD_CCRC)
17b0429d 528 cmd_error = -EILSEQ;
72dc9d96
AD		 529
530 if (cmd->data) {
531 if (host_status & TIFM_MMCSD_DTO)
17b0429d 532 cmd->data->error = -ETIMEDOUT;
72dc9d96 533 else if (host_status & TIFM_MMCSD_DCRC)
17b0429d 534 cmd->data->error = -EILSEQ;
72dc9d96 535 }
4020f2d7
AD		 536
537 writel(TIFM_FIFO_INT_SETALL,
538 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
539 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
540
541 if (host->req->stop) {
72dc9d96
AD		 542 if (host->cmd_flags & SCMD_ACTIVE) {
543 host->req->stop->error = cmd_error;
544 host->cmd_flags |= SCMD_READY;
545 } else {
546 cmd->error = cmd_error;
547 host->cmd_flags |= SCMD_ACTIVE;
4020f2d7 548 tifm_sd_exec(host, host->req->stop);
4020f2d7 549 goto done;
4020f2d7 550 }
72dc9d96
AD		 551 } else
552 cmd->error = cmd_error;
553 } else {
554 if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
555 if (!(host->cmd_flags & CMD_READY)) {
556 host->cmd_flags |= CMD_READY;
557 tifm_sd_fetch_resp(cmd, sock);
558 } else if (host->cmd_flags & SCMD_ACTIVE) {
559 host->cmd_flags |= SCMD_READY;
560 tifm_sd_fetch_resp(host->req->stop,
561 sock);
562 }
4020f2d7 563 }
72dc9d96
AD		 564 if (host_status & TIFM_MMCSD_BRS)
565 host->cmd_flags |= BRS_READY;
4020f2d7
AD		 566 }
567
72dc9d96
AD		 568 if (host->no_dma && cmd->data) {
569 if (host_status & TIFM_MMCSD_AE)
570 writel(host_status & TIFM_MMCSD_AE,
571 sock->addr + SOCK_MMCSD_STATUS);
572
573 if (host_status & (TIFM_MMCSD_AE | TIFM_MMCSD_AF
574 | TIFM_MMCSD_BRS)) {
575 local_irq_save(flags);
13cdf48e 576 tifm_sd_transfer_data(host);
72dc9d96
AD		 577 local_irq_restore(flags);
578 host_status &= ~TIFM_MMCSD_AE;
579 }
4020f2d7 580 }
4020f2d7 581
72dc9d96
AD		 582 if (host_status & TIFM_MMCSD_EOFB)
583 host->cmd_flags &= ~CARD_BUSY;
584 else if (host_status & TIFM_MMCSD_CB)
585 host->cmd_flags |= CARD_BUSY;
586
587 tifm_sd_check_status(host);
588 }
4020f2d7 589done:
72dc9d96 590 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
4020f2d7 591 spin_unlock(&sock->lock);
4020f2d7
AD		 592}
593
4020f2d7 594static void tifm_sd_set_data_timeout(struct tifm_sd *host,
2e8ce5e7 595 struct mmc_data *data)
4020f2d7
AD		 596{
597 struct tifm_dev *sock = host->dev;
598 unsigned int data_timeout = data->timeout_clks;
599
600 if (fixed_timeout)
601 return;
602
603 data_timeout += data->timeout_ns /
83d420ba 604 ((1000000000UL / host->clk_freq) * host->clk_div);
4020f2d7
AD		 605
606 if (data_timeout < 0xffff) {
4020f2d7 607 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
83d420ba
AD		 608 writel((~TIFM_MMCSD_DPE)
609 & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
610 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
4020f2d7 611 } else {
4020f2d7 612 data_timeout = (data_timeout >> 10) + 1;
2e8ce5e7 613 if (data_timeout > 0xffff)
4020f2d7
AD		 614 data_timeout = 0; /* set to unlimited */
615 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
83d420ba
AD		 616 writel(TIFM_MMCSD_DPE
617 | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
618 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
4020f2d7
AD		 619 }
620}
621
622static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
623{
624 struct tifm_sd *host = mmc_priv(mmc);
625 struct tifm_dev *sock = host->dev;
626 unsigned long flags;
4020f2d7
AD		 627 struct mmc_data *r_data = mrq->cmd->data;
628
629 spin_lock_irqsave(&sock->lock, flags);
0007d483 630 if (host->eject) {
255d01af 631 mrq->cmd->error = -ENOMEDIUM;
4020f2d7
AD		 632 goto err_out;
633 }
634
635 if (host->req) {
a3c76eb9 636 pr_err("%s : unfinished request detected\n",
d1b26863 637 dev_name(&sock->dev));
255d01af
PO		 638 mrq->cmd->error = -ETIMEDOUT;
639 goto err_out;
640 }
641
13cdf48e
AD		 642 host->cmd_flags = 0;
643 host->block_pos = 0;
644 host->sg_pos = 0;
645
b37a0506
AD		 646 if (mrq->data && !is_power_of_2(mrq->data->blksz))
647 host->no_dma = 1;
648 else
649 host->no_dma = no_dma ? 1 : 0;
650
4020f2d7
AD		 651 if (r_data) {
652 tifm_sd_set_data_timeout(host, r_data);
653
13cdf48e
AD		 654 if ((r_data->flags & MMC_DATA_WRITE) && !mrq->stop)
655 writel(TIFM_MMCSD_EOFB
656 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
657 sock->addr + SOCK_MMCSD_INT_ENABLE);
dfef26d9 658
13cdf48e 659 if (host->no_dma) {
dfef26d9
AD		 660 writel(TIFM_MMCSD_BUFINT
661 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
662 sock->addr + SOCK_MMCSD_INT_ENABLE);
663 writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
664 | (TIFM_MMCSD_FIFO_SIZE - 1),
665 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
666
13cdf48e 667 host->sg_len = r_data->sg_len;
dfef26d9 668 } else {
13cdf48e
AD		 669 sg_init_one(&host->bounce_buf, host->bounce_buf_data,
670 r_data->blksz);
671
672 if(1 != tifm_map_sg(sock, &host->bounce_buf, 1,
673 r_data->flags & MMC_DATA_WRITE
674 ? PCI_DMA_TODEVICE
675 : PCI_DMA_FROMDEVICE)) {
a3c76eb9 676 pr_err("%s : scatterlist map failed\n",
d1b26863 677 dev_name(&sock->dev));
b37a0506 678 mrq->cmd->error = -ENOMEM;
13cdf48e
AD		 679 goto err_out;
680 }
681 host->sg_len = tifm_map_sg(sock, r_data->sg,
682 r_data->sg_len,
683 r_data->flags
684 & MMC_DATA_WRITE
685 ? PCI_DMA_TODEVICE
686 : PCI_DMA_FROMDEVICE);
687 if (host->sg_len < 1) {
a3c76eb9 688 pr_err("%s : scatterlist map failed\n",
d1b26863 689 dev_name(&sock->dev));
13cdf48e
AD		 690 tifm_unmap_sg(sock, &host->bounce_buf, 1,
691 r_data->flags & MMC_DATA_WRITE
692 ? PCI_DMA_TODEVICE
693 : PCI_DMA_FROMDEVICE);
b37a0506 694 mrq->cmd->error = -ENOMEM;
dfef26d9
AD		 695 goto err_out;
696 }
4020f2d7 697
13cdf48e
AD		 698 writel(TIFM_FIFO_INT_SETALL,
699 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
700 writel(ilog2(r_data->blksz) - 2,
701 sock->addr + SOCK_FIFO_PAGE_SIZE);
702 writel(TIFM_FIFO_ENABLE,
703 sock->addr + SOCK_FIFO_CONTROL);
704 writel(TIFM_FIFO_INTMASK,
705 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
706
707 if (r_data->flags & MMC_DATA_WRITE)
708 writel(TIFM_MMCSD_TXDE,
709 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
710 else
711 writel(TIFM_MMCSD_RXDE,
712 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
713
714 tifm_sd_set_dma_data(host, r_data);
dfef26d9 715 }
13cdf48e
AD		 716
717 writel(r_data->blocks - 1,
718 sock->addr + SOCK_MMCSD_NUM_BLOCKS);
719 writel(r_data->blksz - 1,
720 sock->addr + SOCK_MMCSD_BLOCK_LEN);
4020f2d7
AD		 721 }
722
723 host->req = mrq;
0803dd0c 724 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
4020f2d7 725 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 726 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 727 tifm_sd_exec(host, mrq->cmd);
728 spin_unlock_irqrestore(&sock->lock, flags);
729 return;
730
731err_out:
255d01af 732 spin_unlock_irqrestore(&sock->lock, flags);
4020f2d7
AD		 733 mmc_request_done(mmc, mrq);
734}
735
8e02f858 736static void tifm_sd_end_cmd(unsigned long data)
4020f2d7 737{
8e02f858 738 struct tifm_sd *host = (struct tifm_sd*)data;
4020f2d7
AD		 739 struct tifm_dev *sock = host->dev;
740 struct mmc_host *mmc = tifm_get_drvdata(sock);
741 struct mmc_request *mrq;
e069d79d 742 struct mmc_data *r_data = NULL;
4020f2d7
AD		 743 unsigned long flags;
744
745 spin_lock_irqsave(&sock->lock, flags);
746
0803dd0c 747 del_timer(&host->timer);
4020f2d7 748 mrq = host->req;
e069d79d 749 host->req = NULL;
4020f2d7
AD		 750
751 if (!mrq) {
a3c76eb9 752 pr_err(" %s : no request to complete?\n",
d1b26863 753 dev_name(&sock->dev));
4020f2d7
AD		 754 spin_unlock_irqrestore(&sock->lock, flags);
755 return;
756 }
757
758 r_data = mrq->cmd->data;
759 if (r_data) {
dfef26d9 760 if (host->no_dma) {
13cdf48e
AD		 761 writel((~TIFM_MMCSD_BUFINT)
762 & readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
763 sock->addr + SOCK_MMCSD_INT_ENABLE);
4020f2d7 764 } else {
13cdf48e
AD		 765 tifm_unmap_sg(sock, &host->bounce_buf, 1,
766 (r_data->flags & MMC_DATA_WRITE)
767 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
dfef26d9
AD		 768 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
769 (r_data->flags & MMC_DATA_WRITE)
770 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
4020f2d7 771 }
13cdf48e
AD		 772
773 r_data->bytes_xfered = r_data->blocks
774 - readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
775 r_data->bytes_xfered *= r_data->blksz;
776 r_data->bytes_xfered += r_data->blksz
777 - readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
4020f2d7
AD		 778 }
779
780 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 781 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 782
783 spin_unlock_irqrestore(&sock->lock, flags);
4020f2d7
AD		 784 mmc_request_done(mmc, mrq);
785}
786
2ee4f620 787static void tifm_sd_abort(struct timer_list *t)
4020f2d7 788{
2ee4f620 789 struct tifm_sd *host = from_timer(host, t, timer);
8e02f858 790
a3c76eb9 791 pr_err("%s : card failed to respond for a long period of time "
91f8d011 792 "(%x, %x)\n",
d1b26863 793 dev_name(&host->dev->dev), host->req->cmd->opcode, host->cmd_flags);
8e02f858 794
8e02f858 795 tifm_eject(host->dev);
4020f2d7
AD		 796}
797
798static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
799{
800 struct tifm_sd *host = mmc_priv(mmc);
801 struct tifm_dev *sock = host->dev;
802 unsigned int clk_div1, clk_div2;
803 unsigned long flags;
804
805 spin_lock_irqsave(&sock->lock, flags);
806
91f8d011
AD		 807 dev_dbg(&sock->dev, "ios: clock = %u, vdd = %x, bus_mode = %x, "
808 "chip_select = %x, power_mode = %x, bus_width = %x\n",
809 ios->clock, ios->vdd, ios->bus_mode, ios->chip_select,
810 ios->power_mode, ios->bus_width);
811
4020f2d7
AD		 812 if (ios->bus_width == MMC_BUS_WIDTH_4) {
813 writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
814 sock->addr + SOCK_MMCSD_CONFIG);
815 } else {
2e8ce5e7
AD		 816 writel((~TIFM_MMCSD_4BBUS)
817 & readl(sock->addr + SOCK_MMCSD_CONFIG),
818 sock->addr + SOCK_MMCSD_CONFIG);
4020f2d7
AD		 819 }
820
821 if (ios->clock) {
822 clk_div1 = 20000000 / ios->clock;
823 if (!clk_div1)
824 clk_div1 = 1;
825
826 clk_div2 = 24000000 / ios->clock;
827 if (!clk_div2)
828 clk_div2 = 1;
829
830 if ((20000000 / clk_div1) > ios->clock)
831 clk_div1++;
832 if ((24000000 / clk_div2) > ios->clock)
833 clk_div2++;
834 if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
835 host->clk_freq = 20000000;
836 host->clk_div = clk_div1;
2e8ce5e7
AD		 837 writel((~TIFM_CTRL_FAST_CLK)
838 & readl(sock->addr + SOCK_CONTROL),
839 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 840 } else {
841 host->clk_freq = 24000000;
842 host->clk_div = clk_div2;
2e8ce5e7
AD		 843 writel(TIFM_CTRL_FAST_CLK
844 | readl(sock->addr + SOCK_CONTROL),
845 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 846 }
847 } else {
848 host->clk_div = 0;
849 }
850 host->clk_div &= TIFM_MMCSD_CLKMASK;
2e8ce5e7
AD		 851 writel(host->clk_div
852 | ((~TIFM_MMCSD_CLKMASK)
853 & readl(sock->addr + SOCK_MMCSD_CONFIG)),
854 sock->addr + SOCK_MMCSD_CONFIG);
4020f2d7 855
0007d483 856 host->open_drain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
4020f2d7
AD		 857
858 /* chip_select : maybe later */
859 //vdd
860 //power is set before probe / after remove
4020f2d7
AD		 861
862 spin_unlock_irqrestore(&sock->lock, flags);
863}
864
865static int tifm_sd_ro(struct mmc_host *mmc)
866{
0007d483 867 int rc = 0;
4020f2d7
AD		 868 struct tifm_sd *host = mmc_priv(mmc);
869 struct tifm_dev *sock = host->dev;
870 unsigned long flags;
871
872 spin_lock_irqsave(&sock->lock, flags);
0007d483
AD		 873 if (TIFM_MMCSD_CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE))
874 rc = 1;
4020f2d7
AD		 875 spin_unlock_irqrestore(&sock->lock, flags);
876 return rc;
877}
878
dfef26d9 879static const struct mmc_host_ops tifm_sd_ops = {
4020f2d7
AD		 880 .request = tifm_sd_request,
881 .set_ios = tifm_sd_ios,
882 .get_ro = tifm_sd_ro
883};
884
8e02f858 885static int tifm_sd_initialize_host(struct tifm_sd *host)
4020f2d7 886{
8e02f858
AD		 887 int rc;
888 unsigned int host_status = 0;
4020f2d7 889 struct tifm_dev *sock = host->dev;
4020f2d7 890
8e02f858
AD		 891 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
892 mmiowb();
893 host->clk_div = 61;
894 host->clk_freq = 20000000;
895 writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
896 writel(host->clk_div | TIFM_MMCSD_POWER,
897 sock->addr + SOCK_MMCSD_CONFIG);
898
899 /* wait up to 0.51 sec for reset */
5897d657 900 for (rc = 32; rc <= 256; rc <<= 1) {
8e02f858
AD		 901 if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
902 rc = 0;
903 break;
904 }
905 msleep(rc);
906 }
907
908 if (rc) {
a3c76eb9 909 pr_err("%s : controller failed to reset\n",
d1b26863 910 dev_name(&sock->dev));
8e02f858
AD		 911 return -ENODEV;
912 }
913
914 writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
915 writel(host->clk_div | TIFM_MMCSD_POWER,
916 sock->addr + SOCK_MMCSD_CONFIG);
917 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
918
919 // command timeout fixed to 64 clocks for now
920 writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
921 writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
922
5897d657 923 for (rc = 16; rc <= 64; rc <<= 1) {
8e02f858
AD		 924 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
925 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
926 if (!(host_status & TIFM_MMCSD_ERRMASK)
927 && (host_status & TIFM_MMCSD_EOC)) {
928 rc = 0;
929 break;
930 }
931 msleep(rc);
932 }
933
934 if (rc) {
a3c76eb9 935 pr_err("%s : card not ready - probe failed on initialization\n",
d1b26863 936 dev_name(&sock->dev));
8e02f858
AD		 937 return -ENODEV;
938 }
939
5897d657
AD		 940 writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC
941 | TIFM_MMCSD_ERRMASK,
8e02f858
AD		 942 sock->addr + SOCK_MMCSD_INT_ENABLE);
943 mmiowb();
944
945 return 0;
4020f2d7
AD		 946}
947
948static int tifm_sd_probe(struct tifm_dev *sock)
949{
950 struct mmc_host *mmc;
951 struct tifm_sd *host;
952 int rc = -EIO;
953
2e8ce5e7
AD		 954 if (!(TIFM_SOCK_STATE_OCCUPIED
955 & readl(sock->addr + SOCK_PRESENT_STATE))) {
6606110d
JP		 956 pr_warn("%s : card gone, unexpectedly\n",
957 dev_name(&sock->dev));
4020f2d7
AD		 958 return rc;
959 }
960
961 mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
962 if (!mmc)
963 return -ENOMEM;
964
965 host = mmc_priv(mmc);
4020f2d7 966 tifm_set_drvdata(sock, mmc);
8e02f858 967 host->dev = sock;
4020f2d7
AD		 968 host->timeout_jiffies = msecs_to_jiffies(1000);
969
dfef26d9 970 tasklet_init(&host->finish_tasklet, tifm_sd_end_cmd,
8e02f858 971 (unsigned long)host);
2ee4f620 972 timer_setup(&host->timer, tifm_sd_abort, 0);
8e02f858 973
4020f2d7
AD		 974 mmc->ops = &tifm_sd_ops;
975 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
23af6039 976 mmc->caps = MMC_CAP_4_BIT_DATA;
4020f2d7
AD		 977 mmc->f_min = 20000000 / 60;
978 mmc->f_max = 24000000;
13cdf48e
AD		 979
980 mmc->max_blk_count = 2048;
a36274e0 981 mmc->max_segs = mmc->max_blk_count;
13cdf48e
AD		 982 mmc->max_blk_size = min(TIFM_MMCSD_MAX_BLOCK_SIZE, PAGE_SIZE);
983 mmc->max_seg_size = mmc->max_blk_count * mmc->max_blk_size;
984 mmc->max_req_size = mmc->max_seg_size;
13cdf48e 985
4552f0cb
AD		 986 sock->card_event = tifm_sd_card_event;
987 sock->data_event = tifm_sd_data_event;
8e02f858 988 rc = tifm_sd_initialize_host(host);
4020f2d7 989
8e02f858
AD		 990 if (!rc)
991 rc = mmc_add_host(mmc);
91f8d011
AD		 992 if (!rc)
993 return 0;
4020f2d7 994
8e02f858 995 mmc_free_host(mmc);
4020f2d7
AD		 996 return rc;
997}
998
999static void tifm_sd_remove(struct tifm_dev *sock)
1000{
1001 struct mmc_host *mmc = tifm_get_drvdata(sock);
1002 struct tifm_sd *host = mmc_priv(mmc);
b039d4a1 1003 unsigned long flags;
4020f2d7 1004
592d372a 1005 spin_lock_irqsave(&sock->lock, flags);
0007d483 1006 host->eject = 1;
b039d4a1
AD		 1007 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
1008 mmiowb();
592d372a
AD		 1009 spin_unlock_irqrestore(&sock->lock, flags);
1010
1011 tasklet_kill(&host->finish_tasklet);
1012
b039d4a1 1013 spin_lock_irqsave(&sock->lock, flags);
b039d4a1
AD		 1014 if (host->req) {
1015 writel(TIFM_FIFO_INT_SETALL,
1016 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
1017 writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
17b0429d 1018 host->req->cmd->error = -ENOMEDIUM;
592d372a 1019 if (host->req->stop)
17b0429d 1020 host->req->stop->error = -ENOMEDIUM;
b039d4a1
AD		 1021 tasklet_schedule(&host->finish_tasklet);
1022 }
1023 spin_unlock_irqrestore(&sock->lock, flags);
8e02f858 1024 mmc_remove_host(mmc);
592d372a 1025 dev_dbg(&sock->dev, "after remove\n");
4020f2d7 1026
4020f2d7
AD		 1027 mmc_free_host(mmc);
1028}
1029
dba4acca
AD		 1030#ifdef CONFIG_PM
1031
1032static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
1033{
ccbd4830 1034 return 0;
dba4acca
AD		 1035}
1036
1037static int tifm_sd_resume(struct tifm_dev *sock)
1038{
1039 struct mmc_host *mmc = tifm_get_drvdata(sock);
1040 struct tifm_sd *host = mmc_priv(mmc);
5897d657 1041 int rc;
dba4acca 1042
5897d657
AD		 1043 rc = tifm_sd_initialize_host(host);
1044 dev_dbg(&sock->dev, "resume initialize %d\n", rc);
1045
1046 if (rc)
1047 host->eject = 1;
5897d657
AD		 1048
1049 return rc;
dba4acca
AD		 1050}
1051
1052#else
1053
1054#define tifm_sd_suspend NULL
1055#define tifm_sd_resume NULL
1056
1057#endif /* CONFIG_PM */
1058
e23f2b8a
AD		 1059static struct tifm_device_id tifm_sd_id_tbl[] = {
1060 { TIFM_TYPE_SD }, { }
4020f2d7
AD		 1061};
1062
1063static struct tifm_driver tifm_sd_driver = {
1064 .driver = {
1065 .name = DRIVER_NAME,
1066 .owner = THIS_MODULE
1067 },
1068 .id_table = tifm_sd_id_tbl,
1069 .probe = tifm_sd_probe,
dba4acca
AD		 1070 .remove = tifm_sd_remove,
1071 .suspend = tifm_sd_suspend,
1072 .resume = tifm_sd_resume
4020f2d7
AD		 1073};
1074
1075static int __init tifm_sd_init(void)
1076{
1077 return tifm_register_driver(&tifm_sd_driver);
1078}
1079
1080static void __exit tifm_sd_exit(void)
1081{
1082 tifm_unregister_driver(&tifm_sd_driver);
1083}
1084
1085MODULE_AUTHOR("Alex Dubov");
1086MODULE_DESCRIPTION("TI FlashMedia SD driver");
1087MODULE_LICENSE("GPL");
1088MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
1089MODULE_VERSION(DRIVER_VERSION);
1090
1091module_init(tifm_sd_init);
1092module_exit(tifm_sd_exit);
Linux 6.x block layer and io_uring tree(s)