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mmc: sunxi: Factor out clock phase setting code into a helper function
[linux-2.6-block.git] / drivers / mmc / host / sunxi-mmc.c
CommitLineData
3cbcb160
DL		 1/*
2 * Driver for sunxi SD/MMC host controllers
3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
6 * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/io.h>
18#include <linux/device.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/err.h>
22
23#include <linux/clk.h>
3cbcb160
DL		 24#include <linux/gpio.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27#include <linux/scatterlist.h>
28#include <linux/dma-mapping.h>
29#include <linux/slab.h>
30#include <linux/reset.h>
f771f6e8 31#include <linux/regulator/consumer.h>
3cbcb160
DL		 32
33#include <linux/of_address.h>
34#include <linux/of_gpio.h>
35#include <linux/of_platform.h>
36
37#include <linux/mmc/host.h>
38#include <linux/mmc/sd.h>
39#include <linux/mmc/sdio.h>
40#include <linux/mmc/mmc.h>
41#include <linux/mmc/core.h>
42#include <linux/mmc/card.h>
43#include <linux/mmc/slot-gpio.h>
44
45/* register offset definitions */
46#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
47#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
48#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
49#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
50#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
51#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
52#define SDXC_REG_CMDR (0x18) /* SMC Command Register */
53#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
54#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
55#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
56#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
57#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
58#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
59#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
60#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
61#define SDXC_REG_STAS (0x3C) /* SMC Status Register */
62#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
63#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
64#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
65#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
66#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
67#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
68#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
69#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
70#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
71#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
72#define SDXC_REG_CHDA (0x90)
73#define SDXC_REG_CBDA (0x94)
74
75#define mmc_readl(host, reg) \
76 readl((host)->reg_base + SDXC_##reg)
77#define mmc_writel(host, reg, value) \
78 writel((value), (host)->reg_base + SDXC_##reg)
79
80/* global control register bits */
81#define SDXC_SOFT_RESET BIT(0)
82#define SDXC_FIFO_RESET BIT(1)
83#define SDXC_DMA_RESET BIT(2)
84#define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
85#define SDXC_DMA_ENABLE_BIT BIT(5)
86#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
87#define SDXC_POSEDGE_LATCH_DATA BIT(9)
88#define SDXC_DDR_MODE BIT(10)
89#define SDXC_MEMORY_ACCESS_DONE BIT(29)
90#define SDXC_ACCESS_DONE_DIRECT BIT(30)
91#define SDXC_ACCESS_BY_AHB BIT(31)
92#define SDXC_ACCESS_BY_DMA (0 << 31)
93#define SDXC_HARDWARE_RESET \
94 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
95
96/* clock control bits */
97#define SDXC_CARD_CLOCK_ON BIT(16)
98#define SDXC_LOW_POWER_ON BIT(17)
99
100/* bus width */
101#define SDXC_WIDTH1 0
102#define SDXC_WIDTH4 1
103#define SDXC_WIDTH8 2
104
105/* smc command bits */
106#define SDXC_RESP_EXPIRE BIT(6)
107#define SDXC_LONG_RESPONSE BIT(7)
108#define SDXC_CHECK_RESPONSE_CRC BIT(8)
109#define SDXC_DATA_EXPIRE BIT(9)
110#define SDXC_WRITE BIT(10)
111#define SDXC_SEQUENCE_MODE BIT(11)
112#define SDXC_SEND_AUTO_STOP BIT(12)
113#define SDXC_WAIT_PRE_OVER BIT(13)
114#define SDXC_STOP_ABORT_CMD BIT(14)
115#define SDXC_SEND_INIT_SEQUENCE BIT(15)
116#define SDXC_UPCLK_ONLY BIT(21)
117#define SDXC_READ_CEATA_DEV BIT(22)
118#define SDXC_CCS_EXPIRE BIT(23)
119#define SDXC_ENABLE_BIT_BOOT BIT(24)
120#define SDXC_ALT_BOOT_OPTIONS BIT(25)
121#define SDXC_BOOT_ACK_EXPIRE BIT(26)
122#define SDXC_BOOT_ABORT BIT(27)
123#define SDXC_VOLTAGE_SWITCH BIT(28)
124#define SDXC_USE_HOLD_REGISTER BIT(29)
125#define SDXC_START BIT(31)
126
127/* interrupt bits */
128#define SDXC_RESP_ERROR BIT(1)
129#define SDXC_COMMAND_DONE BIT(2)
130#define SDXC_DATA_OVER BIT(3)
131#define SDXC_TX_DATA_REQUEST BIT(4)
132#define SDXC_RX_DATA_REQUEST BIT(5)
133#define SDXC_RESP_CRC_ERROR BIT(6)
134#define SDXC_DATA_CRC_ERROR BIT(7)
135#define SDXC_RESP_TIMEOUT BIT(8)
136#define SDXC_DATA_TIMEOUT BIT(9)
137#define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
138#define SDXC_FIFO_RUN_ERROR BIT(11)
139#define SDXC_HARD_WARE_LOCKED BIT(12)
140#define SDXC_START_BIT_ERROR BIT(13)
141#define SDXC_AUTO_COMMAND_DONE BIT(14)
142#define SDXC_END_BIT_ERROR BIT(15)
143#define SDXC_SDIO_INTERRUPT BIT(16)
144#define SDXC_CARD_INSERT BIT(30)
145#define SDXC_CARD_REMOVE BIT(31)
146#define SDXC_INTERRUPT_ERROR_BIT \
147 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
148 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
149 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
150#define SDXC_INTERRUPT_DONE_BIT \
151 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
152 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
153
154/* status */
155#define SDXC_RXWL_FLAG BIT(0)
156#define SDXC_TXWL_FLAG BIT(1)
157#define SDXC_FIFO_EMPTY BIT(2)
158#define SDXC_FIFO_FULL BIT(3)
159#define SDXC_CARD_PRESENT BIT(8)
160#define SDXC_CARD_DATA_BUSY BIT(9)
161#define SDXC_DATA_FSM_BUSY BIT(10)
162#define SDXC_DMA_REQUEST BIT(31)
163#define SDXC_FIFO_SIZE 16
164
165/* Function select */
166#define SDXC_CEATA_ON (0xceaa << 16)
167#define SDXC_SEND_IRQ_RESPONSE BIT(0)
168#define SDXC_SDIO_READ_WAIT BIT(1)
169#define SDXC_ABORT_READ_DATA BIT(2)
170#define SDXC_SEND_CCSD BIT(8)
171#define SDXC_SEND_AUTO_STOPCCSD BIT(9)
172#define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
173
174/* IDMA controller bus mod bit field */
175#define SDXC_IDMAC_SOFT_RESET BIT(0)
176#define SDXC_IDMAC_FIX_BURST BIT(1)
177#define SDXC_IDMAC_IDMA_ON BIT(7)
178#define SDXC_IDMAC_REFETCH_DES BIT(31)
179
180/* IDMA status bit field */
181#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
182#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
183#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
184#define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
185#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
186#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
187#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
188#define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
189#define SDXC_IDMAC_IDLE (0 << 13)
190#define SDXC_IDMAC_SUSPEND (1 << 13)
191#define SDXC_IDMAC_DESC_READ (2 << 13)
192#define SDXC_IDMAC_DESC_CHECK (3 << 13)
193#define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
194#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
195#define SDXC_IDMAC_READ (6 << 13)
196#define SDXC_IDMAC_WRITE (7 << 13)
197#define SDXC_IDMAC_DESC_CLOSE (8 << 13)
198
199/*
200* If the idma-des-size-bits of property is ie 13, bufsize bits are:
201* Bits 0-12: buf1 size
202* Bits 13-25: buf2 size
203* Bits 26-31: not used
204* Since we only ever set buf1 size, we can simply store it directly.
205*/
206#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
207#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
208#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
209#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
210#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
211#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
212#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
213
51424b28
HG		 214#define SDXC_CLK_400K 0
215#define SDXC_CLK_25M 1
216#define SDXC_CLK_50M 2
217#define SDXC_CLK_50M_DDR 3
2a7aa63a 218#define SDXC_CLK_50M_DDR_8BIT 4
51424b28
HG		 219
220struct sunxi_mmc_clk_delay {
221 u32 output;
222 u32 sample;
223};
224
3cbcb160
DL		 225struct sunxi_idma_des {
226 u32 config;
227 u32 buf_size;
228 u32 buf_addr_ptr1;
229 u32 buf_addr_ptr2;
230};
231
86a93317
HG		 232struct sunxi_mmc_cfg {
233 u32 idma_des_size_bits;
234 const struct sunxi_mmc_clk_delay *clk_delays;
235};
236
3cbcb160
DL		 237struct sunxi_mmc_host {
238 struct mmc_host *mmc;
239 struct reset_control *reset;
86a93317 240 const struct sunxi_mmc_cfg *cfg;
3cbcb160
DL		 241
242 /* IO mapping base */
243 void __iomem *reg_base;
244
245 /* clock management */
246 struct clk *clk_ahb;
247 struct clk *clk_mmc;
6c09bb85
MR		 248 struct clk *clk_sample;
249 struct clk *clk_output;
3cbcb160
DL		 250
251 /* irq */
252 spinlock_t lock;
253 int irq;
254 u32 int_sum;
255 u32 sdio_imask;
256
257 /* dma */
3cbcb160
DL		 258 dma_addr_t sg_dma;
259 void *sg_cpu;
260 bool wait_dma;
261
262 struct mmc_request *mrq;
263 struct mmc_request *manual_stop_mrq;
264 int ferror;
f771f6e8
CYT		 265
266 /* vqmmc */
267 bool vqmmc_enabled;
3cbcb160
DL		 268};
269
270static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
271{
272 unsigned long expire = jiffies + msecs_to_jiffies(250);
273 u32 rval;
274
0f0fcd37 275 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
3cbcb160
DL		 276 do {
277 rval = mmc_readl(host, REG_GCTRL);
278 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
279
280 if (rval & SDXC_HARDWARE_RESET) {
281 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
282 return -EIO;
283 }
284
285 return 0;
286}
287
288static int sunxi_mmc_init_host(struct mmc_host *mmc)
289{
290 u32 rval;
291 struct sunxi_mmc_host *host = mmc_priv(mmc);
292
293 if (sunxi_mmc_reset_host(host))
294 return -EIO;
295
0314cbd4
CYT		 296 /*
297 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
298 *
299 * TODO: sun9i has a larger FIFO and supports higher trigger values
300 */
3cbcb160 301 mmc_writel(host, REG_FTRGL, 0x20070008);
0314cbd4 302 /* Maximum timeout value */
3cbcb160 303 mmc_writel(host, REG_TMOUT, 0xffffffff);
0314cbd4 304 /* Unmask SDIO interrupt if needed */
3cbcb160 305 mmc_writel(host, REG_IMASK, host->sdio_imask);
0314cbd4 306 /* Clear all pending interrupts */
3cbcb160 307 mmc_writel(host, REG_RINTR, 0xffffffff);
0314cbd4 308 /* Debug register? undocumented */
3cbcb160 309 mmc_writel(host, REG_DBGC, 0xdeb);
0314cbd4 310 /* Enable CEATA support */
3cbcb160 311 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
0314cbd4 312 /* Set DMA descriptor list base address */
3cbcb160
DL		 313 mmc_writel(host, REG_DLBA, host->sg_dma);
314
315 rval = mmc_readl(host, REG_GCTRL);
316 rval |= SDXC_INTERRUPT_ENABLE_BIT;
0314cbd4 317 /* Undocumented, but found in Allwinner code */
3cbcb160
DL		 318 rval &= ~SDXC_ACCESS_DONE_DIRECT;
319 mmc_writel(host, REG_GCTRL, rval);
320
321 return 0;
322}
323
324static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
325 struct mmc_data *data)
326{
327 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
d34712d2 328 dma_addr_t next_desc = host->sg_dma;
86a93317 329 int i, max_len = (1 << host->cfg->idma_des_size_bits);
3cbcb160
DL		 330
331 for (i = 0; i < data->sg_len; i++) {
332 pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
333 SDXC_IDMAC_DES0_DIC;
334
335 if (data->sg[i].length == max_len)
336 pdes[i].buf_size = 0; /* 0 == max_len */
337 else
338 pdes[i].buf_size = data->sg[i].length;
339
d34712d2 340 next_desc += sizeof(struct sunxi_idma_des);
3cbcb160 341 pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
d34712d2 342 pdes[i].buf_addr_ptr2 = (u32)next_desc;
3cbcb160
DL		 343 }
344
345 pdes[0].config |= SDXC_IDMAC_DES0_FD;
e8a59049
HG		 346 pdes[i - 1].config |= SDXC_IDMAC_DES0_LD | SDXC_IDMAC_DES0_ER;
347 pdes[i - 1].config &= ~SDXC_IDMAC_DES0_DIC;
348 pdes[i - 1].buf_addr_ptr2 = 0;
3cbcb160
DL		 349
350 /*
351 * Avoid the io-store starting the idmac hitting io-mem before the
352 * descriptors hit the main-mem.
353 */
354 wmb();
355}
356
357static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
358{
359 if (data->flags & MMC_DATA_WRITE)
360 return DMA_TO_DEVICE;
361 else
362 return DMA_FROM_DEVICE;
363}
364
365static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
366 struct mmc_data *data)
367{
368 u32 i, dma_len;
369 struct scatterlist *sg;
370
371 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
372 sunxi_mmc_get_dma_dir(data));
373 if (dma_len == 0) {
374 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
375 return -ENOMEM;
376 }
377
378 for_each_sg(data->sg, sg, data->sg_len, i) {
379 if (sg->offset & 3 || sg->length & 3) {
380 dev_err(mmc_dev(host->mmc),
381 "unaligned scatterlist: os %x length %d\n",
382 sg->offset, sg->length);
383 return -EINVAL;
384 }
385 }
386
387 return 0;
388}
389
390static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
391 struct mmc_data *data)
392{
393 u32 rval;
394
395 sunxi_mmc_init_idma_des(host, data);
396
397 rval = mmc_readl(host, REG_GCTRL);
398 rval |= SDXC_DMA_ENABLE_BIT;
399 mmc_writel(host, REG_GCTRL, rval);
400 rval |= SDXC_DMA_RESET;
401 mmc_writel(host, REG_GCTRL, rval);
402
403 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
404
405 if (!(data->flags & MMC_DATA_WRITE))
406 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
407
408 mmc_writel(host, REG_DMAC,
409 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
410}
411
412static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
413 struct mmc_request *req)
414{
415 u32 arg, cmd_val, ri;
416 unsigned long expire = jiffies + msecs_to_jiffies(1000);
417
418 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
419 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
420
421 if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
422 cmd_val |= SD_IO_RW_DIRECT;
423 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
424 ((req->cmd->arg >> 28) & 0x7);
425 } else {
426 cmd_val |= MMC_STOP_TRANSMISSION;
427 arg = 0;
428 }
429
430 mmc_writel(host, REG_CARG, arg);
431 mmc_writel(host, REG_CMDR, cmd_val);
432
433 do {
434 ri = mmc_readl(host, REG_RINTR);
435 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
436 time_before(jiffies, expire));
437
438 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
439 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
440 if (req->stop)
441 req->stop->resp[0] = -ETIMEDOUT;
442 } else {
443 if (req->stop)
444 req->stop->resp[0] = mmc_readl(host, REG_RESP0);
445 }
446
447 mmc_writel(host, REG_RINTR, 0xffff);
448}
449
450static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
451{
452 struct mmc_command *cmd = host->mrq->cmd;
453 struct mmc_data *data = host->mrq->data;
454
455 /* For some cmds timeout is normal with sd/mmc cards */
456 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
457 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
458 cmd->opcode == SD_IO_RW_DIRECT))
459 return;
460
461 dev_err(mmc_dev(host->mmc),
462 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
463 host->mmc->index, cmd->opcode,
464 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
465 host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
466 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
467 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
468 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
469 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
470 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
471 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
472 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
473 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
474 );
475}
476
477/* Called in interrupt context! */
478static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
479{
480 struct mmc_request *mrq = host->mrq;
481 struct mmc_data *data = mrq->data;
482 u32 rval;
483
484 mmc_writel(host, REG_IMASK, host->sdio_imask);
485 mmc_writel(host, REG_IDIE, 0);
486
487 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
488 sunxi_mmc_dump_errinfo(host);
489 mrq->cmd->error = -ETIMEDOUT;
490
491 if (data) {
492 data->error = -ETIMEDOUT;
493 host->manual_stop_mrq = mrq;
494 }
495
496 if (mrq->stop)
497 mrq->stop->error = -ETIMEDOUT;
498 } else {
499 if (mrq->cmd->flags & MMC_RSP_136) {
500 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
501 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
502 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
503 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
504 } else {
505 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
506 }
507
508 if (data)
509 data->bytes_xfered = data->blocks * data->blksz;
510 }
511
512 if (data) {
513 mmc_writel(host, REG_IDST, 0x337);
514 mmc_writel(host, REG_DMAC, 0);
515 rval = mmc_readl(host, REG_GCTRL);
516 rval |= SDXC_DMA_RESET;
517 mmc_writel(host, REG_GCTRL, rval);
518 rval &= ~SDXC_DMA_ENABLE_BIT;
519 mmc_writel(host, REG_GCTRL, rval);
520 rval |= SDXC_FIFO_RESET;
521 mmc_writel(host, REG_GCTRL, rval);
522 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
523 sunxi_mmc_get_dma_dir(data));
524 }
525
526 mmc_writel(host, REG_RINTR, 0xffff);
527
528 host->mrq = NULL;
529 host->int_sum = 0;
530 host->wait_dma = false;
531
532 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
533}
534
535static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
536{
537 struct sunxi_mmc_host *host = dev_id;
538 struct mmc_request *mrq;
539 u32 msk_int, idma_int;
540 bool finalize = false;
541 bool sdio_int = false;
542 irqreturn_t ret = IRQ_HANDLED;
543
544 spin_lock(&host->lock);
545
546 idma_int = mmc_readl(host, REG_IDST);
547 msk_int = mmc_readl(host, REG_MISTA);
548
549 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
550 host->mrq, msk_int, idma_int);
551
552 mrq = host->mrq;
553 if (mrq) {
554 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
555 host->wait_dma = false;
556
557 host->int_sum |= msk_int;
558
559 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
560 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
561 !(host->int_sum & SDXC_COMMAND_DONE))
562 mmc_writel(host, REG_IMASK,
563 host->sdio_imask | SDXC_COMMAND_DONE);
564 /* Don't wait for dma on error */
565 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
566 finalize = true;
567 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
568 !host->wait_dma)
569 finalize = true;
570 }
571
572 if (msk_int & SDXC_SDIO_INTERRUPT)
573 sdio_int = true;
574
575 mmc_writel(host, REG_RINTR, msk_int);
576 mmc_writel(host, REG_IDST, idma_int);
577
578 if (finalize)
579 ret = sunxi_mmc_finalize_request(host);
580
581 spin_unlock(&host->lock);
582
583 if (finalize && ret == IRQ_HANDLED)
584 mmc_request_done(host->mmc, mrq);
585
586 if (sdio_int)
587 mmc_signal_sdio_irq(host->mmc);
588
589 return ret;
590}
591
592static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
593{
594 struct sunxi_mmc_host *host = dev_id;
595 struct mmc_request *mrq;
596 unsigned long iflags;
597
598 spin_lock_irqsave(&host->lock, iflags);
599 mrq = host->manual_stop_mrq;
600 spin_unlock_irqrestore(&host->lock, iflags);
601
602 if (!mrq) {
603 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
604 return IRQ_HANDLED;
605 }
606
607 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
dd9b3803
DL		 608
609 /*
610 * We will never have more than one outstanding request,
611 * and we do not complete the request until after
612 * we've cleared host->manual_stop_mrq so we do not need to
613 * spin lock this function.
614 * Additionally we have wait states within this function
615 * so having it in a lock is a very bad idea.
616 */
3cbcb160
DL		 617 sunxi_mmc_send_manual_stop(host, mrq);
618
619 spin_lock_irqsave(&host->lock, iflags);
620 host->manual_stop_mrq = NULL;
621 spin_unlock_irqrestore(&host->lock, iflags);
622
623 mmc_request_done(host->mmc, mrq);
624
625 return IRQ_HANDLED;
626}
627
628static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
629{
7bb9c244 630 unsigned long expire = jiffies + msecs_to_jiffies(750);
3cbcb160
DL		 631 u32 rval;
632
633 rval = mmc_readl(host, REG_CLKCR);
634 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
635
636 if (oclk_en)
637 rval |= SDXC_CARD_CLOCK_ON;
638
639 mmc_writel(host, REG_CLKCR, rval);
640
641 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
642 mmc_writel(host, REG_CMDR, rval);
643
644 do {
645 rval = mmc_readl(host, REG_CMDR);
646 } while (time_before(jiffies, expire) && (rval & SDXC_START));
647
648 /* clear irq status bits set by the command */
649 mmc_writel(host, REG_RINTR,
650 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
651
652 if (rval & SDXC_START) {
653 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
654 return -EIO;
655 }
656
657 return 0;
658}
659
f2cecb70
HG		 660static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
661 struct mmc_ios *ios, u32 rate)
662{
663 int index;
664
665 /* determine delays */
666 if (rate <= 400000) {
667 index = SDXC_CLK_400K;
668 } else if (rate <= 25000000) {
669 index = SDXC_CLK_25M;
670 } else if (rate <= 52000000) {
671 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
672 ios->timing != MMC_TIMING_MMC_DDR52) {
673 index = SDXC_CLK_50M;
674 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
675 index = SDXC_CLK_50M_DDR_8BIT;
676 } else {
677 index = SDXC_CLK_50M_DDR;
678 }
679 } else {
680 return -EINVAL;
681 }
682
683 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
684 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
685
686 return 0;
687}
688
3cbcb160
DL		 689static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
690 struct mmc_ios *ios)
691{
f2cecb70 692 u32 rate, rval, clock = ios->clock;
3cbcb160
DL		 693 int ret;
694
2a7aa63a
CYT		 695 /* 8 bit DDR requires a higher module clock */
696 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
697 ios->bus_width == MMC_BUS_WIDTH_8)
698 clock <<= 1;
699
700 rate = clk_round_rate(host->clk_mmc, clock);
3cbcb160 701 dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
2a7aa63a 702 clock, rate);
3cbcb160
DL		 703
704 /* setting clock rate */
705 ret = clk_set_rate(host->clk_mmc, rate);
706 if (ret) {
707 dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n",
708 rate, ret);
709 return ret;
710 }
711
712 ret = sunxi_mmc_oclk_onoff(host, 0);
713 if (ret)
714 return ret;
715
716 /* clear internal divider */
717 rval = mmc_readl(host, REG_CLKCR);
718 rval &= ~0xff;
2a7aa63a
CYT		 719 /* set internal divider for 8 bit eMMC DDR, so card clock is right */
720 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
721 ios->bus_width == MMC_BUS_WIDTH_8) {
722 rval |= 1;
723 rate >>= 1;
724 }
3cbcb160
DL		 725 mmc_writel(host, REG_CLKCR, rval);
726
f2cecb70
HG		 727 ret = sunxi_mmc_clk_set_phase(host, ios, rate);
728 if (ret)
729 return ret;
3cbcb160
DL		 730
731 return sunxi_mmc_oclk_onoff(host, 1);
732}
733
734static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
735{
736 struct sunxi_mmc_host *host = mmc_priv(mmc);
737 u32 rval;
738
739 /* Set the power state */
740 switch (ios->power_mode) {
741 case MMC_POWER_ON:
742 break;
743
744 case MMC_POWER_UP:
4159215a
CYT		 745 host->ferror = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
746 ios->vdd);
747 if (host->ferror)
748 return;
3cbcb160 749
f771f6e8
CYT		 750 if (!IS_ERR(mmc->supply.vqmmc)) {
751 host->ferror = regulator_enable(mmc->supply.vqmmc);
752 if (host->ferror) {
753 dev_err(mmc_dev(mmc),
754 "failed to enable vqmmc\n");
755 return;
756 }
757 host->vqmmc_enabled = true;
758 }
759
3cbcb160
DL		 760 host->ferror = sunxi_mmc_init_host(mmc);
761 if (host->ferror)
762 return;
763
764 dev_dbg(mmc_dev(mmc), "power on!\n");
765 break;
766
767 case MMC_POWER_OFF:
768 dev_dbg(mmc_dev(mmc), "power off!\n");
769 sunxi_mmc_reset_host(host);
770 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
f771f6e8
CYT		 771 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
772 regulator_disable(mmc->supply.vqmmc);
773 host->vqmmc_enabled = false;
3cbcb160
DL		 774 break;
775 }
776
777 /* set bus width */
778 switch (ios->bus_width) {
779 case MMC_BUS_WIDTH_1:
780 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
781 break;
782 case MMC_BUS_WIDTH_4:
783 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
784 break;
785 case MMC_BUS_WIDTH_8:
786 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
787 break;
788 }
789
790 /* set ddr mode */
791 rval = mmc_readl(host, REG_GCTRL);
2dcb305a
CYT		 792 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
793 ios->timing == MMC_TIMING_MMC_DDR52)
3cbcb160
DL		 794 rval |= SDXC_DDR_MODE;
795 else
796 rval &= ~SDXC_DDR_MODE;
797 mmc_writel(host, REG_GCTRL, rval);
798
799 /* set up clock */
800 if (ios->clock && ios->power_mode) {
801 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
802 /* Android code had a usleep_range(50000, 55000); here */
803 }
804}
805
f771f6e8
CYT		 806static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
807{
808 /* vqmmc regulator is available */
809 if (!IS_ERR(mmc->supply.vqmmc))
810 return mmc_regulator_set_vqmmc(mmc, ios);
811
812 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
813 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
814 return 0;
815
816 return -EINVAL;
817}
818
3cbcb160
DL		 819static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
820{
821 struct sunxi_mmc_host *host = mmc_priv(mmc);
822 unsigned long flags;
823 u32 imask;
824
825 spin_lock_irqsave(&host->lock, flags);
826
827 imask = mmc_readl(host, REG_IMASK);
828 if (enable) {
829 host->sdio_imask = SDXC_SDIO_INTERRUPT;
830 imask |= SDXC_SDIO_INTERRUPT;
831 } else {
832 host->sdio_imask = 0;
833 imask &= ~SDXC_SDIO_INTERRUPT;
834 }
835 mmc_writel(host, REG_IMASK, imask);
836 spin_unlock_irqrestore(&host->lock, flags);
837}
838
839static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
840{
841 struct sunxi_mmc_host *host = mmc_priv(mmc);
842 mmc_writel(host, REG_HWRST, 0);
843 udelay(10);
844 mmc_writel(host, REG_HWRST, 1);
845 udelay(300);
846}
847
848static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
849{
850 struct sunxi_mmc_host *host = mmc_priv(mmc);
851 struct mmc_command *cmd = mrq->cmd;
852 struct mmc_data *data = mrq->data;
853 unsigned long iflags;
854 u32 imask = SDXC_INTERRUPT_ERROR_BIT;
855 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
dd9b3803 856 bool wait_dma = host->wait_dma;
3cbcb160
DL		 857 int ret;
858
859 /* Check for set_ios errors (should never happen) */
860 if (host->ferror) {
861 mrq->cmd->error = host->ferror;
862 mmc_request_done(mmc, mrq);
863 return;
864 }
865
866 if (data) {
867 ret = sunxi_mmc_map_dma(host, data);
868 if (ret < 0) {
869 dev_err(mmc_dev(mmc), "map DMA failed\n");
870 cmd->error = ret;
871 data->error = ret;
872 mmc_request_done(mmc, mrq);
873 return;
874 }
875 }
876
877 if (cmd->opcode == MMC_GO_IDLE_STATE) {
878 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
879 imask |= SDXC_COMMAND_DONE;
880 }
881
882 if (cmd->flags & MMC_RSP_PRESENT) {
883 cmd_val |= SDXC_RESP_EXPIRE;
884 if (cmd->flags & MMC_RSP_136)
885 cmd_val |= SDXC_LONG_RESPONSE;
886 if (cmd->flags & MMC_RSP_CRC)
887 cmd_val |= SDXC_CHECK_RESPONSE_CRC;
888
889 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
890 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
3cbcb160
DL		 891
892 if (cmd->data->stop) {
893 imask |= SDXC_AUTO_COMMAND_DONE;
894 cmd_val |= SDXC_SEND_AUTO_STOP;
895 } else {
896 imask |= SDXC_DATA_OVER;
897 }
898
899 if (cmd->data->flags & MMC_DATA_WRITE)
900 cmd_val |= SDXC_WRITE;
901 else
dd9b3803 902 wait_dma = true;
3cbcb160
DL		 903 } else {
904 imask |= SDXC_COMMAND_DONE;
905 }
906 } else {
907 imask |= SDXC_COMMAND_DONE;
908 }
909
910 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
911 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
912 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
913
914 spin_lock_irqsave(&host->lock, iflags);
915
916 if (host->mrq || host->manual_stop_mrq) {
917 spin_unlock_irqrestore(&host->lock, iflags);
918
919 if (data)
920 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
921 sunxi_mmc_get_dma_dir(data));
922
923 dev_err(mmc_dev(mmc), "request already pending\n");
924 mrq->cmd->error = -EBUSY;
925 mmc_request_done(mmc, mrq);
926 return;
927 }
928
929 if (data) {
930 mmc_writel(host, REG_BLKSZ, data->blksz);
931 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
932 sunxi_mmc_start_dma(host, data);
933 }
934
935 host->mrq = mrq;
dd9b3803 936 host->wait_dma = wait_dma;
3cbcb160
DL		 937 mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
938 mmc_writel(host, REG_CARG, cmd->arg);
939 mmc_writel(host, REG_CMDR, cmd_val);
940
941 spin_unlock_irqrestore(&host->lock, iflags);
942}
943
c1590dd8
HG		 944static int sunxi_mmc_card_busy(struct mmc_host *mmc)
945{
946 struct sunxi_mmc_host *host = mmc_priv(mmc);
947
948 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
949}
950
3cbcb160
DL		 951static struct mmc_host_ops sunxi_mmc_ops = {
952 .request = sunxi_mmc_request,
953 .set_ios = sunxi_mmc_set_ios,
954 .get_ro = mmc_gpio_get_ro,
955 .get_cd = mmc_gpio_get_cd,
956 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
f771f6e8 957 .start_signal_voltage_switch = sunxi_mmc_volt_switch,
3cbcb160 958 .hw_reset = sunxi_mmc_hw_reset,
c1590dd8 959 .card_busy = sunxi_mmc_card_busy,
3cbcb160
DL		 960};
961
51424b28
HG		 962static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
963 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
964 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
965 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
966 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
2a7aa63a
CYT		 967 /* Value from A83T "new timing mode". Works but might not be right. */
968 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
51424b28
HG		 969};
970
971static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
972 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
973 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
974 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
0175249e
CYT		 975 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
976 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
51424b28
HG		 977};
978
86a93317
HG		 979static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
980 .idma_des_size_bits = 13,
981 .clk_delays = sunxi_mmc_clk_delays,
982};
983
984static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
985 .idma_des_size_bits = 16,
986 .clk_delays = sunxi_mmc_clk_delays,
987};
988
989static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
990 .idma_des_size_bits = 16,
991 .clk_delays = sun9i_mmc_clk_delays,
992};
993
994static const struct of_device_id sunxi_mmc_of_match[] = {
995 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
996 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
997 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
998 { /* sentinel */ }
999};
1000MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1001
3cbcb160
DL		 1002static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
1003 struct platform_device *pdev)
1004{
3cbcb160
DL		 1005 int ret;
1006
86a93317
HG		 1007 host->cfg = of_device_get_match_data(&pdev->dev);
1008 if (!host->cfg)
1009 return -EINVAL;
51424b28 1010
3cbcb160
DL		 1011 ret = mmc_regulator_get_supply(host->mmc);
1012 if (ret) {
1013 if (ret != -EPROBE_DEFER)
1014 dev_err(&pdev->dev, "Could not get vmmc supply\n");
1015 return ret;
1016 }
1017
1018 host->reg_base = devm_ioremap_resource(&pdev->dev,
1019 platform_get_resource(pdev, IORESOURCE_MEM, 0));
1020 if (IS_ERR(host->reg_base))
1021 return PTR_ERR(host->reg_base);
1022
1023 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1024 if (IS_ERR(host->clk_ahb)) {
1025 dev_err(&pdev->dev, "Could not get ahb clock\n");
1026 return PTR_ERR(host->clk_ahb);
1027 }
1028
1029 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1030 if (IS_ERR(host->clk_mmc)) {
1031 dev_err(&pdev->dev, "Could not get mmc clock\n");
1032 return PTR_ERR(host->clk_mmc);
1033 }
1034
6c09bb85
MR		 1035 host->clk_output = devm_clk_get(&pdev->dev, "output");
1036 if (IS_ERR(host->clk_output)) {
1037 dev_err(&pdev->dev, "Could not get output clock\n");
1038 return PTR_ERR(host->clk_output);
1039 }
1040
1041 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1042 if (IS_ERR(host->clk_sample)) {
1043 dev_err(&pdev->dev, "Could not get sample clock\n");
1044 return PTR_ERR(host->clk_sample);
1045 }
1046
9e71c589
CYT		 1047 host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
1048 if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1049 return PTR_ERR(host->reset);
3cbcb160
DL		 1050
1051 ret = clk_prepare_enable(host->clk_ahb);
1052 if (ret) {
1053 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret);
1054 return ret;
1055 }
1056
1057 ret = clk_prepare_enable(host->clk_mmc);
1058 if (ret) {
1059 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
1060 goto error_disable_clk_ahb;
1061 }
1062
6c09bb85
MR		 1063 ret = clk_prepare_enable(host->clk_output);
1064 if (ret) {
1065 dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
1066 goto error_disable_clk_mmc;
1067 }
1068
1069 ret = clk_prepare_enable(host->clk_sample);
1070 if (ret) {
1071 dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
1072 goto error_disable_clk_output;
1073 }
1074
3cbcb160
DL		 1075 if (!IS_ERR(host->reset)) {
1076 ret = reset_control_deassert(host->reset);
1077 if (ret) {
1078 dev_err(&pdev->dev, "reset err %d\n", ret);
6c09bb85 1079 goto error_disable_clk_sample;
3cbcb160
DL		 1080 }
1081 }
1082
1083 /*
1084 * Sometimes the controller asserts the irq on boot for some reason,
1085 * make sure the controller is in a sane state before enabling irqs.
1086 */
1087 ret = sunxi_mmc_reset_host(host);
1088 if (ret)
1089 goto error_assert_reset;
1090
1091 host->irq = platform_get_irq(pdev, 0);
1092 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1093 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1094
1095error_assert_reset:
1096 if (!IS_ERR(host->reset))
1097 reset_control_assert(host->reset);
6c09bb85
MR		 1098error_disable_clk_sample:
1099 clk_disable_unprepare(host->clk_sample);
1100error_disable_clk_output:
1101 clk_disable_unprepare(host->clk_output);
3cbcb160
DL		 1102error_disable_clk_mmc:
1103 clk_disable_unprepare(host->clk_mmc);
1104error_disable_clk_ahb:
1105 clk_disable_unprepare(host->clk_ahb);
1106 return ret;
1107}
1108
1109static int sunxi_mmc_probe(struct platform_device *pdev)
1110{
1111 struct sunxi_mmc_host *host;
1112 struct mmc_host *mmc;
1113 int ret;
1114
1115 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1116 if (!mmc) {
1117 dev_err(&pdev->dev, "mmc alloc host failed\n");
1118 return -ENOMEM;
1119 }
1120
1121 host = mmc_priv(mmc);
1122 host->mmc = mmc;
1123 spin_lock_init(&host->lock);
1124
1125 ret = sunxi_mmc_resource_request(host, pdev);
1126 if (ret)
1127 goto error_free_host;
1128
1129 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1130 &host->sg_dma, GFP_KERNEL);
1131 if (!host->sg_cpu) {
1132 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1133 ret = -ENOMEM;
1134 goto error_free_host;
1135 }
1136
1137 mmc->ops = &sunxi_mmc_ops;
1138 mmc->max_blk_count = 8192;
1139 mmc->max_blk_size = 4096;
1140 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
86a93317 1141 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);
3cbcb160 1142 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
2dcb305a 1143 /* 400kHz ~ 52MHz */
3cbcb160 1144 mmc->f_min = 400000;
2dcb305a 1145 mmc->f_max = 52000000;
3df01a93 1146 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
aed26fca 1147 MMC_CAP_1_8V_DDR |
a4101dcb 1148 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
3cbcb160
DL		 1149
1150 ret = mmc_of_parse(mmc);
1151 if (ret)
1152 goto error_free_dma;
1153
1154 ret = mmc_add_host(mmc);
1155 if (ret)
1156 goto error_free_dma;
1157
1158 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1159 platform_set_drvdata(pdev, mmc);
1160 return 0;
1161
1162error_free_dma:
1163 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1164error_free_host:
1165 mmc_free_host(mmc);
1166 return ret;
1167}
1168
1169static int sunxi_mmc_remove(struct platform_device *pdev)
1170{
1171 struct mmc_host *mmc = platform_get_drvdata(pdev);
1172 struct sunxi_mmc_host *host = mmc_priv(mmc);
1173
1174 mmc_remove_host(mmc);
1175 disable_irq(host->irq);
1176 sunxi_mmc_reset_host(host);
1177
1178 if (!IS_ERR(host->reset))
1179 reset_control_assert(host->reset);
1180
4c5f4bf4
HG		 1181 clk_disable_unprepare(host->clk_sample);
1182 clk_disable_unprepare(host->clk_output);
3cbcb160
DL		 1183 clk_disable_unprepare(host->clk_mmc);
1184 clk_disable_unprepare(host->clk_ahb);
1185
1186 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1187 mmc_free_host(mmc);
1188
1189 return 0;
1190}
1191
1192static struct platform_driver sunxi_mmc_driver = {
1193 .driver = {
1194 .name = "sunxi-mmc",
3cbcb160
DL		 1195 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1196 },
1197 .probe = sunxi_mmc_probe,
1198 .remove = sunxi_mmc_remove,
1199};
1200module_platform_driver(sunxi_mmc_driver);
1201
1202MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1203MODULE_LICENSE("GPL v2");
1204MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>");
1205MODULE_ALIAS("platform:sunxi-mmc");
Linux 6.x block layer and io_uring tree(s)