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mmc: sunxi: Gate the clock when rate is 0
[linux-2.6-block.git] / drivers / mmc / host / sunxi-mmc.c
CommitLineData
3cbcb160
DL		 1/*
2 * Driver for sunxi SD/MMC host controllers
3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
6 * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/io.h>
18#include <linux/device.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/err.h>
22
23#include <linux/clk.h>
3cbcb160
DL		 24#include <linux/gpio.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27#include <linux/scatterlist.h>
28#include <linux/dma-mapping.h>
29#include <linux/slab.h>
30#include <linux/reset.h>
f771f6e8 31#include <linux/regulator/consumer.h>
3cbcb160
DL		 32
33#include <linux/of_address.h>
34#include <linux/of_gpio.h>
35#include <linux/of_platform.h>
36
37#include <linux/mmc/host.h>
38#include <linux/mmc/sd.h>
39#include <linux/mmc/sdio.h>
40#include <linux/mmc/mmc.h>
41#include <linux/mmc/core.h>
42#include <linux/mmc/card.h>
43#include <linux/mmc/slot-gpio.h>
44
45/* register offset definitions */
46#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
47#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
48#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
49#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
50#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
51#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
52#define SDXC_REG_CMDR (0x18) /* SMC Command Register */
53#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
54#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
55#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
56#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
57#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
58#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
59#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
60#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
61#define SDXC_REG_STAS (0x3C) /* SMC Status Register */
62#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
63#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
64#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
65#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
66#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
67#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
68#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
69#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
70#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
71#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
72#define SDXC_REG_CHDA (0x90)
73#define SDXC_REG_CBDA (0x94)
74
e1b8dfd1
IZ		 75/* New registers introduced in A64 */
76#define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */
77#define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */
78#define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */
79#define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */
80#define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */
81
3cbcb160
DL		 82#define mmc_readl(host, reg) \
83 readl((host)->reg_base + SDXC_##reg)
84#define mmc_writel(host, reg, value) \
85 writel((value), (host)->reg_base + SDXC_##reg)
86
87/* global control register bits */
88#define SDXC_SOFT_RESET BIT(0)
89#define SDXC_FIFO_RESET BIT(1)
90#define SDXC_DMA_RESET BIT(2)
91#define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
92#define SDXC_DMA_ENABLE_BIT BIT(5)
93#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
94#define SDXC_POSEDGE_LATCH_DATA BIT(9)
95#define SDXC_DDR_MODE BIT(10)
96#define SDXC_MEMORY_ACCESS_DONE BIT(29)
97#define SDXC_ACCESS_DONE_DIRECT BIT(30)
98#define SDXC_ACCESS_BY_AHB BIT(31)
99#define SDXC_ACCESS_BY_DMA (0 << 31)
100#define SDXC_HARDWARE_RESET \
101 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
102
103/* clock control bits */
104#define SDXC_CARD_CLOCK_ON BIT(16)
105#define SDXC_LOW_POWER_ON BIT(17)
106
107/* bus width */
108#define SDXC_WIDTH1 0
109#define SDXC_WIDTH4 1
110#define SDXC_WIDTH8 2
111
112/* smc command bits */
113#define SDXC_RESP_EXPIRE BIT(6)
114#define SDXC_LONG_RESPONSE BIT(7)
115#define SDXC_CHECK_RESPONSE_CRC BIT(8)
116#define SDXC_DATA_EXPIRE BIT(9)
117#define SDXC_WRITE BIT(10)
118#define SDXC_SEQUENCE_MODE BIT(11)
119#define SDXC_SEND_AUTO_STOP BIT(12)
120#define SDXC_WAIT_PRE_OVER BIT(13)
121#define SDXC_STOP_ABORT_CMD BIT(14)
122#define SDXC_SEND_INIT_SEQUENCE BIT(15)
123#define SDXC_UPCLK_ONLY BIT(21)
124#define SDXC_READ_CEATA_DEV BIT(22)
125#define SDXC_CCS_EXPIRE BIT(23)
126#define SDXC_ENABLE_BIT_BOOT BIT(24)
127#define SDXC_ALT_BOOT_OPTIONS BIT(25)
128#define SDXC_BOOT_ACK_EXPIRE BIT(26)
129#define SDXC_BOOT_ABORT BIT(27)
130#define SDXC_VOLTAGE_SWITCH BIT(28)
131#define SDXC_USE_HOLD_REGISTER BIT(29)
132#define SDXC_START BIT(31)
133
134/* interrupt bits */
135#define SDXC_RESP_ERROR BIT(1)
136#define SDXC_COMMAND_DONE BIT(2)
137#define SDXC_DATA_OVER BIT(3)
138#define SDXC_TX_DATA_REQUEST BIT(4)
139#define SDXC_RX_DATA_REQUEST BIT(5)
140#define SDXC_RESP_CRC_ERROR BIT(6)
141#define SDXC_DATA_CRC_ERROR BIT(7)
142#define SDXC_RESP_TIMEOUT BIT(8)
143#define SDXC_DATA_TIMEOUT BIT(9)
144#define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
145#define SDXC_FIFO_RUN_ERROR BIT(11)
146#define SDXC_HARD_WARE_LOCKED BIT(12)
147#define SDXC_START_BIT_ERROR BIT(13)
148#define SDXC_AUTO_COMMAND_DONE BIT(14)
149#define SDXC_END_BIT_ERROR BIT(15)
150#define SDXC_SDIO_INTERRUPT BIT(16)
151#define SDXC_CARD_INSERT BIT(30)
152#define SDXC_CARD_REMOVE BIT(31)
153#define SDXC_INTERRUPT_ERROR_BIT \
154 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
155 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
156 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
157#define SDXC_INTERRUPT_DONE_BIT \
158 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
159 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
160
161/* status */
162#define SDXC_RXWL_FLAG BIT(0)
163#define SDXC_TXWL_FLAG BIT(1)
164#define SDXC_FIFO_EMPTY BIT(2)
165#define SDXC_FIFO_FULL BIT(3)
166#define SDXC_CARD_PRESENT BIT(8)
167#define SDXC_CARD_DATA_BUSY BIT(9)
168#define SDXC_DATA_FSM_BUSY BIT(10)
169#define SDXC_DMA_REQUEST BIT(31)
170#define SDXC_FIFO_SIZE 16
171
172/* Function select */
173#define SDXC_CEATA_ON (0xceaa << 16)
174#define SDXC_SEND_IRQ_RESPONSE BIT(0)
175#define SDXC_SDIO_READ_WAIT BIT(1)
176#define SDXC_ABORT_READ_DATA BIT(2)
177#define SDXC_SEND_CCSD BIT(8)
178#define SDXC_SEND_AUTO_STOPCCSD BIT(9)
179#define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
180
181/* IDMA controller bus mod bit field */
182#define SDXC_IDMAC_SOFT_RESET BIT(0)
183#define SDXC_IDMAC_FIX_BURST BIT(1)
184#define SDXC_IDMAC_IDMA_ON BIT(7)
185#define SDXC_IDMAC_REFETCH_DES BIT(31)
186
187/* IDMA status bit field */
188#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
189#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
190#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
191#define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
192#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
193#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
194#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
195#define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
196#define SDXC_IDMAC_IDLE (0 << 13)
197#define SDXC_IDMAC_SUSPEND (1 << 13)
198#define SDXC_IDMAC_DESC_READ (2 << 13)
199#define SDXC_IDMAC_DESC_CHECK (3 << 13)
200#define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
201#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
202#define SDXC_IDMAC_READ (6 << 13)
203#define SDXC_IDMAC_WRITE (7 << 13)
204#define SDXC_IDMAC_DESC_CLOSE (8 << 13)
205
206/*
207* If the idma-des-size-bits of property is ie 13, bufsize bits are:
208* Bits 0-12: buf1 size
209* Bits 13-25: buf2 size
210* Bits 26-31: not used
211* Since we only ever set buf1 size, we can simply store it directly.
212*/
213#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
214#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
215#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
216#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
217#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
218#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
219#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
220
51424b28
HG		 221#define SDXC_CLK_400K 0
222#define SDXC_CLK_25M 1
223#define SDXC_CLK_50M 2
224#define SDXC_CLK_50M_DDR 3
2a7aa63a 225#define SDXC_CLK_50M_DDR_8BIT 4
51424b28 226
e1b8dfd1
IZ		 227#define SDXC_2X_TIMING_MODE BIT(31)
228
229#define SDXC_CAL_START BIT(15)
230#define SDXC_CAL_DONE BIT(14)
231#define SDXC_CAL_DL_SHIFT 8
232#define SDXC_CAL_DL_SW_EN BIT(7)
233#define SDXC_CAL_DL_SW_SHIFT 0
234#define SDXC_CAL_DL_MASK 0x3f
235
236#define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/
237
51424b28
HG		 238struct sunxi_mmc_clk_delay {
239 u32 output;
240 u32 sample;
241};
242
3cbcb160 243struct sunxi_idma_des {
2dd110b2
MW		 244 __le32 config;
245 __le32 buf_size;
246 __le32 buf_addr_ptr1;
247 __le32 buf_addr_ptr2;
3cbcb160
DL		 248};
249
86a93317
HG		 250struct sunxi_mmc_cfg {
251 u32 idma_des_size_bits;
252 const struct sunxi_mmc_clk_delay *clk_delays;
e1b8dfd1
IZ		 253
254 /* does the IP block support autocalibration? */
255 bool can_calibrate;
86a93317
HG		 256};
257
3cbcb160
DL		 258struct sunxi_mmc_host {
259 struct mmc_host *mmc;
260 struct reset_control *reset;
86a93317 261 const struct sunxi_mmc_cfg *cfg;
3cbcb160
DL		 262
263 /* IO mapping base */
264 void __iomem *reg_base;
265
266 /* clock management */
267 struct clk *clk_ahb;
268 struct clk *clk_mmc;
6c09bb85
MR		 269 struct clk *clk_sample;
270 struct clk *clk_output;
3cbcb160
DL		 271
272 /* irq */
273 spinlock_t lock;
274 int irq;
275 u32 int_sum;
276 u32 sdio_imask;
277
278 /* dma */
3cbcb160
DL		 279 dma_addr_t sg_dma;
280 void *sg_cpu;
281 bool wait_dma;
282
283 struct mmc_request *mrq;
284 struct mmc_request *manual_stop_mrq;
285 int ferror;
f771f6e8
CYT		 286
287 /* vqmmc */
288 bool vqmmc_enabled;
3cbcb160
DL		 289};
290
291static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
292{
293 unsigned long expire = jiffies + msecs_to_jiffies(250);
294 u32 rval;
295
0f0fcd37 296 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
3cbcb160
DL		 297 do {
298 rval = mmc_readl(host, REG_GCTRL);
299 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
300
301 if (rval & SDXC_HARDWARE_RESET) {
302 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
303 return -EIO;
304 }
305
306 return 0;
307}
308
309static int sunxi_mmc_init_host(struct mmc_host *mmc)
310{
311 u32 rval;
312 struct sunxi_mmc_host *host = mmc_priv(mmc);
313
314 if (sunxi_mmc_reset_host(host))
315 return -EIO;
316
0314cbd4
CYT		 317 /*
318 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
319 *
320 * TODO: sun9i has a larger FIFO and supports higher trigger values
321 */
3cbcb160 322 mmc_writel(host, REG_FTRGL, 0x20070008);
0314cbd4 323 /* Maximum timeout value */
3cbcb160 324 mmc_writel(host, REG_TMOUT, 0xffffffff);
0314cbd4 325 /* Unmask SDIO interrupt if needed */
3cbcb160 326 mmc_writel(host, REG_IMASK, host->sdio_imask);
0314cbd4 327 /* Clear all pending interrupts */
3cbcb160 328 mmc_writel(host, REG_RINTR, 0xffffffff);
0314cbd4 329 /* Debug register? undocumented */
3cbcb160 330 mmc_writel(host, REG_DBGC, 0xdeb);
0314cbd4 331 /* Enable CEATA support */
3cbcb160 332 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
0314cbd4 333 /* Set DMA descriptor list base address */
3cbcb160
DL		 334 mmc_writel(host, REG_DLBA, host->sg_dma);
335
336 rval = mmc_readl(host, REG_GCTRL);
337 rval |= SDXC_INTERRUPT_ENABLE_BIT;
0314cbd4 338 /* Undocumented, but found in Allwinner code */
3cbcb160
DL		 339 rval &= ~SDXC_ACCESS_DONE_DIRECT;
340 mmc_writel(host, REG_GCTRL, rval);
341
342 return 0;
343}
344
345static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
346 struct mmc_data *data)
347{
348 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
d34712d2 349 dma_addr_t next_desc = host->sg_dma;
86a93317 350 int i, max_len = (1 << host->cfg->idma_des_size_bits);
3cbcb160
DL		 351
352 for (i = 0; i < data->sg_len; i++) {
2dd110b2
MW		 353 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
354 SDXC_IDMAC_DES0_OWN |
355 SDXC_IDMAC_DES0_DIC);
3cbcb160
DL		 356
357 if (data->sg[i].length == max_len)
358 pdes[i].buf_size = 0; /* 0 == max_len */
359 else
2dd110b2 360 pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
3cbcb160 361
d34712d2 362 next_desc += sizeof(struct sunxi_idma_des);
2dd110b2
MW		 363 pdes[i].buf_addr_ptr1 =
364 cpu_to_le32(sg_dma_address(&data->sg[i]));
365 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
3cbcb160
DL		 366 }
367
2dd110b2
MW		 368 pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
369 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
370 SDXC_IDMAC_DES0_ER);
371 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
e8a59049 372 pdes[i - 1].buf_addr_ptr2 = 0;
3cbcb160
DL		 373
374 /*
375 * Avoid the io-store starting the idmac hitting io-mem before the
376 * descriptors hit the main-mem.
377 */
378 wmb();
379}
380
381static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
382{
383 if (data->flags & MMC_DATA_WRITE)
384 return DMA_TO_DEVICE;
385 else
386 return DMA_FROM_DEVICE;
387}
388
389static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
390 struct mmc_data *data)
391{
392 u32 i, dma_len;
393 struct scatterlist *sg;
394
395 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
396 sunxi_mmc_get_dma_dir(data));
397 if (dma_len == 0) {
398 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
399 return -ENOMEM;
400 }
401
402 for_each_sg(data->sg, sg, data->sg_len, i) {
403 if (sg->offset & 3 || sg->length & 3) {
404 dev_err(mmc_dev(host->mmc),
405 "unaligned scatterlist: os %x length %d\n",
406 sg->offset, sg->length);
407 return -EINVAL;
408 }
409 }
410
411 return 0;
412}
413
414static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
415 struct mmc_data *data)
416{
417 u32 rval;
418
419 sunxi_mmc_init_idma_des(host, data);
420
421 rval = mmc_readl(host, REG_GCTRL);
422 rval |= SDXC_DMA_ENABLE_BIT;
423 mmc_writel(host, REG_GCTRL, rval);
424 rval |= SDXC_DMA_RESET;
425 mmc_writel(host, REG_GCTRL, rval);
426
427 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
428
429 if (!(data->flags & MMC_DATA_WRITE))
430 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
431
432 mmc_writel(host, REG_DMAC,
433 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
434}
435
436static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
437 struct mmc_request *req)
438{
439 u32 arg, cmd_val, ri;
440 unsigned long expire = jiffies + msecs_to_jiffies(1000);
441
442 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
443 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
444
445 if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
446 cmd_val |= SD_IO_RW_DIRECT;
447 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
448 ((req->cmd->arg >> 28) & 0x7);
449 } else {
450 cmd_val |= MMC_STOP_TRANSMISSION;
451 arg = 0;
452 }
453
454 mmc_writel(host, REG_CARG, arg);
455 mmc_writel(host, REG_CMDR, cmd_val);
456
457 do {
458 ri = mmc_readl(host, REG_RINTR);
459 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
460 time_before(jiffies, expire));
461
462 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
463 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
464 if (req->stop)
465 req->stop->resp[0] = -ETIMEDOUT;
466 } else {
467 if (req->stop)
468 req->stop->resp[0] = mmc_readl(host, REG_RESP0);
469 }
470
471 mmc_writel(host, REG_RINTR, 0xffff);
472}
473
474static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
475{
476 struct mmc_command *cmd = host->mrq->cmd;
477 struct mmc_data *data = host->mrq->data;
478
479 /* For some cmds timeout is normal with sd/mmc cards */
480 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
481 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
482 cmd->opcode == SD_IO_RW_DIRECT))
483 return;
484
485 dev_err(mmc_dev(host->mmc),
486 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
487 host->mmc->index, cmd->opcode,
488 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
489 host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
490 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
491 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
492 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
493 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
494 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
495 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
496 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
497 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
498 );
499}
500
501/* Called in interrupt context! */
502static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
503{
504 struct mmc_request *mrq = host->mrq;
505 struct mmc_data *data = mrq->data;
506 u32 rval;
507
508 mmc_writel(host, REG_IMASK, host->sdio_imask);
509 mmc_writel(host, REG_IDIE, 0);
510
511 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
512 sunxi_mmc_dump_errinfo(host);
513 mrq->cmd->error = -ETIMEDOUT;
514
515 if (data) {
516 data->error = -ETIMEDOUT;
517 host->manual_stop_mrq = mrq;
518 }
519
520 if (mrq->stop)
521 mrq->stop->error = -ETIMEDOUT;
522 } else {
523 if (mrq->cmd->flags & MMC_RSP_136) {
524 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
525 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
526 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
527 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
528 } else {
529 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
530 }
531
532 if (data)
533 data->bytes_xfered = data->blocks * data->blksz;
534 }
535
536 if (data) {
537 mmc_writel(host, REG_IDST, 0x337);
538 mmc_writel(host, REG_DMAC, 0);
539 rval = mmc_readl(host, REG_GCTRL);
540 rval |= SDXC_DMA_RESET;
541 mmc_writel(host, REG_GCTRL, rval);
542 rval &= ~SDXC_DMA_ENABLE_BIT;
543 mmc_writel(host, REG_GCTRL, rval);
544 rval |= SDXC_FIFO_RESET;
545 mmc_writel(host, REG_GCTRL, rval);
546 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
547 sunxi_mmc_get_dma_dir(data));
548 }
549
550 mmc_writel(host, REG_RINTR, 0xffff);
551
552 host->mrq = NULL;
553 host->int_sum = 0;
554 host->wait_dma = false;
555
556 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
557}
558
559static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
560{
561 struct sunxi_mmc_host *host = dev_id;
562 struct mmc_request *mrq;
563 u32 msk_int, idma_int;
564 bool finalize = false;
565 bool sdio_int = false;
566 irqreturn_t ret = IRQ_HANDLED;
567
568 spin_lock(&host->lock);
569
570 idma_int = mmc_readl(host, REG_IDST);
571 msk_int = mmc_readl(host, REG_MISTA);
572
573 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
574 host->mrq, msk_int, idma_int);
575
576 mrq = host->mrq;
577 if (mrq) {
578 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
579 host->wait_dma = false;
580
581 host->int_sum |= msk_int;
582
583 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
584 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
585 !(host->int_sum & SDXC_COMMAND_DONE))
586 mmc_writel(host, REG_IMASK,
587 host->sdio_imask | SDXC_COMMAND_DONE);
588 /* Don't wait for dma on error */
589 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
590 finalize = true;
591 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
592 !host->wait_dma)
593 finalize = true;
594 }
595
596 if (msk_int & SDXC_SDIO_INTERRUPT)
597 sdio_int = true;
598
599 mmc_writel(host, REG_RINTR, msk_int);
600 mmc_writel(host, REG_IDST, idma_int);
601
602 if (finalize)
603 ret = sunxi_mmc_finalize_request(host);
604
605 spin_unlock(&host->lock);
606
607 if (finalize && ret == IRQ_HANDLED)
608 mmc_request_done(host->mmc, mrq);
609
610 if (sdio_int)
611 mmc_signal_sdio_irq(host->mmc);
612
613 return ret;
614}
615
616static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
617{
618 struct sunxi_mmc_host *host = dev_id;
619 struct mmc_request *mrq;
620 unsigned long iflags;
621
622 spin_lock_irqsave(&host->lock, iflags);
623 mrq = host->manual_stop_mrq;
624 spin_unlock_irqrestore(&host->lock, iflags);
625
626 if (!mrq) {
627 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
628 return IRQ_HANDLED;
629 }
630
631 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
dd9b3803
DL		 632
633 /*
634 * We will never have more than one outstanding request,
635 * and we do not complete the request until after
636 * we've cleared host->manual_stop_mrq so we do not need to
637 * spin lock this function.
638 * Additionally we have wait states within this function
639 * so having it in a lock is a very bad idea.
640 */
3cbcb160
DL		 641 sunxi_mmc_send_manual_stop(host, mrq);
642
643 spin_lock_irqsave(&host->lock, iflags);
644 host->manual_stop_mrq = NULL;
645 spin_unlock_irqrestore(&host->lock, iflags);
646
647 mmc_request_done(host->mmc, mrq);
648
649 return IRQ_HANDLED;
650}
651
652static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
653{
7bb9c244 654 unsigned long expire = jiffies + msecs_to_jiffies(750);
3cbcb160
DL		 655 u32 rval;
656
657 rval = mmc_readl(host, REG_CLKCR);
658 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
659
660 if (oclk_en)
661 rval |= SDXC_CARD_CLOCK_ON;
662
663 mmc_writel(host, REG_CLKCR, rval);
664
665 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
666 mmc_writel(host, REG_CMDR, rval);
667
668 do {
669 rval = mmc_readl(host, REG_CMDR);
670 } while (time_before(jiffies, expire) && (rval & SDXC_START));
671
672 /* clear irq status bits set by the command */
673 mmc_writel(host, REG_RINTR,
674 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
675
676 if (rval & SDXC_START) {
677 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
678 return -EIO;
679 }
680
681 return 0;
682}
683
e1b8dfd1
IZ		 684static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
685{
686 u32 reg = readl(host->reg_base + reg_off);
687 u32 delay;
688 unsigned long timeout;
689
690 if (!host->cfg->can_calibrate)
691 return 0;
692
693 reg &= ~(SDXC_CAL_DL_MASK << SDXC_CAL_DL_SW_SHIFT);
694 reg &= ~SDXC_CAL_DL_SW_EN;
695
696 writel(reg | SDXC_CAL_START, host->reg_base + reg_off);
697
698 dev_dbg(mmc_dev(host->mmc), "calibration started\n");
699
700 timeout = jiffies + HZ * SDXC_CAL_TIMEOUT;
701
702 while (!((reg = readl(host->reg_base + reg_off)) & SDXC_CAL_DONE)) {
703 if (time_before(jiffies, timeout))
704 cpu_relax();
705 else {
706 reg &= ~SDXC_CAL_START;
707 writel(reg, host->reg_base + reg_off);
708
709 return -ETIMEDOUT;
710 }
711 }
712
713 delay = (reg >> SDXC_CAL_DL_SHIFT) & SDXC_CAL_DL_MASK;
714
715 reg &= ~SDXC_CAL_START;
716 reg |= (delay << SDXC_CAL_DL_SW_SHIFT) | SDXC_CAL_DL_SW_EN;
717
718 writel(reg, host->reg_base + reg_off);
719
720 dev_dbg(mmc_dev(host->mmc), "calibration ended, reg is 0x%x\n", reg);
721
722 return 0;
723}
724
f2cecb70
HG		 725static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
726 struct mmc_ios *ios, u32 rate)
727{
728 int index;
729
b465646e
HG		 730 if (!host->cfg->clk_delays)
731 return 0;
732
f2cecb70
HG		 733 /* determine delays */
734 if (rate <= 400000) {
735 index = SDXC_CLK_400K;
736 } else if (rate <= 25000000) {
737 index = SDXC_CLK_25M;
738 } else if (rate <= 52000000) {
739 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
740 ios->timing != MMC_TIMING_MMC_DDR52) {
741 index = SDXC_CLK_50M;
742 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
743 index = SDXC_CLK_50M_DDR_8BIT;
744 } else {
745 index = SDXC_CLK_50M_DDR;
746 }
747 } else {
748 return -EINVAL;
749 }
750
751 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
752 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
753
754 return 0;
755}
756
3cbcb160
DL		 757static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
758 struct mmc_ios *ios)
759{
63311bec
JFM		 760 long rate;
761 u32 rval, clock = ios->clock;
3cbcb160
DL		 762 int ret;
763
39cc281f
MR		 764 ret = sunxi_mmc_oclk_onoff(host, 0);
765 if (ret)
766 return ret;
767
9479074e
MR		 768 if (!ios->clock)
769 return 0;
770
2a7aa63a
CYT		 771 /* 8 bit DDR requires a higher module clock */
772 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
773 ios->bus_width == MMC_BUS_WIDTH_8)
774 clock <<= 1;
775
776 rate = clk_round_rate(host->clk_mmc, clock);
63311bec
JFM		 777 if (rate < 0) {
778 dev_err(mmc_dev(host->mmc), "error rounding clk to %d: %ld\n",
779 clock, rate);
780 return rate;
781 }
782 dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %ld\n",
2a7aa63a 783 clock, rate);
3cbcb160
DL		 784
785 /* setting clock rate */
786 ret = clk_set_rate(host->clk_mmc, rate);
787 if (ret) {
63311bec 788 dev_err(mmc_dev(host->mmc), "error setting clk to %ld: %d\n",
3cbcb160
DL		 789 rate, ret);
790 return ret;
791 }
792
3cbcb160
DL		 793 /* clear internal divider */
794 rval = mmc_readl(host, REG_CLKCR);
795 rval &= ~0xff;
2a7aa63a
CYT		 796 /* set internal divider for 8 bit eMMC DDR, so card clock is right */
797 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
798 ios->bus_width == MMC_BUS_WIDTH_8) {
799 rval |= 1;
800 rate >>= 1;
801 }
3cbcb160
DL		 802 mmc_writel(host, REG_CLKCR, rval);
803
f2cecb70
HG		 804 ret = sunxi_mmc_clk_set_phase(host, ios, rate);
805 if (ret)
806 return ret;
3cbcb160 807
e1b8dfd1
IZ		 808 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
809 if (ret)
810 return ret;
811
812 /* TODO: enable calibrate on sdc2 SDXC_REG_DS_DL_REG of A64 */
813
3cbcb160
DL		 814 return sunxi_mmc_oclk_onoff(host, 1);
815}
816
817static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
818{
819 struct sunxi_mmc_host *host = mmc_priv(mmc);
820 u32 rval;
821
822 /* Set the power state */
823 switch (ios->power_mode) {
824 case MMC_POWER_ON:
825 break;
826
827 case MMC_POWER_UP:
424feb59
MR		 828 if (!IS_ERR(mmc->supply.vmmc)) {
829 host->ferror = mmc_regulator_set_ocr(mmc,
830 mmc->supply.vmmc,
831 ios->vdd);
832 if (host->ferror)
833 return;
834 }
3cbcb160 835
f771f6e8
CYT		 836 if (!IS_ERR(mmc->supply.vqmmc)) {
837 host->ferror = regulator_enable(mmc->supply.vqmmc);
838 if (host->ferror) {
839 dev_err(mmc_dev(mmc),
840 "failed to enable vqmmc\n");
841 return;
842 }
843 host->vqmmc_enabled = true;
844 }
845
3cbcb160
DL		 846 host->ferror = sunxi_mmc_init_host(mmc);
847 if (host->ferror)
848 return;
849
850 dev_dbg(mmc_dev(mmc), "power on!\n");
851 break;
852
853 case MMC_POWER_OFF:
854 dev_dbg(mmc_dev(mmc), "power off!\n");
855 sunxi_mmc_reset_host(host);
424feb59
MR		 856 if (!IS_ERR(mmc->supply.vmmc))
857 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
858
f771f6e8
CYT		 859 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
860 regulator_disable(mmc->supply.vqmmc);
861 host->vqmmc_enabled = false;
3cbcb160
DL		 862 break;
863 }
864
865 /* set bus width */
866 switch (ios->bus_width) {
867 case MMC_BUS_WIDTH_1:
868 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
869 break;
870 case MMC_BUS_WIDTH_4:
871 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
872 break;
873 case MMC_BUS_WIDTH_8:
874 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
875 break;
876 }
877
878 /* set ddr mode */
879 rval = mmc_readl(host, REG_GCTRL);
2dcb305a
CYT		 880 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
881 ios->timing == MMC_TIMING_MMC_DDR52)
3cbcb160
DL		 882 rval |= SDXC_DDR_MODE;
883 else
884 rval &= ~SDXC_DDR_MODE;
885 mmc_writel(host, REG_GCTRL, rval);
886
887 /* set up clock */
9479074e 888 if (ios->power_mode) {
3cbcb160
DL		 889 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
890 /* Android code had a usleep_range(50000, 55000); here */
891 }
892}
893
f771f6e8
CYT		 894static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
895{
896 /* vqmmc regulator is available */
897 if (!IS_ERR(mmc->supply.vqmmc))
898 return mmc_regulator_set_vqmmc(mmc, ios);
899
900 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
901 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
902 return 0;
903
904 return -EINVAL;
905}
906
3cbcb160
DL		 907static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
908{
909 struct sunxi_mmc_host *host = mmc_priv(mmc);
910 unsigned long flags;
911 u32 imask;
912
913 spin_lock_irqsave(&host->lock, flags);
914
915 imask = mmc_readl(host, REG_IMASK);
916 if (enable) {
917 host->sdio_imask = SDXC_SDIO_INTERRUPT;
918 imask |= SDXC_SDIO_INTERRUPT;
919 } else {
920 host->sdio_imask = 0;
921 imask &= ~SDXC_SDIO_INTERRUPT;
922 }
923 mmc_writel(host, REG_IMASK, imask);
924 spin_unlock_irqrestore(&host->lock, flags);
925}
926
927static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
928{
929 struct sunxi_mmc_host *host = mmc_priv(mmc);
930 mmc_writel(host, REG_HWRST, 0);
931 udelay(10);
932 mmc_writel(host, REG_HWRST, 1);
933 udelay(300);
934}
935
936static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
937{
938 struct sunxi_mmc_host *host = mmc_priv(mmc);
939 struct mmc_command *cmd = mrq->cmd;
940 struct mmc_data *data = mrq->data;
941 unsigned long iflags;
942 u32 imask = SDXC_INTERRUPT_ERROR_BIT;
943 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
dd9b3803 944 bool wait_dma = host->wait_dma;
3cbcb160
DL		 945 int ret;
946
947 /* Check for set_ios errors (should never happen) */
948 if (host->ferror) {
949 mrq->cmd->error = host->ferror;
950 mmc_request_done(mmc, mrq);
951 return;
952 }
953
954 if (data) {
955 ret = sunxi_mmc_map_dma(host, data);
956 if (ret < 0) {
957 dev_err(mmc_dev(mmc), "map DMA failed\n");
958 cmd->error = ret;
959 data->error = ret;
960 mmc_request_done(mmc, mrq);
961 return;
962 }
963 }
964
965 if (cmd->opcode == MMC_GO_IDLE_STATE) {
966 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
967 imask |= SDXC_COMMAND_DONE;
968 }
969
970 if (cmd->flags & MMC_RSP_PRESENT) {
971 cmd_val |= SDXC_RESP_EXPIRE;
972 if (cmd->flags & MMC_RSP_136)
973 cmd_val |= SDXC_LONG_RESPONSE;
974 if (cmd->flags & MMC_RSP_CRC)
975 cmd_val |= SDXC_CHECK_RESPONSE_CRC;
976
977 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
978 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
3cbcb160
DL		 979
980 if (cmd->data->stop) {
981 imask |= SDXC_AUTO_COMMAND_DONE;
982 cmd_val |= SDXC_SEND_AUTO_STOP;
983 } else {
984 imask |= SDXC_DATA_OVER;
985 }
986
987 if (cmd->data->flags & MMC_DATA_WRITE)
988 cmd_val |= SDXC_WRITE;
989 else
dd9b3803 990 wait_dma = true;
3cbcb160
DL		 991 } else {
992 imask |= SDXC_COMMAND_DONE;
993 }
994 } else {
995 imask |= SDXC_COMMAND_DONE;
996 }
997
998 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
999 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
1000 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
1001
1002 spin_lock_irqsave(&host->lock, iflags);
1003
1004 if (host->mrq || host->manual_stop_mrq) {
1005 spin_unlock_irqrestore(&host->lock, iflags);
1006
1007 if (data)
1008 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
1009 sunxi_mmc_get_dma_dir(data));
1010
1011 dev_err(mmc_dev(mmc), "request already pending\n");
1012 mrq->cmd->error = -EBUSY;
1013 mmc_request_done(mmc, mrq);
1014 return;
1015 }
1016
1017 if (data) {
1018 mmc_writel(host, REG_BLKSZ, data->blksz);
1019 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
1020 sunxi_mmc_start_dma(host, data);
1021 }
1022
1023 host->mrq = mrq;
dd9b3803 1024 host->wait_dma = wait_dma;
3cbcb160
DL		 1025 mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
1026 mmc_writel(host, REG_CARG, cmd->arg);
1027 mmc_writel(host, REG_CMDR, cmd_val);
1028
1029 spin_unlock_irqrestore(&host->lock, iflags);
1030}
1031
c1590dd8
HG		 1032static int sunxi_mmc_card_busy(struct mmc_host *mmc)
1033{
1034 struct sunxi_mmc_host *host = mmc_priv(mmc);
1035
1036 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
1037}
1038
3cbcb160
DL		 1039static struct mmc_host_ops sunxi_mmc_ops = {
1040 .request = sunxi_mmc_request,
1041 .set_ios = sunxi_mmc_set_ios,
1042 .get_ro = mmc_gpio_get_ro,
1043 .get_cd = mmc_gpio_get_cd,
1044 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
f771f6e8 1045 .start_signal_voltage_switch = sunxi_mmc_volt_switch,
3cbcb160 1046 .hw_reset = sunxi_mmc_hw_reset,
c1590dd8 1047 .card_busy = sunxi_mmc_card_busy,
3cbcb160
DL		 1048};
1049
51424b28
HG		 1050static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
1051 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1052 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1053 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
1054 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
2a7aa63a
CYT		 1055 /* Value from A83T "new timing mode". Works but might not be right. */
1056 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
51424b28
HG		 1057};
1058
1059static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
1060 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1061 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1062 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
0175249e
CYT		 1063 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
1064 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
51424b28
HG		 1065};
1066
86a93317
HG		 1067static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
1068 .idma_des_size_bits = 13,
b465646e 1069 .clk_delays = NULL,
e1b8dfd1 1070 .can_calibrate = false,
86a93317
HG		 1071};
1072
1073static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
b465646e
HG		 1074 .idma_des_size_bits = 16,
1075 .clk_delays = NULL,
e1b8dfd1 1076 .can_calibrate = false,
b465646e
HG		 1077};
1078
1079static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
86a93317
HG		 1080 .idma_des_size_bits = 16,
1081 .clk_delays = sunxi_mmc_clk_delays,
e1b8dfd1 1082 .can_calibrate = false,
86a93317
HG		 1083};
1084
1085static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
1086 .idma_des_size_bits = 16,
1087 .clk_delays = sun9i_mmc_clk_delays,
e1b8dfd1
IZ		 1088 .can_calibrate = false,
1089};
1090
1091static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
1092 .idma_des_size_bits = 16,
1093 .clk_delays = NULL,
1094 .can_calibrate = true,
86a93317
HG		 1095};
1096
1097static const struct of_device_id sunxi_mmc_of_match[] = {
1098 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
1099 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
b465646e 1100 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
86a93317 1101 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
e1b8dfd1 1102 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
86a93317
HG		 1103 { /* sentinel */ }
1104};
1105MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1106
3cbcb160
DL		 1107static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
1108 struct platform_device *pdev)
1109{
3cbcb160
DL		 1110 int ret;
1111
86a93317
HG		 1112 host->cfg = of_device_get_match_data(&pdev->dev);
1113 if (!host->cfg)
1114 return -EINVAL;
51424b28 1115
3cbcb160
DL		 1116 ret = mmc_regulator_get_supply(host->mmc);
1117 if (ret) {
1118 if (ret != -EPROBE_DEFER)
1119 dev_err(&pdev->dev, "Could not get vmmc supply\n");
1120 return ret;
1121 }
1122
1123 host->reg_base = devm_ioremap_resource(&pdev->dev,
1124 platform_get_resource(pdev, IORESOURCE_MEM, 0));
1125 if (IS_ERR(host->reg_base))
1126 return PTR_ERR(host->reg_base);
1127
1128 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1129 if (IS_ERR(host->clk_ahb)) {
1130 dev_err(&pdev->dev, "Could not get ahb clock\n");
1131 return PTR_ERR(host->clk_ahb);
1132 }
1133
1134 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1135 if (IS_ERR(host->clk_mmc)) {
1136 dev_err(&pdev->dev, "Could not get mmc clock\n");
1137 return PTR_ERR(host->clk_mmc);
1138 }
1139
b465646e
HG		 1140 if (host->cfg->clk_delays) {
1141 host->clk_output = devm_clk_get(&pdev->dev, "output");
1142 if (IS_ERR(host->clk_output)) {
1143 dev_err(&pdev->dev, "Could not get output clock\n");
1144 return PTR_ERR(host->clk_output);
1145 }
6c09bb85 1146
b465646e
HG		 1147 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1148 if (IS_ERR(host->clk_sample)) {
1149 dev_err(&pdev->dev, "Could not get sample clock\n");
1150 return PTR_ERR(host->clk_sample);
1151 }
6c09bb85
MR		 1152 }
1153
9e71c589
CYT		 1154 host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
1155 if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1156 return PTR_ERR(host->reset);
3cbcb160
DL		 1157
1158 ret = clk_prepare_enable(host->clk_ahb);
1159 if (ret) {
1160 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret);
1161 return ret;
1162 }
1163
1164 ret = clk_prepare_enable(host->clk_mmc);
1165 if (ret) {
1166 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
1167 goto error_disable_clk_ahb;
1168 }
1169
6c09bb85
MR		 1170 ret = clk_prepare_enable(host->clk_output);
1171 if (ret) {
1172 dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
1173 goto error_disable_clk_mmc;
1174 }
1175
1176 ret = clk_prepare_enable(host->clk_sample);
1177 if (ret) {
1178 dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
1179 goto error_disable_clk_output;
1180 }
1181
3cbcb160
DL		 1182 if (!IS_ERR(host->reset)) {
1183 ret = reset_control_deassert(host->reset);
1184 if (ret) {
1185 dev_err(&pdev->dev, "reset err %d\n", ret);
6c09bb85 1186 goto error_disable_clk_sample;
3cbcb160
DL		 1187 }
1188 }
1189
1190 /*
1191 * Sometimes the controller asserts the irq on boot for some reason,
1192 * make sure the controller is in a sane state before enabling irqs.
1193 */
1194 ret = sunxi_mmc_reset_host(host);
1195 if (ret)
1196 goto error_assert_reset;
1197
1198 host->irq = platform_get_irq(pdev, 0);
1199 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1200 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1201
1202error_assert_reset:
1203 if (!IS_ERR(host->reset))
1204 reset_control_assert(host->reset);
6c09bb85
MR		 1205error_disable_clk_sample:
1206 clk_disable_unprepare(host->clk_sample);
1207error_disable_clk_output:
1208 clk_disable_unprepare(host->clk_output);
3cbcb160
DL		 1209error_disable_clk_mmc:
1210 clk_disable_unprepare(host->clk_mmc);
1211error_disable_clk_ahb:
1212 clk_disable_unprepare(host->clk_ahb);
1213 return ret;
1214}
1215
1216static int sunxi_mmc_probe(struct platform_device *pdev)
1217{
1218 struct sunxi_mmc_host *host;
1219 struct mmc_host *mmc;
1220 int ret;
1221
1222 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1223 if (!mmc) {
1224 dev_err(&pdev->dev, "mmc alloc host failed\n");
1225 return -ENOMEM;
1226 }
1227
1228 host = mmc_priv(mmc);
1229 host->mmc = mmc;
1230 spin_lock_init(&host->lock);
1231
1232 ret = sunxi_mmc_resource_request(host, pdev);
1233 if (ret)
1234 goto error_free_host;
1235
1236 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1237 &host->sg_dma, GFP_KERNEL);
1238 if (!host->sg_cpu) {
1239 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1240 ret = -ENOMEM;
1241 goto error_free_host;
1242 }
1243
1244 mmc->ops = &sunxi_mmc_ops;
1245 mmc->max_blk_count = 8192;
1246 mmc->max_blk_size = 4096;
1247 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
86a93317 1248 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);
3cbcb160 1249 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
2dcb305a 1250 /* 400kHz ~ 52MHz */
3cbcb160 1251 mmc->f_min = 400000;
2dcb305a 1252 mmc->f_max = 52000000;
3df01a93 1253 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
a4101dcb 1254 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
3cbcb160 1255
b465646e
HG		 1256 if (host->cfg->clk_delays)
1257 mmc->caps |= MMC_CAP_1_8V_DDR;
1258
3cbcb160
DL		 1259 ret = mmc_of_parse(mmc);
1260 if (ret)
1261 goto error_free_dma;
1262
1263 ret = mmc_add_host(mmc);
1264 if (ret)
1265 goto error_free_dma;
1266
1267 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1268 platform_set_drvdata(pdev, mmc);
1269 return 0;
1270
1271error_free_dma:
1272 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1273error_free_host:
1274 mmc_free_host(mmc);
1275 return ret;
1276}
1277
1278static int sunxi_mmc_remove(struct platform_device *pdev)
1279{
1280 struct mmc_host *mmc = platform_get_drvdata(pdev);
1281 struct sunxi_mmc_host *host = mmc_priv(mmc);
1282
1283 mmc_remove_host(mmc);
1284 disable_irq(host->irq);
1285 sunxi_mmc_reset_host(host);
1286
1287 if (!IS_ERR(host->reset))
1288 reset_control_assert(host->reset);
1289
4c5f4bf4
HG		 1290 clk_disable_unprepare(host->clk_sample);
1291 clk_disable_unprepare(host->clk_output);
3cbcb160
DL		 1292 clk_disable_unprepare(host->clk_mmc);
1293 clk_disable_unprepare(host->clk_ahb);
1294
1295 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1296 mmc_free_host(mmc);
1297
1298 return 0;
1299}
1300
1301static struct platform_driver sunxi_mmc_driver = {
1302 .driver = {
1303 .name = "sunxi-mmc",
3cbcb160
DL		 1304 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1305 },
1306 .probe = sunxi_mmc_probe,
1307 .remove = sunxi_mmc_remove,
1308};
1309module_platform_driver(sunxi_mmc_driver);
1310
1311MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1312MODULE_LICENSE("GPL v2");
1313MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>");
1314MODULE_ALIAS("platform:sunxi-mmc");
Linux 6.x block layer and io_uring tree(s)