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dt-bindings: mmc: rockchip-dw-mshc: add description for px30
[linux-2.6-block.git] / drivers / mmc / host / sunxi-mmc.c
CommitLineData
3cbcb160
DL		 1/*
2 * Driver for sunxi SD/MMC host controllers
3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
1907e386 6 * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
3cbcb160 7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
4fb3ce07 8 * (C) Copyright 2017 Sootech SA
3cbcb160
DL		 9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 */
15
3cbcb160 16#include <linux/clk.h>
ff39e7f7 17#include <linux/clk/sunxi-ng.h>
743b819e
MR		 18#include <linux/delay.h>
19#include <linux/device.h>
3cbcb160 20#include <linux/dma-mapping.h>
743b819e
MR		 21#include <linux/err.h>
22#include <linux/gpio.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/kernel.h>
26#include <linux/mmc/card.h>
27#include <linux/mmc/core.h>
3cbcb160 28#include <linux/mmc/host.h>
743b819e 29#include <linux/mmc/mmc.h>
3cbcb160
DL		 30#include <linux/mmc/sd.h>
31#include <linux/mmc/sdio.h>
3cbcb160 32#include <linux/mmc/slot-gpio.h>
743b819e
MR		 33#include <linux/module.h>
34#include <linux/of_address.h>
35#include <linux/of_gpio.h>
36#include <linux/of_platform.h>
37#include <linux/platform_device.h>
9a8e1e8c 38#include <linux/pm_runtime.h>
743b819e
MR		 39#include <linux/regulator/consumer.h>
40#include <linux/reset.h>
41#include <linux/scatterlist.h>
42#include <linux/slab.h>
43#include <linux/spinlock.h>
3cbcb160
DL		 44
45/* register offset definitions */
46#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
47#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
48#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
49#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
50#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
51#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
52#define SDXC_REG_CMDR (0x18) /* SMC Command Register */
53#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
54#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
55#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
56#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
57#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
58#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
59#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
60#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
61#define SDXC_REG_STAS (0x3C) /* SMC Status Register */
62#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
63#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
64#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
65#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
66#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
67#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
68#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
69#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
70#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
71#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
72#define SDXC_REG_CHDA (0x90)
73#define SDXC_REG_CBDA (0x94)
74
e1b8dfd1
IZ		 75/* New registers introduced in A64 */
76#define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */
77#define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */
78#define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */
79#define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */
80#define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */
81
3cbcb160
DL		 82#define mmc_readl(host, reg) \
83 readl((host)->reg_base + SDXC_##reg)
84#define mmc_writel(host, reg, value) \
85 writel((value), (host)->reg_base + SDXC_##reg)
86
87/* global control register bits */
88#define SDXC_SOFT_RESET BIT(0)
89#define SDXC_FIFO_RESET BIT(1)
90#define SDXC_DMA_RESET BIT(2)
91#define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
92#define SDXC_DMA_ENABLE_BIT BIT(5)
93#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
94#define SDXC_POSEDGE_LATCH_DATA BIT(9)
95#define SDXC_DDR_MODE BIT(10)
96#define SDXC_MEMORY_ACCESS_DONE BIT(29)
97#define SDXC_ACCESS_DONE_DIRECT BIT(30)
98#define SDXC_ACCESS_BY_AHB BIT(31)
99#define SDXC_ACCESS_BY_DMA (0 << 31)
100#define SDXC_HARDWARE_RESET \
101 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
102
103/* clock control bits */
16e821e3 104#define SDXC_MASK_DATA0 BIT(31)
3cbcb160
DL		 105#define SDXC_CARD_CLOCK_ON BIT(16)
106#define SDXC_LOW_POWER_ON BIT(17)
107
108/* bus width */
109#define SDXC_WIDTH1 0
110#define SDXC_WIDTH4 1
111#define SDXC_WIDTH8 2
112
113/* smc command bits */
114#define SDXC_RESP_EXPIRE BIT(6)
115#define SDXC_LONG_RESPONSE BIT(7)
116#define SDXC_CHECK_RESPONSE_CRC BIT(8)
117#define SDXC_DATA_EXPIRE BIT(9)
118#define SDXC_WRITE BIT(10)
119#define SDXC_SEQUENCE_MODE BIT(11)
120#define SDXC_SEND_AUTO_STOP BIT(12)
121#define SDXC_WAIT_PRE_OVER BIT(13)
122#define SDXC_STOP_ABORT_CMD BIT(14)
123#define SDXC_SEND_INIT_SEQUENCE BIT(15)
124#define SDXC_UPCLK_ONLY BIT(21)
125#define SDXC_READ_CEATA_DEV BIT(22)
126#define SDXC_CCS_EXPIRE BIT(23)
127#define SDXC_ENABLE_BIT_BOOT BIT(24)
128#define SDXC_ALT_BOOT_OPTIONS BIT(25)
129#define SDXC_BOOT_ACK_EXPIRE BIT(26)
130#define SDXC_BOOT_ABORT BIT(27)
131#define SDXC_VOLTAGE_SWITCH BIT(28)
132#define SDXC_USE_HOLD_REGISTER BIT(29)
133#define SDXC_START BIT(31)
134
135/* interrupt bits */
136#define SDXC_RESP_ERROR BIT(1)
137#define SDXC_COMMAND_DONE BIT(2)
138#define SDXC_DATA_OVER BIT(3)
139#define SDXC_TX_DATA_REQUEST BIT(4)
140#define SDXC_RX_DATA_REQUEST BIT(5)
141#define SDXC_RESP_CRC_ERROR BIT(6)
142#define SDXC_DATA_CRC_ERROR BIT(7)
143#define SDXC_RESP_TIMEOUT BIT(8)
144#define SDXC_DATA_TIMEOUT BIT(9)
145#define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
146#define SDXC_FIFO_RUN_ERROR BIT(11)
147#define SDXC_HARD_WARE_LOCKED BIT(12)
148#define SDXC_START_BIT_ERROR BIT(13)
149#define SDXC_AUTO_COMMAND_DONE BIT(14)
150#define SDXC_END_BIT_ERROR BIT(15)
151#define SDXC_SDIO_INTERRUPT BIT(16)
152#define SDXC_CARD_INSERT BIT(30)
153#define SDXC_CARD_REMOVE BIT(31)
154#define SDXC_INTERRUPT_ERROR_BIT \
155 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
156 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
157 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
158#define SDXC_INTERRUPT_DONE_BIT \
159 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
160 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
161
162/* status */
163#define SDXC_RXWL_FLAG BIT(0)
164#define SDXC_TXWL_FLAG BIT(1)
165#define SDXC_FIFO_EMPTY BIT(2)
166#define SDXC_FIFO_FULL BIT(3)
167#define SDXC_CARD_PRESENT BIT(8)
168#define SDXC_CARD_DATA_BUSY BIT(9)
169#define SDXC_DATA_FSM_BUSY BIT(10)
170#define SDXC_DMA_REQUEST BIT(31)
171#define SDXC_FIFO_SIZE 16
172
173/* Function select */
174#define SDXC_CEATA_ON (0xceaa << 16)
175#define SDXC_SEND_IRQ_RESPONSE BIT(0)
176#define SDXC_SDIO_READ_WAIT BIT(1)
177#define SDXC_ABORT_READ_DATA BIT(2)
178#define SDXC_SEND_CCSD BIT(8)
179#define SDXC_SEND_AUTO_STOPCCSD BIT(9)
180#define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
181
182/* IDMA controller bus mod bit field */
183#define SDXC_IDMAC_SOFT_RESET BIT(0)
184#define SDXC_IDMAC_FIX_BURST BIT(1)
185#define SDXC_IDMAC_IDMA_ON BIT(7)
186#define SDXC_IDMAC_REFETCH_DES BIT(31)
187
188/* IDMA status bit field */
189#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
190#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
191#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
192#define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
193#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
194#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
195#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
196#define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
197#define SDXC_IDMAC_IDLE (0 << 13)
198#define SDXC_IDMAC_SUSPEND (1 << 13)
199#define SDXC_IDMAC_DESC_READ (2 << 13)
200#define SDXC_IDMAC_DESC_CHECK (3 << 13)
201#define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
202#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
203#define SDXC_IDMAC_READ (6 << 13)
204#define SDXC_IDMAC_WRITE (7 << 13)
205#define SDXC_IDMAC_DESC_CLOSE (8 << 13)
206
207/*
208* If the idma-des-size-bits of property is ie 13, bufsize bits are:
209* Bits 0-12: buf1 size
210* Bits 13-25: buf2 size
211* Bits 26-31: not used
212* Since we only ever set buf1 size, we can simply store it directly.
213*/
214#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
215#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
216#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
217#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
218#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
219#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
220#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
221
51424b28
HG		 222#define SDXC_CLK_400K 0
223#define SDXC_CLK_25M 1
224#define SDXC_CLK_50M 2
225#define SDXC_CLK_50M_DDR 3
2a7aa63a 226#define SDXC_CLK_50M_DDR_8BIT 4
51424b28 227
e1b8dfd1
IZ		 228#define SDXC_2X_TIMING_MODE BIT(31)
229
230#define SDXC_CAL_START BIT(15)
231#define SDXC_CAL_DONE BIT(14)
232#define SDXC_CAL_DL_SHIFT 8
233#define SDXC_CAL_DL_SW_EN BIT(7)
234#define SDXC_CAL_DL_SW_SHIFT 0
235#define SDXC_CAL_DL_MASK 0x3f
236
237#define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/
238
51424b28
HG		 239struct sunxi_mmc_clk_delay {
240 u32 output;
241 u32 sample;
242};
243
3cbcb160 244struct sunxi_idma_des {
2dd110b2
MW		 245 __le32 config;
246 __le32 buf_size;
247 __le32 buf_addr_ptr1;
248 __le32 buf_addr_ptr2;
3cbcb160
DL		 249};
250
86a93317
HG		 251struct sunxi_mmc_cfg {
252 u32 idma_des_size_bits;
253 const struct sunxi_mmc_clk_delay *clk_delays;
e1b8dfd1
IZ		 254
255 /* does the IP block support autocalibration? */
256 bool can_calibrate;
9a37e53e 257
16e821e3
MR		 258 /* Does DATA0 needs to be masked while the clock is updated */
259 bool mask_data0;
260
ff39e7f7 261 /* hardware only supports new timing mode */
9a37e53e 262 bool needs_new_timings;
ff39e7f7
CYT		 263
264 /* hardware can switch between old and new timing modes */
265 bool has_timings_switch;
86a93317
HG		 266};
267
3cbcb160 268struct sunxi_mmc_host {
774c0103 269 struct device *dev;
3cbcb160
DL		 270 struct mmc_host *mmc;
271 struct reset_control *reset;
86a93317 272 const struct sunxi_mmc_cfg *cfg;
3cbcb160
DL		 273
274 /* IO mapping base */
275 void __iomem *reg_base;
276
277 /* clock management */
278 struct clk *clk_ahb;
279 struct clk *clk_mmc;
6c09bb85
MR		 280 struct clk *clk_sample;
281 struct clk *clk_output;
3cbcb160
DL		 282
283 /* irq */
284 spinlock_t lock;
285 int irq;
286 u32 int_sum;
287 u32 sdio_imask;
288
289 /* dma */
3cbcb160
DL		 290 dma_addr_t sg_dma;
291 void *sg_cpu;
292 bool wait_dma;
293
294 struct mmc_request *mrq;
295 struct mmc_request *manual_stop_mrq;
296 int ferror;
f771f6e8
CYT		 297
298 /* vqmmc */
299 bool vqmmc_enabled;
ff39e7f7
CYT		 300
301 /* timings */
302 bool use_new_timings;
3cbcb160
DL		 303};
304
305static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
306{
307 unsigned long expire = jiffies + msecs_to_jiffies(250);
308 u32 rval;
309
0f0fcd37 310 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
3cbcb160
DL		 311 do {
312 rval = mmc_readl(host, REG_GCTRL);
313 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
314
315 if (rval & SDXC_HARDWARE_RESET) {
316 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
317 return -EIO;
318 }
319
320 return 0;
321}
322
0fc4c61f 323static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
3cbcb160
DL		 324{
325 u32 rval;
3cbcb160
DL		 326
327 if (sunxi_mmc_reset_host(host))
328 return -EIO;
329
0314cbd4
CYT		 330 /*
331 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
332 *
333 * TODO: sun9i has a larger FIFO and supports higher trigger values
334 */
3cbcb160 335 mmc_writel(host, REG_FTRGL, 0x20070008);
0314cbd4 336 /* Maximum timeout value */
3cbcb160 337 mmc_writel(host, REG_TMOUT, 0xffffffff);
0314cbd4 338 /* Unmask SDIO interrupt if needed */
3cbcb160 339 mmc_writel(host, REG_IMASK, host->sdio_imask);
0314cbd4 340 /* Clear all pending interrupts */
3cbcb160 341 mmc_writel(host, REG_RINTR, 0xffffffff);
0314cbd4 342 /* Debug register? undocumented */
3cbcb160 343 mmc_writel(host, REG_DBGC, 0xdeb);
0314cbd4 344 /* Enable CEATA support */
3cbcb160 345 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
0314cbd4 346 /* Set DMA descriptor list base address */
3cbcb160
DL		 347 mmc_writel(host, REG_DLBA, host->sg_dma);
348
349 rval = mmc_readl(host, REG_GCTRL);
350 rval |= SDXC_INTERRUPT_ENABLE_BIT;
0314cbd4 351 /* Undocumented, but found in Allwinner code */
3cbcb160
DL		 352 rval &= ~SDXC_ACCESS_DONE_DIRECT;
353 mmc_writel(host, REG_GCTRL, rval);
354
355 return 0;
356}
357
358static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
359 struct mmc_data *data)
360{
361 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
d34712d2 362 dma_addr_t next_desc = host->sg_dma;
86a93317 363 int i, max_len = (1 << host->cfg->idma_des_size_bits);
3cbcb160
DL		 364
365 for (i = 0; i < data->sg_len; i++) {
2dd110b2
MW		 366 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
367 SDXC_IDMAC_DES0_OWN |
368 SDXC_IDMAC_DES0_DIC);
3cbcb160
DL		 369
370 if (data->sg[i].length == max_len)
371 pdes[i].buf_size = 0; /* 0 == max_len */
372 else
2dd110b2 373 pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
3cbcb160 374
d34712d2 375 next_desc += sizeof(struct sunxi_idma_des);
2dd110b2
MW		 376 pdes[i].buf_addr_ptr1 =
377 cpu_to_le32(sg_dma_address(&data->sg[i]));
378 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
3cbcb160
DL		 379 }
380
2dd110b2
MW		 381 pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
382 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
383 SDXC_IDMAC_DES0_ER);
384 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
e8a59049 385 pdes[i - 1].buf_addr_ptr2 = 0;
3cbcb160
DL		 386
387 /*
388 * Avoid the io-store starting the idmac hitting io-mem before the
389 * descriptors hit the main-mem.
390 */
391 wmb();
392}
393
3cbcb160
DL		 394static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
395 struct mmc_data *data)
396{
397 u32 i, dma_len;
398 struct scatterlist *sg;
399
400 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
feeef096 401 mmc_get_dma_dir(data));
3cbcb160
DL		 402 if (dma_len == 0) {
403 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
404 return -ENOMEM;
405 }
406
407 for_each_sg(data->sg, sg, data->sg_len, i) {
408 if (sg->offset & 3 || sg->length & 3) {
409 dev_err(mmc_dev(host->mmc),
410 "unaligned scatterlist: os %x length %d\n",
411 sg->offset, sg->length);
412 return -EINVAL;
413 }
414 }
415
416 return 0;
417}
418
419static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
420 struct mmc_data *data)
421{
422 u32 rval;
423
424 sunxi_mmc_init_idma_des(host, data);
425
426 rval = mmc_readl(host, REG_GCTRL);
427 rval |= SDXC_DMA_ENABLE_BIT;
428 mmc_writel(host, REG_GCTRL, rval);
429 rval |= SDXC_DMA_RESET;
430 mmc_writel(host, REG_GCTRL, rval);
431
432 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
433
434 if (!(data->flags & MMC_DATA_WRITE))
435 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
436
437 mmc_writel(host, REG_DMAC,
438 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
439}
440
441static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
442 struct mmc_request *req)
443{
444 u32 arg, cmd_val, ri;
445 unsigned long expire = jiffies + msecs_to_jiffies(1000);
446
447 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
448 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
449
450 if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
451 cmd_val |= SD_IO_RW_DIRECT;
452 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
453 ((req->cmd->arg >> 28) & 0x7);
454 } else {
455 cmd_val |= MMC_STOP_TRANSMISSION;
456 arg = 0;
457 }
458
459 mmc_writel(host, REG_CARG, arg);
460 mmc_writel(host, REG_CMDR, cmd_val);
461
462 do {
463 ri = mmc_readl(host, REG_RINTR);
464 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
465 time_before(jiffies, expire));
466
467 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
468 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
469 if (req->stop)
470 req->stop->resp[0] = -ETIMEDOUT;
471 } else {
472 if (req->stop)
473 req->stop->resp[0] = mmc_readl(host, REG_RESP0);
474 }
475
476 mmc_writel(host, REG_RINTR, 0xffff);
477}
478
479static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
480{
481 struct mmc_command *cmd = host->mrq->cmd;
482 struct mmc_data *data = host->mrq->data;
483
484 /* For some cmds timeout is normal with sd/mmc cards */
485 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
486 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
487 cmd->opcode == SD_IO_RW_DIRECT))
488 return;
489
bd675698 490 dev_dbg(mmc_dev(host->mmc),
3cbcb160
DL		 491 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
492 host->mmc->index, cmd->opcode,
493 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
494 host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
495 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
496 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
497 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
498 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
499 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
500 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
501 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
502 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
503 );
504}
505
506/* Called in interrupt context! */
507static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
508{
509 struct mmc_request *mrq = host->mrq;
510 struct mmc_data *data = mrq->data;
511 u32 rval;
512
513 mmc_writel(host, REG_IMASK, host->sdio_imask);
514 mmc_writel(host, REG_IDIE, 0);
515
516 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
517 sunxi_mmc_dump_errinfo(host);
518 mrq->cmd->error = -ETIMEDOUT;
519
520 if (data) {
521 data->error = -ETIMEDOUT;
522 host->manual_stop_mrq = mrq;
523 }
524
525 if (mrq->stop)
526 mrq->stop->error = -ETIMEDOUT;
527 } else {
528 if (mrq->cmd->flags & MMC_RSP_136) {
529 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
530 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
531 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
532 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
533 } else {
534 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
535 }
536
537 if (data)
538 data->bytes_xfered = data->blocks * data->blksz;
539 }
540
541 if (data) {
542 mmc_writel(host, REG_IDST, 0x337);
543 mmc_writel(host, REG_DMAC, 0);
544 rval = mmc_readl(host, REG_GCTRL);
545 rval |= SDXC_DMA_RESET;
546 mmc_writel(host, REG_GCTRL, rval);
547 rval &= ~SDXC_DMA_ENABLE_BIT;
548 mmc_writel(host, REG_GCTRL, rval);
549 rval |= SDXC_FIFO_RESET;
550 mmc_writel(host, REG_GCTRL, rval);
551 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
feeef096 552 mmc_get_dma_dir(data));
3cbcb160
DL		 553 }
554
555 mmc_writel(host, REG_RINTR, 0xffff);
556
557 host->mrq = NULL;
558 host->int_sum = 0;
559 host->wait_dma = false;
560
561 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
562}
563
564static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
565{
566 struct sunxi_mmc_host *host = dev_id;
567 struct mmc_request *mrq;
568 u32 msk_int, idma_int;
569 bool finalize = false;
570 bool sdio_int = false;
571 irqreturn_t ret = IRQ_HANDLED;
572
573 spin_lock(&host->lock);
574
575 idma_int = mmc_readl(host, REG_IDST);
576 msk_int = mmc_readl(host, REG_MISTA);
577
578 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
579 host->mrq, msk_int, idma_int);
580
581 mrq = host->mrq;
582 if (mrq) {
583 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
584 host->wait_dma = false;
585
586 host->int_sum |= msk_int;
587
588 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
589 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
590 !(host->int_sum & SDXC_COMMAND_DONE))
591 mmc_writel(host, REG_IMASK,
592 host->sdio_imask | SDXC_COMMAND_DONE);
593 /* Don't wait for dma on error */
594 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
595 finalize = true;
596 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
597 !host->wait_dma)
598 finalize = true;
599 }
600
601 if (msk_int & SDXC_SDIO_INTERRUPT)
602 sdio_int = true;
603
604 mmc_writel(host, REG_RINTR, msk_int);
605 mmc_writel(host, REG_IDST, idma_int);
606
607 if (finalize)
608 ret = sunxi_mmc_finalize_request(host);
609
610 spin_unlock(&host->lock);
611
612 if (finalize && ret == IRQ_HANDLED)
613 mmc_request_done(host->mmc, mrq);
614
615 if (sdio_int)
616 mmc_signal_sdio_irq(host->mmc);
617
618 return ret;
619}
620
621static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
622{
623 struct sunxi_mmc_host *host = dev_id;
624 struct mmc_request *mrq;
625 unsigned long iflags;
626
627 spin_lock_irqsave(&host->lock, iflags);
628 mrq = host->manual_stop_mrq;
629 spin_unlock_irqrestore(&host->lock, iflags);
630
631 if (!mrq) {
632 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
633 return IRQ_HANDLED;
634 }
635
636 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
dd9b3803
DL		 637
638 /*
639 * We will never have more than one outstanding request,
640 * and we do not complete the request until after
641 * we've cleared host->manual_stop_mrq so we do not need to
642 * spin lock this function.
643 * Additionally we have wait states within this function
644 * so having it in a lock is a very bad idea.
645 */
3cbcb160
DL		 646 sunxi_mmc_send_manual_stop(host, mrq);
647
648 spin_lock_irqsave(&host->lock, iflags);
649 host->manual_stop_mrq = NULL;
650 spin_unlock_irqrestore(&host->lock, iflags);
651
652 mmc_request_done(host->mmc, mrq);
653
654 return IRQ_HANDLED;
655}
656
657static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
658{
7bb9c244 659 unsigned long expire = jiffies + msecs_to_jiffies(750);
3cbcb160
DL		 660 u32 rval;
661
43c15e96
MR		 662 dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
663 oclk_en ? "en" : "dis");
664
3cbcb160 665 rval = mmc_readl(host, REG_CLKCR);
16e821e3 666 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
3cbcb160
DL		 667
668 if (oclk_en)
669 rval |= SDXC_CARD_CLOCK_ON;
16e821e3
MR		 670 if (host->cfg->mask_data0)
671 rval |= SDXC_MASK_DATA0;
3cbcb160
DL		 672
673 mmc_writel(host, REG_CLKCR, rval);
674
675 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
676 mmc_writel(host, REG_CMDR, rval);
677
678 do {
679 rval = mmc_readl(host, REG_CMDR);
680 } while (time_before(jiffies, expire) && (rval & SDXC_START));
681
682 /* clear irq status bits set by the command */
683 mmc_writel(host, REG_RINTR,
684 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
685
686 if (rval & SDXC_START) {
687 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
688 return -EIO;
689 }
690
16e821e3
MR		 691 if (host->cfg->mask_data0) {
692 rval = mmc_readl(host, REG_CLKCR);
693 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
694 }
695
3cbcb160
DL		 696 return 0;
697}
698
e1b8dfd1
IZ		 699static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
700{
e1b8dfd1
IZ		 701 if (!host->cfg->can_calibrate)
702 return 0;
703
860fdf89
MR		 704 /*
705 * FIXME:
706 * This is not clear how the calibration is supposed to work
707 * yet. The best rate have been obtained by simply setting the
708 * delay to 0, as Allwinner does in its BSP.
709 *
710 * The only mode that doesn't have such a delay is HS400, that
711 * is in itself a TODO.
712 */
713 writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
e1b8dfd1
IZ		 714
715 return 0;
716}
717
f2cecb70
HG		 718static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
719 struct mmc_ios *ios, u32 rate)
720{
721 int index;
722
a6461134 723 /* clk controller delays not used under new timings mode */
ff39e7f7 724 if (host->use_new_timings)
b465646e
HG		 725 return 0;
726
a6461134
CYT		 727 /* some old controllers don't support delays */
728 if (!host->cfg->clk_delays)
729 return 0;
730
f2cecb70
HG		 731 /* determine delays */
732 if (rate <= 400000) {
733 index = SDXC_CLK_400K;
734 } else if (rate <= 25000000) {
735 index = SDXC_CLK_25M;
736 } else if (rate <= 52000000) {
737 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
738 ios->timing != MMC_TIMING_MMC_DDR52) {
739 index = SDXC_CLK_50M;
740 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
741 index = SDXC_CLK_50M_DDR_8BIT;
742 } else {
743 index = SDXC_CLK_50M_DDR;
744 }
745 } else {
43c15e96 746 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
f2cecb70
HG		 747 return -EINVAL;
748 }
749
750 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
751 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
752
753 return 0;
754}
755
3cbcb160
DL		 756static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
757 struct mmc_ios *ios)
758{
43c15e96 759 struct mmc_host *mmc = host->mmc;
63311bec 760 long rate;
c903a2ae 761 u32 rval, clock = ios->clock, div = 1;
3cbcb160
DL		 762 int ret;
763
39cc281f
MR		 764 ret = sunxi_mmc_oclk_onoff(host, 0);
765 if (ret)
766 return ret;
767
43c15e96
MR		 768 /* Our clock is gated now */
769 mmc->actual_clock = 0;
770
9479074e
MR		 771 if (!ios->clock)
772 return 0;
773
c903a2ae
CYT		 774 /*
775 * Under the old timing mode, 8 bit DDR requires the module
776 * clock to be double the card clock. Under the new timing
777 * mode, all DDR modes require a doubled module clock.
778 *
779 * We currently only support the standard MMC DDR52 mode.
780 * This block should be updated once support for other DDR
781 * modes is added.
782 */
2a7aa63a 783 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
c903a2ae
CYT		 784 (host->use_new_timings ||
785 ios->bus_width == MMC_BUS_WIDTH_8)) {
786 div = 2;
2a7aa63a 787 clock <<= 1;
c903a2ae 788 }
2a7aa63a 789
b939e0b7 790 if (host->use_new_timings && host->cfg->has_timings_switch) {
ff39e7f7
CYT		 791 ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
792 if (ret) {
793 dev_err(mmc_dev(mmc),
794 "error setting new timing mode\n");
795 return ret;
796 }
797 }
798
2a7aa63a 799 rate = clk_round_rate(host->clk_mmc, clock);
63311bec 800 if (rate < 0) {
43c15e96 801 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
63311bec
JFM		 802 clock, rate);
803 return rate;
804 }
43c15e96 805 dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
2a7aa63a 806 clock, rate);
3cbcb160
DL		 807
808 /* setting clock rate */
809 ret = clk_set_rate(host->clk_mmc, rate);
810 if (ret) {
43c15e96 811 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",
3cbcb160
DL		 812 rate, ret);
813 return ret;
814 }
815
c903a2ae 816 /* set internal divider */
3cbcb160
DL		 817 rval = mmc_readl(host, REG_CLKCR);
818 rval &= ~0xff;
c903a2ae 819 rval |= div - 1;
3cbcb160
DL		 820 mmc_writel(host, REG_CLKCR, rval);
821
082bb85f
CYT		 822 /* update card clock rate to account for internal divider */
823 rate /= div;
824
ff39e7f7 825 if (host->use_new_timings) {
26cb2be4
CYT		 826 /* Don't touch the delay bits */
827 rval = mmc_readl(host, REG_SD_NTSR);
828 rval |= SDXC_2X_TIMING_MODE;
829 mmc_writel(host, REG_SD_NTSR, rval);
830 }
9a37e53e 831
082bb85f 832 /* sunxi_mmc_clk_set_phase expects the actual card clock rate */
f2cecb70
HG		 833 ret = sunxi_mmc_clk_set_phase(host, ios, rate);
834 if (ret)
835 return ret;
3cbcb160 836
e1b8dfd1
IZ		 837 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
838 if (ret)
839 return ret;
840
860fdf89
MR		 841 /*
842 * FIXME:
843 *
844 * In HS400 we'll also need to calibrate the data strobe
845 * signal. This should only happen on the MMC2 controller (at
846 * least on the A64).
847 */
e1b8dfd1 848
43c15e96
MR		 849 ret = sunxi_mmc_oclk_onoff(host, 1);
850 if (ret)
851 return ret;
852
853 /* And we just enabled our clock back */
082bb85f 854 mmc->actual_clock = rate;
43c15e96
MR		 855
856 return 0;
3cbcb160
DL		 857}
858
3f6c808e
MR		 859static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host,
860 unsigned char width)
861{
862 switch (width) {
863 case MMC_BUS_WIDTH_1:
864 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
865 break;
866 case MMC_BUS_WIDTH_4:
867 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
868 break;
869 case MMC_BUS_WIDTH_8:
870 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
871 break;
872 }
873}
874
ad04d955
MR		 875static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios)
876{
877 u32 rval;
878
879 /* set ddr mode */
880 rval = mmc_readl(host, REG_GCTRL);
881 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
882 ios->timing == MMC_TIMING_MMC_DDR52)
883 rval |= SDXC_DDR_MODE;
884 else
885 rval &= ~SDXC_DDR_MODE;
886 mmc_writel(host, REG_GCTRL, rval);
887
888 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
889 /* Android code had a usleep_range(50000, 55000); here */
890}
891
e27e1f3d
MR		 892static void sunxi_mmc_card_power(struct sunxi_mmc_host *host,
893 struct mmc_ios *ios)
3cbcb160 894{
e27e1f3d 895 struct mmc_host *mmc = host->mmc;
3cbcb160 896
3cbcb160 897 switch (ios->power_mode) {
3cbcb160 898 case MMC_POWER_UP:
e27e1f3d
MR		 899 dev_dbg(mmc_dev(mmc), "Powering card up\n");
900
424feb59
MR		 901 if (!IS_ERR(mmc->supply.vmmc)) {
902 host->ferror = mmc_regulator_set_ocr(mmc,
903 mmc->supply.vmmc,
904 ios->vdd);
905 if (host->ferror)
906 return;
907 }
3cbcb160 908
f771f6e8
CYT		 909 if (!IS_ERR(mmc->supply.vqmmc)) {
910 host->ferror = regulator_enable(mmc->supply.vqmmc);
911 if (host->ferror) {
912 dev_err(mmc_dev(mmc),
913 "failed to enable vqmmc\n");
914 return;
915 }
916 host->vqmmc_enabled = true;
917 }
3cbcb160
DL		 918 break;
919
920 case MMC_POWER_OFF:
e27e1f3d
MR		 921 dev_dbg(mmc_dev(mmc), "Powering card off\n");
922
424feb59
MR		 923 if (!IS_ERR(mmc->supply.vmmc))
924 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
925
f771f6e8
CYT		 926 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
927 regulator_disable(mmc->supply.vqmmc);
e27e1f3d 928
f771f6e8 929 host->vqmmc_enabled = false;
3cbcb160 930 break;
e27e1f3d
MR		 931
932 default:
933 dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n");
934 break;
3cbcb160 935 }
e27e1f3d
MR		 936}
937
938static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
939{
940 struct sunxi_mmc_host *host = mmc_priv(mmc);
941
e27e1f3d 942 sunxi_mmc_card_power(host, ios);
3f6c808e 943 sunxi_mmc_set_bus_width(host, ios->bus_width);
ad04d955 944 sunxi_mmc_set_clk(host, ios);
3cbcb160
DL		 945}
946
f771f6e8
CYT		 947static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
948{
949 /* vqmmc regulator is available */
950 if (!IS_ERR(mmc->supply.vqmmc))
951 return mmc_regulator_set_vqmmc(mmc, ios);
952
953 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
954 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
955 return 0;
956
957 return -EINVAL;
958}
959
3cbcb160
DL		 960static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
961{
962 struct sunxi_mmc_host *host = mmc_priv(mmc);
963 unsigned long flags;
964 u32 imask;
965
9a8e1e8c
MR		 966 if (enable)
967 pm_runtime_get_noresume(host->dev);
968
3cbcb160
DL		 969 spin_lock_irqsave(&host->lock, flags);
970
971 imask = mmc_readl(host, REG_IMASK);
972 if (enable) {
973 host->sdio_imask = SDXC_SDIO_INTERRUPT;
974 imask |= SDXC_SDIO_INTERRUPT;
975 } else {
976 host->sdio_imask = 0;
977 imask &= ~SDXC_SDIO_INTERRUPT;
978 }
979 mmc_writel(host, REG_IMASK, imask);
980 spin_unlock_irqrestore(&host->lock, flags);
9a8e1e8c
MR		 981
982 if (!enable)
983 pm_runtime_put_noidle(host->mmc->parent);
3cbcb160
DL		 984}
985
986static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
987{
988 struct sunxi_mmc_host *host = mmc_priv(mmc);
989 mmc_writel(host, REG_HWRST, 0);
990 udelay(10);
991 mmc_writel(host, REG_HWRST, 1);
992 udelay(300);
993}
994
995static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
996{
997 struct sunxi_mmc_host *host = mmc_priv(mmc);
998 struct mmc_command *cmd = mrq->cmd;
999 struct mmc_data *data = mrq->data;
1000 unsigned long iflags;
1001 u32 imask = SDXC_INTERRUPT_ERROR_BIT;
1002 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
dd9b3803 1003 bool wait_dma = host->wait_dma;
3cbcb160
DL		 1004 int ret;
1005
1006 /* Check for set_ios errors (should never happen) */
1007 if (host->ferror) {
1008 mrq->cmd->error = host->ferror;
1009 mmc_request_done(mmc, mrq);
1010 return;
1011 }
1012
1013 if (data) {
1014 ret = sunxi_mmc_map_dma(host, data);
1015 if (ret < 0) {
1016 dev_err(mmc_dev(mmc), "map DMA failed\n");
1017 cmd->error = ret;
1018 data->error = ret;
1019 mmc_request_done(mmc, mrq);
1020 return;
1021 }
1022 }
1023
1024 if (cmd->opcode == MMC_GO_IDLE_STATE) {
1025 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
1026 imask |= SDXC_COMMAND_DONE;
1027 }
1028
1029 if (cmd->flags & MMC_RSP_PRESENT) {
1030 cmd_val |= SDXC_RESP_EXPIRE;
1031 if (cmd->flags & MMC_RSP_136)
1032 cmd_val |= SDXC_LONG_RESPONSE;
1033 if (cmd->flags & MMC_RSP_CRC)
1034 cmd_val |= SDXC_CHECK_RESPONSE_CRC;
1035
1036 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
1037 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
3cbcb160
DL		 1038
1039 if (cmd->data->stop) {
1040 imask |= SDXC_AUTO_COMMAND_DONE;
1041 cmd_val |= SDXC_SEND_AUTO_STOP;
1042 } else {
1043 imask |= SDXC_DATA_OVER;
1044 }
1045
1046 if (cmd->data->flags & MMC_DATA_WRITE)
1047 cmd_val |= SDXC_WRITE;
1048 else
dd9b3803 1049 wait_dma = true;
3cbcb160
DL		 1050 } else {
1051 imask |= SDXC_COMMAND_DONE;
1052 }
1053 } else {
1054 imask |= SDXC_COMMAND_DONE;
1055 }
1056
1057 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
1058 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
1059 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
1060
1061 spin_lock_irqsave(&host->lock, iflags);
1062
1063 if (host->mrq || host->manual_stop_mrq) {
1064 spin_unlock_irqrestore(&host->lock, iflags);
1065
1066 if (data)
1067 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
feeef096 1068 mmc_get_dma_dir(data));
3cbcb160
DL		 1069
1070 dev_err(mmc_dev(mmc), "request already pending\n");
1071 mrq->cmd->error = -EBUSY;
1072 mmc_request_done(mmc, mrq);
1073 return;
1074 }
1075
1076 if (data) {
1077 mmc_writel(host, REG_BLKSZ, data->blksz);
1078 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
1079 sunxi_mmc_start_dma(host, data);
1080 }
1081
1082 host->mrq = mrq;
dd9b3803 1083 host->wait_dma = wait_dma;
3cbcb160
DL		 1084 mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
1085 mmc_writel(host, REG_CARG, cmd->arg);
1086 mmc_writel(host, REG_CMDR, cmd_val);
1087
1088 spin_unlock_irqrestore(&host->lock, iflags);
1089}
1090
c1590dd8
HG		 1091static int sunxi_mmc_card_busy(struct mmc_host *mmc)
1092{
1093 struct sunxi_mmc_host *host = mmc_priv(mmc);
1094
1095 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
1096}
1097
1f8029c3 1098static const struct mmc_host_ops sunxi_mmc_ops = {
3cbcb160
DL		 1099 .request = sunxi_mmc_request,
1100 .set_ios = sunxi_mmc_set_ios,
1101 .get_ro = mmc_gpio_get_ro,
1102 .get_cd = mmc_gpio_get_cd,
1103 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
f771f6e8 1104 .start_signal_voltage_switch = sunxi_mmc_volt_switch,
3cbcb160 1105 .hw_reset = sunxi_mmc_hw_reset,
c1590dd8 1106 .card_busy = sunxi_mmc_card_busy,
3cbcb160
DL		 1107};
1108
51424b28
HG		 1109static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
1110 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1111 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1112 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
1113 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
2a7aa63a
CYT		 1114 /* Value from A83T "new timing mode". Works but might not be right. */
1115 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
51424b28
HG		 1116};
1117
1118static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
1119 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1120 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1121 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
0175249e
CYT		 1122 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
1123 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
51424b28
HG		 1124};
1125
86a93317
HG		 1126static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
1127 .idma_des_size_bits = 13,
b465646e 1128 .clk_delays = NULL,
e1b8dfd1 1129 .can_calibrate = false,
86a93317
HG		 1130};
1131
1132static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
b465646e
HG		 1133 .idma_des_size_bits = 16,
1134 .clk_delays = NULL,
e1b8dfd1 1135 .can_calibrate = false,
b465646e
HG		 1136};
1137
1138static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
86a93317
HG		 1139 .idma_des_size_bits = 16,
1140 .clk_delays = sunxi_mmc_clk_delays,
e1b8dfd1 1141 .can_calibrate = false,
86a93317
HG		 1142};
1143
ac98caef
CYT		 1144static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = {
1145 .idma_des_size_bits = 16,
1146 .clk_delays = sunxi_mmc_clk_delays,
1147 .can_calibrate = false,
1148 .has_timings_switch = true,
1149};
1150
86a93317
HG		 1151static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
1152 .idma_des_size_bits = 16,
1153 .clk_delays = sun9i_mmc_clk_delays,
e1b8dfd1
IZ		 1154 .can_calibrate = false,
1155};
1156
1157static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
1158 .idma_des_size_bits = 16,
1159 .clk_delays = NULL,
1160 .can_calibrate = true,
16e821e3 1161 .mask_data0 = true,
9a37e53e 1162 .needs_new_timings = true,
86a93317
HG		 1163};
1164
4fb3ce07
MR		 1165static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
1166 .idma_des_size_bits = 13,
1167 .clk_delays = NULL,
1168 .can_calibrate = true,
1169};
1170
86a93317
HG		 1171static const struct of_device_id sunxi_mmc_of_match[] = {
1172 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
1173 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
b465646e 1174 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
ac98caef 1175 { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg },
86a93317 1176 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
e1b8dfd1 1177 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
4fb3ce07 1178 { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
86a93317
HG		 1179 { /* sentinel */ }
1180};
1181MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
1182
774c0103
MR		 1183static int sunxi_mmc_enable(struct sunxi_mmc_host *host)
1184{
1185 int ret;
1186
d8181941
MR		 1187 if (!IS_ERR(host->reset)) {
1188 ret = reset_control_reset(host->reset);
1189 if (ret) {
1190 dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n",
1191 ret);
1192 return ret;
1193 }
1194 }
1195
774c0103
MR		 1196 ret = clk_prepare_enable(host->clk_ahb);
1197 if (ret) {
d8181941
MR		 1198 dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret);
1199 goto error_assert_reset;
774c0103
MR		 1200 }
1201
1202 ret = clk_prepare_enable(host->clk_mmc);
1203 if (ret) {
1204 dev_err(host->dev, "Enable mmc clk err %d\n", ret);
1205 goto error_disable_clk_ahb;
1206 }
1207
1208 ret = clk_prepare_enable(host->clk_output);
1209 if (ret) {
1210 dev_err(host->dev, "Enable output clk err %d\n", ret);
1211 goto error_disable_clk_mmc;
1212 }
1213
1214 ret = clk_prepare_enable(host->clk_sample);
1215 if (ret) {
1216 dev_err(host->dev, "Enable sample clk err %d\n", ret);
1217 goto error_disable_clk_output;
1218 }
1219
774c0103
MR		 1220 /*
1221 * Sometimes the controller asserts the irq on boot for some reason,
1222 * make sure the controller is in a sane state before enabling irqs.
1223 */
1224 ret = sunxi_mmc_reset_host(host);
1225 if (ret)
d8181941 1226 goto error_disable_clk_sample;
774c0103
MR		 1227
1228 return 0;
1229
774c0103
MR		 1230error_disable_clk_sample:
1231 clk_disable_unprepare(host->clk_sample);
1232error_disable_clk_output:
1233 clk_disable_unprepare(host->clk_output);
1234error_disable_clk_mmc:
1235 clk_disable_unprepare(host->clk_mmc);
1236error_disable_clk_ahb:
1237 clk_disable_unprepare(host->clk_ahb);
d8181941
MR		 1238error_assert_reset:
1239 if (!IS_ERR(host->reset))
1240 reset_control_assert(host->reset);
774c0103
MR		 1241 return ret;
1242}
1243
1244static void sunxi_mmc_disable(struct sunxi_mmc_host *host)
1245{
1246 sunxi_mmc_reset_host(host);
1247
774c0103
MR		 1248 clk_disable_unprepare(host->clk_sample);
1249 clk_disable_unprepare(host->clk_output);
1250 clk_disable_unprepare(host->clk_mmc);
1251 clk_disable_unprepare(host->clk_ahb);
d8181941
MR		 1252
1253 if (!IS_ERR(host->reset))
1254 reset_control_assert(host->reset);
774c0103
MR		 1255}
1256
3cbcb160
DL		 1257static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
1258 struct platform_device *pdev)
1259{
3cbcb160
DL		 1260 int ret;
1261
86a93317
HG		 1262 host->cfg = of_device_get_match_data(&pdev->dev);
1263 if (!host->cfg)
1264 return -EINVAL;
51424b28 1265
3cbcb160 1266 ret = mmc_regulator_get_supply(host->mmc);
aaab3c46 1267 if (ret)
3cbcb160 1268 return ret;
3cbcb160
DL		 1269
1270 host->reg_base = devm_ioremap_resource(&pdev->dev,
1271 platform_get_resource(pdev, IORESOURCE_MEM, 0));
1272 if (IS_ERR(host->reg_base))
1273 return PTR_ERR(host->reg_base);
1274
1275 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1276 if (IS_ERR(host->clk_ahb)) {
1277 dev_err(&pdev->dev, "Could not get ahb clock\n");
1278 return PTR_ERR(host->clk_ahb);
1279 }
1280
1281 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
1282 if (IS_ERR(host->clk_mmc)) {
1283 dev_err(&pdev->dev, "Could not get mmc clock\n");
1284 return PTR_ERR(host->clk_mmc);
1285 }
1286
b465646e
HG		 1287 if (host->cfg->clk_delays) {
1288 host->clk_output = devm_clk_get(&pdev->dev, "output");
1289 if (IS_ERR(host->clk_output)) {
1290 dev_err(&pdev->dev, "Could not get output clock\n");
1291 return PTR_ERR(host->clk_output);
1292 }
6c09bb85 1293
b465646e
HG		 1294 host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1295 if (IS_ERR(host->clk_sample)) {
1296 dev_err(&pdev->dev, "Could not get sample clock\n");
1297 return PTR_ERR(host->clk_sample);
1298 }
6c09bb85
MR		 1299 }
1300
5e40ddac
PZ		 1301 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1302 "ahb");
9e71c589
CYT		 1303 if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1304 return PTR_ERR(host->reset);
3cbcb160 1305
774c0103 1306 ret = sunxi_mmc_enable(host);
3cbcb160 1307 if (ret)
774c0103 1308 return ret;
3cbcb160
DL		 1309
1310 host->irq = platform_get_irq(pdev, 0);
2408a085
AY		 1311 if (host->irq <= 0) {
1312 ret = -EINVAL;
774c0103 1313 goto error_disable_mmc;
2408a085
AY		 1314 }
1315
3cbcb160
DL		 1316 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1317 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1318
774c0103
MR		 1319error_disable_mmc:
1320 sunxi_mmc_disable(host);
3cbcb160
DL		 1321 return ret;
1322}
1323
1324static int sunxi_mmc_probe(struct platform_device *pdev)
1325{
1326 struct sunxi_mmc_host *host;
1327 struct mmc_host *mmc;
1328 int ret;
1329
1330 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1331 if (!mmc) {
1332 dev_err(&pdev->dev, "mmc alloc host failed\n");
1333 return -ENOMEM;
1334 }
cb1214d2 1335 platform_set_drvdata(pdev, mmc);
3cbcb160
DL		 1336
1337 host = mmc_priv(mmc);
774c0103 1338 host->dev = &pdev->dev;
3cbcb160
DL		 1339 host->mmc = mmc;
1340 spin_lock_init(&host->lock);
1341
1342 ret = sunxi_mmc_resource_request(host, pdev);
1343 if (ret)
1344 goto error_free_host;
1345
1346 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1347 &host->sg_dma, GFP_KERNEL);
1348 if (!host->sg_cpu) {
1349 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1350 ret = -ENOMEM;
1351 goto error_free_host;
1352 }
1353
ff39e7f7
CYT		 1354 if (host->cfg->has_timings_switch) {
1355 /*
1356 * Supports both old and new timing modes.
1357 * Try setting the clk to new timing mode.
1358 */
1359 sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
1360
1361 /* And check the result */
1362 ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc);
1363 if (ret < 0) {
1364 /*
1365 * For whatever reason we were not able to get
1366 * the current active mode. Default to old mode.
1367 */
1368 dev_warn(&pdev->dev, "MMC clk timing mode unknown\n");
1369 host->use_new_timings = false;
1370 } else {
1371 host->use_new_timings = !!ret;
1372 }
1373 } else if (host->cfg->needs_new_timings) {
1374 /* Supports new timing mode only */
1375 host->use_new_timings = true;
1376 }
1377
3cbcb160
DL		 1378 mmc->ops = &sunxi_mmc_ops;
1379 mmc->max_blk_count = 8192;
1380 mmc->max_blk_size = 4096;
1381 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
86a93317 1382 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);
3cbcb160 1383 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
2dcb305a 1384 /* 400kHz ~ 52MHz */
3cbcb160 1385 mmc->f_min = 400000;
2dcb305a 1386 mmc->f_max = 52000000;
3df01a93 1387 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
a4101dcb 1388 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
3cbcb160 1389
c903a2ae 1390 if (host->cfg->clk_delays || host->use_new_timings)
88023d43 1391 mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
b465646e 1392
3cbcb160 1393 ret = mmc_of_parse(mmc);
eef797ac
MR		 1394 if (ret)
1395 goto error_free_dma;
1396
1397 ret = sunxi_mmc_init_host(host);
3cbcb160
DL		 1398 if (ret)
1399 goto error_free_dma;
1400
9a8e1e8c
MR		 1401 pm_runtime_set_active(&pdev->dev);
1402 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1403 pm_runtime_use_autosuspend(&pdev->dev);
1404 pm_runtime_enable(&pdev->dev);
1405
3cbcb160
DL		 1406 ret = mmc_add_host(mmc);
1407 if (ret)
1408 goto error_free_dma;
1409
1410 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
3cbcb160
DL		 1411 return 0;
1412
1413error_free_dma:
1414 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1415error_free_host:
1416 mmc_free_host(mmc);
1417 return ret;
1418}
1419
1420static int sunxi_mmc_remove(struct platform_device *pdev)
1421{
1422 struct mmc_host *mmc = platform_get_drvdata(pdev);
1423 struct sunxi_mmc_host *host = mmc_priv(mmc);
1424
1425 mmc_remove_host(mmc);
9a8e1e8c 1426 pm_runtime_force_suspend(&pdev->dev);
3cbcb160 1427 disable_irq(host->irq);
774c0103 1428 sunxi_mmc_disable(host);
3cbcb160
DL		 1429 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1430 mmc_free_host(mmc);
1431
1432 return 0;
1433}
1434
af6b8ff4
UH		 1435#ifdef CONFIG_PM
1436static int sunxi_mmc_runtime_resume(struct device *dev)
9a8e1e8c
MR		 1437{
1438 struct mmc_host *mmc = dev_get_drvdata(dev);
1439 struct sunxi_mmc_host *host = mmc_priv(mmc);
1440 int ret;
1441
1442 ret = sunxi_mmc_enable(host);
1443 if (ret)
1444 return ret;
1445
1446 sunxi_mmc_init_host(host);
1447 sunxi_mmc_set_bus_width(host, mmc->ios.bus_width);
1448 sunxi_mmc_set_clk(host, &mmc->ios);
b8ba3578 1449 enable_irq(host->irq);
9a8e1e8c
MR		 1450
1451 return 0;
1452}
1453
af6b8ff4 1454static int sunxi_mmc_runtime_suspend(struct device *dev)
9a8e1e8c
MR		 1455{
1456 struct mmc_host *mmc = dev_get_drvdata(dev);
1457 struct sunxi_mmc_host *host = mmc_priv(mmc);
1458
b8ba3578
SM		 1459 /*
1460 * When clocks are off, it's possible receiving
1461 * fake interrupts, which will stall the system.
1462 * Disabling the irq will prevent this.
1463 */
1464 disable_irq(host->irq);
9a8e1e8c
MR		 1465 sunxi_mmc_reset_host(host);
1466 sunxi_mmc_disable(host);
1467
1468 return 0;
1469}
af6b8ff4 1470#endif
9a8e1e8c
MR		 1471
1472static const struct dev_pm_ops sunxi_mmc_pm_ops = {
1473 SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend,
1474 sunxi_mmc_runtime_resume,
1475 NULL)
1476};
1477
3cbcb160
DL		 1478static struct platform_driver sunxi_mmc_driver = {
1479 .driver = {
1480 .name = "sunxi-mmc",
3cbcb160 1481 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
9a8e1e8c 1482 .pm = &sunxi_mmc_pm_ops,
3cbcb160
DL		 1483 },
1484 .probe = sunxi_mmc_probe,
1485 .remove = sunxi_mmc_remove,
1486};
1487module_platform_driver(sunxi_mmc_driver);
1488
1489MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1490MODULE_LICENSE("GPL v2");
1907e386 1491MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>");
3cbcb160 1492MODULE_ALIAS("platform:sunxi-mmc");
Linux 6.x block layer and io_uring tree(s)