Commit | Line | Data |
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2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
d129bceb | 2 | /* |
70f10482 | 3 | * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver |
d129bceb | 4 | * |
1978fda8 GC |
5 | * Header file for Host Controller registers and I/O accessors. |
6 | * | |
b69c9058 | 7 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb | 8 | */ |
1978fda8 GC |
9 | #ifndef __SDHCI_HW_H |
10 | #define __SDHCI_HW_H | |
d129bceb | 11 | |
fa091010 | 12 | #include <linux/bits.h> |
0c7ad106 | 13 | #include <linux/scatterlist.h> |
4e4141a5 AV |
14 | #include <linux/compiler.h> |
15 | #include <linux/types.h> | |
16 | #include <linux/io.h> | |
210583f4 | 17 | #include <linux/leds.h> |
b8789ec4 | 18 | #include <linux/interrupt.h> |
0c7ad106 | 19 | |
83f13cc9 | 20 | #include <linux/mmc/host.h> |
1978fda8 | 21 | |
d129bceb PO |
22 | /* |
23 | * Controller registers | |
24 | */ | |
25 | ||
26 | #define SDHCI_DMA_ADDRESS 0x00 | |
8edf6371 | 27 | #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS |
e65953d4 | 28 | #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS |
d129bceb PO |
29 | |
30 | #define SDHCI_BLOCK_SIZE 0x04 | |
bab76961 | 31 | #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) |
d129bceb PO |
32 | |
33 | #define SDHCI_BLOCK_COUNT 0x06 | |
34 | ||
35 | #define SDHCI_ARGUMENT 0x08 | |
36 | ||
37 | #define SDHCI_TRANSFER_MODE 0x0C | |
38 | #define SDHCI_TRNS_DMA 0x01 | |
39 | #define SDHCI_TRNS_BLK_CNT_EN 0x02 | |
e89d456f | 40 | #define SDHCI_TRNS_AUTO_CMD12 0x04 |
8edf6371 | 41 | #define SDHCI_TRNS_AUTO_CMD23 0x08 |
427b6514 | 42 | #define SDHCI_TRNS_AUTO_SEL 0x0C |
d129bceb PO |
43 | #define SDHCI_TRNS_READ 0x10 |
44 | #define SDHCI_TRNS_MULTI 0x20 | |
45 | ||
46 | #define SDHCI_COMMAND 0x0E | |
47 | #define SDHCI_CMD_RESP_MASK 0x03 | |
48 | #define SDHCI_CMD_CRC 0x08 | |
49 | #define SDHCI_CMD_INDEX 0x10 | |
50 | #define SDHCI_CMD_DATA 0x20 | |
574e3f56 | 51 | #define SDHCI_CMD_ABORTCMD 0xC0 |
d129bceb PO |
52 | |
53 | #define SDHCI_CMD_RESP_NONE 0x00 | |
54 | #define SDHCI_CMD_RESP_LONG 0x01 | |
55 | #define SDHCI_CMD_RESP_SHORT 0x02 | |
56 | #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 | |
57 | ||
58 | #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) | |
22113efd | 59 | #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) |
d129bceb PO |
60 | |
61 | #define SDHCI_RESPONSE 0x10 | |
62 | ||
63 | #define SDHCI_BUFFER 0x20 | |
64 | ||
65 | #define SDHCI_PRESENT_STATE 0x24 | |
66 | #define SDHCI_CMD_INHIBIT 0x00000001 | |
67 | #define SDHCI_DATA_INHIBIT 0x00000002 | |
68 | #define SDHCI_DOING_WRITE 0x00000100 | |
69 | #define SDHCI_DOING_READ 0x00000200 | |
70 | #define SDHCI_SPACE_AVAILABLE 0x00000400 | |
71 | #define SDHCI_DATA_AVAILABLE 0x00000800 | |
72 | #define SDHCI_CARD_PRESENT 0x00010000 | |
69d91ed1 EZW |
73 | #define SDHCI_CARD_PRES_SHIFT 16 |
74 | #define SDHCI_CD_STABLE 0x00020000 | |
75 | #define SDHCI_CD_LVL 0x00040000 | |
76 | #define SDHCI_CD_LVL_SHIFT 18 | |
d129bceb | 77 | #define SDHCI_WRITE_PROTECT 0x00080000 |
f2119df6 AN |
78 | #define SDHCI_DATA_LVL_MASK 0x00F00000 |
79 | #define SDHCI_DATA_LVL_SHIFT 20 | |
7756a96d | 80 | #define SDHCI_DATA_0_LVL_MASK 0x00100000 |
b0921d5c | 81 | #define SDHCI_CMD_LVL 0x01000000 |
d129bceb | 82 | |
d6d50a15 | 83 | #define SDHCI_HOST_CONTROL 0x28 |
d129bceb PO |
84 | #define SDHCI_CTRL_LED 0x01 |
85 | #define SDHCI_CTRL_4BITBUS 0x02 | |
077df884 | 86 | #define SDHCI_CTRL_HISPD 0x04 |
2134a922 PO |
87 | #define SDHCI_CTRL_DMA_MASK 0x18 |
88 | #define SDHCI_CTRL_SDMA 0x00 | |
89 | #define SDHCI_CTRL_ADMA1 0x08 | |
90 | #define SDHCI_CTRL_ADMA32 0x10 | |
91 | #define SDHCI_CTRL_ADMA64 0x18 | |
4c4faff6 | 92 | #define SDHCI_CTRL_ADMA3 0x18 |
6e8e1acd | 93 | #define SDHCI_CTRL_8BITBUS 0x20 |
3794c542 ZB |
94 | #define SDHCI_CTRL_CDTEST_INS 0x40 |
95 | #define SDHCI_CTRL_CDTEST_EN 0x80 | |
d129bceb PO |
96 | |
97 | #define SDHCI_POWER_CONTROL 0x29 | |
146ad66e PO |
98 | #define SDHCI_POWER_ON 0x01 |
99 | #define SDHCI_POWER_180 0x0A | |
100 | #define SDHCI_POWER_300 0x0C | |
101 | #define SDHCI_POWER_330 0x0E | |
d129bceb PO |
102 | |
103 | #define SDHCI_BLOCK_GAP_CONTROL 0x2A | |
104 | ||
2df3b71b | 105 | #define SDHCI_WAKE_UP_CONTROL 0x2B |
5f619704 DD |
106 | #define SDHCI_WAKE_ON_INT 0x01 |
107 | #define SDHCI_WAKE_ON_INSERT 0x02 | |
108 | #define SDHCI_WAKE_ON_REMOVE 0x04 | |
d129bceb PO |
109 | |
110 | #define SDHCI_CLOCK_CONTROL 0x2C | |
111 | #define SDHCI_DIVIDER_SHIFT 8 | |
85105c53 ZG |
112 | #define SDHCI_DIVIDER_HI_SHIFT 6 |
113 | #define SDHCI_DIV_MASK 0xFF | |
114 | #define SDHCI_DIV_MASK_LEN 8 | |
115 | #define SDHCI_DIV_HI_MASK 0x300 | |
c3ed3877 | 116 | #define SDHCI_PROG_CLOCK_MODE 0x0020 |
d129bceb | 117 | #define SDHCI_CLOCK_CARD_EN 0x0004 |
1beabbdb | 118 | #define SDHCI_CLOCK_PLL_EN 0x0008 |
d129bceb PO |
119 | #define SDHCI_CLOCK_INT_STABLE 0x0002 |
120 | #define SDHCI_CLOCK_INT_EN 0x0001 | |
121 | ||
122 | #define SDHCI_TIMEOUT_CONTROL 0x2E | |
123 | ||
124 | #define SDHCI_SOFTWARE_RESET 0x2F | |
125 | #define SDHCI_RESET_ALL 0x01 | |
126 | #define SDHCI_RESET_CMD 0x02 | |
127 | #define SDHCI_RESET_DATA 0x04 | |
128 | ||
129 | #define SDHCI_INT_STATUS 0x30 | |
130 | #define SDHCI_INT_ENABLE 0x34 | |
131 | #define SDHCI_SIGNAL_ENABLE 0x38 | |
132 | #define SDHCI_INT_RESPONSE 0x00000001 | |
133 | #define SDHCI_INT_DATA_END 0x00000002 | |
a4071fbb | 134 | #define SDHCI_INT_BLK_GAP 0x00000004 |
d129bceb | 135 | #define SDHCI_INT_DMA_END 0x00000008 |
a406f5a3 PO |
136 | #define SDHCI_INT_SPACE_AVAIL 0x00000010 |
137 | #define SDHCI_INT_DATA_AVAIL 0x00000020 | |
d129bceb PO |
138 | #define SDHCI_INT_CARD_INSERT 0x00000040 |
139 | #define SDHCI_INT_CARD_REMOVE 0x00000080 | |
140 | #define SDHCI_INT_CARD_INT 0x00000100 | |
f37b20eb | 141 | #define SDHCI_INT_RETUNE 0x00001000 |
f12e39db | 142 | #define SDHCI_INT_CQE 0x00004000 |
964f9ce2 | 143 | #define SDHCI_INT_ERROR 0x00008000 |
d129bceb PO |
144 | #define SDHCI_INT_TIMEOUT 0x00010000 |
145 | #define SDHCI_INT_CRC 0x00020000 | |
146 | #define SDHCI_INT_END_BIT 0x00040000 | |
147 | #define SDHCI_INT_INDEX 0x00080000 | |
148 | #define SDHCI_INT_DATA_TIMEOUT 0x00100000 | |
149 | #define SDHCI_INT_DATA_CRC 0x00200000 | |
150 | #define SDHCI_INT_DATA_END_BIT 0x00400000 | |
151 | #define SDHCI_INT_BUS_POWER 0x00800000 | |
869f8a69 | 152 | #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 |
2134a922 | 153 | #define SDHCI_INT_ADMA_ERROR 0x02000000 |
d129bceb PO |
154 | |
155 | #define SDHCI_INT_NORMAL_MASK 0x00007FFF | |
156 | #define SDHCI_INT_ERROR_MASK 0xFFFF8000 | |
157 | ||
158 | #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ | |
af849c86 AH |
159 | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ |
160 | SDHCI_INT_AUTO_CMD_ERR) | |
d129bceb | 161 | #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ |
a406f5a3 | 162 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ |
d129bceb | 163 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ |
a4071fbb HZ |
164 | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \ |
165 | SDHCI_INT_BLK_GAP) | |
7260cf5e | 166 | #define SDHCI_INT_ALL_MASK ((unsigned int)-1) |
d129bceb | 167 | |
f12e39db AH |
168 | #define SDHCI_CQE_INT_ERR_MASK ( \ |
169 | SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \ | |
170 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \ | |
171 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) | |
172 | ||
173 | #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) | |
174 | ||
869f8a69 | 175 | #define SDHCI_AUTO_CMD_STATUS 0x3C |
af849c86 AH |
176 | #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002 |
177 | #define SDHCI_AUTO_CMD_CRC 0x00000004 | |
178 | #define SDHCI_AUTO_CMD_END_BIT 0x00000008 | |
179 | #define SDHCI_AUTO_CMD_INDEX 0x00000010 | |
d129bceb | 180 | |
f2119df6 | 181 | #define SDHCI_HOST_CONTROL2 0x3E |
49c468fc AN |
182 | #define SDHCI_CTRL_UHS_MASK 0x0007 |
183 | #define SDHCI_CTRL_UHS_SDR12 0x0000 | |
184 | #define SDHCI_CTRL_UHS_SDR25 0x0001 | |
185 | #define SDHCI_CTRL_UHS_SDR50 0x0002 | |
186 | #define SDHCI_CTRL_UHS_SDR104 0x0003 | |
187 | #define SDHCI_CTRL_UHS_DDR50 0x0004 | |
e9fb05d5 | 188 | #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ |
f2119df6 | 189 | #define SDHCI_CTRL_VDD_180 0x0008 |
d6d50a15 AN |
190 | #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 |
191 | #define SDHCI_CTRL_DRV_TYPE_B 0x0000 | |
192 | #define SDHCI_CTRL_DRV_TYPE_A 0x0010 | |
193 | #define SDHCI_CTRL_DRV_TYPE_C 0x0020 | |
194 | #define SDHCI_CTRL_DRV_TYPE_D 0x0030 | |
b513ea25 AN |
195 | #define SDHCI_CTRL_EXEC_TUNING 0x0040 |
196 | #define SDHCI_CTRL_TUNED_CLK 0x0080 | |
427b6514 | 197 | #define SDHCI_CMD23_ENABLE 0x0800 |
b3f80b43 | 198 | #define SDHCI_CTRL_V4_MODE 0x1000 |
685e444b | 199 | #define SDHCI_CTRL_64BIT_ADDR 0x2000 |
d6d50a15 | 200 | #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 |
d129bceb PO |
201 | |
202 | #define SDHCI_CAPABILITIES 0x40 | |
a8e809ec | 203 | #define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0) |
1c8cde92 | 204 | #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 |
a8e809ec MY |
205 | #define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8) |
206 | #define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8) | |
1d676e02 PO |
207 | #define SDHCI_MAX_BLOCK_MASK 0x00030000 |
208 | #define SDHCI_MAX_BLOCK_SHIFT 16 | |
15ec4461 | 209 | #define SDHCI_CAN_DO_8BIT 0x00040000 |
2134a922 PO |
210 | #define SDHCI_CAN_DO_ADMA2 0x00080000 |
211 | #define SDHCI_CAN_DO_ADMA1 0x00100000 | |
077df884 | 212 | #define SDHCI_CAN_DO_HISPD 0x00200000 |
a13abc7b | 213 | #define SDHCI_CAN_DO_SDMA 0x00400000 |
e71d4b81 | 214 | #define SDHCI_CAN_DO_SUSPEND 0x00800000 |
146ad66e PO |
215 | #define SDHCI_CAN_VDD_330 0x01000000 |
216 | #define SDHCI_CAN_VDD_300 0x02000000 | |
217 | #define SDHCI_CAN_VDD_180 0x04000000 | |
685e444b | 218 | #define SDHCI_CAN_64BIT_V4 0x08000000 |
2134a922 | 219 | #define SDHCI_CAN_64BIT 0x10000000 |
d129bceb | 220 | |
2941e4ca | 221 | #define SDHCI_CAPABILITIES_1 0x44 |
f2119df6 AN |
222 | #define SDHCI_SUPPORT_SDR50 0x00000001 |
223 | #define SDHCI_SUPPORT_SDR104 0x00000002 | |
224 | #define SDHCI_SUPPORT_DDR50 0x00000004 | |
d6d50a15 AN |
225 | #define SDHCI_DRIVER_TYPE_A 0x00000010 |
226 | #define SDHCI_DRIVER_TYPE_C 0x00000020 | |
227 | #define SDHCI_DRIVER_TYPE_D 0x00000040 | |
a8e809ec | 228 | #define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8) |
cf2b5eea | 229 | #define SDHCI_USE_SDR50_TUNING 0x00002000 |
a8e809ec MY |
230 | #define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14) |
231 | #define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16) | |
4c4faff6 | 232 | #define SDHCI_CAN_DO_ADMA3 0x08000000 |
e9fb05d5 | 233 | #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ |
f2119df6 | 234 | |
f2119df6 | 235 | #define SDHCI_MAX_CURRENT 0x48 |
bad37e1a | 236 | #define SDHCI_MAX_CURRENT_LIMIT 0xFF |
f2119df6 AN |
237 | #define SDHCI_MAX_CURRENT_330_MASK 0x0000FF |
238 | #define SDHCI_MAX_CURRENT_330_SHIFT 0 | |
239 | #define SDHCI_MAX_CURRENT_300_MASK 0x00FF00 | |
240 | #define SDHCI_MAX_CURRENT_300_SHIFT 8 | |
241 | #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 | |
242 | #define SDHCI_MAX_CURRENT_180_SHIFT 16 | |
243 | #define SDHCI_MAX_CURRENT_MULTIPLIER 4 | |
d129bceb PO |
244 | |
245 | /* 4C-4F reserved for more max current */ | |
246 | ||
2134a922 PO |
247 | #define SDHCI_SET_ACMD12_ERROR 0x50 |
248 | #define SDHCI_SET_INT_ERROR 0x52 | |
249 | ||
250 | #define SDHCI_ADMA_ERROR 0x54 | |
251 | ||
252 | /* 55-57 reserved */ | |
253 | ||
254 | #define SDHCI_ADMA_ADDRESS 0x58 | |
e57a5f61 | 255 | #define SDHCI_ADMA_ADDRESS_HI 0x5C |
2134a922 PO |
256 | |
257 | /* 60-FB reserved */ | |
d129bceb | 258 | |
52983382 KL |
259 | #define SDHCI_PRESET_FOR_SDR12 0x66 |
260 | #define SDHCI_PRESET_FOR_SDR25 0x68 | |
261 | #define SDHCI_PRESET_FOR_SDR50 0x6A | |
262 | #define SDHCI_PRESET_FOR_SDR104 0x6C | |
263 | #define SDHCI_PRESET_FOR_DDR50 0x6E | |
e9fb05d5 | 264 | #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ |
fa091010 MY |
265 | #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) |
266 | #define SDHCI_PRESET_CLKGEN_SEL BIT(10) | |
267 | #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) | |
52983382 | 268 | |
d129bceb PO |
269 | #define SDHCI_SLOT_INT_STATUS 0xFC |
270 | ||
271 | #define SDHCI_HOST_VERSION 0xFE | |
4a965505 PO |
272 | #define SDHCI_VENDOR_VER_MASK 0xFF00 |
273 | #define SDHCI_VENDOR_VER_SHIFT 8 | |
274 | #define SDHCI_SPEC_VER_MASK 0x00FF | |
275 | #define SDHCI_SPEC_VER_SHIFT 0 | |
2134a922 PO |
276 | #define SDHCI_SPEC_100 0 |
277 | #define SDHCI_SPEC_200 1 | |
85105c53 | 278 | #define SDHCI_SPEC_300 2 |
18da1990 CZ |
279 | #define SDHCI_SPEC_400 3 |
280 | #define SDHCI_SPEC_410 4 | |
281 | #define SDHCI_SPEC_420 5 | |
d129bceb | 282 | |
0397526d ZG |
283 | /* |
284 | * End of controller registers. | |
285 | */ | |
286 | ||
287 | #define SDHCI_MAX_DIV_SPEC_200 256 | |
288 | #define SDHCI_MAX_DIV_SPEC_300 2046 | |
289 | ||
f6a03cbf MV |
290 | /* |
291 | * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. | |
292 | */ | |
293 | #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) | |
294 | #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) | |
295 | ||
739d46dc AH |
296 | /* ADMA2 32-bit DMA descriptor size */ |
297 | #define SDHCI_ADMA2_32_DESC_SZ 8 | |
298 | ||
0545230f AH |
299 | /* ADMA2 32-bit descriptor */ |
300 | struct sdhci_adma2_32_desc { | |
301 | __le16 cmd; | |
302 | __le16 len; | |
303 | __le32 addr; | |
04a5ae6f AH |
304 | } __packed __aligned(4); |
305 | ||
306 | /* ADMA2 data alignment */ | |
307 | #define SDHCI_ADMA2_ALIGN 4 | |
308 | #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) | |
309 | ||
310 | /* | |
311 | * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte | |
312 | * alignment for the descriptor table even in 32-bit DMA mode. Memory | |
313 | * allocation is at least 8 byte aligned anyway, so just stipulate 8 always. | |
314 | */ | |
315 | #define SDHCI_ADMA2_DESC_ALIGN 8 | |
0545230f | 316 | |
685e444b CZ |
317 | /* |
318 | * ADMA2 64-bit DMA descriptor size | |
319 | * According to SD Host Controller spec v4.10, there are two kinds of | |
320 | * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit | |
321 | * Descriptor, if Host Version 4 Enable is set in the Host Control 2 | |
322 | * register, 128-bit Descriptor will be selected. | |
323 | */ | |
324 | #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) | |
e57a5f61 | 325 | |
e57a5f61 AH |
326 | /* |
327 | * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte | |
328 | * aligned. | |
329 | */ | |
330 | struct sdhci_adma2_64_desc { | |
331 | __le16 cmd; | |
332 | __le16 len; | |
333 | __le32 addr_lo; | |
334 | __le32 addr_hi; | |
335 | } __packed __aligned(4); | |
336 | ||
739d46dc AH |
337 | #define ADMA2_TRAN_VALID 0x21 |
338 | #define ADMA2_NOP_END_VALID 0x3 | |
339 | #define ADMA2_END 0x2 | |
340 | ||
4fb213f8 AH |
341 | /* |
342 | * Maximum segments assuming a 512KiB maximum requisition size and a minimum | |
343 | * 4KiB page size. | |
344 | */ | |
345 | #define SDHCI_MAX_SEGS 128 | |
346 | ||
4e9f8fe5 AH |
347 | /* Allow for a a command request and a data request at the same time */ |
348 | #define SDHCI_MAX_MRQS 2 | |
349 | ||
fc1fa1b7 KVA |
350 | /* |
351 | * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms. | |
352 | * However since the start time of the command, the time between | |
353 | * command and response, and the time between response and start of data is | |
354 | * not known, set the command transfer time to 10ms. | |
355 | */ | |
356 | #define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */ | |
357 | ||
d31911b9 HC |
358 | enum sdhci_cookie { |
359 | COOKIE_UNMAPPED, | |
94538e51 RK |
360 | COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */ |
361 | COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ | |
83f13cc9 UH |
362 | }; |
363 | ||
364 | struct sdhci_host { | |
365 | /* Data set by hardware interface driver */ | |
366 | const char *hw_name; /* Hardware bus name */ | |
367 | ||
368 | unsigned int quirks; /* Deviations from spec. */ | |
369 | ||
370 | /* Controller doesn't honor resets unless we touch the clock register */ | |
371 | #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) | |
372 | /* Controller has bad caps bits, but really supports DMA */ | |
373 | #define SDHCI_QUIRK_FORCE_DMA (1<<1) | |
374 | /* Controller doesn't like to be reset when there is no card inserted. */ | |
375 | #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2) | |
376 | /* Controller doesn't like clearing the power reg before a change */ | |
377 | #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3) | |
378 | /* Controller has flaky internal state so reset it on each ios change */ | |
379 | #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4) | |
380 | /* Controller has an unusable DMA engine */ | |
381 | #define SDHCI_QUIRK_BROKEN_DMA (1<<5) | |
382 | /* Controller has an unusable ADMA engine */ | |
383 | #define SDHCI_QUIRK_BROKEN_ADMA (1<<6) | |
384 | /* Controller can only DMA from 32-bit aligned addresses */ | |
385 | #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7) | |
386 | /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ | |
387 | #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8) | |
388 | /* Controller can only ADMA chunks that are a multiple of 32 bits */ | |
389 | #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9) | |
390 | /* Controller needs to be reset after each request to stay stable */ | |
391 | #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10) | |
392 | /* Controller needs voltage and power writes to happen separately */ | |
393 | #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11) | |
394 | /* Controller provides an incorrect timeout value for transfers */ | |
395 | #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12) | |
396 | /* Controller has an issue with buffer bits for small transfers */ | |
397 | #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) | |
398 | /* Controller does not provide transfer-complete interrupt when not busy */ | |
399 | #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14) | |
400 | /* Controller has unreliable card detection */ | |
401 | #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15) | |
402 | /* Controller reports inverted write-protect state */ | |
403 | #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) | |
75d27ea1 AH |
404 | /* Controller has unusable command queue engine */ |
405 | #define SDHCI_QUIRK_BROKEN_CQE (1<<17) | |
83f13cc9 UH |
406 | /* Controller does not like fast PIO transfers */ |
407 | #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) | |
bd29f58b AH |
408 | /* Controller does not have a LED */ |
409 | #define SDHCI_QUIRK_NO_LED (1<<19) | |
83f13cc9 UH |
410 | /* Controller has to be forced to use block size of 2048 bytes */ |
411 | #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20) | |
412 | /* Controller cannot do multi-block transfers */ | |
413 | #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21) | |
414 | /* Controller can only handle 1-bit data transfers */ | |
415 | #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22) | |
416 | /* Controller needs 10ms delay between applying power and clock */ | |
417 | #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23) | |
418 | /* Controller uses SDCLK instead of TMCLK for data timeouts */ | |
419 | #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24) | |
420 | /* Controller reports wrong base clock capability */ | |
421 | #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25) | |
422 | /* Controller cannot support End Attribute in NOP ADMA descriptor */ | |
423 | #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26) | |
424 | /* Controller is missing device caps. Use caps provided by host */ | |
425 | #define SDHCI_QUIRK_MISSING_CAPS (1<<27) | |
426 | /* Controller uses Auto CMD12 command to stop the transfer */ | |
427 | #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28) | |
428 | /* Controller doesn't have HISPD bit field in HI-SPEED SD card */ | |
429 | #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29) | |
430 | /* Controller treats ADMA descriptors with length 0000h incorrectly */ | |
431 | #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30) | |
432 | /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */ | |
433 | #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31) | |
434 | ||
435 | unsigned int quirks2; /* More deviations from spec. */ | |
436 | ||
437 | #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0) | |
438 | #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1) | |
439 | /* The system physically doesn't support 1.8v, even if the host does */ | |
440 | #define SDHCI_QUIRK2_NO_1_8_V (1<<2) | |
441 | #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3) | |
442 | #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4) | |
443 | /* Controller has a non-standard host control register */ | |
444 | #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5) | |
445 | /* Controller does not support HS200 */ | |
446 | #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6) | |
447 | /* Controller does not support DDR50 */ | |
448 | #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) | |
449 | /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ | |
450 | #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) | |
451 | /* Controller does not support 64-bit DMA */ | |
452 | #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9) | |
453 | /* need clear transfer mode register before send cmd */ | |
454 | #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10) | |
455 | /* Capability register bit-63 indicates HS400 support */ | |
456 | #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11) | |
457 | /* forced tuned clock */ | |
458 | #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12) | |
459 | /* disable the block count for single block transactions */ | |
460 | #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13) | |
461 | /* Controller broken with using ACMD23 */ | |
462 | #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) | |
d1955c3a SG |
463 | /* Broken Clock divider zero in controller */ |
464 | #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) | |
1284c248 KVA |
465 | /* Controller has CRC in 136 bit Command Response */ |
466 | #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16) | |
a999fd93 AH |
467 | /* |
468 | * Disable HW timeout if the requested timeout is more than the maximum | |
469 | * obtainable timeout. | |
470 | */ | |
471 | #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) | |
e65953d4 CZ |
472 | /* |
473 | * 32-bit block count may not support eMMC where upper bits of CMD23 are used | |
474 | * for other purposes. Consequently we support 16-bit block count by default. | |
475 | * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit | |
476 | * block count. | |
477 | */ | |
478 | #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) | |
83f13cc9 UH |
479 | |
480 | int irq; /* Device IRQ */ | |
481 | void __iomem *ioaddr; /* Mapped address */ | |
18e762e3 | 482 | phys_addr_t mapbase; /* physical address base */ |
bd9b9027 LW |
483 | char *bounce_buffer; /* For packing SDMA reads/writes */ |
484 | dma_addr_t bounce_addr; | |
485 | unsigned int bounce_buffer_size; | |
83f13cc9 UH |
486 | |
487 | const struct sdhci_ops *ops; /* Low level hw interface */ | |
488 | ||
489 | /* Internal data */ | |
490 | struct mmc_host *mmc; /* MMC structure */ | |
bf60e592 | 491 | struct mmc_host_ops mmc_host_ops; /* MMC host ops */ |
83f13cc9 UH |
492 | u64 dma_mask; /* custom DMA mask */ |
493 | ||
74479c5d | 494 | #if IS_ENABLED(CONFIG_LEDS_CLASS) |
83f13cc9 UH |
495 | struct led_classdev led; /* LED control */ |
496 | char led_name[32]; | |
497 | #endif | |
498 | ||
499 | spinlock_t lock; /* Mutex */ | |
500 | ||
501 | int flags; /* Host attributes */ | |
502 | #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */ | |
503 | #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */ | |
504 | #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ | |
505 | #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ | |
506 | #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */ | |
83f13cc9 UH |
507 | #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ |
508 | #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ | |
509 | #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ | |
83f13cc9 UH |
510 | #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */ |
511 | #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */ | |
8cb851a4 AH |
512 | #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ |
513 | #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ | |
514 | #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ | |
83f13cc9 UH |
515 | |
516 | unsigned int version; /* SDHCI spec. version */ | |
517 | ||
518 | unsigned int max_clk; /* Max possible freq (MHz) */ | |
519 | unsigned int timeout_clk; /* Timeout freq (KHz) */ | |
520 | unsigned int clk_mul; /* Clock Muliplier value */ | |
521 | ||
522 | unsigned int clock; /* Current clock (MHz) */ | |
523 | u8 pwr; /* Current voltage */ | |
524 | ||
525 | bool runtime_suspended; /* Host is runtime suspended */ | |
526 | bool bus_on; /* Bus power prevents runtime suspend */ | |
527 | bool preset_enabled; /* Preset is enabled */ | |
ed1563de | 528 | bool pending_reset; /* Cmd/data reset is pending */ |
58e79b60 | 529 | bool irq_wake_enabled; /* IRQ wakeup is enabled */ |
b3f80b43 | 530 | bool v4_mode; /* Host Version 4 Enable */ |
18e762e3 | 531 | bool use_external_dma; /* Host selects to use external DMA */ |
4730831c | 532 | bool always_defer_done; /* Always defer to complete requests */ |
83f13cc9 | 533 | |
4e9f8fe5 | 534 | struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ |
83f13cc9 | 535 | struct mmc_command *cmd; /* Current command */ |
7c89a3d9 | 536 | struct mmc_command *data_cmd; /* Current data command */ |
83f13cc9 UH |
537 | struct mmc_data *data; /* Current data request */ |
538 | unsigned int data_early:1; /* Data finished before cmd */ | |
83f13cc9 UH |
539 | |
540 | struct sg_mapping_iter sg_miter; /* SG state for PIO */ | |
541 | unsigned int blocks; /* remaining PIO blocks */ | |
542 | ||
543 | int sg_count; /* Mapped sg entries */ | |
544 | ||
545 | void *adma_table; /* ADMA descriptor table */ | |
546 | void *align_buffer; /* Bounce buffer */ | |
547 | ||
548 | size_t adma_table_sz; /* ADMA descriptor table size */ | |
549 | size_t align_buffer_sz; /* Bounce buffer size */ | |
550 | ||
551 | dma_addr_t adma_addr; /* Mapped ADMA descr. table */ | |
552 | dma_addr_t align_addr; /* Mapped bounce buffer */ | |
553 | ||
a663f64b VB |
554 | unsigned int desc_sz; /* ADMA current descriptor size */ |
555 | unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */ | |
83f13cc9 | 556 | |
c07a48c2 AH |
557 | struct workqueue_struct *complete_wq; /* Request completion wq */ |
558 | struct work_struct complete_work; /* Request completion work */ | |
83f13cc9 UH |
559 | |
560 | struct timer_list timer; /* Timer for timeouts */ | |
d7422fb4 | 561 | struct timer_list data_timer; /* Timer for data timeouts */ |
83f13cc9 | 562 | |
18e762e3 CZ |
563 | #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) |
564 | struct dma_chan *rx_chan; | |
565 | struct dma_chan *tx_chan; | |
566 | #endif | |
567 | ||
28da3589 AH |
568 | u32 caps; /* CAPABILITY_0 */ |
569 | u32 caps1; /* CAPABILITY_1 */ | |
6132a3bf | 570 | bool read_caps; /* Capability flags have been read */ |
83f13cc9 UH |
571 | |
572 | unsigned int ocr_avail_sdio; /* OCR bit masks */ | |
573 | unsigned int ocr_avail_sd; | |
574 | unsigned int ocr_avail_mmc; | |
575 | u32 ocr_mask; /* available voltages */ | |
576 | ||
577 | unsigned timing; /* Current timing */ | |
578 | ||
579 | u32 thread_isr; | |
580 | ||
581 | /* cached registers */ | |
582 | u32 ier; | |
583 | ||
f12e39db AH |
584 | bool cqe_on; /* CQE is operating */ |
585 | u32 cqe_ier; /* CQE interrupt mask */ | |
586 | u32 cqe_err_ier; /* CQE error interrupt mask */ | |
587 | ||
83f13cc9 UH |
588 | wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ |
589 | unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */ | |
590 | ||
591 | unsigned int tuning_count; /* Timer count for re-tuning */ | |
592 | unsigned int tuning_mode; /* Re-tuning mode supported by host */ | |
7d8bb1f4 | 593 | unsigned int tuning_err; /* Error code for re-tuning */ |
83f13cc9 | 594 | #define SDHCI_TUNING_MODE_1 0 |
f37b20eb DA |
595 | #define SDHCI_TUNING_MODE_2 1 |
596 | #define SDHCI_TUNING_MODE_3 2 | |
83b600b8 AH |
597 | /* Delay (ms) between tuning commands */ |
598 | int tuning_delay; | |
1d8cd065 | 599 | int tuning_loop_count; |
83f13cc9 | 600 | |
c846a00f SK |
601 | /* Host SDMA buffer boundary. */ |
602 | u32 sdma_boundary; | |
603 | ||
e93be38a JZ |
604 | /* Host ADMA table count */ |
605 | u32 adma_table_cnt; | |
606 | ||
fc1fa1b7 KVA |
607 | u64 data_timeout; |
608 | ||
1a91a36a | 609 | unsigned long private[] ____cacheline_aligned; |
83f13cc9 UH |
610 | }; |
611 | ||
b8c86fc5 | 612 | struct sdhci_ops { |
4e4141a5 | 613 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
dc297c92 MF |
614 | u32 (*read_l)(struct sdhci_host *host, int reg); |
615 | u16 (*read_w)(struct sdhci_host *host, int reg); | |
616 | u8 (*read_b)(struct sdhci_host *host, int reg); | |
617 | void (*write_l)(struct sdhci_host *host, u32 val, int reg); | |
618 | void (*write_w)(struct sdhci_host *host, u16 val, int reg); | |
619 | void (*write_b)(struct sdhci_host *host, u8 val, int reg); | |
4e4141a5 AV |
620 | #endif |
621 | ||
8114634c | 622 | void (*set_clock)(struct sdhci_host *host, unsigned int clock); |
1dceb041 AH |
623 | void (*set_power)(struct sdhci_host *host, unsigned char mode, |
624 | unsigned short vdd); | |
8114634c | 625 | |
f12e39db AH |
626 | u32 (*irq)(struct sdhci_host *host, u32 intmask); |
627 | ||
4ee7dde4 | 628 | int (*set_dma_mask)(struct sdhci_host *host); |
b8c86fc5 | 629 | int (*enable_dma)(struct sdhci_host *host); |
4240ff0a | 630 | unsigned int (*get_max_clock)(struct sdhci_host *host); |
a9e58f25 | 631 | unsigned int (*get_min_clock)(struct sdhci_host *host); |
8cc35289 | 632 | /* get_timeout_clock should return clk rate in unit of Hz */ |
4240ff0a | 633 | unsigned int (*get_timeout_clock)(struct sdhci_host *host); |
a6ff5aeb | 634 | unsigned int (*get_max_timeout_count)(struct sdhci_host *host); |
b45e668a AD |
635 | void (*set_timeout)(struct sdhci_host *host, |
636 | struct mmc_command *cmd); | |
2317f56c | 637 | void (*set_bus_width)(struct sdhci_host *host, int width); |
643a81ff PR |
638 | void (*platform_send_init_74_clocks)(struct sdhci_host *host, |
639 | u8 power_mode); | |
2dfb579c | 640 | unsigned int (*get_ro)(struct sdhci_host *host); |
03231f9b | 641 | void (*reset)(struct sdhci_host *host, u8 mask); |
45251812 | 642 | int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); |
13e64501 | 643 | void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); |
20758b66 | 644 | void (*hw_reset)(struct sdhci_host *host); |
a4071fbb | 645 | void (*adma_workaround)(struct sdhci_host *host, u32 intmask); |
722e1280 | 646 | void (*card_event)(struct sdhci_host *host); |
9d967a61 | 647 | void (*voltage_switch)(struct sdhci_host *host); |
54552e49 JZ |
648 | void (*adma_write_desc)(struct sdhci_host *host, void **desc, |
649 | dma_addr_t addr, int len, unsigned int cmd); | |
1774b002 BW |
650 | void (*request_done)(struct sdhci_host *host, |
651 | struct mmc_request *mrq); | |
d129bceb | 652 | }; |
b8c86fc5 | 653 | |
4e4141a5 AV |
654 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
655 | ||
656 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) | |
657 | { | |
dc297c92 MF |
658 | if (unlikely(host->ops->write_l)) |
659 | host->ops->write_l(host, val, reg); | |
4e4141a5 AV |
660 | else |
661 | writel(val, host->ioaddr + reg); | |
662 | } | |
663 | ||
664 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) | |
665 | { | |
dc297c92 MF |
666 | if (unlikely(host->ops->write_w)) |
667 | host->ops->write_w(host, val, reg); | |
4e4141a5 AV |
668 | else |
669 | writew(val, host->ioaddr + reg); | |
670 | } | |
671 | ||
672 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) | |
673 | { | |
dc297c92 MF |
674 | if (unlikely(host->ops->write_b)) |
675 | host->ops->write_b(host, val, reg); | |
4e4141a5 AV |
676 | else |
677 | writeb(val, host->ioaddr + reg); | |
678 | } | |
679 | ||
680 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) | |
681 | { | |
dc297c92 MF |
682 | if (unlikely(host->ops->read_l)) |
683 | return host->ops->read_l(host, reg); | |
4e4141a5 AV |
684 | else |
685 | return readl(host->ioaddr + reg); | |
686 | } | |
687 | ||
688 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) | |
689 | { | |
dc297c92 MF |
690 | if (unlikely(host->ops->read_w)) |
691 | return host->ops->read_w(host, reg); | |
4e4141a5 AV |
692 | else |
693 | return readw(host->ioaddr + reg); | |
694 | } | |
695 | ||
696 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) | |
697 | { | |
dc297c92 MF |
698 | if (unlikely(host->ops->read_b)) |
699 | return host->ops->read_b(host, reg); | |
4e4141a5 AV |
700 | else |
701 | return readb(host->ioaddr + reg); | |
702 | } | |
703 | ||
704 | #else | |
705 | ||
706 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) | |
707 | { | |
708 | writel(val, host->ioaddr + reg); | |
709 | } | |
710 | ||
711 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) | |
712 | { | |
713 | writew(val, host->ioaddr + reg); | |
714 | } | |
715 | ||
716 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) | |
717 | { | |
718 | writeb(val, host->ioaddr + reg); | |
719 | } | |
720 | ||
721 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) | |
722 | { | |
723 | return readl(host->ioaddr + reg); | |
724 | } | |
725 | ||
726 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) | |
727 | { | |
728 | return readw(host->ioaddr + reg); | |
729 | } | |
730 | ||
731 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) | |
732 | { | |
733 | return readb(host->ioaddr + reg); | |
734 | } | |
735 | ||
736 | #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ | |
b8c86fc5 | 737 | |
15becf68 AH |
738 | struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size); |
739 | void sdhci_free_host(struct sdhci_host *host); | |
b8c86fc5 PO |
740 | |
741 | static inline void *sdhci_priv(struct sdhci_host *host) | |
742 | { | |
178b0fa0 | 743 | return host->private; |
b8c86fc5 PO |
744 | } |
745 | ||
15becf68 | 746 | void sdhci_card_detect(struct sdhci_host *host); |
8784edc8 MY |
747 | void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver, |
748 | const u32 *caps, const u32 *caps1); | |
15becf68 | 749 | int sdhci_setup_host(struct sdhci_host *host); |
4180ffa8 | 750 | void sdhci_cleanup_host(struct sdhci_host *host); |
15becf68 AH |
751 | int __sdhci_add_host(struct sdhci_host *host); |
752 | int sdhci_add_host(struct sdhci_host *host); | |
753 | void sdhci_remove_host(struct sdhci_host *host, int dead); | |
754 | void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); | |
b8c86fc5 | 755 | |
6132a3bf AH |
756 | static inline void sdhci_read_caps(struct sdhci_host *host) |
757 | { | |
758 | __sdhci_read_caps(host, NULL, NULL, NULL); | |
759 | } | |
760 | ||
fb9ee047 LD |
761 | u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, |
762 | unsigned int *actual_clock); | |
1771059c | 763 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); |
fec79673 | 764 | void sdhci_enable_clk(struct sdhci_host *host, u16 clk); |
1dceb041 AH |
765 | void sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
766 | unsigned short vdd); | |
6c92ae1e NSJ |
767 | void sdhci_set_power_and_bus_voltage(struct sdhci_host *host, |
768 | unsigned char mode, | |
769 | unsigned short vdd); | |
606d3131 AH |
770 | void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, |
771 | unsigned short vdd); | |
d462c1b4 | 772 | void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq); |
2317f56c | 773 | void sdhci_set_bus_width(struct sdhci_host *host, int width); |
03231f9b | 774 | void sdhci_reset(struct sdhci_host *host, u8 mask); |
96d7b78c | 775 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); |
85a882c2 | 776 | int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); |
6a6d4ceb | 777 | void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
c376ea9e HZ |
778 | int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
779 | struct mmc_ios *ios); | |
2f05b6ab | 780 | void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); |
54552e49 JZ |
781 | void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, |
782 | dma_addr_t addr, int len, unsigned int cmd); | |
2317f56c | 783 | |
b8c86fc5 | 784 | #ifdef CONFIG_PM |
15becf68 AH |
785 | int sdhci_suspend_host(struct sdhci_host *host); |
786 | int sdhci_resume_host(struct sdhci_host *host); | |
15becf68 | 787 | int sdhci_runtime_suspend_host(struct sdhci_host *host); |
c6303c5d | 788 | int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset); |
66fd8ad5 AH |
789 | #endif |
790 | ||
f12e39db AH |
791 | void sdhci_cqe_enable(struct mmc_host *mmc); |
792 | void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery); | |
793 | bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, | |
794 | int *data_error); | |
795 | ||
d2898172 | 796 | void sdhci_dumpregs(struct sdhci_host *host); |
b3f80b43 | 797 | void sdhci_enable_v4_mode(struct sdhci_host *host); |
d2898172 | 798 | |
6663c419 | 799 | void sdhci_start_tuning(struct sdhci_host *host); |
800 | void sdhci_end_tuning(struct sdhci_host *host); | |
801 | void sdhci_reset_tuning(struct sdhci_host *host); | |
802 | void sdhci_send_tuning(struct sdhci_host *host, u32 opcode); | |
7353788c | 803 | void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode); |
18e762e3 | 804 | void sdhci_switch_external_dma(struct sdhci_host *host, bool en); |
7907ebe7 | 805 | void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable); |
7d76ed77 | 806 | void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); |
6663c419 | 807 | |
1978fda8 | 808 | #endif /* __SDHCI_HW_H */ |