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Merge tag 'pm-6.16-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
d129bceb 2/*
70f10482 3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 4 *
b69c9058 5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb 6 *
84c46a53
PO		 7 * Thanks to the following companies for their support:
8 *
9 * - JMicron (hardware and technical support)
d129bceb
PO		 10 */
11
fa091010 12#include <linux/bitfield.h>
d129bceb 13#include <linux/delay.h>
18e762e3 14#include <linux/dmaengine.h>
5a436cc0 15#include <linux/ktime.h>
d129bceb 16#include <linux/highmem.h>
b8c86fc5 17#include <linux/io.h>
88b47679 18#include <linux/module.h>
d129bceb 19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
11763609 21#include <linux/scatterlist.h>
bd9b9027 22#include <linux/sizes.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
92e0c44b 25#include <linux/of.h>
6eb2c8e1 26#include <linux/bug.h>
2f730fec
PO		 27#include <linux/leds.h>
28
22113efd 29#include <linux/mmc/mmc.h>
d129bceb 30#include <linux/mmc/host.h>
473b095a 31#include <linux/mmc/card.h>
85cc1c33 32#include <linux/mmc/sdio.h>
bec9d4e5 33#include <linux/mmc/slot-gpio.h>
d129bceb 34
d129bceb
PO		 35#include "sdhci.h"
36
37#define DRIVER_NAME "sdhci"
d129bceb 38
d129bceb 39#define DBG(f, x...) \
f421865d 40 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
d129bceb 41
85ad90e2
AH		 42#define SDHCI_DUMP(f, x...) \
43 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
845c939e 50static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
a374a72b 51
d2898172 52void sdhci_dumpregs(struct sdhci_host *host)
d129bceb 53{
85ad90e2
AH		 54 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
55
56 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
57 sdhci_readl(host, SDHCI_DMA_ADDRESS),
58 sdhci_readw(host, SDHCI_HOST_VERSION));
59 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
60 sdhci_readw(host, SDHCI_BLOCK_SIZE),
61 sdhci_readw(host, SDHCI_BLOCK_COUNT));
62 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
63 sdhci_readl(host, SDHCI_ARGUMENT),
64 sdhci_readw(host, SDHCI_TRANSFER_MODE));
65 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
66 sdhci_readl(host, SDHCI_PRESENT_STATE),
67 sdhci_readb(host, SDHCI_HOST_CONTROL));
68 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
69 sdhci_readb(host, SDHCI_POWER_CONTROL),
70 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
71 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
72 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
73 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
74 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
75 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
76 sdhci_readl(host, SDHCI_INT_STATUS));
77 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
78 sdhci_readl(host, SDHCI_INT_ENABLE),
79 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
869f8a69
AH		 80 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
81 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
85ad90e2
AH		 82 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
83 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
84 sdhci_readl(host, SDHCI_CAPABILITIES),
85 sdhci_readl(host, SDHCI_CAPABILITIES_1));
86 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
87 sdhci_readw(host, SDHCI_COMMAND),
88 sdhci_readl(host, SDHCI_MAX_CURRENT));
89 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
7962302f
AH		 90 sdhci_readl(host, SDHCI_RESPONSE),
91 sdhci_readl(host, SDHCI_RESPONSE + 4));
85ad90e2 92 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
7962302f
AH		 93 sdhci_readl(host, SDHCI_RESPONSE + 8),
94 sdhci_readl(host, SDHCI_RESPONSE + 12));
85ad90e2
AH		 95 SDHCI_DUMP("Host ctl2: 0x%08x\n",
96 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 97
e57a5f61 98 if (host->flags & SDHCI_USE_ADMA) {
85ad90e2
AH		 99 if (host->flags & SDHCI_USE_64_BIT_DMA) {
100 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
101 sdhci_readl(host, SDHCI_ADMA_ERROR),
102 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
103 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
104 } else {
105 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
106 sdhci_readl(host, SDHCI_ADMA_ERROR),
107 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
108 }
e57a5f61 109 }
be3f4ae0 110
0f8186f1
VS		 111 if (host->ops->dump_uhs2_regs)
112 host->ops->dump_uhs2_regs(host);
113
d1fe0762
SG		 114 if (host->ops->dump_vendor_regs)
115 host->ops->dump_vendor_regs(host);
116
85ad90e2 117 SDHCI_DUMP("============================================\n");
d129bceb 118}
d2898172 119EXPORT_SYMBOL_GPL(sdhci_dumpregs);
d129bceb
PO		 120
121/*****************************************************************************\
122 * *
123 * Low level functions *
124 * *
125\*****************************************************************************/
126
b3f80b43
CZ		 127static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
128{
129 u16 ctrl2;
130
97207c12 131 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
b3f80b43
CZ		 132 if (ctrl2 & SDHCI_CTRL_V4_MODE)
133 return;
134
135 ctrl2 |= SDHCI_CTRL_V4_MODE;
97207c12 136 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
b3f80b43
CZ		 137}
138
139/*
140 * This can be called before sdhci_add_host() by Vendor's host controller
141 * driver to enable v4 mode if supported.
142 */
143void sdhci_enable_v4_mode(struct sdhci_host *host)
144{
145 host->v4_mode = true;
146 sdhci_do_enable_v4_mode(host);
147}
148EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
149
9cbb2358 150bool sdhci_data_line_cmd(struct mmc_command *cmd)
56a590dc
AH		 151{
152 return cmd->data || cmd->flags & MMC_RSP_BUSY;
153}
9cbb2358 154EXPORT_SYMBOL_GPL(sdhci_data_line_cmd);
56a590dc 155
7260cf5e
AV		 156static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
157{
5b4f1f6c 158 u32 present;
7260cf5e 159
c79396c1 160 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
da012e1e 161 !mmc_card_is_removable(host->mmc) || mmc_host_can_gpio_cd(host->mmc))
66fd8ad5
AH		 162 return;
163
5b4f1f6c
RK		 164 if (enable) {
165 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
166 SDHCI_CARD_PRESENT;
d25928d1 167
5b4f1f6c
RK		 168 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
169 SDHCI_INT_CARD_INSERT;
170 } else {
171 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
172 }
b537f94c
RK		 173
174 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
175 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 176}
177
178static void sdhci_enable_card_detection(struct sdhci_host *host)
179{
180 sdhci_set_card_detection(host, true);
181}
182
183static void sdhci_disable_card_detection(struct sdhci_host *host)
184{
185 sdhci_set_card_detection(host, false);
186}
187
02d0b685
UH		 188static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
189{
190 if (host->bus_on)
191 return;
192 host->bus_on = true;
bac53336 193 pm_runtime_get_noresume(mmc_dev(host->mmc));
02d0b685
UH		 194}
195
196static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
197{
198 if (!host->bus_on)
199 return;
200 host->bus_on = false;
bac53336 201 pm_runtime_put_noidle(mmc_dev(host->mmc));
02d0b685
UH		 202}
203
03231f9b 204void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 205{
5a436cc0 206 ktime_t timeout;
393c1a34 207
4e4141a5 208 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 209
f0710a55 210 if (mask & SDHCI_RESET_ALL) {
d129bceb 211 host->clock = 0;
f0710a55
AH		 212 /* Reset-all turns off SD Bus Power */
213 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
214 sdhci_runtime_pm_bus_off(host);
215 }
d129bceb 216
e16514d8 217 /* Wait max 100 ms */
5a436cc0 218 timeout = ktime_add_ms(ktime_get(), 100);
e16514d8
PO		 219
220 /* hw clears the bit when it's done */
b704441e
AD		 221 while (1) {
222 bool timedout = ktime_after(ktime_get(), timeout);
223
224 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
225 break;
226 if (timedout) {
a3c76eb9 227 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8 228 mmc_hostname(host->mmc), (int)mask);
efe8f5c9 229 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
e16514d8
PO		 230 sdhci_dumpregs(host);
231 return;
232 }
5a436cc0 233 udelay(10);
d129bceb 234 }
03231f9b
RK		 235}
236EXPORT_SYMBOL_GPL(sdhci_reset);
237
fca267f0 238bool sdhci_do_reset(struct sdhci_host *host, u8 mask)
03231f9b
RK		 239{
240 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
d3940f27
AH		 241 struct mmc_host *mmc = host->mmc;
242
243 if (!mmc->ops->get_cd(mmc))
aa990722 244 return false;
03231f9b 245 }
063a9dbb 246
03231f9b 247 host->ops->reset(host, mask);
393c1a34 248
aa990722
AH		 249 return true;
250}
fca267f0 251EXPORT_SYMBOL_GPL(sdhci_do_reset);
aa990722
AH		 252
253static void sdhci_reset_for_all(struct sdhci_host *host)
254{
255 if (sdhci_do_reset(host, SDHCI_RESET_ALL)) {
da91a8f9
RK		 256 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
257 if (host->ops->enable_dma)
258 host->ops->enable_dma(host);
259 }
da91a8f9
RK		 260 /* Resetting the controller clears many */
261 host->preset_enabled = false;
3abc1e80 262 }
d129bceb
PO		 263}
264
1e63d297
AH		 265enum sdhci_reset_reason {
266 SDHCI_RESET_FOR_INIT,
267 SDHCI_RESET_FOR_REQUEST_ERROR,
268 SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY,
269 SDHCI_RESET_FOR_TUNING_ABORT,
270 SDHCI_RESET_FOR_CARD_REMOVED,
271 SDHCI_RESET_FOR_CQE_RECOVERY,
272};
273
274static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason)
275{
acc13958
PS		 276 if (host->quirks2 & SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) {
277 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
278 return;
279 }
280
1e63d297
AH		 281 switch (reason) {
282 case SDHCI_RESET_FOR_INIT:
283 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
284 break;
285 case SDHCI_RESET_FOR_REQUEST_ERROR:
286 case SDHCI_RESET_FOR_TUNING_ABORT:
287 case SDHCI_RESET_FOR_CARD_REMOVED:
288 case SDHCI_RESET_FOR_CQE_RECOVERY:
289 sdhci_do_reset(host, SDHCI_RESET_CMD);
290 sdhci_do_reset(host, SDHCI_RESET_DATA);
291 break;
292 case SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY:
293 sdhci_do_reset(host, SDHCI_RESET_DATA);
294 break;
295 }
296}
297
298#define sdhci_reset_for(h, r) sdhci_reset_for_reason((h), SDHCI_RESET_FOR_##r)
299
f5c1ab82 300static void sdhci_set_default_irqs(struct sdhci_host *host)
d129bceb 301{
b537f94c
RK		 302 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
303 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
304 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
305 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
306 SDHCI_INT_RESPONSE;
307
f37b20eb
DA		 308 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
309 host->tuning_mode == SDHCI_TUNING_MODE_3)
310 host->ier |= SDHCI_INT_RETUNE;
311
b537f94c
RK		 312 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
313 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
f5c1ab82
AH		 314}
315
685e444b
CZ		 316static void sdhci_config_dma(struct sdhci_host *host)
317{
318 u8 ctrl;
319 u16 ctrl2;
320
321 if (host->version < SDHCI_SPEC_200)
322 return;
323
324 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
325
326 /*
327 * Always adjust the DMA selection as some controllers
328 * (e.g. JMicron) can't do PIO properly when the selection
329 * is ADMA.
330 */
331 ctrl &= ~SDHCI_CTRL_DMA_MASK;
332 if (!(host->flags & SDHCI_REQ_USE_DMA))
333 goto out;
334
335 /* Note if DMA Select is zero then SDMA is selected */
336 if (host->flags & SDHCI_USE_ADMA)
337 ctrl |= SDHCI_CTRL_ADMA32;
338
339 if (host->flags & SDHCI_USE_64_BIT_DMA) {
340 /*
341 * If v4 mode, all supported DMA can be 64-bit addressing if
342 * controller supports 64-bit system address, otherwise only
343 * ADMA can support 64-bit addressing.
344 */
345 if (host->v4_mode) {
346 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
347 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
348 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
349 } else if (host->flags & SDHCI_USE_ADMA) {
350 /*
351 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
352 * set SDHCI_CTRL_ADMA64.
353 */
354 ctrl |= SDHCI_CTRL_ADMA64;
355 }
356 }
357
358out:
359 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
360}
361
f5c1ab82
AH		 362static void sdhci_init(struct sdhci_host *host, int soft)
363{
364 struct mmc_host *mmc = host->mmc;
49769d4d 365 unsigned long flags;
f5c1ab82
AH		 366
367 if (soft)
1e63d297 368 sdhci_reset_for(host, INIT);
f5c1ab82 369 else
aa990722 370 sdhci_reset_for_all(host);
f5c1ab82 371
b3f80b43
CZ		 372 if (host->v4_mode)
373 sdhci_do_enable_v4_mode(host);
374
49769d4d 375 spin_lock_irqsave(&host->lock, flags);
f5c1ab82 376 sdhci_set_default_irqs(host);
49769d4d 377 spin_unlock_irqrestore(&host->lock, flags);
2f4cbb3d 378
f12e39db
AH		 379 host->cqe_on = false;
380
2f4cbb3d
NP		 381 if (soft) {
382 /* force clock reconfiguration */
383 host->clock = 0;
c981cdfb 384 host->reinit_uhs = true;
d3940f27 385 mmc->ops->set_ios(mmc, &mmc->ios);
2f4cbb3d 386 }
7260cf5e 387}
d129bceb 388
7260cf5e
AV		 389static void sdhci_reinit(struct sdhci_host *host)
390{
dcaac3f7
RR		 391 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
392
2f4cbb3d 393 sdhci_init(host, 0);
7260cf5e 394 sdhci_enable_card_detection(host);
dcaac3f7
RR		 395
396 /*
397 * A change to the card detect bits indicates a change in present state,
398 * refer sdhci_set_card_detection(). A card detect interrupt might have
399 * been missed while the host controller was being reset, so trigger a
400 * rescan to check.
401 */
402 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
403 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 404}
405
061d17a6 406static void __sdhci_led_activate(struct sdhci_host *host)
d129bceb
PO		 407{
408 u8 ctrl;
409
bd29f58b
AH		 410 if (host->quirks & SDHCI_QUIRK_NO_LED)
411 return;
412
4e4141a5 413 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 414 ctrl |= SDHCI_CTRL_LED;
4e4141a5 415 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 416}
417
061d17a6 418static void __sdhci_led_deactivate(struct sdhci_host *host)
d129bceb
PO		 419{
420 u8 ctrl;
421
bd29f58b
AH		 422 if (host->quirks & SDHCI_QUIRK_NO_LED)
423 return;
424
4e4141a5 425 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 426 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 427 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 428}
429
4f78230f 430#if IS_REACHABLE(CONFIG_LEDS_CLASS)
2f730fec 431static void sdhci_led_control(struct led_classdev *led,
061d17a6 432 enum led_brightness brightness)
2f730fec
PO		 433{
434 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
435 unsigned long flags;
436
437 spin_lock_irqsave(&host->lock, flags);
438
66fd8ad5
AH		 439 if (host->runtime_suspended)
440 goto out;
441
2f730fec 442 if (brightness == LED_OFF)
061d17a6 443 __sdhci_led_deactivate(host);
2f730fec 444 else
061d17a6 445 __sdhci_led_activate(host);
66fd8ad5 446out:
2f730fec
PO		 447 spin_unlock_irqrestore(&host->lock, flags);
448}
061d17a6
AH		 449
450static int sdhci_led_register(struct sdhci_host *host)
451{
452 struct mmc_host *mmc = host->mmc;
453
bd29f58b
AH		 454 if (host->quirks & SDHCI_QUIRK_NO_LED)
455 return 0;
456
061d17a6
AH		 457 snprintf(host->led_name, sizeof(host->led_name),
458 "%s::", mmc_hostname(mmc));
459
460 host->led.name = host->led_name;
461 host->led.brightness = LED_OFF;
462 host->led.default_trigger = mmc_hostname(mmc);
463 host->led.brightness_set = sdhci_led_control;
464
465 return led_classdev_register(mmc_dev(mmc), &host->led);
466}
467
468static void sdhci_led_unregister(struct sdhci_host *host)
469{
bd29f58b
AH		 470 if (host->quirks & SDHCI_QUIRK_NO_LED)
471 return;
472
061d17a6
AH		 473 led_classdev_unregister(&host->led);
474}
475
476static inline void sdhci_led_activate(struct sdhci_host *host)
477{
478}
479
480static inline void sdhci_led_deactivate(struct sdhci_host *host)
481{
482}
483
484#else
485
486static inline int sdhci_led_register(struct sdhci_host *host)
487{
488 return 0;
489}
490
491static inline void sdhci_led_unregister(struct sdhci_host *host)
492{
493}
494
495static inline void sdhci_led_activate(struct sdhci_host *host)
496{
497 __sdhci_led_activate(host);
498}
499
500static inline void sdhci_led_deactivate(struct sdhci_host *host)
501{
502 __sdhci_led_deactivate(host);
503}
504
2f730fec
PO		 505#endif
506
9cbb2358
VS		 507void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
508 unsigned long timeout)
97a1abae
AH		 509{
510 if (sdhci_data_line_cmd(mrq->cmd))
511 mod_timer(&host->data_timer, timeout);
512 else
513 mod_timer(&host->timer, timeout);
514}
9cbb2358 515EXPORT_SYMBOL_GPL(sdhci_mod_timer);
97a1abae
AH		 516
517static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
518{
519 if (sdhci_data_line_cmd(mrq->cmd))
8fa7292f 520 timer_delete(&host->data_timer);
97a1abae 521 else
8fa7292f 522 timer_delete(&host->timer);
97a1abae
AH		 523}
524
525static inline bool sdhci_has_requests(struct sdhci_host *host)
526{
527 return host->cmd || host->data_cmd;
528}
529
d129bceb
PO		 530/*****************************************************************************\
531 * *
532 * Core functions *
533 * *
534\*****************************************************************************/
535
a406f5a3 536static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 537{
7659150c 538 size_t blksize, len, chunk;
3f649ab7 539 u32 scratch;
7659150c 540 u8 *buf;
d129bceb 541
a406f5a3 542 DBG("PIO reading\n");
d129bceb 543
a406f5a3 544 blksize = host->data->blksz;
7659150c 545 chunk = 0;
d129bceb 546
a406f5a3 547 while (blksize) {
bf3a35ac 548 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 549
7659150c 550 len = min(host->sg_miter.length, blksize);
d129bceb 551
7659150c
PO		 552 blksize -= len;
553 host->sg_miter.consumed = len;
14d836e7 554
7659150c 555 buf = host->sg_miter.addr;
d129bceb 556
7659150c
PO		 557 while (len) {
558 if (chunk == 0) {
4e4141a5 559 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 560 chunk = 4;
a406f5a3 561 }
7659150c
PO		 562
563 *buf = scratch & 0xFF;
564
565 buf++;
566 scratch >>= 8;
567 chunk--;
568 len--;
d129bceb 569 }
a406f5a3 570 }
7659150c
PO		 571
572 sg_miter_stop(&host->sg_miter);
a406f5a3 573}
d129bceb 574
a406f5a3
PO		 575static void sdhci_write_block_pio(struct sdhci_host *host)
576{
7659150c
PO		 577 size_t blksize, len, chunk;
578 u32 scratch;
579 u8 *buf;
d129bceb 580
a406f5a3
PO		 581 DBG("PIO writing\n");
582
583 blksize = host->data->blksz;
7659150c
PO		 584 chunk = 0;
585 scratch = 0;
d129bceb 586
a406f5a3 587 while (blksize) {
bf3a35ac 588 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 589
7659150c
PO		 590 len = min(host->sg_miter.length, blksize);
591
592 blksize -= len;
593 host->sg_miter.consumed = len;
594
595 buf = host->sg_miter.addr;
d129bceb 596
7659150c
PO		 597 while (len) {
598 scratch |= (u32)*buf << (chunk * 8);
599
600 buf++;
601 chunk++;
602 len--;
603
604 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 605 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 606 chunk = 0;
607 scratch = 0;
d129bceb 608 }
d129bceb
PO		 609 }
610 }
7659150c
PO		 611
612 sg_miter_stop(&host->sg_miter);
a406f5a3
PO		 613}
614
615static void sdhci_transfer_pio(struct sdhci_host *host)
616{
617 u32 mask;
618
7659150c 619 if (host->blocks == 0)
a406f5a3
PO		 620 return;
621
622 if (host->data->flags & MMC_DATA_READ)
623 mask = SDHCI_DATA_AVAILABLE;
624 else
625 mask = SDHCI_SPACE_AVAILABLE;
626
4a3cba32
PO		 627 /*
628 * Some controllers (JMicron JMB38x) mess up the buffer bits
629 * for transfers < 4 bytes. As long as it is just one block,
630 * we can ignore the bits.
631 */
632 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
633 (host->data->blocks == 1))
634 mask = ~0;
635
4e4141a5 636 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 637 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
638 udelay(100);
639
a406f5a3
PO		 640 if (host->data->flags & MMC_DATA_READ)
641 sdhci_read_block_pio(host);
642 else
643 sdhci_write_block_pio(host);
d129bceb 644
7659150c
PO		 645 host->blocks--;
646 if (host->blocks == 0)
a406f5a3 647 break;
a406f5a3 648 }
d129bceb 649
a406f5a3 650 DBG("PIO transfer complete.\n");
d129bceb
PO		 651}
652
48857d9b 653static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 654 struct mmc_data *data, int cookie)
48857d9b
RK		 655{
656 int sg_count;
657
94538e51
RK		 658 /*
659 * If the data buffers are already mapped, return the previous
660 * dma_map_sg() result.
661 */
662 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 663 return data->sg_count;
48857d9b 664
bd9b9027
LW		 665 /* Bounce write requests to the bounce buffer */
666 if (host->bounce_buffer) {
667 unsigned int length = data->blksz * data->blocks;
668
669 if (length > host->bounce_buffer_size) {
670 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
671 mmc_hostname(host->mmc), length,
672 host->bounce_buffer_size);
673 return -EIO;
674 }
675 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
676 /* Copy the data to the bounce buffer */
e93577ec
AD		 677 if (host->ops->copy_to_bounce_buffer) {
678 host->ops->copy_to_bounce_buffer(host,
679 data, length);
680 } else {
681 sg_copy_to_buffer(data->sg, data->sg_len,
682 host->bounce_buffer, length);
683 }
bd9b9027
LW		 684 }
685 /* Switch ownership to the DMA */
bac53336 686 dma_sync_single_for_device(mmc_dev(host->mmc),
bd9b9027
LW		 687 host->bounce_addr,
688 host->bounce_buffer_size,
689 mmc_get_dma_dir(data));
690 /* Just a dummy value */
691 sg_count = 1;
692 } else {
693 /* Just access the data directly from memory */
694 sg_count = dma_map_sg(mmc_dev(host->mmc),
695 data->sg, data->sg_len,
696 mmc_get_dma_dir(data));
697 }
48857d9b
RK		 698
699 if (sg_count == 0)
700 return -ENOSPC;
701
702 data->sg_count = sg_count;
c0999b72 703 data->host_cookie = cookie;
48857d9b
RK		 704
705 return sg_count;
706}
707
4438592c 708static char *sdhci_kmap_atomic(struct scatterlist *sg)
2134a922 709{
47722e3f 710 return kmap_local_page(sg_page(sg)) + sg->offset;
2134a922
PO		 711}
712
4438592c 713static void sdhci_kunmap_atomic(void *buffer)
2134a922 714{
47722e3f 715 kunmap_local(buffer);
2134a922
PO		 716}
717
54552e49
JZ		 718void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
719 dma_addr_t addr, int len, unsigned int cmd)
118cd17d 720{
54552e49 721 struct sdhci_adma2_64_desc *dma_desc = *desc;
118cd17d 722
e57a5f61 723 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 724 dma_desc->cmd = cpu_to_le16(cmd);
725 dma_desc->len = cpu_to_le16(len);
38eee2e8 726 dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
e57a5f61
AH		 727
728 if (host->flags & SDHCI_USE_64_BIT_DMA)
38eee2e8 729 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
54552e49
JZ		 730
731 *desc += host->desc_sz;
732}
733EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
734
735static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
736 void **desc, dma_addr_t addr,
737 int len, unsigned int cmd)
738{
739 if (host->ops->adma_write_desc)
740 host->ops->adma_write_desc(host, desc, addr, len, cmd);
07be55b5
JZ		 741 else
742 sdhci_adma_write_desc(host, desc, addr, len, cmd);
118cd17d
BD		 743}
744
b5ffa674
AH		 745static void sdhci_adma_mark_end(void *desc)
746{
e57a5f61 747 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 748
e57a5f61 749 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 750 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 751}
752
60c64762
RK		 753static void sdhci_adma_table_pre(struct sdhci_host *host,
754 struct mmc_data *data, int sg_count)
2134a922 755{
2134a922 756 struct scatterlist *sg;
acc3ad13
RK		 757 dma_addr_t addr, align_addr;
758 void *desc, *align;
759 char *buffer;
760 int len, offset, i;
2134a922
PO		 761
762 /*
763 * The spec does not specify endianness of descriptor table.
764 * We currently guess that it is LE.
765 */
766
60c64762 767 host->sg_count = sg_count;
2134a922 768
4efaa6fb 769 desc = host->adma_table;
2134a922
PO		 770 align = host->align_buffer;
771
772 align_addr = host->align_addr;
773
774 for_each_sg(data->sg, sg, host->sg_count, i) {
775 addr = sg_dma_address(sg);
776 len = sg_dma_len(sg);
777
778 /*
acc3ad13
RK		 779 * The SDHCI specification states that ADMA addresses must
780 * be 32-bit aligned. If they aren't, then we use a bounce
781 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 782 * alignment.
783 */
04a5ae6f
AH		 784 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
785 SDHCI_ADMA2_MASK;
2134a922
PO		 786 if (offset) {
787 if (data->flags & MMC_DATA_WRITE) {
4438592c 788 buffer = sdhci_kmap_atomic(sg);
2134a922 789 memcpy(align, buffer, offset);
4438592c 790 sdhci_kunmap_atomic(buffer);
2134a922
PO		 791 }
792
118cd17d 793 /* tran, valid */
54552e49
JZ		 794 __sdhci_adma_write_desc(host, &desc, align_addr,
795 offset, ADMA2_TRAN_VALID);
2134a922
PO		 796
797 BUG_ON(offset > 65536);
798
04a5ae6f
AH		 799 align += SDHCI_ADMA2_ALIGN;
800 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 801
2134a922
PO		 802 addr += offset;
803 len -= offset;
804 }
805
3d7c194b
AH		 806 /*
807 * The block layer forces a minimum segment size of PAGE_SIZE,
808 * so 'len' can be too big here if PAGE_SIZE >= 64KiB. Write
809 * multiple descriptors, noting that the ADMA table is sized
810 * for 4KiB chunks anyway, so it will be big enough.
811 */
812 while (len > host->max_adma) {
813 int n = 32 * 1024; /* 32KiB*/
814
815 __sdhci_adma_write_desc(host, &desc, addr, n, ADMA2_TRAN_VALID);
816 addr += n;
817 len -= n;
818 }
2134a922 819
54552e49
JZ		 820 /* tran, valid */
821 if (len)
822 __sdhci_adma_write_desc(host, &desc, addr, len,
823 ADMA2_TRAN_VALID);
2134a922
PO		 824
825 /*
826 * If this triggers then we have a calculation bug
827 * somewhere. :/
828 */
76fe379a 829 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 830 }
831
70764a90 832 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 833 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 834 if (desc != host->adma_table) {
76fe379a 835 desc -= host->desc_sz;
b5ffa674 836 sdhci_adma_mark_end(desc);
70764a90
TA		 837 }
838 } else {
acc3ad13 839 /* Add a terminating entry - nop, end, valid */
54552e49 840 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 841 }
2134a922
PO		 842}
843
844static void sdhci_adma_table_post(struct sdhci_host *host,
845 struct mmc_data *data)
846{
2134a922
PO		 847 struct scatterlist *sg;
848 int i, size;
1c3d5f6d 849 void *align;
2134a922 850 char *buffer;
2134a922 851
47fa9613
RK		 852 if (data->flags & MMC_DATA_READ) {
853 bool has_unaligned = false;
de0b65a7 854
47fa9613
RK		 855 /* Do a quick scan of the SG list for any unaligned mappings */
856 for_each_sg(data->sg, sg, host->sg_count, i)
857 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
858 has_unaligned = true;
859 break;
860 }
2134a922 861
47fa9613
RK		 862 if (has_unaligned) {
863 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 864 data->sg_len, DMA_FROM_DEVICE);
2134a922 865
47fa9613 866 align = host->align_buffer;
2134a922 867
47fa9613
RK		 868 for_each_sg(data->sg, sg, host->sg_count, i) {
869 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
870 size = SDHCI_ADMA2_ALIGN -
871 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
872
4438592c 873 buffer = sdhci_kmap_atomic(sg);
47fa9613 874 memcpy(buffer, align, size);
4438592c 875 sdhci_kunmap_atomic(buffer);
2134a922 876
47fa9613
RK		 877 align += SDHCI_ADMA2_ALIGN;
878 }
2134a922
PO		 879 }
880 }
881 }
2134a922
PO		 882}
883
38eee2e8
MY		 884static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
885{
886 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
887 if (host->flags & SDHCI_USE_64_BIT_DMA)
888 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
889}
890
917a0c52 891static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
bd9b9027
LW		 892{
893 if (host->bounce_buffer)
894 return host->bounce_addr;
895 else
896 return sg_dma_address(host->data->sg);
897}
898
917a0c52
CZ		 899static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
900{
38eee2e8
MY		 901 if (host->v4_mode)
902 sdhci_set_adma_addr(host, addr);
903 else
917a0c52 904 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
917a0c52
CZ		 905}
906
0bb28d73
AH		 907static unsigned int sdhci_target_timeout(struct sdhci_host *host,
908 struct mmc_command *cmd,
909 struct mmc_data *data)
910{
911 unsigned int target_timeout;
912
913 /* timeout in us */
914 if (!data) {
915 target_timeout = cmd->busy_timeout * 1000;
916 } else {
917 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
918 if (host->clock && data->timeout_clks) {
919 unsigned long long val;
920
921 /*
922 * data->timeout_clks is in units of clock cycles.
923 * host->clock is in Hz. target_timeout is in us.
924 * Hence, us = 1000000 * cycles / Hz. Round up.
925 */
926 val = 1000000ULL * data->timeout_clks;
927 if (do_div(val, host->clock))
928 target_timeout++;
929 target_timeout += val;
930 }
931 }
932
933 return target_timeout;
934}
935
fc1fa1b7
KVA		 936static void sdhci_calc_sw_timeout(struct sdhci_host *host,
937 struct mmc_command *cmd)
938{
939 struct mmc_data *data = cmd->data;
940 struct mmc_host *mmc = host->mmc;
941 struct mmc_ios *ios = &mmc->ios;
942 unsigned char bus_width = 1 << ios->bus_width;
943 unsigned int blksz;
944 unsigned int freq;
945 u64 target_timeout;
946 u64 transfer_time;
947
948 target_timeout = sdhci_target_timeout(host, cmd, data);
949 target_timeout *= NSEC_PER_USEC;
950
951 if (data) {
952 blksz = data->blksz;
d2f025b0 953 freq = mmc->actual_clock ? : host->clock;
fc1fa1b7
KVA		 954 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
955 do_div(transfer_time, freq);
956 /* multiply by '2' to account for any unknowns */
957 transfer_time = transfer_time * 2;
958 /* calculate timeout for the entire data */
959 host->data_timeout = data->blocks * target_timeout +
960 transfer_time;
961 } else {
962 host->data_timeout = target_timeout;
963 }
964
965 if (host->data_timeout)
966 host->data_timeout += MMC_CMD_TRANSFER_TIME;
967}
968
a999fd93
AH		 969static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
970 bool *too_big)
d129bceb 971{
1c8cde92 972 u8 count;
401059df 973 struct mmc_data *data;
1c8cde92 974 unsigned target_timeout, current_timeout;
d129bceb 975
9c6bb8c6 976 *too_big = false;
a999fd93 977
ee53ab5d
PO		 978 /*
979 * If the host controller provides us with an incorrect timeout
e30314f2 980 * value, just skip the check and use the maximum. The hardware may take
ee53ab5d
PO		 981 * longer to time out, but that's much better than having a too-short
982 * timeout value.
983 */
11a2f1b7 984 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
e30314f2 985 return host->max_timeout_count;
e538fbe8 986
9c6bb8c6 987 /* Unspecified command, assume max */
401059df 988 if (cmd == NULL)
e30314f2 989 return host->max_timeout_count;
401059df
BC		 990
991 data = cmd->data;
a3c7778f 992 /* Unspecified timeout, assume max */
1d4d7744 993 if (!data && !cmd->busy_timeout)
e30314f2 994 return host->max_timeout_count;
d129bceb 995
a3c7778f 996 /* timeout in us */
0bb28d73 997 target_timeout = sdhci_target_timeout(host, cmd, data);
81b39802 998
1c8cde92
PO		 999 /*
1000 * Figure out needed cycles.
1001 * We do this in steps in order to fit inside a 32 bit int.
1002 * The first step is the minimum timeout, which will have a
1003 * minimum resolution of 6 bits:
1004 * (1) 2^13*1000 > 2^22,
1005 * (2) host->timeout_clk < 2^16
1006 * =>
1007 * (1) / (2) > 2^6
1008 */
1009 count = 0;
1010 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
1011 while (current_timeout < target_timeout) {
1012 count++;
1013 current_timeout <<= 1;
9c6bb8c6
BH		 1014 if (count > host->max_timeout_count) {
1015 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
1016 DBG("Too large timeout 0x%x requested for CMD%d!\n",
1017 count, cmd->opcode);
1018 count = host->max_timeout_count;
1019 *too_big = true;
1c8cde92 1020 break;
9c6bb8c6 1021 }
1c8cde92
PO		 1022 }
1023
ee53ab5d
PO		 1024 return count;
1025}
1026
6aa943ab
AV		 1027static void sdhci_set_transfer_irqs(struct sdhci_host *host)
1028{
1029 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
1030 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
1031
1032 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 1033 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 1034 else
b537f94c
RK		 1035 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
1036
af849c86
AH		 1037 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
1038 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1039 else
1040 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1041
b537f94c
RK		 1042 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1043 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 1044}
1045
7907ebe7 1046void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
a999fd93
AH		 1047{
1048 if (enable)
1049 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1050 else
1051 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1052 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1053 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1054}
7907ebe7 1055EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
a999fd93 1056
7d76ed77 1057void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d 1058{
7d76ed77
FA		 1059 bool too_big = false;
1060 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1061
1062 if (too_big &&
1063 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1064 sdhci_calc_sw_timeout(host, cmd);
1065 sdhci_set_data_timeout_irq(host, false);
1066 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1067 sdhci_set_data_timeout_irq(host, true);
1068 }
a999fd93 1069
7d76ed77
FA		 1070 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1071}
1072EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
a999fd93 1073
7d76ed77
FA		 1074static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1075{
1076 if (host->ops->set_timeout)
1077 host->ops->set_timeout(host, cmd);
1078 else
1079 __sdhci_set_timeout(host, cmd);
b45e668a
AD		 1080}
1081
9cbb2358 1082void sdhci_initialize_data(struct sdhci_host *host, struct mmc_data *data)
b45e668a 1083{
43dea098
AH		 1084 WARN_ON(host->data);
1085
ee53ab5d
PO		 1086 /* Sanity checks */
1087 BUG_ON(data->blksz * data->blocks > 524288);
1088 BUG_ON(data->blksz > host->mmc->max_blk_size);
1089 BUG_ON(data->blocks > 65535);
1090
1091 host->data = data;
1092 host->data_early = 0;
f6a03cbf 1093 host->data->bytes_xfered = 0;
15db1836 1094}
9cbb2358 1095EXPORT_SYMBOL_GPL(sdhci_initialize_data);
15db1836
FA		 1096
1097static inline void sdhci_set_block_info(struct sdhci_host *host,
1098 struct mmc_data *data)
1099{
1100 /* Set the DMA boundary value and block size */
1101 sdhci_writew(host,
1102 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1103 SDHCI_BLOCK_SIZE);
1104 /*
1105 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1106 * can be supported, in that case 16-bit block count register must be 0.
1107 */
1108 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1109 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1110 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1111 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1112 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1113 } else {
1114 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1115 }
1116}
1117
9cbb2358 1118void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data)
15db1836 1119{
fce14421 1120 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2134a922 1121 struct scatterlist *sg;
df953925 1122 unsigned int length_mask, offset_mask;
a0eaf0f9 1123 int i;
2134a922 1124
fce14421
RK		 1125 host->flags |= SDHCI_REQ_USE_DMA;
1126
1127 /*
1128 * FIXME: This doesn't account for merging when mapping the
1129 * scatterlist.
1130 *
1131 * The assumption here being that alignment and lengths are
1132 * the same after DMA mapping to device address space.
1133 */
a0eaf0f9 1134 length_mask = 0;
df953925 1135 offset_mask = 0;
2134a922 1136 if (host->flags & SDHCI_USE_ADMA) {
df953925 1137 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 1138 length_mask = 3;
df953925
RK		 1139 /*
1140 * As we use up to 3 byte chunks to work
1141 * around alignment problems, we need to
1142 * check the offset as well.
1143 */
1144 offset_mask = 3;
1145 }
2134a922
PO		 1146 } else {
1147 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 1148 length_mask = 3;
df953925
RK		 1149 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1150 offset_mask = 3;
2134a922
PO		 1151 }
1152
df953925 1153 if (unlikely(length_mask | offset_mask)) {
2134a922 1154 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 1155 if (sg->length & length_mask) {
2e4456f0 1156 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 1157 sg->length);
2134a922
PO		 1158 host->flags &= ~SDHCI_REQ_USE_DMA;
1159 break;
1160 }
a0eaf0f9 1161 if (sg->offset & offset_mask) {
2e4456f0 1162 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 1163 host->flags &= ~SDHCI_REQ_USE_DMA;
1164 break;
1165 }
1166 }
1167 }
1168 }
1169
20dbd07e
CL		 1170 sdhci_config_dma(host);
1171
8f1934ce 1172 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 1173 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 1174
1175 if (sg_cnt <= 0) {
1176 /*
1177 * This only happens when someone fed
1178 * us an invalid request.
1179 */
1180 WARN_ON(1);
1181 host->flags &= ~SDHCI_REQ_USE_DMA;
1182 } else if (host->flags & SDHCI_USE_ADMA) {
1183 sdhci_adma_table_pre(host, data, sg_cnt);
38eee2e8 1184 sdhci_set_adma_addr(host, host->adma_addr);
8f1934ce 1185 } else {
60c64762 1186 WARN_ON(sg_cnt != 1);
917a0c52 1187 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
8f1934ce
PO		 1188 }
1189 }
1190
8f1934ce 1191 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 1192 int flags;
1193
1194 flags = SG_MITER_ATOMIC;
1195 if (host->data->flags & MMC_DATA_READ)
1196 flags |= SG_MITER_TO_SG;
1197 else
1198 flags |= SG_MITER_FROM_SG;
1199 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 1200 host->blocks = data->blocks;
d129bceb 1201 }
c7fa9963 1202
6aa943ab 1203 sdhci_set_transfer_irqs(host);
9cbb2358
VS		 1204}
1205EXPORT_SYMBOL_GPL(sdhci_prepare_dma);
1206
1207static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1208{
1209 struct mmc_data *data = cmd->data;
1210
1211 sdhci_initialize_data(host, data);
1212
1213 sdhci_prepare_dma(host, data);
6aa943ab 1214
15db1836 1215 sdhci_set_block_info(host, data);
c7fa9963
PO		 1216}
1217
18e762e3
CZ		 1218#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1219
1220static int sdhci_external_dma_init(struct sdhci_host *host)
1221{
1222 int ret = 0;
1223 struct mmc_host *mmc = host->mmc;
1224
bac53336 1225 host->tx_chan = dma_request_chan(mmc_dev(mmc), "tx");
18e762e3
CZ		 1226 if (IS_ERR(host->tx_chan)) {
1227 ret = PTR_ERR(host->tx_chan);
1228 if (ret != -EPROBE_DEFER)
1229 pr_warn("Failed to request TX DMA channel.\n");
1230 host->tx_chan = NULL;
1231 return ret;
1232 }
1233
bac53336 1234 host->rx_chan = dma_request_chan(mmc_dev(mmc), "rx");
18e762e3
CZ		 1235 if (IS_ERR(host->rx_chan)) {
1236 if (host->tx_chan) {
1237 dma_release_channel(host->tx_chan);
1238 host->tx_chan = NULL;
1239 }
1240
1241 ret = PTR_ERR(host->rx_chan);
1242 if (ret != -EPROBE_DEFER)
1243 pr_warn("Failed to request RX DMA channel.\n");
1244 host->rx_chan = NULL;
1245 }
1246
1247 return ret;
1248}
1249
1250static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1251 struct mmc_data *data)
1252{
1253 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1254}
1255
1256static int sdhci_external_dma_setup(struct sdhci_host *host,
1257 struct mmc_command *cmd)
1258{
1259 int ret, i;
1215c025 1260 enum dma_transfer_direction dir;
18e762e3
CZ		 1261 struct dma_async_tx_descriptor *desc;
1262 struct mmc_data *data = cmd->data;
1263 struct dma_chan *chan;
1264 struct dma_slave_config cfg;
1265 dma_cookie_t cookie;
1266 int sg_cnt;
1267
1268 if (!host->mapbase)
1269 return -EINVAL;
1270
522654d5 1271 memset(&cfg, 0, sizeof(cfg));
18e762e3
CZ		 1272 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1273 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1274 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1275 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1276 cfg.src_maxburst = data->blksz / 4;
1277 cfg.dst_maxburst = data->blksz / 4;
1278
1279 /* Sanity check: all the SG entries must be aligned by block size. */
1280 for (i = 0; i < data->sg_len; i++) {
1281 if ((data->sg + i)->length % data->blksz)
1282 return -EINVAL;
1283 }
1284
1285 chan = sdhci_external_dma_channel(host, data);
1286
1287 ret = dmaengine_slave_config(chan, &cfg);
1288 if (ret)
1289 return ret;
1290
1291 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1292 if (sg_cnt <= 0)
1293 return -EINVAL;
1294
1215c025
CZ		 1295 dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
1296 desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
18e762e3
CZ		 1297 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1298 if (!desc)
1299 return -EINVAL;
1300
1301 desc->callback = NULL;
1302 desc->callback_param = NULL;
1303
1304 cookie = dmaengine_submit(desc);
1305 if (dma_submit_error(cookie))
1306 ret = cookie;
1307
1308 return ret;
1309}
1310
1311static void sdhci_external_dma_release(struct sdhci_host *host)
1312{
1313 if (host->tx_chan) {
1314 dma_release_channel(host->tx_chan);
1315 host->tx_chan = NULL;
1316 }
1317
1318 if (host->rx_chan) {
1319 dma_release_channel(host->rx_chan);
1320 host->rx_chan = NULL;
1321 }
1322
1323 sdhci_switch_external_dma(host, false);
1324}
1325
1326static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1327 struct mmc_command *cmd)
1328{
1329 struct mmc_data *data = cmd->data;
1330
1331 sdhci_initialize_data(host, data);
1332
1333 host->flags |= SDHCI_REQ_USE_DMA;
1334 sdhci_set_transfer_irqs(host);
1335
1336 sdhci_set_block_info(host, data);
1337}
1338
1339static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1340 struct mmc_command *cmd)
1341{
1342 if (!sdhci_external_dma_setup(host, cmd)) {
1343 __sdhci_external_dma_prepare_data(host, cmd);
1344 } else {
1345 sdhci_external_dma_release(host);
1346 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1347 mmc_hostname(host->mmc));
1348 sdhci_prepare_data(host, cmd);
1349 }
1350}
1351
1352static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1353 struct mmc_command *cmd)
1354{
1355 struct dma_chan *chan;
1356
1357 if (!cmd->data)
1358 return;
1359
1360 chan = sdhci_external_dma_channel(host, cmd->data);
1361 if (chan)
1362 dma_async_issue_pending(chan);
1363}
1364
1365#else
1366
1367static inline int sdhci_external_dma_init(struct sdhci_host *host)
1368{
1369 return -EOPNOTSUPP;
1370}
1371
1372static inline void sdhci_external_dma_release(struct sdhci_host *host)
1373{
1374}
1375
1376static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1377 struct mmc_command *cmd)
1378{
1379 /* This should never happen */
1380 WARN_ON_ONCE(1);
1381}
1382
1383static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1384 struct mmc_command *cmd)
1385{
1386}
1387
1388static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1389 struct mmc_data *data)
1390{
1391 return NULL;
1392}
1393
1394#endif
1395
1396void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1397{
1398 host->use_external_dma = en;
1399}
1400EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1401
0293d501
AH		 1402static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1403 struct mmc_request *mrq)
1404{
20845bef
AH		 1405 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1406 !mrq->cap_cmd_during_tfr;
0293d501
AH		 1407}
1408
ed633033
AH		 1409static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1410 struct mmc_request *mrq)
1411{
1412 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1413}
1414
1415static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1416 struct mmc_request *mrq)
1417{
1418 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1419}
1420
427b6514
CZ		 1421static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1422 struct mmc_command *cmd,
1423 u16 *mode)
1424{
1425 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1426 (cmd->opcode != SD_IO_RW_EXTENDED);
ed633033 1427 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
427b6514
CZ		 1428 u16 ctrl2;
1429
1430 /*
1431 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1432 * Select' is recommended rather than use of 'Auto CMD12
b3e1ea16
JZ		 1433 * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
1434 * here because some controllers (e.g sdhci-of-dwmshc) expect it.
427b6514 1435 */
b3e1ea16
JZ		 1436 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1437 (use_cmd12 || use_cmd23)) {
427b6514
CZ		 1438 *mode |= SDHCI_TRNS_AUTO_SEL;
1439
1440 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1441 if (use_cmd23)
1442 ctrl2 |= SDHCI_CMD23_ENABLE;
1443 else
1444 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1445 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1446
1447 return;
1448 }
1449
1450 /*
1451 * If we are sending CMD23, CMD12 never gets sent
1452 * on successful completion (so no Auto-CMD12).
1453 */
1454 if (use_cmd12)
1455 *mode |= SDHCI_TRNS_AUTO_CMD12;
1456 else if (use_cmd23)
1457 *mode |= SDHCI_TRNS_AUTO_CMD23;
1458}
1459
c7fa9963 1460static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 1461 struct mmc_command *cmd)
c7fa9963 1462{
d3fc5d71 1463 u16 mode = 0;
e89d456f 1464 struct mmc_data *data = cmd->data;
c7fa9963 1465
2b558c13 1466 if (data == NULL) {
9b8ffea6
VW		 1467 if (host->quirks2 &
1468 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
0086fc21 1469 /* must not clear SDHCI_TRANSFER_MODE when tuning */
63abdf72 1470 if (!mmc_op_tuning(cmd->opcode))
0086fc21 1471 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
9b8ffea6 1472 } else {
2b558c13 1473 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 1474 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1475 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 1476 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 1477 }
c7fa9963 1478 return;
2b558c13 1479 }
c7fa9963 1480
e538fbe8
PO		 1481 WARN_ON(!host->data);
1482
d3fc5d71
VY		 1483 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1484 mode = SDHCI_TRNS_BLK_CNT_EN;
1485
e89d456f 1486 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 1487 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
427b6514 1488 sdhci_auto_cmd_select(host, cmd, &mode);
ed633033 1489 if (sdhci_auto_cmd23(host, cmd->mrq))
a4c73aba 1490 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
c4512f79 1491 }
8edf6371 1492
c7fa9963
PO		 1493 if (data->flags & MMC_DATA_READ)
1494 mode |= SDHCI_TRNS_READ;
c9fddbc4 1495 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 1496 mode |= SDHCI_TRNS_DMA;
1497
4e4141a5 1498 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 1499}
1500
fca267f0 1501bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
0cc563ce
AH		 1502{
1503 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1504 ((mrq->cmd && mrq->cmd->error) ||
1505 (mrq->sbc && mrq->sbc->error) ||
4bf78099 1506 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
0cc563ce
AH		 1507 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1508}
fca267f0 1509EXPORT_SYMBOL_GPL(sdhci_needs_reset);
0cc563ce 1510
15db1836 1511static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
4e9f8fe5
AH		 1512{
1513 int i;
1514
1515 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1516 if (host->mrqs_done[i] == mrq) {
1517 WARN_ON(1);
1518 return;
1519 }
1520 }
1521
1522 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1523 if (!host->mrqs_done[i]) {
1524 host->mrqs_done[i] = mrq;
1525 break;
1526 }
1527 }
1528
1529 WARN_ON(i >= SDHCI_MAX_MRQS);
15db1836
FA		 1530}
1531
9cbb2358 1532void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
15db1836
FA		 1533{
1534 if (host->cmd && host->cmd->mrq == mrq)
1535 host->cmd = NULL;
1536
1537 if (host->data_cmd && host->data_cmd->mrq == mrq)
1538 host->data_cmd = NULL;
1539
845c939e
AH		 1540 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1541 host->deferred_cmd = NULL;
1542
15db1836
FA		 1543 if (host->data && host->data->mrq == mrq)
1544 host->data = NULL;
1545
1546 if (sdhci_needs_reset(host, mrq))
1547 host->pending_reset = true;
1548
1549 sdhci_set_mrq_done(host, mrq);
4e9f8fe5 1550
e9a07299
AH		 1551 sdhci_del_timer(host, mrq);
1552
1553 if (!sdhci_has_requests(host))
1554 sdhci_led_deactivate(host);
4e9f8fe5 1555}
9cbb2358 1556EXPORT_SYMBOL_GPL(__sdhci_finish_mrq);
4e9f8fe5 1557
9cbb2358 1558void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
a6d3bdd5 1559{
4e9f8fe5 1560 __sdhci_finish_mrq(host, mrq);
2e72ab9b 1561
c07a48c2 1562 queue_work(host->complete_wq, &host->complete_work);
a6d3bdd5 1563}
9cbb2358 1564EXPORT_SYMBOL_GPL(sdhci_finish_mrq);
a6d3bdd5 1565
9cbb2358 1566void __sdhci_finish_data_common(struct sdhci_host *host, bool defer_reset)
d129bceb 1567{
33a57adb
AH		 1568 struct mmc_command *data_cmd = host->data_cmd;
1569 struct mmc_data *data = host->data;
d129bceb 1570
d129bceb 1571 host->data = NULL;
7c89a3d9 1572 host->data_cmd = NULL;
d129bceb 1573
4bf78099
AH		 1574 /*
1575 * The controller needs a reset of internal state machines upon error
1576 * conditions.
1577 */
1578 if (data->error) {
9cbb2358
VS		 1579 if (defer_reset)
1580 host->pending_reset = true;
1581 else if (!host->cmd || host->cmd == data_cmd)
1e63d297
AH		 1582 sdhci_reset_for(host, REQUEST_ERROR);
1583 else
1584 sdhci_reset_for(host, REQUEST_ERROR_DATA_ONLY);
4bf78099
AH		 1585 }
1586
add8913d
RK		 1587 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1588 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1589 sdhci_adma_table_post(host, data);
d129bceb
PO		 1590
1591 /*
c9b74c5b
PO		 1592 * The specification states that the block count register must
1593 * be updated, but it does not specify at what point in the
1594 * data flow. That makes the register entirely useless to read
1595 * back so we have to assume that nothing made it to the card
1596 * in the event of an error.
d129bceb 1597 */
c9b74c5b
PO		 1598 if (data->error)
1599 data->bytes_xfered = 0;
d129bceb 1600 else
c9b74c5b 1601 data->bytes_xfered = data->blksz * data->blocks;
9cbb2358
VS		 1602}
1603EXPORT_SYMBOL_GPL(__sdhci_finish_data_common);
1604
1605static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1606{
1607 struct mmc_data *data = host->data;
1608
1609 __sdhci_finish_data_common(host, false);
d129bceb 1610
e89d456f
AW		 1611 /*
1612 * Need to send CMD12 if -
fdbbe6cf 1613 * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
e89d456f
AW		 1614 * b) error in multiblock transfer
1615 */
1616 if (data->stop &&
fdbbe6cf
YL		 1617 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1618 data->error)) {
20845bef
AH		 1619 /*
1620 * 'cap_cmd_during_tfr' request must not use the command line
1621 * after mmc_command_done() has been called. It is upper layer's
1622 * responsibility to send the stop command if required.
1623 */
1624 if (data->mrq->cap_cmd_during_tfr) {
19d2f695 1625 __sdhci_finish_mrq(host, data->mrq);
20845bef
AH		 1626 } else {
1627 /* Avoid triggering warning in sdhci_send_command() */
1628 host->cmd = NULL;
845c939e
AH		 1629 if (!sdhci_send_command(host, data->stop)) {
1630 if (sw_data_timeout) {
1631 /*
1632 * This is anyway a sw data timeout, so
1633 * give up now.
1634 */
1635 data->stop->error = -EIO;
1636 __sdhci_finish_mrq(host, data->mrq);
1637 } else {
1638 WARN_ON(host->deferred_cmd);
1639 host->deferred_cmd = data->stop;
1640 }
1641 }
20845bef 1642 }
a6d3bdd5 1643 } else {
19d2f695 1644 __sdhci_finish_mrq(host, data->mrq);
a6d3bdd5 1645 }
d129bceb
PO		 1646}
1647
845c939e
AH		 1648static void sdhci_finish_data(struct sdhci_host *host)
1649{
1650 __sdhci_finish_data(host, false);
1651}
1652
1653static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 1654{
1655 int flags;
fd2208d7 1656 u32 mask;
7cb2c76f 1657 unsigned long timeout;
d129bceb
PO		 1658
1659 WARN_ON(host->cmd);
1660
96776200
RK		 1661 /* Initially, a command has no error */
1662 cmd->error = 0;
1663
fc605f1d
AH		 1664 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1665 cmd->opcode == MMC_STOP_TRANSMISSION)
1666 cmd->flags |= MMC_RSP_BUSY;
1667
fd2208d7 1668 mask = SDHCI_CMD_INHIBIT;
56a590dc 1669 if (sdhci_data_line_cmd(cmd))
fd2208d7
PO		 1670 mask |= SDHCI_DATA_INHIBIT;
1671
1672 /* We shouldn't wait for data inihibit for stop commands, even
1673 though they might use busy signaling */
a4c73aba 1674 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
fd2208d7
PO		 1675 mask &= ~SDHCI_DATA_INHIBIT;
1676
845c939e
AH		 1677 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1678 return false;
d129bceb 1679
d129bceb 1680 host->cmd = cmd;
15db1836 1681 host->data_timeout = 0;
56a590dc 1682 if (sdhci_data_line_cmd(cmd)) {
7c89a3d9
AH		 1683 WARN_ON(host->data_cmd);
1684 host->data_cmd = cmd;
15db1836 1685 sdhci_set_timeout(host, cmd);
7c89a3d9 1686 }
d129bceb 1687
18e762e3
CZ		 1688 if (cmd->data) {
1689 if (host->use_external_dma)
1690 sdhci_external_dma_prepare_data(host, cmd);
1691 else
1692 sdhci_prepare_data(host, cmd);
1693 }
d129bceb 1694
4e4141a5 1695 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1696
e89d456f 1697 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1698
d129bceb 1699 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
845c939e
AH		 1700 WARN_ONCE(1, "Unsupported response type!\n");
1701 /*
1702 * This does not happen in practice because 136-bit response
1703 * commands never have busy waiting, so rather than complicate
1704 * the error path, just remove busy waiting and continue.
1705 */
1706 cmd->flags &= ~MMC_RSP_BUSY;
d129bceb
PO		 1707 }
1708
1709 if (!(cmd->flags & MMC_RSP_PRESENT))
1710 flags = SDHCI_CMD_RESP_NONE;
1711 else if (cmd->flags & MMC_RSP_136)
1712 flags = SDHCI_CMD_RESP_LONG;
1713 else if (cmd->flags & MMC_RSP_BUSY)
1714 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1715 else
1716 flags = SDHCI_CMD_RESP_SHORT;
1717
1718 if (cmd->flags & MMC_RSP_CRC)
1719 flags |= SDHCI_CMD_CRC;
1720 if (cmd->flags & MMC_RSP_OPCODE)
1721 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1722
1723 /* CMD19 is special in that the Data Present Select should be set */
b98e7e8d 1724 if (cmd->data || mmc_op_tuning(cmd->opcode))
d129bceb
PO		 1725 flags |= SDHCI_CMD_DATA;
1726
fc1fa1b7
KVA		 1727 timeout = jiffies;
1728 if (host->data_timeout)
1729 timeout += nsecs_to_jiffies(host->data_timeout);
1730 else if (!cmd->data && cmd->busy_timeout > 9000)
1731 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1732 else
1733 timeout += 10 * HZ;
1734 sdhci_mod_timer(host, cmd->mrq, timeout);
1735
18e762e3
CZ		 1736 if (host->use_external_dma)
1737 sdhci_external_dma_pre_transfer(host, cmd);
1738
4e4141a5 1739 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
845c939e
AH		 1740
1741 return true;
d129bceb
PO		 1742}
1743
9cbb2358
VS		 1744bool sdhci_present_error(struct sdhci_host *host,
1745 struct mmc_command *cmd, bool present)
e872f1e2
AH		 1746{
1747 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1748 cmd->error = -ENOMEDIUM;
1749 return true;
1750 }
1751
1752 return false;
1753}
9cbb2358 1754EXPORT_SYMBOL_GPL(sdhci_present_error);
e872f1e2 1755
845c939e
AH		 1756static bool sdhci_send_command_retry(struct sdhci_host *host,
1757 struct mmc_command *cmd,
1758 unsigned long flags)
1759 __releases(host->lock)
1760 __acquires(host->lock)
1761{
1762 struct mmc_command *deferred_cmd = host->deferred_cmd;
1763 int timeout = 10; /* Approx. 10 ms */
1764 bool present;
1765
1766 while (!sdhci_send_command(host, cmd)) {
1767 if (!timeout--) {
1768 pr_err("%s: Controller never released inhibit bit(s).\n",
1769 mmc_hostname(host->mmc));
efe8f5c9 1770 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
845c939e
AH		 1771 sdhci_dumpregs(host);
1772 cmd->error = -EIO;
1773 return false;
1774 }
1775
1776 spin_unlock_irqrestore(&host->lock, flags);
1777
1778 usleep_range(1000, 1250);
1779
1780 present = host->mmc->ops->get_cd(host->mmc);
1781
1782 spin_lock_irqsave(&host->lock, flags);
1783
1784 /* A deferred command might disappear, handle that */
1785 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1786 return true;
1787
1788 if (sdhci_present_error(host, cmd, present))
1789 return false;
1790 }
1791
1792 if (cmd == host->deferred_cmd)
1793 host->deferred_cmd = NULL;
1794
1795 return true;
1796}
1797
4a5fc119
AH		 1798static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1799{
1800 int i, reg;
1801
1802 for (i = 0; i < 4; i++) {
1803 reg = SDHCI_RESPONSE + (3 - i) * 4;
1804 cmd->resp[i] = sdhci_readl(host, reg);
1805 }
1806
1284c248
KVA		 1807 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1808 return;
1809
4a5fc119
AH		 1810 /* CRC is stripped so we need to do some shifting */
1811 for (i = 0; i < 4; i++) {
1812 cmd->resp[i] <<= 8;
1813 if (i != 3)
1814 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1815 }
1816}
1817
d129bceb
PO		 1818static void sdhci_finish_command(struct sdhci_host *host)
1819{
e0a5640a 1820 struct mmc_command *cmd = host->cmd;
d129bceb 1821
e0a5640a
AH		 1822 host->cmd = NULL;
1823
1824 if (cmd->flags & MMC_RSP_PRESENT) {
1825 if (cmd->flags & MMC_RSP_136) {
4a5fc119 1826 sdhci_read_rsp_136(host, cmd);
d129bceb 1827 } else {
e0a5640a 1828 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1829 }
1830 }
1831
20845bef
AH		 1832 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1833 mmc_command_done(host->mmc, cmd->mrq);
1834
6bde8681
AH		 1835 /*
1836 * The host can send and interrupt when the busy state has
1837 * ended, allowing us to wait without wasting CPU cycles.
1838 * The busy signal uses DAT0 so this is similar to waiting
1839 * for data to complete.
1840 *
1841 * Note: The 1.0 specification is a bit ambiguous about this
1842 * feature so there might be some problems with older
1843 * controllers.
1844 */
e0a5640a
AH		 1845 if (cmd->flags & MMC_RSP_BUSY) {
1846 if (cmd->data) {
6bde8681
AH		 1847 DBG("Cannot wait for busy signal when also doing a data transfer");
1848 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
ea968023
AH		 1849 cmd == host->data_cmd) {
1850 /* Command complete before busy is ended */
6bde8681
AH		 1851 return;
1852 }
1853 }
1854
e89d456f 1855 /* Finished CMD23, now send actual command. */
a4c73aba 1856 if (cmd == cmd->mrq->sbc) {
845c939e
AH		 1857 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1858 WARN_ON(host->deferred_cmd);
1859 host->deferred_cmd = cmd->mrq->cmd;
1860 }
e89d456f 1861 } else {
e538fbe8 1862
e89d456f
AW		 1863 /* Processed actual command. */
1864 if (host->data && host->data_early)
1865 sdhci_finish_data(host);
d129bceb 1866
e0a5640a 1867 if (!cmd->data)
19d2f695 1868 __sdhci_finish_mrq(host, cmd->mrq);
e89d456f 1869 }
d129bceb
PO		 1870}
1871
52983382
KL		 1872static u16 sdhci_get_preset_value(struct sdhci_host *host)
1873{
d975f121 1874 u16 preset = 0;
52983382 1875
d975f121 1876 switch (host->timing) {
d0244847
AC		 1877 case MMC_TIMING_MMC_HS:
1878 case MMC_TIMING_SD_HS:
1879 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1880 break;
d975f121 1881 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1882 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1883 break;
d975f121 1884 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1885 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1886 break;
d975f121 1887 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1888 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1889 break;
d975f121
RK		 1890 case MMC_TIMING_UHS_SDR104:
1891 case MMC_TIMING_MMC_HS200:
52983382
KL		 1892 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1893 break;
d975f121 1894 case MMC_TIMING_UHS_DDR50:
0dafa60e 1895 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1896 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1897 break;
e9fb05d5
AH		 1898 case MMC_TIMING_MMC_HS400:
1899 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1900 break;
10c8298a
VS		 1901 case MMC_TIMING_UHS2_SPEED_A:
1902 case MMC_TIMING_UHS2_SPEED_A_HD:
1903 case MMC_TIMING_UHS2_SPEED_B:
1904 case MMC_TIMING_UHS2_SPEED_B_HD:
1905 preset = sdhci_readw(host, SDHCI_PRESET_FOR_UHS2);
1906 break;
52983382
KL		 1907 default:
1908 pr_warn("%s: Invalid UHS-I mode selected\n",
1909 mmc_hostname(host->mmc));
1910 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1911 break;
1912 }
1913 return preset;
1914}
1915
fb9ee047
LD		 1916u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1917 unsigned int *actual_clock)
d129bceb 1918{
c3ed3877 1919 int div = 0; /* Initialized for compiler warning */
df16219f 1920 int real_div = div, clk_mul = 1;
c3ed3877 1921 u16 clk = 0;
5497159c 1922 bool switch_base_clk = false;
d129bceb 1923
85105c53 1924 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1925 if (host->preset_enabled) {
52983382
KL		 1926 u16 pre_val;
1927
1928 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1929 pre_val = sdhci_get_preset_value(host);
fa091010 1930 div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
52983382 1931 if (host->clk_mul &&
fa091010 1932 (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
52983382
KL		 1933 clk = SDHCI_PROG_CLOCK_MODE;
1934 real_div = div + 1;
1935 clk_mul = host->clk_mul;
1936 } else {
1937 real_div = max_t(int, 1, div << 1);
1938 }
1939 goto clock_set;
1940 }
1941
c3ed3877
AN		 1942 /*
1943 * Check if the Host Controller supports Programmable Clock
1944 * Mode.
1945 */
1946 if (host->clk_mul) {
52983382
KL		 1947 for (div = 1; div <= 1024; div++) {
1948 if ((host->max_clk * host->clk_mul / div)
1949 <= clock)
1950 break;
1951 }
5497159c 1952 if ((host->max_clk * host->clk_mul / div) <= clock) {
1953 /*
1954 * Set Programmable Clock Mode in the Clock
1955 * Control register.
1956 */
1957 clk = SDHCI_PROG_CLOCK_MODE;
1958 real_div = div;
1959 clk_mul = host->clk_mul;
1960 div--;
1961 } else {
1962 /*
1963 * Divisor can be too small to reach clock
1964 * speed requirement. Then use the base clock.
1965 */
1966 switch_base_clk = true;
1967 }
1968 }
1969
1970 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1971 /* Version 3.00 divisors must be a multiple of 2. */
1972 if (host->max_clk <= clock)
1973 div = 1;
1974 else {
1975 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1976 div += 2) {
1977 if ((host->max_clk / div) <= clock)
1978 break;
1979 }
85105c53 1980 }
df16219f 1981 real_div = div;
c3ed3877 1982 div >>= 1;
d1955c3a
SG		 1983 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1984 && !div && host->max_clk <= 25000000)
1985 div = 1;
85105c53
ZG		 1986 }
1987 } else {
1988 /* Version 2.00 divisors must be a power of 2. */
0397526d 1989 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1990 if ((host->max_clk / div) <= clock)
1991 break;
1992 }
df16219f 1993 real_div = div;
c3ed3877 1994 div >>= 1;
d129bceb 1995 }
d129bceb 1996
52983382 1997clock_set:
03d6f5ff 1998 if (real_div)
fb9ee047 1999 *actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 2000 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 2001 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
2002 << SDHCI_DIVIDER_HI_SHIFT;
fb9ee047
LD		 2003
2004 return clk;
2005}
2006EXPORT_SYMBOL_GPL(sdhci_calc_clk);
2007
fec79673 2008void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
fb9ee047 2009{
5a436cc0 2010 ktime_t timeout;
fb9ee047 2011
d129bceb 2012 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 2013 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 2014
4a9e0d1a
BC		 2015 /* Wait max 150 ms */
2016 timeout = ktime_add_ms(ktime_get(), 150);
b704441e
AD		 2017 while (1) {
2018 bool timedout = ktime_after(ktime_get(), timeout);
2019
2020 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2021 if (clk & SDHCI_CLOCK_INT_STABLE)
2022 break;
2023 if (timedout) {
2e4456f0
MV		 2024 pr_err("%s: Internal clock never stabilised.\n",
2025 mmc_hostname(host->mmc));
efe8f5c9 2026 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
d129bceb
PO		 2027 sdhci_dumpregs(host);
2028 return;
2029 }
5a436cc0 2030 udelay(10);
7cb2c76f 2031 }
d129bceb 2032
1beabbdb
BC		 2033 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
2034 clk |= SDHCI_CLOCK_PLL_EN;
2035 clk &= ~SDHCI_CLOCK_INT_STABLE;
2036 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2037
2038 /* Wait max 150 ms */
2039 timeout = ktime_add_ms(ktime_get(), 150);
2040 while (1) {
2041 bool timedout = ktime_after(ktime_get(), timeout);
2042
2043 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2044 if (clk & SDHCI_CLOCK_INT_STABLE)
2045 break;
2046 if (timedout) {
2047 pr_err("%s: PLL clock never stabilised.\n",
2048 mmc_hostname(host->mmc));
efe8f5c9 2049 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
1beabbdb
BC		 2050 sdhci_dumpregs(host);
2051 return;
2052 }
2053 udelay(10);
2054 }
2055 }
2056
d129bceb 2057 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 2058 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 2059}
fec79673
RH		 2060EXPORT_SYMBOL_GPL(sdhci_enable_clk);
2061
2062void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
2063{
2064 u16 clk;
2065
2066 host->mmc->actual_clock = 0;
2067
dcc3bcfc 2068 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
fec79673 2069
dcc3bcfc 2070 if (clock == 0)
fec79673
RH		 2071 return;
2072
2073 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2074 sdhci_enable_clk(host, clk);
2075}
1771059c 2076EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 2077
1dceb041
AH		 2078static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2079 unsigned short vdd)
146ad66e 2080{
3a48edc4 2081 struct mmc_host *mmc = host->mmc;
1dceb041 2082
1dceb041 2083 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1dceb041
AH		 2084
2085 if (mode != MMC_POWER_OFF)
2086 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2087 else
2088 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2089}
2090
6eb2c8e1
VS		 2091unsigned short sdhci_get_vdd_value(unsigned short vdd)
2092{
2093 switch (1 << vdd) {
2094 case MMC_VDD_165_195:
2095 /*
2096 * Without a regulator, SDHCI does not support 2.0v
2097 * so we only get here if the driver deliberately
2098 * added the 2.0v range to ocr_avail. Map it to 1.8v
2099 * for the purpose of turning on the power.
2100 */
2101 case MMC_VDD_20_21:
2102 return SDHCI_POWER_180;
2103 case MMC_VDD_29_30:
2104 case MMC_VDD_30_31:
2105 return SDHCI_POWER_300;
2106 case MMC_VDD_32_33:
2107 case MMC_VDD_33_34:
2108 /*
2109 * 3.4V ~ 3.6V are valid only for those platforms where it's
2110 * known that the voltage range is supported by hardware.
2111 */
2112 case MMC_VDD_34_35:
2113 case MMC_VDD_35_36:
2114 return SDHCI_POWER_330;
2115 default:
2116 return 0;
2117 }
2118}
2119EXPORT_SYMBOL_GPL(sdhci_get_vdd_value);
2120
606d3131
AH		 2121void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2122 unsigned short vdd)
1dceb041 2123{
8364248a 2124 u8 pwr = 0;
146ad66e 2125
24fbb3ca 2126 if (mode != MMC_POWER_OFF) {
6eb2c8e1
VS		 2127 pwr = sdhci_get_vdd_value(vdd);
2128 if (!pwr) {
9d5de93f
AH		 2129 WARN(1, "%s: Invalid vdd %#x\n",
2130 mmc_hostname(host->mmc), vdd);
ae628903
PO		 2131 }
2132 }
2133
2134 if (host->pwr == pwr)
e921a8b6 2135 return;
146ad66e 2136
ae628903
PO		 2137 host->pwr = pwr;
2138
2139 if (pwr == 0) {
4e4141a5 2140 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 2141 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2142 sdhci_runtime_pm_bus_off(host);
e921a8b6
RK		 2143 } else {
2144 /*
2145 * Spec says that we should clear the power reg before setting
2146 * a new value. Some controllers don't seem to like this though.
2147 */
2148 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2149 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 2150
e921a8b6
RK		 2151 /*
2152 * At least the Marvell CaFe chip gets confused if we set the
2153 * voltage and set turn on power at the same time, so set the
2154 * voltage first.
2155 */
2156 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2157 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 2158
e921a8b6 2159 pwr |= SDHCI_POWER_ON;
146ad66e 2160
e921a8b6 2161 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 2162
e921a8b6
RK		 2163 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2164 sdhci_runtime_pm_bus_on(host);
f0710a55 2165
e921a8b6
RK		 2166 /*
2167 * Some controllers need an extra 10ms delay of 10ms before
2168 * they can apply clock after applying power
2169 */
2170 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2171 mdelay(10);
2172 }
1dceb041 2173}
606d3131 2174EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
918f4cbd 2175
606d3131
AH		 2176void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2177 unsigned short vdd)
1dceb041 2178{
606d3131
AH		 2179 if (IS_ERR(host->mmc->supply.vmmc))
2180 sdhci_set_power_noreg(host, mode, vdd);
1dceb041 2181 else
606d3131 2182 sdhci_set_power_reg(host, mode, vdd);
146ad66e 2183}
606d3131 2184EXPORT_SYMBOL_GPL(sdhci_set_power);
146ad66e 2185
6c92ae1e
NSJ		 2186/*
2187 * Some controllers need to configure a valid bus voltage on their power
2188 * register regardless of whether an external regulator is taking care of power
2189 * supply. This helper function takes care of it if set as the controller's
2190 * sdhci_ops.set_power callback.
2191 */
2192void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2193 unsigned char mode,
2194 unsigned short vdd)
2195{
2196 if (!IS_ERR(host->mmc->supply.vmmc)) {
2197 struct mmc_host *mmc = host->mmc;
2198
2199 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2200 }
2201 sdhci_set_power_noreg(host, mode, vdd);
2202}
2203EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
2204
d129bceb
PO		 2205/*****************************************************************************\
2206 * *
2207 * MMC callbacks *
2208 * *
2209\*****************************************************************************/
2210
d462c1b4 2211void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
d129bceb 2212{
e872f1e2
AH		 2213 struct sdhci_host *host = mmc_priv(mmc);
2214 struct mmc_command *cmd;
d129bceb 2215 unsigned long flags;
e872f1e2 2216 bool present;
d129bceb 2217
04e079cf 2218 /* Firstly check card presence */
8d28b7a7 2219 present = mmc->ops->get_cd(mmc);
2836766a 2220
d129bceb
PO		 2221 spin_lock_irqsave(&host->lock, flags);
2222
061d17a6 2223 sdhci_led_activate(host);
e89d456f 2224
e872f1e2
AH		 2225 if (sdhci_present_error(host, mrq->cmd, present))
2226 goto out_finish;
2227
2228 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2229
845c939e
AH		 2230 if (!sdhci_send_command_retry(host, cmd, flags))
2231 goto out_finish;
e872f1e2
AH		 2232
2233 spin_unlock_irqrestore(&host->lock, flags);
2234
2235 return;
d129bceb 2236
e872f1e2
AH		 2237out_finish:
2238 sdhci_finish_mrq(host, mrq);
d129bceb
PO		 2239 spin_unlock_irqrestore(&host->lock, flags);
2240}
d462c1b4 2241EXPORT_SYMBOL_GPL(sdhci_request);
d129bceb 2242
48ef8a2a
BW		 2243int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq)
2244{
2245 struct sdhci_host *host = mmc_priv(mmc);
2246 struct mmc_command *cmd;
2247 unsigned long flags;
2248 int ret = 0;
2249
2250 spin_lock_irqsave(&host->lock, flags);
2251
2252 if (sdhci_present_error(host, mrq->cmd, true)) {
2253 sdhci_finish_mrq(host, mrq);
2254 goto out_finish;
2255 }
2256
2257 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2258
2259 /*
2260 * The HSQ may send a command in interrupt context without polling
2261 * the busy signaling, which means we should return BUSY if controller
2262 * has not released inhibit bits to allow HSQ trying to send request
2263 * again in non-atomic context. So we should not finish this request
2264 * here.
2265 */
2266 if (!sdhci_send_command(host, cmd))
2267 ret = -EBUSY;
2268 else
2269 sdhci_led_activate(host);
2270
2271out_finish:
2272 spin_unlock_irqrestore(&host->lock, flags);
2273 return ret;
2274}
2275EXPORT_SYMBOL_GPL(sdhci_request_atomic);
2276
2317f56c
RK		 2277void sdhci_set_bus_width(struct sdhci_host *host, int width)
2278{
2279 u8 ctrl;
2280
2281 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2282 if (width == MMC_BUS_WIDTH_8) {
2283 ctrl &= ~SDHCI_CTRL_4BITBUS;
98f94ea6 2284 ctrl |= SDHCI_CTRL_8BITBUS;
2317f56c 2285 } else {
98f94ea6 2286 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2317f56c
RK		 2287 ctrl &= ~SDHCI_CTRL_8BITBUS;
2288 if (width == MMC_BUS_WIDTH_4)
2289 ctrl |= SDHCI_CTRL_4BITBUS;
2290 else
2291 ctrl &= ~SDHCI_CTRL_4BITBUS;
2292 }
2293 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2294}
2295EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2296
96d7b78c
RK		 2297void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2298{
2299 u16 ctrl_2;
2300
2301 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2302 /* Select Bus Speed Mode for host */
2303 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2304 if ((timing == MMC_TIMING_MMC_HS200) ||
2305 (timing == MMC_TIMING_UHS_SDR104))
2306 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2307 else if (timing == MMC_TIMING_UHS_SDR12)
2308 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
07bcc411 2309 else if (timing == MMC_TIMING_UHS_SDR25)
96d7b78c
RK		 2310 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2311 else if (timing == MMC_TIMING_UHS_SDR50)
2312 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2313 else if ((timing == MMC_TIMING_UHS_DDR50) ||
2314 (timing == MMC_TIMING_MMC_DDR52))
2315 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 2316 else if (timing == MMC_TIMING_MMC_HS400)
2317 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 2318 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2319}
2320EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2321
c981cdfb
AH		 2322static bool sdhci_timing_has_preset(unsigned char timing)
2323{
2324 switch (timing) {
2325 case MMC_TIMING_UHS_SDR12:
2326 case MMC_TIMING_UHS_SDR25:
2327 case MMC_TIMING_UHS_SDR50:
2328 case MMC_TIMING_UHS_SDR104:
2329 case MMC_TIMING_UHS_DDR50:
2330 case MMC_TIMING_MMC_DDR52:
2331 return true;
496182a3 2332 }
c981cdfb
AH		 2333 return false;
2334}
2335
2336static bool sdhci_preset_needed(struct sdhci_host *host, unsigned char timing)
2337{
2338 return !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2339 sdhci_timing_has_preset(timing);
2340}
2341
2342static bool sdhci_presetable_values_change(struct sdhci_host *host, struct mmc_ios *ios)
2343{
2344 /*
2345 * Preset Values are: Driver Strength, Clock Generator and SDCLK/RCLK
2346 * Frequency. Check if preset values need to be enabled, or the Driver
2347 * Strength needs updating. Note, clock changes are handled separately.
2348 */
2349 return !host->preset_enabled &&
2350 (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type);
2351}
2352
10c8298a 2353void sdhci_set_ios_common(struct mmc_host *mmc, struct mmc_ios *ios)
d129bceb 2354{
ded97e0b 2355 struct sdhci_host *host = mmc_priv(mmc);
1e72859e 2356
d129bceb
PO		 2357 /*
2358 * Reset the chip on each power off.
2359 * Should clear out any weird states.
2360 */
2361 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 2362 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 2363 sdhci_reinit(host);
d129bceb
PO		 2364 }
2365
52983382 2366 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 2367 (ios->power_mode == MMC_POWER_UP) &&
2368 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 2369 sdhci_enable_preset_value(host, false);
2370
373073ef 2371 if (!ios->clock || ios->clock != host->clock) {
1771059c 2372 host->ops->set_clock(host, ios->clock);
373073ef 2373 host->clock = ios->clock;
03d6f5ff
AD		 2374
2375 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2376 host->clock) {
d2f025b0
JZ		 2377 host->timeout_clk = mmc->actual_clock ?
2378 mmc->actual_clock / 1000 :
03d6f5ff 2379 host->clock / 1000;
d2f025b0 2380 mmc->max_busy_timeout =
03d6f5ff
AD		 2381 host->ops->get_max_timeout_count ?
2382 host->ops->get_max_timeout_count(host) :
2383 1 << 27;
d2f025b0 2384 mmc->max_busy_timeout /= host->timeout_clk;
03d6f5ff 2385 }
373073ef 2386 }
10c8298a
VS		 2387}
2388EXPORT_SYMBOL_GPL(sdhci_set_ios_common);
2389
2390void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2391{
2392 struct sdhci_host *host = mmc_priv(mmc);
2393 bool reinit_uhs = host->reinit_uhs;
2394 bool turning_on_clk;
2395 u8 ctrl;
2396
2397 host->reinit_uhs = false;
2398
2399 if (ios->power_mode == MMC_POWER_UNDEFINED)
2400 return;
2401
2402 if (host->flags & SDHCI_DEVICE_DEAD) {
2403 if (!IS_ERR(mmc->supply.vmmc) &&
2404 ios->power_mode == MMC_POWER_OFF)
2405 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2406 return;
2407 }
2408
2409 turning_on_clk = ios->clock != host->clock && ios->clock && !host->clock;
2410
2411 sdhci_set_ios_common(mmc, ios);
d129bceb 2412
606d3131
AH		 2413 if (host->ops->set_power)
2414 host->ops->set_power(host, ios->power_mode, ios->vdd);
2415 else
2416 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 2417
643a81ff
PR		 2418 if (host->ops->platform_send_init_74_clocks)
2419 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2420
2317f56c 2421 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 2422
c981cdfb
AH		 2423 /*
2424 * Special case to avoid multiple clock changes during voltage
2425 * switching.
2426 */
2427 if (!reinit_uhs &&
2428 turning_on_clk &&
2429 host->timing == ios->timing &&
2430 host->version >= SDHCI_SPEC_300 &&
2431 !sdhci_presetable_values_change(host, ios))
2432 return;
2433
15ec4461 2434 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 2435
501639bf 2436 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2437 if (ios->timing == MMC_TIMING_SD_HS ||
2438 ios->timing == MMC_TIMING_MMC_HS ||
2439 ios->timing == MMC_TIMING_MMC_HS400 ||
2440 ios->timing == MMC_TIMING_MMC_HS200 ||
2441 ios->timing == MMC_TIMING_MMC_DDR52 ||
2442 ios->timing == MMC_TIMING_UHS_SDR50 ||
2443 ios->timing == MMC_TIMING_UHS_SDR104 ||
2444 ios->timing == MMC_TIMING_UHS_DDR50 ||
2445 ios->timing == MMC_TIMING_UHS_SDR25)
2446 ctrl |= SDHCI_CTRL_HISPD;
2447 else
2448 ctrl &= ~SDHCI_CTRL_HISPD;
2449 }
cd9277c0 2450
d6d50a15 2451 if (host->version >= SDHCI_SPEC_300) {
49c468fc 2452 u16 clk, ctrl_2;
49c468fc 2453
beaba9e4
AH		 2454 /*
2455 * According to SDHCI Spec v3.00, if the Preset Value
2456 * Enable in the Host Control 2 register is set, we
2457 * need to reset SD Clock Enable before changing High
2458 * Speed Enable to avoid generating clock glitches.
2459 */
2460 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2461 if (clk & SDHCI_CLOCK_CARD_EN) {
2462 clk &= ~SDHCI_CLOCK_CARD_EN;
2463 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2464 }
2465
2466 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2467
da91a8f9 2468 if (!host->preset_enabled) {
d6d50a15
AN		 2469 /*
2470 * We only need to set Driver Strength if the
2471 * preset value enable is not set.
2472 */
da91a8f9 2473 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 2474 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2475 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2476 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 2477 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2478 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 2479 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2480 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 2481 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2482 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2483 else {
2e4456f0
MV		 2484 pr_warn("%s: invalid driver type, default to driver type B\n",
2485 mmc_hostname(mmc));
43e943a0
PG		 2486 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2487 }
d6d50a15
AN		 2488
2489 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
c981cdfb 2490 host->drv_type = ios->drv_type;
d6d50a15 2491 }
49c468fc 2492
96d7b78c 2493 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 2494 host->timing = ios->timing;
49c468fc 2495
c981cdfb 2496 if (sdhci_preset_needed(host, ios->timing)) {
52983382
KL		 2497 u16 preset;
2498
2499 sdhci_enable_preset_value(host, true);
2500 preset = sdhci_get_preset_value(host);
fa091010
MY		 2501 ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
2502 preset);
c981cdfb 2503 host->drv_type = ios->drv_type;
52983382
KL		 2504 }
2505
49c468fc 2506 /* Re-enable SD Clock */
1771059c 2507 host->ops->set_clock(host, host->clock);
758535c4
AN		 2508 } else
2509 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb 2510}
6a6d4ceb 2511EXPORT_SYMBOL_GPL(sdhci_set_ios);
d129bceb 2512
ded97e0b 2513static int sdhci_get_cd(struct mmc_host *mmc)
66fd8ad5
AH		 2514{
2515 struct sdhci_host *host = mmc_priv(mmc);
ded97e0b 2516 int gpio_cd = mmc_gpio_get_cd(mmc);
94144a46
KL		 2517
2518 if (host->flags & SDHCI_DEVICE_DEAD)
2519 return 0;
2520
88af5655 2521 /* If nonremovable, assume that the card is always present. */
d2f025b0 2522 if (!mmc_card_is_removable(mmc))
94144a46
KL		 2523 return 1;
2524
88af5655
II		 2525 /*
2526 * Try slot gpio detect, if defined it take precedence
2527 * over build in controller functionality
2528 */
287980e4 2529 if (gpio_cd >= 0)
94144a46
KL		 2530 return !!gpio_cd;
2531
88af5655
II		 2532 /* If polling, assume that the card is always present. */
2533 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2534 return 1;
2535
94144a46
KL		 2536 /* Host native card detect */
2537 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2538}
2539
2caa11bc
AS		 2540int sdhci_get_cd_nogpio(struct mmc_host *mmc)
2541{
2542 struct sdhci_host *host = mmc_priv(mmc);
2543 unsigned long flags;
2544 int ret = 0;
2545
2546 spin_lock_irqsave(&host->lock, flags);
2547
2548 if (host->flags & SDHCI_DEVICE_DEAD)
2549 goto out;
2550
2551 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2552out:
2553 spin_unlock_irqrestore(&host->lock, flags);
2554
2555 return ret;
2556}
2557EXPORT_SYMBOL_GPL(sdhci_get_cd_nogpio);
2558
254274cd 2559int sdhci_get_ro(struct mmc_host *mmc)
d129bceb 2560{
254274cd 2561 struct sdhci_host *host = mmc_priv(mmc);
fbd64f90 2562 bool allow_invert = false;
2dfb579c 2563 int is_readonly;
d129bceb 2564
fbd64f90 2565 if (host->flags & SDHCI_DEVICE_DEAD) {
2dfb579c 2566 is_readonly = 0;
fbd64f90 2567 } else if (host->ops->get_ro) {
2dfb579c 2568 is_readonly = host->ops->get_ro(host);
2e1a26ed 2569 } else if (mmc_host_can_gpio_ro(mmc)) {
254274cd 2570 is_readonly = mmc_gpio_get_ro(mmc);
fbd64f90 2571 /* Do not invert twice */
254274cd 2572 allow_invert = !(mmc->caps2 & MMC_CAP2_RO_ACTIVE_HIGH);
fbd64f90 2573 } else {
2dfb579c
WS		 2574 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2575 & SDHCI_WRITE_PROTECT);
fbd64f90
AH		 2576 allow_invert = true;
2577 }
d129bceb 2578
fbd64f90
AH		 2579 if (is_readonly >= 0 &&
2580 allow_invert &&
2581 (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT))
2582 is_readonly = !is_readonly;
2583
2584 return is_readonly;
d129bceb 2585}
254274cd 2586EXPORT_SYMBOL_GPL(sdhci_get_ro);
82b0e23a 2587
20758b66
AH		 2588static void sdhci_hw_reset(struct mmc_host *mmc)
2589{
2590 struct sdhci_host *host = mmc_priv(mmc);
2591
2592 if (host->ops && host->ops->hw_reset)
2593 host->ops->hw_reset(host);
2594}
2595
66fd8ad5
AH		 2596static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2597{
be138554 2598 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 2599 if (enable)
b537f94c 2600 host->ier |= SDHCI_INT_CARD_INT;
ef104333 2601 else
b537f94c
RK		 2602 host->ier &= ~SDHCI_INT_CARD_INT;
2603
2604 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2605 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333 2606 }
66fd8ad5
AH		 2607}
2608
2f05b6ab 2609void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
66fd8ad5
AH		 2610{
2611 struct sdhci_host *host = mmc_priv(mmc);
2612 unsigned long flags;
f75979b7 2613
923713b3 2614 if (enable)
bac53336 2615 pm_runtime_get_noresume(mmc_dev(mmc));
923713b3 2616
66fd8ad5
AH		 2617 spin_lock_irqsave(&host->lock, flags);
2618 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 2619 spin_unlock_irqrestore(&host->lock, flags);
923713b3
HG		 2620
2621 if (!enable)
bac53336 2622 pm_runtime_put_noidle(mmc_dev(mmc));
f75979b7 2623}
2f05b6ab 2624EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
f75979b7 2625
89f3c365
AH		 2626static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2627{
2628 struct sdhci_host *host = mmc_priv(mmc);
2629 unsigned long flags;
2630
2631 spin_lock_irqsave(&host->lock, flags);
a84ad324 2632 sdhci_enable_sdio_irq_nolock(host, true);
89f3c365
AH		 2633 spin_unlock_irqrestore(&host->lock, flags);
2634}
2635
c376ea9e
HZ		 2636int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2637 struct mmc_ios *ios)
f2119df6 2638{
ded97e0b 2639 struct sdhci_host *host = mmc_priv(mmc);
20b92a30 2640 u16 ctrl;
6231f3de 2641 int ret;
f2119df6 2642
20b92a30
KL		 2643 /*
2644 * Signal Voltage Switching is only applicable for Host Controllers
2645 * v3.00 and above.
2646 */
2647 if (host->version < SDHCI_SPEC_300)
2648 return 0;
6231f3de 2649
f2119df6 2650 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 2651
21f5998f 2652 switch (ios->signal_voltage) {
20b92a30 2653 case MMC_SIGNAL_VOLTAGE_330:
8cb851a4
AH		 2654 if (!(host->flags & SDHCI_SIGNALING_330))
2655 return -EINVAL;
20b92a30
KL		 2656 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2657 ctrl &= ~SDHCI_CTRL_VDD_180;
2658 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 2659
3a48edc4 2660 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 2661 ret = mmc_regulator_set_vqmmc(mmc, ios);
9cbe0fc8 2662 if (ret < 0) {
6606110d
JP		 2663 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2664 mmc_hostname(mmc));
20b92a30
KL		 2665 return -EIO;
2666 }
2667 }
2668 /* Wait for 5ms */
2669 usleep_range(5000, 5500);
f2119df6 2670
20b92a30
KL		 2671 /* 3.3V regulator output should be stable within 5 ms */
2672 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2673 if (!(ctrl & SDHCI_CTRL_VDD_180))
2674 return 0;
6231f3de 2675
b0b19ce6 2676 pr_warn("%s: 3.3V regulator output did not become stable\n",
6606110d 2677 mmc_hostname(mmc));
20b92a30
KL		 2678
2679 return -EAGAIN;
2680 case MMC_SIGNAL_VOLTAGE_180:
8cb851a4
AH		 2681 if (!(host->flags & SDHCI_SIGNALING_180))
2682 return -EINVAL;
3a48edc4 2683 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 2684 ret = mmc_regulator_set_vqmmc(mmc, ios);
9cbe0fc8 2685 if (ret < 0) {
6606110d
JP		 2686 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2687 mmc_hostname(mmc));
20b92a30
KL		 2688 return -EIO;
2689 }
2690 }
6231f3de 2691
6231f3de
PR		 2692 /*
2693 * Enable 1.8V Signal Enable in the Host Control2
2694 * register
2695 */
20b92a30
KL		 2696 ctrl |= SDHCI_CTRL_VDD_180;
2697 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 2698
9d967a61
VY		 2699 /* Some controller need to do more when switching */
2700 if (host->ops->voltage_switch)
2701 host->ops->voltage_switch(host);
2702
20b92a30
KL		 2703 /* 1.8V regulator output should be stable within 5 ms */
2704 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2705 if (ctrl & SDHCI_CTRL_VDD_180)
2706 return 0;
f2119df6 2707
b0b19ce6 2708 pr_warn("%s: 1.8V regulator output did not become stable\n",
6606110d 2709 mmc_hostname(mmc));
f2119df6 2710
20b92a30
KL		 2711 return -EAGAIN;
2712 case MMC_SIGNAL_VOLTAGE_120:
8cb851a4
AH		 2713 if (!(host->flags & SDHCI_SIGNALING_120))
2714 return -EINVAL;
3a48edc4 2715 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 2716 ret = mmc_regulator_set_vqmmc(mmc, ios);
9cbe0fc8 2717 if (ret < 0) {
6606110d
JP		 2718 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2719 mmc_hostname(mmc));
20b92a30 2720 return -EIO;
f2119df6
AN		 2721 }
2722 }
6231f3de 2723 return 0;
20b92a30 2724 default:
f2119df6
AN		 2725 /* No signal voltage switch required */
2726 return 0;
20b92a30 2727 }
f2119df6 2728}
c376ea9e 2729EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
f2119df6 2730
20b92a30
KL		 2731static int sdhci_card_busy(struct mmc_host *mmc)
2732{
2733 struct sdhci_host *host = mmc_priv(mmc);
2734 u32 present_state;
2735
e613cc47 2736 /* Check whether DAT[0] is 0 */
20b92a30 2737 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
20b92a30 2738
e613cc47 2739 return !(present_state & SDHCI_DATA_0_LVL_MASK);
20b92a30
KL		 2740}
2741
b5540ce1
AH		 2742static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2743{
2744 struct sdhci_host *host = mmc_priv(mmc);
2745 unsigned long flags;
2746
2747 spin_lock_irqsave(&host->lock, flags);
2748 host->flags |= SDHCI_HS400_TUNING;
2749 spin_unlock_irqrestore(&host->lock, flags);
2750
2751 return 0;
2752}
2753
6663c419 2754void sdhci_start_tuning(struct sdhci_host *host)
da4bc4f2
AH		 2755{
2756 u16 ctrl;
2757
2758 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2759 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2760 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2761 ctrl |= SDHCI_CTRL_TUNED_CLK;
2762 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2763
2764 /*
2765 * As per the Host Controller spec v3.00, tuning command
2766 * generates Buffer Read Ready interrupt, so enable that.
2767 *
2768 * Note: The spec clearly says that when tuning sequence
2769 * is being performed, the controller does not generate
2770 * interrupts other than Buffer Read Ready interrupt. But
2771 * to make sure we don't hit a controller bug, we _only_
2772 * enable Buffer Read Ready interrupt here.
2773 */
2774 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2775 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2776}
6663c419 2777EXPORT_SYMBOL_GPL(sdhci_start_tuning);
da4bc4f2 2778
6663c419 2779void sdhci_end_tuning(struct sdhci_host *host)
da4bc4f2
AH		 2780{
2781 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2782 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2783}
6663c419 2784EXPORT_SYMBOL_GPL(sdhci_end_tuning);
da4bc4f2 2785
6663c419 2786void sdhci_reset_tuning(struct sdhci_host *host)
da4bc4f2
AH		 2787{
2788 u16 ctrl;
2789
2790 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2791 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2792 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2793 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2794}
6663c419 2795EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
da4bc4f2 2796
7353788c 2797void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
da4bc4f2
AH		 2798{
2799 sdhci_reset_tuning(host);
2800
1e63d297 2801 sdhci_reset_for(host, TUNING_ABORT);
da4bc4f2
AH		 2802
2803 sdhci_end_tuning(host);
2804
21adc2e4 2805 mmc_send_abort_tuning(host->mmc, opcode);
da4bc4f2 2806}
7353788c 2807EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
da4bc4f2
AH		 2808
2809/*
2810 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2811 * tuning command does not have a data payload (or rather the hardware does it
2812 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2813 * interrupt setup is different to other commands and there is no timeout
2814 * interrupt so special handling is needed.
2815 */
6663c419 2816void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
da4bc4f2
AH		 2817{
2818 struct mmc_host *mmc = host->mmc;
c7836d15
MY		 2819 struct mmc_command cmd = {};
2820 struct mmc_request mrq = {};
2a85ef25 2821 unsigned long flags;
c846a00f 2822 u32 b = host->sdma_boundary;
2a85ef25
AH		 2823
2824 spin_lock_irqsave(&host->lock, flags);
da4bc4f2
AH		 2825
2826 cmd.opcode = opcode;
2827 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2828 cmd.mrq = &mrq;
2829
2830 mrq.cmd = &cmd;
2831 /*
2832 * In response to CMD19, the card sends 64 bytes of tuning
2833 * block to the Host Controller. So we set the block size
2834 * to 64 here.
2835 */
85336109
AH		 2836 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2837 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
c846a00f 2838 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
85336109 2839 else
c846a00f 2840 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
da4bc4f2
AH		 2841
2842 /*
2843 * The tuning block is sent by the card to the host controller.
2844 * So we set the TRNS_READ bit in the Transfer Mode register.
2845 * This also takes care of setting DMA Enable and Multi Block
2846 * Select in the same register to 0.
2847 */
2848 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2849
845c939e
AH		 2850 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2851 spin_unlock_irqrestore(&host->lock, flags);
2852 host->tuning_done = 0;
2853 return;
2854 }
da4bc4f2
AH		 2855
2856 host->cmd = NULL;
2857
2858 sdhci_del_timer(host, &mrq);
2859
2860 host->tuning_done = 0;
2861
2862 spin_unlock_irqrestore(&host->lock, flags);
2863
2864 /* Wait for Buffer Read Ready interrupt */
2865 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2866 msecs_to_jiffies(50));
2867
da4bc4f2 2868}
6663c419 2869EXPORT_SYMBOL_GPL(sdhci_send_tuning);
da4bc4f2 2870
9cc811a3 2871int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
6b11e70b
AH		 2872{
2873 int i;
2874
2875 /*
2876 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
1d8cd065 2877 * of loops reaches tuning loop count.
6b11e70b 2878 */
1d8cd065 2879 for (i = 0; i < host->tuning_loop_count; i++) {
6b11e70b
AH		 2880 u16 ctrl;
2881
2a85ef25 2882 sdhci_send_tuning(host, opcode);
6b11e70b
AH		 2883
2884 if (!host->tuning_done) {
811ba676
FA		 2885 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2886 mmc_hostname(host->mmc));
2a85ef25 2887 sdhci_abort_tuning(host, opcode);
7d8bb1f4 2888 return -ETIMEDOUT;
6b11e70b
AH		 2889 }
2890
2b06e159
BC		 2891 /* Spec does not require a delay between tuning cycles */
2892 if (host->tuning_delay > 0)
2893 mdelay(host->tuning_delay);
2894
6b11e70b
AH		 2895 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2896 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2897 if (ctrl & SDHCI_CTRL_TUNED_CLK)
7d8bb1f4 2898 return 0; /* Success! */
6b11e70b
AH		 2899 break;
2900 }
2901
6b11e70b
AH		 2902 }
2903
2904 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2905 mmc_hostname(host->mmc));
2906 sdhci_reset_tuning(host);
7d8bb1f4 2907 return -EAGAIN;
6b11e70b 2908}
9cc811a3 2909EXPORT_SYMBOL_GPL(__sdhci_execute_tuning);
6b11e70b 2910
85a882c2 2911int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 2912{
4b6f37d3 2913 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 2914 int err = 0;
38e40bf5 2915 unsigned int tuning_count = 0;
b5540ce1 2916 bool hs400_tuning;
b513ea25 2917
b5540ce1 2918 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
b5540ce1 2919
38e40bf5
AH		 2920 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2921 tuning_count = host->tuning_count;
2922
b513ea25 2923 /*
9faac7b9
WY		 2924 * The Host Controller needs tuning in case of SDR104 and DDR50
2925 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2926 * the Capabilities register.
069c9f14
G		 2927 * If the Host Controller supports the HS200 mode then the
2928 * tuning function has to be executed.
b513ea25 2929 */
4b6f37d3 2930 switch (host->timing) {
b5540ce1 2931 /* HS400 tuning is done in HS200 mode */
e9fb05d5 2932 case MMC_TIMING_MMC_HS400:
b5540ce1 2933 err = -EINVAL;
2a85ef25 2934 goto out;
b5540ce1 2935
4b6f37d3 2936 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 2937 /*
2938 * Periodic re-tuning for HS400 is not expected to be needed, so
2939 * disable it here.
2940 */
2941 if (hs400_tuning)
2942 tuning_count = 0;
2943 break;
2944
4b6f37d3 2945 case MMC_TIMING_UHS_SDR104:
9faac7b9 2946 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 2947 break;
2948
2949 case MMC_TIMING_UHS_SDR50:
4228b213 2950 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
4b6f37d3 2951 break;
df561f66 2952 fallthrough;
4b6f37d3
RK		 2953
2954 default:
2a85ef25 2955 goto out;
b513ea25
AN		 2956 }
2957
45251812 2958 if (host->ops->platform_execute_tuning) {
8a8fa879 2959 err = host->ops->platform_execute_tuning(host, opcode);
2a85ef25 2960 goto out;
45251812
DA		 2961 }
2962
d2f025b0 2963 mmc->retune_period = tuning_count;
b513ea25 2964
83b600b8
AH		 2965 if (host->tuning_delay < 0)
2966 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2967
6b11e70b 2968 sdhci_start_tuning(host);
da4bc4f2 2969
7d8bb1f4 2970 host->tuning_err = __sdhci_execute_tuning(host, opcode);
cf2b5eea 2971
da4bc4f2 2972 sdhci_end_tuning(host);
2a85ef25 2973out:
8a8fa879 2974 host->flags &= ~SDHCI_HS400_TUNING;
6b11e70b 2975
b513ea25
AN		 2976 return err;
2977}
85a882c2 2978EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
b513ea25 2979
10c8298a 2980void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2981{
4d55c5a1
AN		 2982 /* Host Controller v3.00 defines preset value registers */
2983 if (host->version < SDHCI_SPEC_300)
2984 return;
2985
4d55c5a1
AN		 2986 /*
2987 * We only enable or disable Preset Value if they are not already
2988 * enabled or disabled respectively. Otherwise, we bail out.
2989 */
da91a8f9
RK		 2990 if (host->preset_enabled != enable) {
2991 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2992
2993 if (enable)
2994 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2995 else
2996 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2997
4d55c5a1 2998 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2999
3000 if (enable)
3001 host->flags |= SDHCI_PV_ENABLED;
3002 else
3003 host->flags &= ~SDHCI_PV_ENABLED;
3004
3005 host->preset_enabled = enable;
4d55c5a1 3006 }
66fd8ad5 3007}
10c8298a 3008EXPORT_SYMBOL_GPL(sdhci_enable_preset_value);
66fd8ad5 3009
348487cb
HC		 3010static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
3011 int err)
3012{
348487cb
HC		 3013 struct mmc_data *data = mrq->data;
3014
f48f039c 3015 if (data->host_cookie != COOKIE_UNMAPPED)
d2f025b0 3016 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
feeef096 3017 mmc_get_dma_dir(data));
771a3dc2
RK		 3018
3019 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 3020}
3021
d3c6aac3 3022static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
348487cb
HC		 3023{
3024 struct sdhci_host *host = mmc_priv(mmc);
3025
d31911b9 3026 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb 3027
bd9b9027
LW		 3028 /*
3029 * No pre-mapping in the pre hook if we're using the bounce buffer,
3030 * for that we would need two bounce buffers since one buffer is
3031 * in flight when this is getting called.
3032 */
3033 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
94538e51 3034 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 3035}
3036
5d0d11c5
AH		 3037static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
3038{
3039 if (host->data_cmd) {
3040 host->data_cmd->error = err;
3041 sdhci_finish_mrq(host, host->data_cmd->mrq);
3042 }
3043
3044 if (host->cmd) {
3045 host->cmd->error = err;
3046 sdhci_finish_mrq(host, host->cmd->mrq);
3047 }
3048}
3049
71e69211 3050static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 3051{
71e69211 3052 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 3053 unsigned long flags;
2836766a 3054 int present;
d129bceb 3055
722e1280
CD		 3056 /* First check if client has provided their own card event */
3057 if (host->ops->card_event)
3058 host->ops->card_event(host);
3059
d3940f27 3060 present = mmc->ops->get_cd(mmc);
2836766a 3061
d129bceb
PO		 3062 spin_lock_irqsave(&host->lock, flags);
3063
5d0d11c5
AH		 3064 /* Check sdhci_has_requests() first in case we are runtime suspended */
3065 if (sdhci_has_requests(host) && !present) {
a3c76eb9 3066 pr_err("%s: Card removed during transfer!\n",
d2f025b0 3067 mmc_hostname(mmc));
a3c76eb9 3068 pr_err("%s: Resetting controller.\n",
d2f025b0 3069 mmc_hostname(mmc));
d129bceb 3070
1e63d297 3071 sdhci_reset_for(host, CARD_REMOVED);
d129bceb 3072
5d0d11c5 3073 sdhci_error_out_mrqs(host, -ENOMEDIUM);
d129bceb
PO		 3074 }
3075
3076 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 3077}
3078
3079static const struct mmc_host_ops sdhci_ops = {
3080 .request = sdhci_request,
348487cb
HC		 3081 .post_req = sdhci_post_req,
3082 .pre_req = sdhci_pre_req,
71e69211 3083 .set_ios = sdhci_set_ios,
94144a46 3084 .get_cd = sdhci_get_cd,
71e69211 3085 .get_ro = sdhci_get_ro,
32f18e59 3086 .card_hw_reset = sdhci_hw_reset,
71e69211 3087 .enable_sdio_irq = sdhci_enable_sdio_irq,
89f3c365 3088 .ack_sdio_irq = sdhci_ack_sdio_irq,
71e69211 3089 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 3090 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 3091 .execute_tuning = sdhci_execute_tuning,
71e69211 3092 .card_event = sdhci_card_event,
20b92a30 3093 .card_busy = sdhci_card_busy,
71e69211
GL		 3094};
3095
3096/*****************************************************************************\
3097 * *
c07a48c2 3098 * Request done *
71e69211
GL		 3099 * *
3100\*****************************************************************************/
3101
fca267f0
VS		 3102void sdhci_request_done_dma(struct sdhci_host *host, struct mmc_request *mrq)
3103{
3104 struct mmc_data *data = mrq->data;
3105
3106 if (data && data->host_cookie == COOKIE_MAPPED) {
3107 if (host->bounce_buffer) {
3108 /*
3109 * On reads, copy the bounced data into the
3110 * sglist
3111 */
3112 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
3113 unsigned int length = data->bytes_xfered;
3114
3115 if (length > host->bounce_buffer_size) {
3116 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
3117 mmc_hostname(host->mmc),
3118 host->bounce_buffer_size,
3119 data->bytes_xfered);
3120 /* Cap it down and continue */
3121 length = host->bounce_buffer_size;
3122 }
3123 dma_sync_single_for_cpu(mmc_dev(host->mmc),
3124 host->bounce_addr,
3125 host->bounce_buffer_size,
3126 DMA_FROM_DEVICE);
3127 sg_copy_from_buffer(data->sg,
3128 data->sg_len,
3129 host->bounce_buffer,
3130 length);
3131 } else {
3132 /* No copying, just switch ownership */
3133 dma_sync_single_for_cpu(mmc_dev(host->mmc),
3134 host->bounce_addr,
3135 host->bounce_buffer_size,
3136 mmc_get_dma_dir(data));
3137 }
3138 } else {
3139 /* Unmap the raw data */
3140 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3141 data->sg_len,
3142 mmc_get_dma_dir(data));
3143 }
3144 data->host_cookie = COOKIE_UNMAPPED;
3145 }
3146}
3147EXPORT_SYMBOL_GPL(sdhci_request_done_dma);
3148
4e9f8fe5 3149static bool sdhci_request_done(struct sdhci_host *host)
d129bceb 3150{
d129bceb
PO		 3151 unsigned long flags;
3152 struct mmc_request *mrq;
4e9f8fe5 3153 int i;
d129bceb 3154
66fd8ad5
AH		 3155 spin_lock_irqsave(&host->lock, flags);
3156
4e9f8fe5
AH		 3157 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3158 mrq = host->mrqs_done[i];
6ebebeab 3159 if (mrq)
4e9f8fe5 3160 break;
66fd8ad5 3161 }
d129bceb 3162
4e9f8fe5
AH		 3163 if (!mrq) {
3164 spin_unlock_irqrestore(&host->lock, flags);
3165 return true;
3166 }
d129bceb 3167
21e35e89
P		 3168 /*
3169 * The controller needs a reset of internal state machines
3170 * upon error conditions.
3171 */
3172 if (sdhci_needs_reset(host, mrq)) {
3173 /*
3174 * Do not finish until command and data lines are available for
3175 * reset. Note there can only be one other mrq, so it cannot
3176 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3177 * would both be null.
3178 */
3179 if (host->cmd || host->data_cmd) {
3180 spin_unlock_irqrestore(&host->lock, flags);
3181 return true;
3182 }
3183
3184 /* Some controllers need this kick or reset won't work here */
3185 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3186 /* This is to force an update */
3187 host->ops->set_clock(host, host->clock);
3188
1e63d297 3189 sdhci_reset_for(host, REQUEST_ERROR);
21e35e89
P		 3190
3191 host->pending_reset = false;
3192 }
3193
054cedff
RK		 3194 /*
3195 * Always unmap the data buffers if they were mapped by
3196 * sdhci_prepare_data() whenever we finish with a request.
3197 * This avoids leaking DMA mappings on error.
3198 */
3199 if (host->flags & SDHCI_REQ_USE_DMA) {
3200 struct mmc_data *data = mrq->data;
3201
18e762e3
CZ		 3202 if (host->use_external_dma && data &&
3203 (mrq->cmd->error || data->error)) {
3204 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3205
3206 host->mrqs_done[i] = NULL;
3207 spin_unlock_irqrestore(&host->lock, flags);
3208 dmaengine_terminate_sync(chan);
3209 spin_lock_irqsave(&host->lock, flags);
3210 sdhci_set_mrq_done(host, mrq);
3211 }
3212
fca267f0 3213 sdhci_request_done_dma(host, mrq);
054cedff
RK		 3214 }
3215
6ebebeab
AH		 3216 host->mrqs_done[i] = NULL;
3217
d129bceb
PO		 3218 spin_unlock_irqrestore(&host->lock, flags);
3219
1774b002
BW		 3220 if (host->ops->request_done)
3221 host->ops->request_done(host, mrq);
3222 else
3223 mmc_request_done(host->mmc, mrq);
4e9f8fe5
AH		 3224
3225 return false;
3226}
3227
fca267f0 3228void sdhci_complete_work(struct work_struct *work)
4e9f8fe5 3229{
c07a48c2
AH		 3230 struct sdhci_host *host = container_of(work, struct sdhci_host,
3231 complete_work);
4e9f8fe5
AH		 3232
3233 while (!sdhci_request_done(host))
3234 ;
d129bceb 3235}
fca267f0 3236EXPORT_SYMBOL_GPL(sdhci_complete_work);
d129bceb 3237
2ee4f620 3238static void sdhci_timeout_timer(struct timer_list *t)
d129bceb
PO		 3239{
3240 struct sdhci_host *host;
3241 unsigned long flags;
3242
41cb0855 3243 host = timer_container_of(host, t, timer);
d129bceb
PO		 3244
3245 spin_lock_irqsave(&host->lock, flags);
3246
d7422fb4
AH		 3247 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3248 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
3249 mmc_hostname(host->mmc));
efe8f5c9 3250 sdhci_err_stats_inc(host, REQ_TIMEOUT);
d7422fb4
AH		 3251 sdhci_dumpregs(host);
3252
3253 host->cmd->error = -ETIMEDOUT;
3254 sdhci_finish_mrq(host, host->cmd->mrq);
3255 }
3256
d7422fb4
AH		 3257 spin_unlock_irqrestore(&host->lock, flags);
3258}
3259
2ee4f620 3260static void sdhci_timeout_data_timer(struct timer_list *t)
d7422fb4
AH		 3261{
3262 struct sdhci_host *host;
3263 unsigned long flags;
3264
41cb0855 3265 host = timer_container_of(host, t, data_timer);
d7422fb4
AH		 3266
3267 spin_lock_irqsave(&host->lock, flags);
3268
3269 if (host->data || host->data_cmd ||
3270 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2e4456f0
MV		 3271 pr_err("%s: Timeout waiting for hardware interrupt.\n",
3272 mmc_hostname(host->mmc));
efe8f5c9 3273 sdhci_err_stats_inc(host, REQ_TIMEOUT);
d129bceb
PO		 3274 sdhci_dumpregs(host);
3275
3276 if (host->data) {
17b0429d 3277 host->data->error = -ETIMEDOUT;
845c939e 3278 __sdhci_finish_data(host, true);
c07a48c2 3279 queue_work(host->complete_wq, &host->complete_work);
d7422fb4
AH		 3280 } else if (host->data_cmd) {
3281 host->data_cmd->error = -ETIMEDOUT;
3282 sdhci_finish_mrq(host, host->data_cmd->mrq);
d129bceb 3283 } else {
d7422fb4
AH		 3284 host->cmd->error = -ETIMEDOUT;
3285 sdhci_finish_mrq(host, host->cmd->mrq);
d129bceb
PO		 3286 }
3287 }
3288
3289 spin_unlock_irqrestore(&host->lock, flags);
3290}
3291
3292/*****************************************************************************\
3293 * *
3294 * Interrupt handling *
3295 * *
3296\*****************************************************************************/
3297
4bf78099 3298static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
d129bceb 3299{
af849c86
AH		 3300 /* Handle auto-CMD12 error */
3301 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3302 struct mmc_request *mrq = host->data_cmd->mrq;
3303 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3304 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3305 SDHCI_INT_DATA_TIMEOUT :
3306 SDHCI_INT_DATA_CRC;
3307
3308 /* Treat auto-CMD12 error the same as data error */
3309 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3310 *intmask_p |= data_err_bit;
3311 return;
3312 }
3313 }
3314
d129bceb 3315 if (!host->cmd) {
ed1563de
AH		 3316 /*
3317 * SDHCI recovers from errors by resetting the cmd and data
3318 * circuits. Until that is done, there very well might be more
3319 * interrupts, so ignore them in that case.
3320 */
3321 if (host->pending_reset)
3322 return;
2e4456f0
MV		 3323 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3324 mmc_hostname(host->mmc), (unsigned)intmask);
efe8f5c9 3325 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
d129bceb
PO		 3326 sdhci_dumpregs(host);
3327 return;
3328 }
3329
ec014cba
RK		 3330 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3331 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
efe8f5c9 3332 if (intmask & SDHCI_INT_TIMEOUT) {
ec014cba 3333 host->cmd->error = -ETIMEDOUT;
efe8f5c9
SSB		 3334 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3335 } else {
ec014cba 3336 host->cmd->error = -EILSEQ;
efe8f5c9
SSB		 3337 if (!mmc_op_tuning(host->cmd->opcode))
3338 sdhci_err_stats_inc(host, CMD_CRC);
3339 }
4bf78099 3340 /* Treat data command CRC error the same as data CRC error */
71fcbda0
RK		 3341 if (host->cmd->data &&
3342 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3343 SDHCI_INT_CRC) {
3344 host->cmd = NULL;
4bf78099 3345 *intmask_p |= SDHCI_INT_DATA_CRC;
71fcbda0
RK		 3346 return;
3347 }
3348
19d2f695 3349 __sdhci_finish_mrq(host, host->cmd->mrq);
e809517f
PO		 3350 return;
3351 }
3352
af849c86
AH		 3353 /* Handle auto-CMD23 error */
3354 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3355 struct mmc_request *mrq = host->cmd->mrq;
3356 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3357 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3358 -ETIMEDOUT :
3359 -EILSEQ;
3360
efe8f5c9
SSB		 3361 sdhci_err_stats_inc(host, AUTO_CMD);
3362
38929d4f 3363 if (sdhci_auto_cmd23(host, mrq)) {
af849c86 3364 mrq->sbc->error = err;
19d2f695 3365 __sdhci_finish_mrq(host, mrq);
af849c86
AH		 3366 return;
3367 }
3368 }
3369
e809517f 3370 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 3371 sdhci_finish_command(host);
d129bceb
PO		 3372}
3373
08621b18 3374static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0 3375{
1c3d5f6d 3376 void *desc = host->adma_table;
d1c536e3 3377 dma_addr_t dma = host->adma_addr;
6882a8c0
BD		 3378
3379 sdhci_dumpregs(host);
3380
3381 while (true) {
e57a5f61
AH		 3382 struct sdhci_adma2_64_desc *dma_desc = desc;
3383
3384 if (host->flags & SDHCI_USE_64_BIT_DMA)
d1c536e3
RK		 3385 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3386 (unsigned long long)dma,
3387 le32_to_cpu(dma_desc->addr_hi),
e57a5f61
AH		 3388 le32_to_cpu(dma_desc->addr_lo),
3389 le16_to_cpu(dma_desc->len),
3390 le16_to_cpu(dma_desc->cmd));
3391 else
d1c536e3
RK		 3392 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3393 (unsigned long long)dma,
3394 le32_to_cpu(dma_desc->addr_lo),
e57a5f61
AH		 3395 le16_to_cpu(dma_desc->len),
3396 le16_to_cpu(dma_desc->cmd));
6882a8c0 3397
76fe379a 3398 desc += host->desc_sz;
d1c536e3 3399 dma += host->desc_sz;
6882a8c0 3400
0545230f 3401 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 3402 break;
3403 }
3404}
6882a8c0 3405
d129bceb
PO		 3406static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3407{
f4ff24f8
HC		 3408 /*
3409 * CMD19 generates _only_ Buffer Read Ready interrupt if
3410 * use sdhci_send_tuning.
3411 * Need to exclude this case: PIO mode and use mmc_send_tuning,
3412 * If not, sdhci_transfer_pio will never be called, make the
3413 * SDHCI_INT_DATA_AVAIL always there, stuck in irq storm.
3414 */
3415 if (intmask & SDHCI_INT_DATA_AVAIL && !host->data) {
b98e7e8d 3416 if (mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)))) {
b513ea25
AN		 3417 host->tuning_done = 1;
3418 wake_up(&host->buf_ready_int);
3419 return;
3420 }
3421 }
3422
d129bceb 3423 if (!host->data) {
7c89a3d9
AH		 3424 struct mmc_command *data_cmd = host->data_cmd;
3425
d129bceb 3426 /*
e809517f
PO		 3427 * The "data complete" interrupt is also used to
3428 * indicate that a busy state has ended. See comment
3429 * above in sdhci_cmd_irq().
d129bceb 3430 */
7c89a3d9 3431 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8 3432 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
69b962a6 3433 host->data_cmd = NULL;
7c89a3d9 3434 data_cmd->error = -ETIMEDOUT;
efe8f5c9 3435 sdhci_err_stats_inc(host, CMD_TIMEOUT);
19d2f695 3436 __sdhci_finish_mrq(host, data_cmd->mrq);
c5abd5e8
MC		 3437 return;
3438 }
e809517f 3439 if (intmask & SDHCI_INT_DATA_END) {
69b962a6 3440 host->data_cmd = NULL;
e99783a4
CM		 3441 /*
3442 * Some cards handle busy-end interrupt
3443 * before the command completed, so make
3444 * sure we do things in the proper order.
3445 */
ea968023
AH		 3446 if (host->cmd == data_cmd)
3447 return;
3448
19d2f695 3449 __sdhci_finish_mrq(host, data_cmd->mrq);
e809517f
PO		 3450 return;
3451 }
3452 }
d129bceb 3453
ed1563de
AH		 3454 /*
3455 * SDHCI recovers from errors by resetting the cmd and data
3456 * circuits. Until that is done, there very well might be more
3457 * interrupts, so ignore them in that case.
3458 */
3459 if (host->pending_reset)
3460 return;
3461
2e4456f0
MV		 3462 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3463 mmc_hostname(host->mmc), (unsigned)intmask);
efe8f5c9 3464 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
d129bceb
PO		 3465 sdhci_dumpregs(host);
3466
3467 return;
3468 }
3469
efe8f5c9 3470 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
17b0429d 3471 host->data->error = -ETIMEDOUT;
efe8f5c9
SSB		 3472 sdhci_err_stats_inc(host, DAT_TIMEOUT);
3473 } else if (intmask & SDHCI_INT_DATA_END_BIT) {
22113efd 3474 host->data->error = -EILSEQ;
efe8f5c9
SSB		 3475 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3476 sdhci_err_stats_inc(host, DAT_CRC);
b3855668 3477 } else if ((intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_TUNING_ERROR)) &&
22113efd 3478 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
efe8f5c9 3479 != MMC_BUS_TEST_R) {
17b0429d 3480 host->data->error = -EILSEQ;
efe8f5c9
SSB		 3481 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3482 sdhci_err_stats_inc(host, DAT_CRC);
b3855668
AH		 3483 if (intmask & SDHCI_INT_TUNING_ERROR) {
3484 u16 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
3485
3486 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
3487 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
3488 }
efe8f5c9 3489 } else if (intmask & SDHCI_INT_ADMA_ERROR) {
d1c536e3
RK		 3490 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3491 intmask);
08621b18 3492 sdhci_adma_show_error(host);
efe8f5c9 3493 sdhci_err_stats_inc(host, ADMA);
2134a922 3494 host->data->error = -EIO;
a4071fbb
HZ		 3495 if (host->ops->adma_workaround)
3496 host->ops->adma_workaround(host, intmask);
6882a8c0 3497 }
d129bceb 3498
17b0429d 3499 if (host->data->error)
d129bceb
PO		 3500 sdhci_finish_data(host);
3501 else {
a406f5a3 3502 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 3503 sdhci_transfer_pio(host);
3504
6ba736a1
PO		 3505 /*
3506 * We currently don't do anything fancy with DMA
3507 * boundaries, but as we can't disable the feature
3508 * we need to at least restart the transfer.
f6a03cbf
MV		 3509 *
3510 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3511 * should return a valid address to continue from, but as
3512 * some controllers are faulty, don't trust them.
6ba736a1 3513 */
f6a03cbf 3514 if (intmask & SDHCI_INT_DMA_END) {
917a0c52 3515 dma_addr_t dmastart, dmanow;
bd9b9027
LW		 3516
3517 dmastart = sdhci_sdma_address(host);
f6a03cbf
MV		 3518 dmanow = dmastart + host->data->bytes_xfered;
3519 /*
3520 * Force update to the next DMA block boundary.
3521 */
3522 dmanow = (dmanow &
917a0c52 3523 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
f6a03cbf
MV		 3524 SDHCI_DEFAULT_BOUNDARY_SIZE;
3525 host->data->bytes_xfered = dmanow - dmastart;
917a0c52
CZ		 3526 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3527 &dmastart, host->data->bytes_xfered, &dmanow);
3528 sdhci_set_sdma_addr(host, dmanow);
f6a03cbf 3529 }
6ba736a1 3530
e538fbe8 3531 if (intmask & SDHCI_INT_DATA_END) {
7c89a3d9 3532 if (host->cmd == host->data_cmd) {
e538fbe8
PO		 3533 /*
3534 * Data managed to finish before the
3535 * command completed. Make sure we do
3536 * things in the proper order.
3537 */
3538 host->data_early = 1;
3539 } else {
3540 sdhci_finish_data(host);
3541 }
3542 }
d129bceb
PO		 3543 }
3544}
3545
19d2f695
AH		 3546static inline bool sdhci_defer_done(struct sdhci_host *host,
3547 struct mmc_request *mrq)
3548{
3549 struct mmc_data *data = mrq->data;
3550
4730831c 3551 return host->pending_reset || host->always_defer_done ||
19d2f695
AH		 3552 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3553 data->host_cookie == COOKIE_MAPPED);
3554}
3555
7d12e780 3556static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 3557{
19d2f695 3558 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
781e989c 3559 irqreturn_t result = IRQ_NONE;
66fd8ad5 3560 struct sdhci_host *host = dev_id;
41005003 3561 u32 intmask, mask, unexpected = 0;
781e989c 3562 int max_loops = 16;
19d2f695 3563 int i;
d129bceb
PO		 3564
3565 spin_lock(&host->lock);
3566
af5d2b7b 3567 if (host->runtime_suspended) {
66fd8ad5 3568 spin_unlock(&host->lock);
655bca76 3569 return IRQ_NONE;
66fd8ad5
AH		 3570 }
3571
4e4141a5 3572 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 3573 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 3574 result = IRQ_NONE;
3575 goto out;
3576 }
3577
41005003 3578 do {
f12e39db
AH		 3579 DBG("IRQ status 0x%08x\n", intmask);
3580
3581 if (host->ops->irq) {
3582 intmask = host->ops->irq(host, intmask);
3583 if (!intmask)
3584 goto cont;
3585 }
3586
41005003
RK		 3587 /* Clear selected interrupts. */
3588 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3589 SDHCI_INT_BUS_POWER);
3590 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 3591
41005003
RK		 3592 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3593 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3594 SDHCI_CARD_PRESENT;
d129bceb 3595
41005003
RK		 3596 /*
3597 * There is a observation on i.mx esdhc. INSERT
3598 * bit will be immediately set again when it gets
3599 * cleared, if a card is inserted. We have to mask
3600 * the irq to prevent interrupt storm which will
3601 * freeze the system. And the REMOVE gets the
3602 * same situation.
3603 *
3604 * More testing are needed here to ensure it works
3605 * for other platforms though.
3606 */
b537f94c
RK		 3607 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3608 SDHCI_INT_CARD_REMOVE);
3609 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3610 SDHCI_INT_CARD_INSERT;
3611 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3612 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 3613
3614 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3615 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 3616
3617 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3618 SDHCI_INT_CARD_REMOVE);
3619 result = IRQ_WAKE_THREAD;
41005003 3620 }
d129bceb 3621
41005003 3622 if (intmask & SDHCI_INT_CMD_MASK)
4bf78099 3623 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
964f9ce2 3624
41005003
RK		 3625 if (intmask & SDHCI_INT_DATA_MASK)
3626 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 3627
41005003
RK		 3628 if (intmask & SDHCI_INT_BUS_POWER)
3629 pr_err("%s: Card is consuming too much power!\n",
3630 mmc_hostname(host->mmc));
3192a28f 3631
f37b20eb
DA		 3632 if (intmask & SDHCI_INT_RETUNE)
3633 mmc_retune_needed(host->mmc);
3634
161e6d44
GKB		 3635 if ((intmask & SDHCI_INT_CARD_INT) &&
3636 (host->ier & SDHCI_INT_CARD_INT)) {
781e989c 3637 sdhci_enable_sdio_irq_nolock(host, false);
89f3c365 3638 sdio_signal_irq(host->mmc);
781e989c 3639 }
f75979b7 3640
41005003
RK		 3641 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3642 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3643 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
f37b20eb 3644 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
f75979b7 3645
41005003
RK		 3646 if (intmask) {
3647 unexpected |= intmask;
3648 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3649 }
f12e39db 3650cont:
781e989c
RK		 3651 if (result == IRQ_NONE)
3652 result = IRQ_HANDLED;
d129bceb 3653
41005003 3654 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 3655 } while (intmask && --max_loops);
19d2f695
AH		 3656
3657 /* Determine if mrqs can be completed immediately */
3658 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3659 struct mmc_request *mrq = host->mrqs_done[i];
3660
3661 if (!mrq)
3662 continue;
3663
3664 if (sdhci_defer_done(host, mrq)) {
c07a48c2 3665 result = IRQ_WAKE_THREAD;
19d2f695
AH		 3666 } else {
3667 mrqs_done[i] = mrq;
3668 host->mrqs_done[i] = NULL;
3669 }
3670 }
d129bceb 3671out:
845c939e
AH		 3672 if (host->deferred_cmd)
3673 result = IRQ_WAKE_THREAD;
3674
d129bceb
PO		 3675 spin_unlock(&host->lock);
3676
19d2f695
AH		 3677 /* Process mrqs ready for immediate completion */
3678 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1774b002
BW		 3679 if (!mrqs_done[i])
3680 continue;
3681
3682 if (host->ops->request_done)
3683 host->ops->request_done(host, mrqs_done[i]);
3684 else
19d2f695
AH		 3685 mmc_request_done(host->mmc, mrqs_done[i]);
3686 }
3687
6379b237
AS		 3688 if (unexpected) {
3689 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3690 mmc_hostname(host->mmc), unexpected);
efe8f5c9 3691 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
6379b237
AS		 3692 sdhci_dumpregs(host);
3693 }
f75979b7 3694
d129bceb
PO		 3695 return result;
3696}
3697
fca267f0 3698irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
781e989c
RK		 3699{
3700 struct sdhci_host *host = dev_id;
845c939e 3701 struct mmc_command *cmd;
781e989c
RK		 3702 unsigned long flags;
3703 u32 isr;
3704
c07a48c2
AH		 3705 while (!sdhci_request_done(host))
3706 ;
3707
781e989c 3708 spin_lock_irqsave(&host->lock, flags);
845c939e 3709
781e989c
RK		 3710 isr = host->thread_isr;
3711 host->thread_isr = 0;
845c939e
AH		 3712
3713 cmd = host->deferred_cmd;
3714 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3715 sdhci_finish_mrq(host, cmd->mrq);
3716
781e989c
RK		 3717 spin_unlock_irqrestore(&host->lock, flags);
3718
3560db8e 3719 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d3940f27
AH		 3720 struct mmc_host *mmc = host->mmc;
3721
3722 mmc->ops->card_event(mmc);
3723 mmc_detect_change(mmc, msecs_to_jiffies(200));
3560db8e
RK		 3724 }
3725
c07a48c2 3726 return IRQ_HANDLED;
781e989c 3727}
fca267f0 3728EXPORT_SYMBOL_GPL(sdhci_thread_irq);
781e989c 3729
d129bceb
PO		 3730/*****************************************************************************\
3731 * *
3732 * Suspend/resume *
3733 * *
3734\*****************************************************************************/
3735
3736#ifdef CONFIG_PM
9c316b38
AH		 3737
3738static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3739{
3740 return mmc_card_is_removable(host->mmc) &&
3741 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
da012e1e 3742 !mmc_host_can_gpio_cd(host->mmc);
9c316b38
AH		 3743}
3744
84d62605
LD		 3745/*
3746 * To enable wakeup events, the corresponding events have to be enabled in
3747 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3748 * Table' in the SD Host Controller Standard Specification.
3749 * It is useless to restore SDHCI_INT_ENABLE state in
3750 * sdhci_disable_irq_wakeups() since it will be set by
3751 * sdhci_enable_card_detection() or sdhci_init().
3752 */
b8b0f46d 3753bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
ad080d79 3754{
81b14543
AH		 3755 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3756 SDHCI_WAKE_ON_INT;
3757 u32 irq_val = 0;
3758 u8 wake_val = 0;
ad080d79 3759 u8 val;
ad080d79 3760
9c316b38 3761 if (sdhci_cd_irq_can_wakeup(host)) {
81b14543
AH		 3762 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3763 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
84d62605 3764 }
81b14543 3765
d5d568fa
AH		 3766 if (mmc_card_wake_sdio_irq(host->mmc)) {
3767 wake_val |= SDHCI_WAKE_ON_INT;
3768 irq_val |= SDHCI_INT_CARD_INT;
3769 }
3770
3771 if (!irq_val)
3772 return false;
81b14543
AH		 3773
3774 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3775 val &= ~mask;
3776 val |= wake_val;
ad080d79 3777 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
81b14543 3778
84d62605 3779 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
58e79b60
AH		 3780
3781 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3782
3783 return host->irq_wake_enabled;
ad080d79 3784}
b8b0f46d 3785EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
ad080d79 3786
b8b0f46d 3787void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 3788{
3789 u8 val;
3790 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3791 | SDHCI_WAKE_ON_INT;
3792
3793 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3794 val &= ~mask;
3795 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
58e79b60
AH		 3796
3797 disable_irq_wake(host->irq);
3798
3799 host->irq_wake_enabled = false;
ad080d79 3800}
b8b0f46d 3801EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 3802
29495aa0 3803int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 3804{
7260cf5e
AV		 3805 sdhci_disable_card_detection(host);
3806
66c39dfc 3807 mmc_retune_timer_stop(host->mmc);
cf2b5eea 3808
58e79b60
AH		 3809 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3810 !sdhci_enable_irq_wakeups(host)) {
b537f94c
RK		 3811 host->ier = 0;
3812 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3813 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79 3814 free_irq(host->irq, host);
ad080d79 3815 }
58e79b60 3816
4ee14ec6 3817 return 0;
d129bceb
PO		 3818}
3819
b8c86fc5 3820EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 3821
b8c86fc5
PO		 3822int sdhci_resume_host(struct sdhci_host *host)
3823{
d3940f27 3824 struct mmc_host *mmc = host->mmc;
4ee14ec6 3825 int ret = 0;
d129bceb 3826
a13abc7b 3827 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 3828 if (host->ops->enable_dma)
3829 host->ops->enable_dma(host);
3830 }
d129bceb 3831
d2f025b0 3832 if ((mmc->pm_flags & MMC_PM_KEEP_POWER) &&
6308d290
AH		 3833 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3834 /* Card keeps power but host controller does not */
3835 sdhci_init(host, 0);
3836 host->pwr = 0;
3837 host->clock = 0;
c981cdfb 3838 host->reinit_uhs = true;
d3940f27 3839 mmc->ops->set_ios(mmc, &mmc->ios);
6308d290 3840 } else {
d2f025b0 3841 sdhci_init(host, (mmc->pm_flags & MMC_PM_KEEP_POWER));
6308d290 3842 }
b8c86fc5 3843
58e79b60
AH		 3844 if (host->irq_wake_enabled) {
3845 sdhci_disable_irq_wakeups(host);
3846 } else {
14a7b416
HC		 3847 ret = request_threaded_irq(host->irq, sdhci_irq,
3848 sdhci_thread_irq, IRQF_SHARED,
d2f025b0 3849 mmc_hostname(mmc), host);
14a7b416
HC		 3850 if (ret)
3851 return ret;
14a7b416
HC		 3852 }
3853
7260cf5e
AV		 3854 sdhci_enable_card_detection(host);
3855
2f4cbb3d 3856 return ret;
d129bceb
PO		 3857}
3858
b8c86fc5 3859EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5 3860
66fd8ad5
AH		 3861int sdhci_runtime_suspend_host(struct sdhci_host *host)
3862{
3863 unsigned long flags;
66fd8ad5 3864
66c39dfc 3865 mmc_retune_timer_stop(host->mmc);
66fd8ad5
AH		 3866
3867 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 3868 host->ier &= SDHCI_INT_CARD_INT;
3869 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3870 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 3871 spin_unlock_irqrestore(&host->lock, flags);
3872
781e989c 3873 synchronize_hardirq(host->irq);
66fd8ad5
AH		 3874
3875 spin_lock_irqsave(&host->lock, flags);
3876 host->runtime_suspended = true;
3877 spin_unlock_irqrestore(&host->lock, flags);
3878
8a125bad 3879 return 0;
66fd8ad5
AH		 3880}
3881EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3882
c6303c5d 3883int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
66fd8ad5 3884{
d3940f27 3885 struct mmc_host *mmc = host->mmc;
66fd8ad5 3886 unsigned long flags;
8a125bad 3887 int host_flags = host->flags;
66fd8ad5
AH		 3888
3889 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3890 if (host->ops->enable_dma)
3891 host->ops->enable_dma(host);
3892 }
3893
c6303c5d 3894 sdhci_init(host, soft_reset);
66fd8ad5 3895
70bc85ad
ZW		 3896 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3897 mmc->ios.power_mode != MMC_POWER_OFF) {
84ec048b
AH		 3898 /* Force clock and power re-program */
3899 host->pwr = 0;
3900 host->clock = 0;
c981cdfb 3901 host->reinit_uhs = true;
84ec048b
AH		 3902 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3903 mmc->ops->set_ios(mmc, &mmc->ios);
66fd8ad5 3904
84ec048b
AH		 3905 if ((host_flags & SDHCI_PV_ENABLED) &&
3906 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3907 spin_lock_irqsave(&host->lock, flags);
3908 sdhci_enable_preset_value(host, true);
3909 spin_unlock_irqrestore(&host->lock, flags);
3910 }
66fd8ad5 3911
84ec048b
AH		 3912 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3913 mmc->ops->hs400_enhanced_strobe)
3914 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3915 }
086b0ddb 3916
66fd8ad5
AH		 3917 spin_lock_irqsave(&host->lock, flags);
3918
3919 host->runtime_suspended = false;
3920
3921 /* Enable SDIO IRQ */
0e62614b 3922 if (sdio_irq_claimed(mmc))
66fd8ad5
AH		 3923 sdhci_enable_sdio_irq_nolock(host, true);
3924
3925 /* Enable Card Detection */
3926 sdhci_enable_card_detection(host);
3927
3928 spin_unlock_irqrestore(&host->lock, flags);
3929
8a125bad 3930 return 0;
66fd8ad5
AH		 3931}
3932EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3933
162d6f98 3934#endif /* CONFIG_PM */
66fd8ad5 3935
f12e39db
AH		 3936/*****************************************************************************\
3937 * *
3938 * Command Queue Engine (CQE) helpers *
3939 * *
3940\*****************************************************************************/
3941
3942void sdhci_cqe_enable(struct mmc_host *mmc)
3943{
3944 struct sdhci_host *host = mmc_priv(mmc);
3945 unsigned long flags;
3946 u8 ctrl;
3947
3948 spin_lock_irqsave(&host->lock, flags);
3949
3950 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3951 ctrl &= ~SDHCI_CTRL_DMA_MASK;
4c4faff6
SK		 3952 /*
3953 * Host from V4.10 supports ADMA3 DMA type.
3954 * ADMA3 performs integrated descriptor which is more suitable
3955 * for cmd queuing to fetch both command and transfer descriptors.
3956 */
3957 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3958 ctrl |= SDHCI_CTRL_ADMA3;
3959 else if (host->flags & SDHCI_USE_64_BIT_DMA)
f12e39db
AH		 3960 ctrl |= SDHCI_CTRL_ADMA64;
3961 else
3962 ctrl |= SDHCI_CTRL_ADMA32;
3963 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3964
c846a00f 3965 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
f12e39db
AH		 3966 SDHCI_BLOCK_SIZE);
3967
3968 /* Set maximum timeout */
401059df 3969 sdhci_set_timeout(host, NULL);
f12e39db
AH		 3970
3971 host->ier = host->cqe_ier;
3972
3973 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3974 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3975
3976 host->cqe_on = true;
3977
3978 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3979 mmc_hostname(mmc), host->ier,
3980 sdhci_readl(host, SDHCI_INT_STATUS));
3981
f12e39db
AH		 3982 spin_unlock_irqrestore(&host->lock, flags);
3983}
3984EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3985
3986void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3987{
3988 struct sdhci_host *host = mmc_priv(mmc);
3989 unsigned long flags;
3990
3991 spin_lock_irqsave(&host->lock, flags);
3992
3993 sdhci_set_default_irqs(host);
3994
3995 host->cqe_on = false;
3996
1e63d297
AH		 3997 if (recovery)
3998 sdhci_reset_for(host, CQE_RECOVERY);
f12e39db
AH		 3999
4000 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
4001 mmc_hostname(mmc), host->ier,
4002 sdhci_readl(host, SDHCI_INT_STATUS));
4003
f12e39db
AH		 4004 spin_unlock_irqrestore(&host->lock, flags);
4005}
4006EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
4007
4008bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
4009 int *data_error)
4010{
4011 u32 mask;
4012
4013 if (!host->cqe_on)
4014 return false;
4015
efe8f5c9 4016 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC)) {
f12e39db 4017 *cmd_error = -EILSEQ;
faded9b5 4018 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
efe8f5c9
SSB		 4019 sdhci_err_stats_inc(host, CMD_CRC);
4020 } else if (intmask & SDHCI_INT_TIMEOUT) {
f12e39db 4021 *cmd_error = -ETIMEDOUT;
efe8f5c9
SSB		 4022 sdhci_err_stats_inc(host, CMD_TIMEOUT);
4023 } else
f12e39db
AH		 4024 *cmd_error = 0;
4025
b3855668 4026 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC | SDHCI_INT_TUNING_ERROR)) {
f12e39db 4027 *data_error = -EILSEQ;
faded9b5 4028 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
efe8f5c9
SSB		 4029 sdhci_err_stats_inc(host, DAT_CRC);
4030 } else if (intmask & SDHCI_INT_DATA_TIMEOUT) {
f12e39db 4031 *data_error = -ETIMEDOUT;
efe8f5c9
SSB		 4032 sdhci_err_stats_inc(host, DAT_TIMEOUT);
4033 } else if (intmask & SDHCI_INT_ADMA_ERROR) {
f12e39db 4034 *data_error = -EIO;
efe8f5c9
SSB		 4035 sdhci_err_stats_inc(host, ADMA);
4036 } else
f12e39db
AH		 4037 *data_error = 0;
4038
4039 /* Clear selected interrupts. */
4040 mask = intmask & host->cqe_ier;
4041 sdhci_writel(host, mask, SDHCI_INT_STATUS);
4042
4043 if (intmask & SDHCI_INT_BUS_POWER)
4044 pr_err("%s: Card is consuming too much power!\n",
4045 mmc_hostname(host->mmc));
4046
4047 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
4048 if (intmask) {
4049 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
4050 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
4051 mmc_hostname(host->mmc), intmask);
efe8f5c9 4052 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
f12e39db
AH		 4053 sdhci_dumpregs(host);
4054 }
4055
4056 return true;
4057}
4058EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
4059
d129bceb
PO		 4060/*****************************************************************************\
4061 * *
b8c86fc5 4062 * Device allocation/registration *
d129bceb
PO		 4063 * *
4064\*****************************************************************************/
4065
b8c86fc5
PO		 4066struct sdhci_host *sdhci_alloc_host(struct device *dev,
4067 size_t priv_size)
d129bceb 4068{
d129bceb
PO		 4069 struct mmc_host *mmc;
4070 struct sdhci_host *host;
4071
b8c86fc5 4072 WARN_ON(dev == NULL);
d129bceb 4073
b8c86fc5 4074 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 4075 if (!mmc)
b8c86fc5 4076 return ERR_PTR(-ENOMEM);
d129bceb
PO		 4077
4078 host = mmc_priv(mmc);
4079 host->mmc = mmc;
bf60e592
AH		 4080 host->mmc_host_ops = sdhci_ops;
4081 mmc->ops = &host->mmc_host_ops;
d129bceb 4082
8cb851a4
AH		 4083 host->flags = SDHCI_SIGNALING_330;
4084
f12e39db
AH		 4085 host->cqe_ier = SDHCI_CQE_INT_MASK;
4086 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
4087
83b600b8 4088 host->tuning_delay = -1;
1d8cd065 4089 host->tuning_loop_count = MAX_TUNING_LOOP;
83b600b8 4090
c846a00f
SK		 4091 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
4092
e93be38a
JZ		 4093 /*
4094 * The DMA table descriptor count is calculated as the maximum
4095 * number of segments times 2, to allow for an alignment
4096 * descriptor for each segment, plus 1 for a nop end descriptor.
4097 */
4098 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
3d7c194b 4099 host->max_adma = 65536;
e93be38a 4100
e30314f2
SG		 4101 host->max_timeout_count = 0xE;
4102
fca267f0
VS		 4103 host->complete_work_fn = sdhci_complete_work;
4104 host->thread_irq_fn = sdhci_thread_irq;
4105
b8c86fc5
PO		 4106 return host;
4107}
8a4da143 4108
b8c86fc5 4109EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 4110
7b91369b
AC		 4111static int sdhci_set_dma_mask(struct sdhci_host *host)
4112{
4113 struct mmc_host *mmc = host->mmc;
4114 struct device *dev = mmc_dev(mmc);
4115 int ret = -EINVAL;
4116
4117 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
4118 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4119
4120 /* Try 64-bit mask if hardware is capable of it */
4121 if (host->flags & SDHCI_USE_64_BIT_DMA) {
4122 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
4123 if (ret) {
4124 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
4125 mmc_hostname(mmc));
4126 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4127 }
4128 }
4129
4130 /* 32-bit mask as default & fallback */
4131 if (ret) {
4132 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
4133 if (ret)
4134 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
4135 mmc_hostname(mmc));
4136 }
4137
4138 return ret;
4139}
4140
8784edc8
MY		 4141void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
4142 const u32 *caps, const u32 *caps1)
6132a3bf
AH		 4143{
4144 u16 v;
92e0c44b
ZB		 4145 u64 dt_caps_mask = 0;
4146 u64 dt_caps = 0;
6132a3bf
AH		 4147
4148 if (host->read_caps)
4149 return;
4150
4151 host->read_caps = true;
4152
4153 if (debug_quirks)
4154 host->quirks = debug_quirks;
4155
4156 if (debug_quirks2)
4157 host->quirks2 = debug_quirks2;
4158
aa990722 4159 sdhci_reset_for_all(host);
6132a3bf 4160
b3f80b43
CZ		 4161 if (host->v4_mode)
4162 sdhci_do_enable_v4_mode(host);
4163
cb80a7e9
JL		 4164 device_property_read_u64(mmc_dev(host->mmc),
4165 "sdhci-caps-mask", &dt_caps_mask);
4166 device_property_read_u64(mmc_dev(host->mmc),
4167 "sdhci-caps", &dt_caps);
92e0c44b 4168
6132a3bf
AH		 4169 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4170 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4171
92e0c44b
ZB		 4172 if (caps) {
4173 host->caps = *caps;
4174 } else {
4175 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4176 host->caps &= ~lower_32_bits(dt_caps_mask);
4177 host->caps |= lower_32_bits(dt_caps);
4178 }
6132a3bf
AH		 4179
4180 if (host->version < SDHCI_SPEC_300)
4181 return;
4182
92e0c44b
ZB		 4183 if (caps1) {
4184 host->caps1 = *caps1;
4185 } else {
4186 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4187 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4188 host->caps1 |= upper_32_bits(dt_caps);
4189 }
6132a3bf
AH		 4190}
4191EXPORT_SYMBOL_GPL(__sdhci_read_caps);
4192
a68dd9a0 4193static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
bd9b9027
LW		 4194{
4195 struct mmc_host *mmc = host->mmc;
4196 unsigned int max_blocks;
4197 unsigned int bounce_size;
4198 int ret;
4199
4200 /*
4201 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
4202 * has diminishing returns, this is probably because SD/MMC
4203 * cards are usually optimized to handle this size of requests.
4204 */
4205 bounce_size = SZ_64K;
4206 /*
4207 * Adjust downwards to maximum request size if this is less
4208 * than our segment size, else hammer down the maximum
4209 * request size to the maximum buffer size.
4210 */
4211 if (mmc->max_req_size < bounce_size)
4212 bounce_size = mmc->max_req_size;
4213 max_blocks = bounce_size / 512;
4214
4215 /*
4216 * When we just support one segment, we can get significant
4217 * speedups by the help of a bounce buffer to group scattered
4218 * reads/writes together.
4219 */
bac53336 4220 host->bounce_buffer = devm_kmalloc(mmc_dev(mmc),
bd9b9027
LW		 4221 bounce_size,
4222 GFP_KERNEL);
4223 if (!host->bounce_buffer) {
4224 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
4225 mmc_hostname(mmc),
4226 bounce_size);
4227 /*
4228 * Exiting with zero here makes sure we proceed with
4229 * mmc->max_segs == 1.
4230 */
a68dd9a0 4231 return;
bd9b9027
LW		 4232 }
4233
bac53336 4234 host->bounce_addr = dma_map_single(mmc_dev(mmc),
bd9b9027
LW		 4235 host->bounce_buffer,
4236 bounce_size,
4237 DMA_BIDIRECTIONAL);
bac53336 4238 ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr);
49036ba8
TI		 4239 if (ret) {
4240 devm_kfree(mmc_dev(mmc), host->bounce_buffer);
4241 host->bounce_buffer = NULL;
bd9b9027 4242 /* Again fall back to max_segs == 1 */
a68dd9a0 4243 return;
49036ba8
TI		 4244 }
4245
bd9b9027
LW		 4246 host->bounce_buffer_size = bounce_size;
4247
4248 /* Lie about this since we're bouncing */
4249 mmc->max_segs = max_blocks;
4250 mmc->max_seg_size = bounce_size;
4251 mmc->max_req_size = bounce_size;
4252
4253 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
4254 mmc_hostname(mmc), max_blocks, bounce_size);
bd9b9027
LW		 4255}
4256
685e444b
CZ		 4257static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4258{
4259 /*
4260 * According to SD Host Controller spec v4.10, bit[27] added from
4261 * version 4.10 in Capabilities Register is used as 64-bit System
4262 * Address support for V4 mode.
4263 */
4264 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4265 return host->caps & SDHCI_CAN_64BIT_V4;
4266
4267 return host->caps & SDHCI_CAN_64BIT;
4268}
4269
52f5336d 4270int sdhci_setup_host(struct sdhci_host *host)
b8c86fc5
PO		 4271{
4272 struct mmc_host *mmc;
f2119df6
AN		 4273 u32 max_current_caps;
4274 unsigned int ocr_avail;
f5fa92e5 4275 unsigned int override_timeout_clk;
59241757 4276 u32 max_clk;
907be2a6 4277 int ret = 0;
0fcb031e 4278 bool enable_vqmmc = false;
d129bceb 4279
b8c86fc5
PO		 4280 WARN_ON(host == NULL);
4281 if (host == NULL)
4282 return -EINVAL;
d129bceb 4283
b8c86fc5 4284 mmc = host->mmc;
d129bceb 4285
efba142b
JH		 4286 /*
4287 * If there are external regulators, get them. Note this must be done
4288 * early before resetting the host and reading the capabilities so that
4289 * the host can take the appropriate action if regulators are not
4290 * available.
4291 */
0fcb031e
VV		 4292 if (!mmc->supply.vqmmc) {
4293 ret = mmc_regulator_get_supply(mmc);
4294 if (ret)
4295 return ret;
4296 enable_vqmmc = true;
4297 }
efba142b 4298
06ebc601
SL		 4299 DBG("Version: 0x%08x | Present: 0x%08x\n",
4300 sdhci_readw(host, SDHCI_HOST_VERSION),
4301 sdhci_readl(host, SDHCI_PRESENT_STATE));
4302 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
4303 sdhci_readl(host, SDHCI_CAPABILITIES),
4304 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4305
6132a3bf 4306 sdhci_read_caps(host);
d129bceb 4307
f5fa92e5
AH		 4308 override_timeout_clk = host->timeout_clk;
4309
18da1990 4310 if (host->version > SDHCI_SPEC_420) {
2e4456f0
MV		 4311 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
4312 mmc_hostname(mmc), host->version);
4a965505
PO		 4313 }
4314
b8c86fc5 4315 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 4316 host->flags |= SDHCI_USE_SDMA;
28da3589 4317 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
a13abc7b 4318 DBG("Controller doesn't have SDMA capability\n");
67435274 4319 else
a13abc7b 4320 host->flags |= SDHCI_USE_SDMA;
d129bceb 4321
b8c86fc5 4322 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 4323 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 4324 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 4325 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 4326 }
4327
f2119df6 4328 if ((host->version >= SDHCI_SPEC_200) &&
28da3589 4329 (host->caps & SDHCI_CAN_DO_ADMA2))
a13abc7b 4330 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 4331
4332 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4333 (host->flags & SDHCI_USE_ADMA)) {
4334 DBG("Disabling ADMA as it is marked broken\n");
4335 host->flags &= ~SDHCI_USE_ADMA;
4336 }
4337
685e444b 4338 if (sdhci_can_64bit_dma(host))
e57a5f61
AH		 4339 host->flags |= SDHCI_USE_64_BIT_DMA;
4340
18e762e3
CZ		 4341 if (host->use_external_dma) {
4342 ret = sdhci_external_dma_init(host);
4343 if (ret == -EPROBE_DEFER)
4344 goto unreg;
4345 /*
4346 * Fall back to use the DMA/PIO integrated in standard SDHCI
4347 * instead of external DMA devices.
4348 */
4349 else if (ret)
4350 sdhci_switch_external_dma(host, false);
4351 /* Disable internal DMA sources */
4352 else
4353 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4354 }
4355
a13abc7b 4356 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4ee7dde4
AH		 4357 if (host->ops->set_dma_mask)
4358 ret = host->ops->set_dma_mask(host);
4359 else
4360 ret = sdhci_set_dma_mask(host);
7b91369b
AC		 4361
4362 if (!ret && host->ops->enable_dma)
4363 ret = host->ops->enable_dma(host);
4364
4365 if (ret) {
4366 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4367 mmc_hostname(mmc));
4368 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4369
4370 ret = 0;
d129bceb
PO		 4371 }
4372 }
4373
917a0c52
CZ		 4374 /* SDMA does not support 64-bit DMA if v4 mode not set */
4375 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
e57a5f61
AH		 4376 host->flags &= ~SDHCI_USE_SDMA;
4377
2134a922 4378 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 4379 dma_addr_t dma;
4380 void *buf;
4381
a663f64b
VB		 4382 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4383 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4384 else if (!host->alloc_desc_sz)
4385 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4386
4387 host->desc_sz = host->alloc_desc_sz;
4388 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
e66e61cb 4389
04a5ae6f 4390 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
685e444b
CZ		 4391 /*
4392 * Use zalloc to zero the reserved high 32-bits of 128-bit
4393 * descriptors so that they never need to be written.
4394 */
750afb08
LC		 4395 buf = dma_alloc_coherent(mmc_dev(mmc),
4396 host->align_buffer_sz + host->adma_table_sz,
4397 &dma, GFP_KERNEL);
e66e61cb 4398 if (!buf) {
6606110d 4399 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 4400 mmc_hostname(mmc));
4401 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 4402 } else if ((dma + host->align_buffer_sz) &
4403 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 4404 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4405 mmc_hostname(mmc));
d1e49f77 4406 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 4407 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4408 host->adma_table_sz, buf, dma);
4409 } else {
4410 host->align_buffer = buf;
4411 host->align_addr = dma;
edd63fcc 4412
e66e61cb
RK		 4413 host->adma_table = buf + host->align_buffer_sz;
4414 host->adma_addr = dma + host->align_buffer_sz;
4415 }
2134a922
PO		 4416 }
4417
7659150c
PO		 4418 /*
4419 * If we use DMA, then it's up to the caller to set the DMA
4420 * mask, but PIO does not need the hw shim so we set a new
4421 * mask here in that case.
4422 */
a13abc7b 4423 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 4424 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 4425 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 4426 }
d129bceb 4427
c4687d5f 4428 if (host->version >= SDHCI_SPEC_300)
a8e809ec 4429 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
c4687d5f 4430 else
a8e809ec 4431 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
c4687d5f 4432
4240ff0a 4433 host->max_clk *= 1000000;
f27f47ef
AV		 4434 if (host->max_clk == 0 || host->quirks &
4435 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 4436 if (!host->ops->get_max_clock) {
2e4456f0
MV		 4437 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4438 mmc_hostname(mmc));
eb5c20de
AH		 4439 ret = -ENODEV;
4440 goto undma;
4240ff0a
BD		 4441 }
4442 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 4443 }
d129bceb 4444
c3ed3877
AN		 4445 /*
4446 * In case of Host Controller v3.00, find out whether clock
4447 * multiplier is supported.
4448 */
a8e809ec 4449 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
c3ed3877
AN		 4450
4451 /*
4452 * In case the value in Clock Multiplier is 0, then programmable
4453 * clock mode is not supported, otherwise the actual clock
4454 * multiplier is one more than the value of Clock Multiplier
4455 * in the Capabilities Register.
4456 */
4457 if (host->clk_mul)
4458 host->clk_mul += 1;
4459
d129bceb
PO		 4460 /*
4461 * Set host parameters.
4462 */
59241757
DA		 4463 max_clk = host->max_clk;
4464
ce5f036b 4465 if (host->ops->get_min_clock)
a9e58f25 4466 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877 4467 else if (host->version >= SDHCI_SPEC_300) {
2a187d03 4468 if (host->clk_mul)
59241757 4469 max_clk = host->max_clk * host->clk_mul;
2a187d03
MM		 4470 /*
4471 * Divided Clock Mode minimum clock rate is always less than
4472 * Programmable Clock Mode minimum clock rate.
4473 */
4474 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
c3ed3877 4475 } else
0397526d 4476 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 4477
d310ae49 4478 if (!mmc->f_max || mmc->f_max > max_clk)
59241757
DA		 4479 mmc->f_max = max_clk;
4480
28aab053 4481 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a8e809ec 4482 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
8cc35289
SL		 4483
4484 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4485 host->timeout_clk *= 1000;
4486
28aab053 4487 if (host->timeout_clk == 0) {
8cc35289 4488 if (!host->ops->get_timeout_clock) {
28aab053
AD		 4489 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4490 mmc_hostname(mmc));
eb5c20de
AH		 4491 ret = -ENODEV;
4492 goto undma;
28aab053 4493 }
272308ca 4494
8cc35289
SL		 4495 host->timeout_clk =
4496 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4497 1000);
4498 }
272308ca 4499
99513624
AH		 4500 if (override_timeout_clk)
4501 host->timeout_clk = override_timeout_clk;
4502
28aab053 4503 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 4504 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 4505 mmc->max_busy_timeout /= host->timeout_clk;
4506 }
58d1246d 4507
a999fd93
AH		 4508 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4509 !host->ops->get_max_timeout_count)
4510 mmc->max_busy_timeout = 0;
4511
1be64c79 4512 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
781e989c 4513 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 4514
4515 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4516 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 4517
7ed71a9d
CZ		 4518 /*
4519 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4520 * For v4 mode, SDMA may use Auto-CMD23 as well.
4521 */
4f3d3e9b 4522 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 4523 ((host->flags & SDHCI_USE_ADMA) ||
7ed71a9d 4524 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
3bfa6f03 4525 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371 4526 host->flags |= SDHCI_AUTO_CMD23;
f421865d 4527 DBG("Auto-CMD23 available\n");
8edf6371 4528 } else {
f421865d 4529 DBG("Auto-CMD23 unavailable\n");
8edf6371
AW		 4530 }
4531
15ec4461
PR		 4532 /*
4533 * A controller may support 8-bit width, but the board itself
4534 * might not have the pins brought out. Boards that support
4535 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4536 * their platform code before calling sdhci_add_host(), and we
4537 * won't assume 8-bit width for hosts without that CAP.
4538 */
5fe23c7f 4539 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 4540 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 4541
63ef5d8c
JH		 4542 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4543 mmc->caps &= ~MMC_CAP_CMD23;
4544
28da3589 4545 if (host->caps & SDHCI_CAN_DO_HISPD)
a29e7e18 4546 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 4547
176d1ed4 4548 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
860951c5 4549 mmc_card_is_removable(mmc) &&
d2f025b0 4550 mmc_gpio_get_cd(mmc) < 0)
68d1fb7e
AV		 4551 mmc->caps |= MMC_CAP_NEEDS_POLL;
4552
3a48edc4 4553 if (!IS_ERR(mmc->supply.vqmmc)) {
0fcb031e
VV		 4554 if (enable_vqmmc) {
4555 ret = regulator_enable(mmc->supply.vqmmc);
0fcb031e
VV		 4556 host->sdhci_core_to_disable_vqmmc = !ret;
4557 }
1b5190c2
SA		 4558
4559 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 4560 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4561 1950000))
28da3589
AH		 4562 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4563 SDHCI_SUPPORT_SDR50 |
4564 SDHCI_SUPPORT_DDR50);
1b5190c2
SA		 4565
4566 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4567 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4568 3600000))
4569 host->flags &= ~SDHCI_SIGNALING_330;
4570
a3361aba
CB		 4571 if (ret) {
4572 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4573 mmc_hostname(mmc), ret);
4bb74313 4574 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 4575 }
3debc24f 4576
8363c374 4577 }
6231f3de 4578
28da3589
AH		 4579 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4580 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4581 SDHCI_SUPPORT_DDR50);
c16bc9a7
KVA		 4582 /*
4583 * The SDHCI controller in a SoC might support HS200/HS400
4584 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4585 * but if the board is modeled such that the IO lines are not
4586 * connected to 1.8v then HS200/HS400 cannot be supported.
4587 * Disable HS200/HS400 if the board does not have 1.8v connected
4588 * to the IO lines. (Applicable for other modes in 1.8v)
4589 */
4590 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4591 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
28da3589 4592 }
6a66180a 4593
4188bba0 4594 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
28da3589
AH		 4595 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4596 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 4597 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4598
4599 /* SDR104 supports also implies SDR50 support */
28da3589 4600 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
f2119df6 4601 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 4602 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4603 * field can be promoted to support HS200.
4604 */
549c0b18 4605 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 4606 mmc->caps2 |= MMC_CAP2_HS200;
28da3589 4607 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
f2119df6 4608 mmc->caps |= MMC_CAP_UHS_SDR50;
28da3589 4609 }
f2119df6 4610
e9fb05d5 4611 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
28da3589 4612 (host->caps1 & SDHCI_SUPPORT_HS400))
e9fb05d5
AH		 4613 mmc->caps2 |= MMC_CAP2_HS400;
4614
549c0b18
AH		 4615 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4616 (IS_ERR(mmc->supply.vqmmc) ||
4617 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4618 1300000)))
4619 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4620
28da3589
AH		 4621 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4622 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 4623 mmc->caps |= MMC_CAP_UHS_DDR50;
4624
069c9f14 4625 /* Does the host need tuning for SDR50? */
28da3589 4626 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
b513ea25
AN		 4627 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4628
d6d50a15 4629 /* Driver Type(s) (A, C, D) supported by the host */
28da3589 4630 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
d6d50a15 4631 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
28da3589 4632 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
d6d50a15 4633 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
28da3589 4634 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
d6d50a15
AN		 4635 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4636
cf2b5eea 4637 /* Initial value for re-tuning timer count */
a8e809ec
MY		 4638 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4639 host->caps1);
cf2b5eea
AN		 4640
4641 /*
4642 * In case Re-tuning Timer is not disabled, the actual value of
4643 * re-tuning timer will be 2 ^ (n - 1).
4644 */
4645 if (host->tuning_count)
4646 host->tuning_count = 1 << (host->tuning_count - 1);
4647
4648 /* Re-tuning mode supported by the Host Controller */
a8e809ec 4649 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
cf2b5eea 4650
8f230f45 4651 ocr_avail = 0;
bad37e1a 4652
f2119df6
AN		 4653 /*
4654 * According to SD Host Controller spec v3.00, if the Host System
4655 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4656 * the value is meaningful only if Voltage Support in the Capabilities
4657 * register is set. The actual current value is 4 times the register
4658 * value.
4659 */
4660 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 4661 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 4662 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 4663 if (curr > 0) {
4664
4665 /* convert to SDHCI_MAX_CURRENT format */
4666 curr = curr/1000; /* convert to mA */
4667 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4668
4669 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4670 max_current_caps =
804a65b3
MY		 4671 FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) |
4672 FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) |
4673 FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
bad37e1a
PR		 4674 }
4675 }
f2119df6 4676
28da3589 4677 if (host->caps & SDHCI_CAN_VDD_330) {
8f230f45 4678 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 4679
804a65b3
MY		 4680 mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
4681 max_current_caps) *
4682 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 4683 }
28da3589 4684 if (host->caps & SDHCI_CAN_VDD_300) {
8f230f45 4685 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 4686
804a65b3
MY		 4687 mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
4688 max_current_caps) *
4689 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 4690 }
28da3589 4691 if (host->caps & SDHCI_CAN_VDD_180) {
8f230f45
TI		 4692 ocr_avail |= MMC_VDD_165_195;
4693
804a65b3
MY		 4694 mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
4695 max_current_caps) *
4696 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 4697 }
4698
5fd26c7e
UH		 4699 /* If OCR set by host, use it instead. */
4700 if (host->ocr_mask)
4701 ocr_avail = host->ocr_mask;
4702
4703 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 4704 if (mmc->ocr_avail)
52221610 4705 ocr_avail = mmc->ocr_avail;
3a48edc4 4706
8f230f45
TI		 4707 mmc->ocr_avail = ocr_avail;
4708 mmc->ocr_avail_sdio = ocr_avail;
4709 if (host->ocr_avail_sdio)
4710 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4711 mmc->ocr_avail_sd = ocr_avail;
4712 if (host->ocr_avail_sd)
4713 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4714 else /* normal SD controllers don't support 1.8V */
4715 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4716 mmc->ocr_avail_mmc = ocr_avail;
4717 if (host->ocr_avail_mmc)
4718 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 4719
4720 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 4721 pr_err("%s: Hardware doesn't report any support voltages.\n",
4722 mmc_hostname(mmc));
eb5c20de
AH		 4723 ret = -ENODEV;
4724 goto unreg;
146ad66e
PO		 4725 }
4726
8cb851a4
AH		 4727 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4728 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4729 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4730 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4731 host->flags |= SDHCI_SIGNALING_180;
4732
4733 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4734 host->flags |= SDHCI_SIGNALING_120;
4735
d129bceb
PO		 4736 spin_lock_init(&host->lock);
4737
250dcd11
UH		 4738 /*
4739 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4740 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4741 * is less anyway.
4742 */
4743 mmc->max_req_size = 524288;
4744
d129bceb 4745 /*
2134a922
PO		 4746 * Maximum number of segments. Depends on if the hardware
4747 * can do scatter/gather or not.
d129bceb 4748 */
250dcd11 4749 if (host->flags & SDHCI_USE_ADMA) {
4fb213f8 4750 mmc->max_segs = SDHCI_MAX_SEGS;
250dcd11 4751 } else if (host->flags & SDHCI_USE_SDMA) {
a36274e0 4752 mmc->max_segs = 1;
66e8d3b8
CH		 4753 mmc->max_req_size = min_t(size_t, mmc->max_req_size,
4754 dma_max_mapping_size(mmc_dev(mmc)));
250dcd11 4755 } else { /* PIO */
4fb213f8 4756 mmc->max_segs = SDHCI_MAX_SEGS;
250dcd11 4757 }
d129bceb
PO		 4758
4759 /*
4760 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 4761 * of bytes. When doing hardware scatter/gather, each entry cannot
4762 * be larger than 64 KiB though.
d129bceb 4763 */
30652aa3 4764 if (host->flags & SDHCI_USE_ADMA) {
3d7c194b
AH		 4765 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) {
4766 host->max_adma = 65532; /* 32-bit alignment */
30652aa3 4767 mmc->max_seg_size = 65535;
63d20a94
AH		 4768 /*
4769 * sdhci_adma_table_pre() expects to define 1 DMA
4770 * descriptor per segment, so the maximum segment size
4771 * is set accordingly. SDHCI allows up to 64KiB per DMA
4772 * descriptor (16-bit field), but some controllers do
4773 * not support "zero means 65536" reducing the maximum
4774 * for them to 65535. That is a problem if PAGE_SIZE is
4775 * 64KiB because the block layer does not support
4776 * max_seg_size < PAGE_SIZE, however
4777 * sdhci_adma_table_pre() has a workaround to handle
4778 * that case, and split the descriptor. Refer also
4779 * comment in sdhci_adma_table_pre().
4780 */
4781 if (mmc->max_seg_size < PAGE_SIZE)
4782 mmc->max_seg_size = PAGE_SIZE;
3d7c194b 4783 } else {
30652aa3 4784 mmc->max_seg_size = 65536;
3d7c194b 4785 }
30652aa3 4786 } else {
2134a922 4787 mmc->max_seg_size = mmc->max_req_size;
30652aa3 4788 }
d129bceb 4789
fe4a3c7a
PO		 4790 /*
4791 * Maximum block size. This varies from controller to controller and
4792 * is specified in the capabilities register.
4793 */
0633f654
AV		 4794 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4795 mmc->max_blk_size = 2;
4796 } else {
28da3589 4797 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 4798 SDHCI_MAX_BLOCK_SHIFT;
4799 if (mmc->max_blk_size >= 3) {
6606110d
JP		 4800 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4801 mmc_hostname(mmc));
0633f654
AV		 4802 mmc->max_blk_size = 0;
4803 }
4804 }
4805
4806 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 4807
55db890a
PO		 4808 /*
4809 * Maximum block count.
4810 */
1388eefd 4811 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 4812
a68dd9a0 4813 if (mmc->max_segs == 1)
bd9b9027 4814 /* This may alter mmc->*_blk_* parameters */
a68dd9a0 4815 sdhci_allocate_bounce_buffer(host);
bd9b9027 4816
52f5336d
AH		 4817 return 0;
4818
4819unreg:
0fcb031e 4820 if (host->sdhci_core_to_disable_vqmmc)
52f5336d
AH		 4821 regulator_disable(mmc->supply.vqmmc);
4822undma:
4823 if (host->align_buffer)
4824 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4825 host->adma_table_sz, host->align_buffer,
4826 host->align_addr);
4827 host->adma_table = NULL;
4828 host->align_buffer = NULL;
4829
4830 return ret;
4831}
4832EXPORT_SYMBOL_GPL(sdhci_setup_host);
4833
4180ffa8
AH		 4834void sdhci_cleanup_host(struct sdhci_host *host)
4835{
4836 struct mmc_host *mmc = host->mmc;
4837
0fcb031e 4838 if (host->sdhci_core_to_disable_vqmmc)
4180ffa8
AH		 4839 regulator_disable(mmc->supply.vqmmc);
4840
4841 if (host->align_buffer)
4842 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4843 host->adma_table_sz, host->align_buffer,
4844 host->align_addr);
18e762e3
CZ		 4845
4846 if (host->use_external_dma)
4847 sdhci_external_dma_release(host);
4848
4180ffa8
AH		 4849 host->adma_table = NULL;
4850 host->align_buffer = NULL;
4851}
4852EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4853
52f5336d
AH		 4854int __sdhci_add_host(struct sdhci_host *host)
4855{
c07a48c2 4856 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
52f5336d
AH		 4857 struct mmc_host *mmc = host->mmc;
4858 int ret;
4859
2b17b8d7
AH		 4860 if ((mmc->caps2 & MMC_CAP2_CQE) &&
4861 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4862 mmc->caps2 &= ~MMC_CAP2_CQE;
4863 mmc->cqe_ops = NULL;
4864 }
4865
c07a48c2
AH		 4866 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4867 if (!host->complete_wq)
4868 return -ENOMEM;
4869
fca267f0 4870 INIT_WORK(&host->complete_work, host->complete_work_fn);
d129bceb 4871
2ee4f620
KC		 4872 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4873 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
d129bceb 4874
250fb7b4 4875 init_waitqueue_head(&host->buf_ready_int);
b513ea25 4876
2af502ca
SG		 4877 sdhci_init(host, 0);
4878
fca267f0 4879 ret = request_threaded_irq(host->irq, sdhci_irq, host->thread_irq_fn,
781e989c 4880 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 4881 if (ret) {
4882 pr_err("%s: Failed to request IRQ %d: %d\n",
4883 mmc_hostname(mmc), host->irq, ret);
c07a48c2 4884 goto unwq;
0fc81ee3 4885 }
d129bceb 4886
061d17a6 4887 ret = sdhci_led_register(host);
0fc81ee3
MB		 4888 if (ret) {
4889 pr_err("%s: Failed to register LED device: %d\n",
4890 mmc_hostname(mmc), ret);
eb5c20de 4891 goto unirq;
0fc81ee3 4892 }
2f730fec 4893
eb5c20de
AH		 4894 ret = mmc_add_host(mmc);
4895 if (ret)
4896 goto unled;
d129bceb 4897
a3c76eb9 4898 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 4899 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
18e762e3 4900 host->use_external_dma ? "External DMA" :
e57a5f61
AH		 4901 (host->flags & SDHCI_USE_ADMA) ?
4902 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 4903 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 4904
7260cf5e
AV		 4905 sdhci_enable_card_detection(host);
4906
d129bceb
PO		 4907 return 0;
4908
eb5c20de 4909unled:
061d17a6 4910 sdhci_led_unregister(host);
eb5c20de 4911unirq:
aa990722 4912 sdhci_reset_for_all(host);
b537f94c
RK		 4913 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4914 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec 4915 free_irq(host->irq, host);
c07a48c2
AH		 4916unwq:
4917 destroy_workqueue(host->complete_wq);
52f5336d 4918
d129bceb
PO		 4919 return ret;
4920}
52f5336d
AH		 4921EXPORT_SYMBOL_GPL(__sdhci_add_host);
4922
4923int sdhci_add_host(struct sdhci_host *host)
4924{
4925 int ret;
4926
4927 ret = sdhci_setup_host(host);
4928 if (ret)
4929 return ret;
d129bceb 4930
4180ffa8
AH		 4931 ret = __sdhci_add_host(host);
4932 if (ret)
4933 goto cleanup;
4934
4935 return 0;
4936
4937cleanup:
4938 sdhci_cleanup_host(host);
4939
4940 return ret;
52f5336d 4941}
b8c86fc5 4942EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 4943
1e72859e 4944void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 4945{
3a48edc4 4946 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 4947 unsigned long flags;
4948
4949 if (dead) {
4950 spin_lock_irqsave(&host->lock, flags);
4951
4952 host->flags |= SDHCI_DEVICE_DEAD;
4953
5d0d11c5 4954 if (sdhci_has_requests(host)) {
a3c76eb9 4955 pr_err("%s: Controller removed during "
4e743f1f 4956 " transfer!\n", mmc_hostname(mmc));
5d0d11c5 4957 sdhci_error_out_mrqs(host, -ENOMEDIUM);
1e72859e
PO		 4958 }
4959
4960 spin_unlock_irqrestore(&host->lock, flags);
4961 }
4962
7260cf5e
AV		 4963 sdhci_disable_card_detection(host);
4964
4e743f1f 4965 mmc_remove_host(mmc);
d129bceb 4966
061d17a6 4967 sdhci_led_unregister(host);
2f730fec 4968
1e72859e 4969 if (!dead)
aa990722 4970 sdhci_reset_for_all(host);
d129bceb 4971
b537f94c
RK		 4972 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4973 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 4974 free_irq(host->irq, host);
4975
8fa7292f
TG		 4976 timer_delete_sync(&host->timer);
4977 timer_delete_sync(&host->data_timer);
d129bceb 4978
c07a48c2 4979 destroy_workqueue(host->complete_wq);
2134a922 4980
0fcb031e 4981 if (host->sdhci_core_to_disable_vqmmc)
3a48edc4 4982 regulator_disable(mmc->supply.vqmmc);
6231f3de 4983
edd63fcc 4984 if (host->align_buffer)
e66e61cb
RK		 4985 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4986 host->adma_table_sz, host->align_buffer,
4987 host->align_addr);
2134a922 4988
18e762e3
CZ		 4989 if (host->use_external_dma)
4990 sdhci_external_dma_release(host);
4991
4efaa6fb 4992 host->adma_table = NULL;
2134a922 4993 host->align_buffer = NULL;
d129bceb
PO		 4994}
4995
b8c86fc5 4996EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 4997
b8c86fc5 4998void sdhci_free_host(struct sdhci_host *host)
d129bceb 4999{
b8c86fc5 5000 mmc_free_host(host->mmc);
d129bceb
PO		 5001}
5002
b8c86fc5 5003EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 5004
5005/*****************************************************************************\
5006 * *
5007 * Driver init/exit *
5008 * *
5009\*****************************************************************************/
5010
5011static int __init sdhci_drv_init(void)
5012{
a3c76eb9 5013 pr_info(DRIVER_NAME
52fbf9c9 5014 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 5015 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 5016
b8c86fc5 5017 return 0;
d129bceb
PO		 5018}
5019
5020static void __exit sdhci_drv_exit(void)
5021{
d129bceb
PO		 5022}
5023
5024module_init(sdhci_drv_init);
5025module_exit(sdhci_drv_exit);
5026
df673b22 5027module_param(debug_quirks, uint, 0444);
66fd8ad5 5028module_param(debug_quirks2, uint, 0444);
67435274 5029
32710e8f 5030MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 5031MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 5032MODULE_LICENSE("GPL");
67435274 5033
df673b22 5034MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 5035MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux 6.x block layer and io_uring tree(s)