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mmc: core: Rename erase_timeout to cmd_timeout_ms.
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
11763609 21#include <linux/scatterlist.h>
9bea3c85 22#include <linux/regulator/consumer.h>
d129bceb 23
2f730fec
PO		 24#include <linux/leds.h>
25
22113efd 26#include <linux/mmc/mmc.h>
d129bceb 27#include <linux/mmc/host.h>
d129bceb 28
d129bceb
PO		 29#include "sdhci.h"
30
31#define DRIVER_NAME "sdhci"
d129bceb 32
d129bceb 33#define DBG(f, x...) \
c6563178 34 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 35
f9134319
PO		 36#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
37 defined(CONFIG_MMC_SDHCI_MODULE))
38#define SDHCI_USE_LEDS_CLASS
39#endif
40
df673b22 41static unsigned int debug_quirks = 0;
67435274 42
d129bceb
PO		 43static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
44static void sdhci_finish_data(struct sdhci_host *);
45
46static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
47static void sdhci_finish_command(struct sdhci_host *);
48
49static void sdhci_dumpregs(struct sdhci_host *host)
50{
412ab659
PR		 51 printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
52 mmc_hostname(host->mmc));
d129bceb
PO		 53
54 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 55 sdhci_readl(host, SDHCI_DMA_ADDRESS),
56 sdhci_readw(host, SDHCI_HOST_VERSION));
d129bceb 57 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 58 sdhci_readw(host, SDHCI_BLOCK_SIZE),
59 sdhci_readw(host, SDHCI_BLOCK_COUNT));
d129bceb 60 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 61 sdhci_readl(host, SDHCI_ARGUMENT),
62 sdhci_readw(host, SDHCI_TRANSFER_MODE));
d129bceb 63 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 64 sdhci_readl(host, SDHCI_PRESENT_STATE),
65 sdhci_readb(host, SDHCI_HOST_CONTROL));
d129bceb 66 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 67 sdhci_readb(host, SDHCI_POWER_CONTROL),
68 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
d129bceb 69 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 70 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
71 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
d129bceb 72 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 73 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
74 sdhci_readl(host, SDHCI_INT_STATUS));
d129bceb 75 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 76 sdhci_readl(host, SDHCI_INT_ENABLE),
77 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
d129bceb 78 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 79 sdhci_readw(host, SDHCI_ACMD12_ERR),
80 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
e8120ad1 81 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 82 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1
PR		 83 sdhci_readl(host, SDHCI_CAPABILITIES_1));
84 printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
85 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 86 sdhci_readl(host, SDHCI_MAX_CURRENT));
d129bceb 87
be3f4ae0
BD		 88 if (host->flags & SDHCI_USE_ADMA)
89 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
90 readl(host->ioaddr + SDHCI_ADMA_ERROR),
91 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
92
d129bceb
PO		 93 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
94}
95
96/*****************************************************************************\
97 * *
98 * Low level functions *
99 * *
100\*****************************************************************************/
101
7260cf5e
AV		 102static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
103{
104 u32 ier;
105
106 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
107 ier &= ~clear;
108 ier |= set;
109 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
110 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
111}
112
113static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
114{
115 sdhci_clear_set_irqs(host, 0, irqs);
116}
117
118static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
119{
120 sdhci_clear_set_irqs(host, irqs, 0);
121}
122
123static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
124{
125 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
126
68d1fb7e
AV		 127 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
128 return;
129
7260cf5e
AV		 130 if (enable)
131 sdhci_unmask_irqs(host, irqs);
132 else
133 sdhci_mask_irqs(host, irqs);
134}
135
136static void sdhci_enable_card_detection(struct sdhci_host *host)
137{
138 sdhci_set_card_detection(host, true);
139}
140
141static void sdhci_disable_card_detection(struct sdhci_host *host)
142{
143 sdhci_set_card_detection(host, false);
144}
145
d129bceb
PO		 146static void sdhci_reset(struct sdhci_host *host, u8 mask)
147{
e16514d8 148 unsigned long timeout;
063a9dbb 149 u32 uninitialized_var(ier);
e16514d8 150
b8c86fc5 151 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 152 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 153 SDHCI_CARD_PRESENT))
154 return;
155 }
156
063a9dbb
AV		 157 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
158 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
159
4e4141a5 160 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 161
e16514d8 162 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 163 host->clock = 0;
164
e16514d8
PO		 165 /* Wait max 100 ms */
166 timeout = 100;
167
168 /* hw clears the bit when it's done */
4e4141a5 169 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 170 if (timeout == 0) {
acf1da45 171 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 172 mmc_hostname(host->mmc), (int)mask);
173 sdhci_dumpregs(host);
174 return;
175 }
176 timeout--;
177 mdelay(1);
d129bceb 178 }
063a9dbb
AV		 179
180 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
181 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 182}
183
2f4cbb3d
NP		 184static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
185
186static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 187{
2f4cbb3d
NP		 188 if (soft)
189 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
190 else
191 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 192
7260cf5e
AV		 193 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
194 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 195 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
196 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 197 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 198
199 if (soft) {
200 /* force clock reconfiguration */
201 host->clock = 0;
202 sdhci_set_ios(host->mmc, &host->mmc->ios);
203 }
7260cf5e 204}
d129bceb 205
7260cf5e
AV		 206static void sdhci_reinit(struct sdhci_host *host)
207{
2f4cbb3d 208 sdhci_init(host, 0);
7260cf5e 209 sdhci_enable_card_detection(host);
d129bceb
PO		 210}
211
212static void sdhci_activate_led(struct sdhci_host *host)
213{
214 u8 ctrl;
215
4e4141a5 216 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 217 ctrl |= SDHCI_CTRL_LED;
4e4141a5 218 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 219}
220
221static void sdhci_deactivate_led(struct sdhci_host *host)
222{
223 u8 ctrl;
224
4e4141a5 225 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 226 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 227 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 228}
229
f9134319 230#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 231static void sdhci_led_control(struct led_classdev *led,
232 enum led_brightness brightness)
233{
234 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
235 unsigned long flags;
236
237 spin_lock_irqsave(&host->lock, flags);
238
239 if (brightness == LED_OFF)
240 sdhci_deactivate_led(host);
241 else
242 sdhci_activate_led(host);
243
244 spin_unlock_irqrestore(&host->lock, flags);
245}
246#endif
247
d129bceb
PO		 248/*****************************************************************************\
249 * *
250 * Core functions *
251 * *
252\*****************************************************************************/
253
a406f5a3 254static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 255{
7659150c
PO		 256 unsigned long flags;
257 size_t blksize, len, chunk;
7244b85b 258 u32 uninitialized_var(scratch);
7659150c 259 u8 *buf;
d129bceb 260
a406f5a3 261 DBG("PIO reading\n");
d129bceb 262
a406f5a3 263 blksize = host->data->blksz;
7659150c 264 chunk = 0;
d129bceb 265
7659150c 266 local_irq_save(flags);
d129bceb 267
a406f5a3 268 while (blksize) {
7659150c
PO		 269 if (!sg_miter_next(&host->sg_miter))
270 BUG();
d129bceb 271
7659150c 272 len = min(host->sg_miter.length, blksize);
d129bceb 273
7659150c
PO		 274 blksize -= len;
275 host->sg_miter.consumed = len;
14d836e7 276
7659150c 277 buf = host->sg_miter.addr;
d129bceb 278
7659150c
PO		 279 while (len) {
280 if (chunk == 0) {
4e4141a5 281 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 282 chunk = 4;
a406f5a3 283 }
7659150c
PO		 284
285 *buf = scratch & 0xFF;
286
287 buf++;
288 scratch >>= 8;
289 chunk--;
290 len--;
d129bceb 291 }
a406f5a3 292 }
7659150c
PO		 293
294 sg_miter_stop(&host->sg_miter);
295
296 local_irq_restore(flags);
a406f5a3 297}
d129bceb 298
a406f5a3
PO		 299static void sdhci_write_block_pio(struct sdhci_host *host)
300{
7659150c
PO		 301 unsigned long flags;
302 size_t blksize, len, chunk;
303 u32 scratch;
304 u8 *buf;
d129bceb 305
a406f5a3
PO		 306 DBG("PIO writing\n");
307
308 blksize = host->data->blksz;
7659150c
PO		 309 chunk = 0;
310 scratch = 0;
d129bceb 311
7659150c 312 local_irq_save(flags);
d129bceb 313
a406f5a3 314 while (blksize) {
7659150c
PO		 315 if (!sg_miter_next(&host->sg_miter))
316 BUG();
a406f5a3 317
7659150c
PO		 318 len = min(host->sg_miter.length, blksize);
319
320 blksize -= len;
321 host->sg_miter.consumed = len;
322
323 buf = host->sg_miter.addr;
d129bceb 324
7659150c
PO		 325 while (len) {
326 scratch |= (u32)*buf << (chunk * 8);
327
328 buf++;
329 chunk++;
330 len--;
331
332 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 333 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 334 chunk = 0;
335 scratch = 0;
d129bceb 336 }
d129bceb
PO		 337 }
338 }
7659150c
PO		 339
340 sg_miter_stop(&host->sg_miter);
341
342 local_irq_restore(flags);
a406f5a3
PO		 343}
344
345static void sdhci_transfer_pio(struct sdhci_host *host)
346{
347 u32 mask;
348
349 BUG_ON(!host->data);
350
7659150c 351 if (host->blocks == 0)
a406f5a3
PO		 352 return;
353
354 if (host->data->flags & MMC_DATA_READ)
355 mask = SDHCI_DATA_AVAILABLE;
356 else
357 mask = SDHCI_SPACE_AVAILABLE;
358
4a3cba32
PO		 359 /*
360 * Some controllers (JMicron JMB38x) mess up the buffer bits
361 * for transfers < 4 bytes. As long as it is just one block,
362 * we can ignore the bits.
363 */
364 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
365 (host->data->blocks == 1))
366 mask = ~0;
367
4e4141a5 368 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 369 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
370 udelay(100);
371
a406f5a3
PO		 372 if (host->data->flags & MMC_DATA_READ)
373 sdhci_read_block_pio(host);
374 else
375 sdhci_write_block_pio(host);
d129bceb 376
7659150c
PO		 377 host->blocks--;
378 if (host->blocks == 0)
a406f5a3 379 break;
a406f5a3 380 }
d129bceb 381
a406f5a3 382 DBG("PIO transfer complete.\n");
d129bceb
PO		 383}
384
2134a922
PO		 385static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
386{
387 local_irq_save(*flags);
388 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
389}
390
391static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
392{
393 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
394 local_irq_restore(*flags);
395}
396
118cd17d
BD		 397static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
398{
9e506f35
BD		 399 __le32 *dataddr = (__le32 __force *)(desc + 4);
400 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 401
9e506f35
BD		 402 /* SDHCI specification says ADMA descriptors should be 4 byte
403 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 404
9e506f35
BD		 405 cmdlen[0] = cpu_to_le16(cmd);
406 cmdlen[1] = cpu_to_le16(len);
407
408 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 409}
410
8f1934ce 411static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 412 struct mmc_data *data)
413{
414 int direction;
415
416 u8 *desc;
417 u8 *align;
418 dma_addr_t addr;
419 dma_addr_t align_addr;
420 int len, offset;
421
422 struct scatterlist *sg;
423 int i;
424 char *buffer;
425 unsigned long flags;
426
427 /*
428 * The spec does not specify endianness of descriptor table.
429 * We currently guess that it is LE.
430 */
431
432 if (data->flags & MMC_DATA_READ)
433 direction = DMA_FROM_DEVICE;
434 else
435 direction = DMA_TO_DEVICE;
436
437 /*
438 * The ADMA descriptor table is mapped further down as we
439 * need to fill it with data first.
440 */
441
442 host->align_addr = dma_map_single(mmc_dev(host->mmc),
443 host->align_buffer, 128 * 4, direction);
8d8bb39b 444 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 445 goto fail;
2134a922
PO		 446 BUG_ON(host->align_addr & 0x3);
447
448 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
449 data->sg, data->sg_len, direction);
8f1934ce
PO		 450 if (host->sg_count == 0)
451 goto unmap_align;
2134a922
PO		 452
453 desc = host->adma_desc;
454 align = host->align_buffer;
455
456 align_addr = host->align_addr;
457
458 for_each_sg(data->sg, sg, host->sg_count, i) {
459 addr = sg_dma_address(sg);
460 len = sg_dma_len(sg);
461
462 /*
463 * The SDHCI specification states that ADMA
464 * addresses must be 32-bit aligned. If they
465 * aren't, then we use a bounce buffer for
466 * the (up to three) bytes that screw up the
467 * alignment.
468 */
469 offset = (4 - (addr & 0x3)) & 0x3;
470 if (offset) {
471 if (data->flags & MMC_DATA_WRITE) {
472 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 473 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 474 memcpy(align, buffer, offset);
475 sdhci_kunmap_atomic(buffer, &flags);
476 }
477
118cd17d
BD		 478 /* tran, valid */
479 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 480
481 BUG_ON(offset > 65536);
482
2134a922
PO		 483 align += 4;
484 align_addr += 4;
485
486 desc += 8;
487
488 addr += offset;
489 len -= offset;
490 }
491
2134a922
PO		 492 BUG_ON(len > 65536);
493
118cd17d
BD		 494 /* tran, valid */
495 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 496 desc += 8;
497
498 /*
499 * If this triggers then we have a calculation bug
500 * somewhere. :/
501 */
502 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
503 }
504
70764a90
TA		 505 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
506 /*
507 * Mark the last descriptor as the terminating descriptor
508 */
509 if (desc != host->adma_desc) {
510 desc -= 8;
511 desc[0] |= 0x2; /* end */
512 }
513 } else {
514 /*
515 * Add a terminating entry.
516 */
2134a922 517
70764a90
TA		 518 /* nop, end, valid */
519 sdhci_set_adma_desc(desc, 0, 0, 0x3);
520 }
2134a922
PO		 521
522 /*
523 * Resync align buffer as we might have changed it.
524 */
525 if (data->flags & MMC_DATA_WRITE) {
526 dma_sync_single_for_device(mmc_dev(host->mmc),
527 host->align_addr, 128 * 4, direction);
528 }
529
530 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
531 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 532 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 533 goto unmap_entries;
2134a922 534 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 535
536 return 0;
537
538unmap_entries:
539 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
540 data->sg_len, direction);
541unmap_align:
542 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
543 128 * 4, direction);
544fail:
545 return -EINVAL;
2134a922
PO		 546}
547
548static void sdhci_adma_table_post(struct sdhci_host *host,
549 struct mmc_data *data)
550{
551 int direction;
552
553 struct scatterlist *sg;
554 int i, size;
555 u8 *align;
556 char *buffer;
557 unsigned long flags;
558
559 if (data->flags & MMC_DATA_READ)
560 direction = DMA_FROM_DEVICE;
561 else
562 direction = DMA_TO_DEVICE;
563
564 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
565 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
566
567 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
568 128 * 4, direction);
569
570 if (data->flags & MMC_DATA_READ) {
571 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
572 data->sg_len, direction);
573
574 align = host->align_buffer;
575
576 for_each_sg(data->sg, sg, host->sg_count, i) {
577 if (sg_dma_address(sg) & 0x3) {
578 size = 4 - (sg_dma_address(sg) & 0x3);
579
580 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 581 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 582 memcpy(buffer, align, size);
583 sdhci_kunmap_atomic(buffer, &flags);
584
585 align += 4;
586 }
587 }
588 }
589
590 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
591 data->sg_len, direction);
592}
593
ee53ab5d 594static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
d129bceb 595{
1c8cde92
PO		 596 u8 count;
597 unsigned target_timeout, current_timeout;
d129bceb 598
ee53ab5d
PO		 599 /*
600 * If the host controller provides us with an incorrect timeout
601 * value, just skip the check and use 0xE. The hardware may take
602 * longer to time out, but that's much better than having a too-short
603 * timeout value.
604 */
11a2f1b7 605 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 606 return 0xE;
e538fbe8 607
1c8cde92
PO		 608 /* timeout in us */
609 target_timeout = data->timeout_ns / 1000 +
610 data->timeout_clks / host->clock;
d129bceb 611
81b39802
AV		 612 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
613 host->timeout_clk = host->clock / 1000;
614
1c8cde92
PO		 615 /*
616 * Figure out needed cycles.
617 * We do this in steps in order to fit inside a 32 bit int.
618 * The first step is the minimum timeout, which will have a
619 * minimum resolution of 6 bits:
620 * (1) 2^13*1000 > 2^22,
621 * (2) host->timeout_clk < 2^16
622 * =>
623 * (1) / (2) > 2^6
624 */
625 count = 0;
626 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
627 while (current_timeout < target_timeout) {
628 count++;
629 current_timeout <<= 1;
630 if (count >= 0xF)
631 break;
632 }
633
634 if (count >= 0xF) {
635 printk(KERN_WARNING "%s: Too large timeout requested!\n",
636 mmc_hostname(host->mmc));
637 count = 0xE;
638 }
639
ee53ab5d
PO		 640 return count;
641}
642
6aa943ab
AV		 643static void sdhci_set_transfer_irqs(struct sdhci_host *host)
644{
645 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
646 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
647
648 if (host->flags & SDHCI_REQ_USE_DMA)
649 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
650 else
651 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
652}
653
ee53ab5d
PO		 654static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
655{
656 u8 count;
2134a922 657 u8 ctrl;
8f1934ce 658 int ret;
ee53ab5d
PO		 659
660 WARN_ON(host->data);
661
662 if (data == NULL)
663 return;
664
665 /* Sanity checks */
666 BUG_ON(data->blksz * data->blocks > 524288);
667 BUG_ON(data->blksz > host->mmc->max_blk_size);
668 BUG_ON(data->blocks > 65535);
669
670 host->data = data;
671 host->data_early = 0;
672
673 count = sdhci_calc_timeout(host, data);
4e4141a5 674 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
d129bceb 675
a13abc7b 676 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 677 host->flags |= SDHCI_REQ_USE_DMA;
678
2134a922
PO		 679 /*
680 * FIXME: This doesn't account for merging when mapping the
681 * scatterlist.
682 */
683 if (host->flags & SDHCI_REQ_USE_DMA) {
684 int broken, i;
685 struct scatterlist *sg;
686
687 broken = 0;
688 if (host->flags & SDHCI_USE_ADMA) {
689 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
690 broken = 1;
691 } else {
692 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
693 broken = 1;
694 }
695
696 if (unlikely(broken)) {
697 for_each_sg(data->sg, sg, data->sg_len, i) {
698 if (sg->length & 0x3) {
699 DBG("Reverting to PIO because of "
700 "transfer size (%d)\n",
701 sg->length);
702 host->flags &= ~SDHCI_REQ_USE_DMA;
703 break;
704 }
705 }
706 }
c9fddbc4
PO		 707 }
708
709 /*
710 * The assumption here being that alignment is the same after
711 * translation to device address space.
712 */
2134a922
PO		 713 if (host->flags & SDHCI_REQ_USE_DMA) {
714 int broken, i;
715 struct scatterlist *sg;
716
717 broken = 0;
718 if (host->flags & SDHCI_USE_ADMA) {
719 /*
720 * As we use 3 byte chunks to work around
721 * alignment problems, we need to check this
722 * quirk.
723 */
724 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
725 broken = 1;
726 } else {
727 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
728 broken = 1;
729 }
730
731 if (unlikely(broken)) {
732 for_each_sg(data->sg, sg, data->sg_len, i) {
733 if (sg->offset & 0x3) {
734 DBG("Reverting to PIO because of "
735 "bad alignment\n");
736 host->flags &= ~SDHCI_REQ_USE_DMA;
737 break;
738 }
739 }
740 }
741 }
742
8f1934ce
PO		 743 if (host->flags & SDHCI_REQ_USE_DMA) {
744 if (host->flags & SDHCI_USE_ADMA) {
745 ret = sdhci_adma_table_pre(host, data);
746 if (ret) {
747 /*
748 * This only happens when someone fed
749 * us an invalid request.
750 */
751 WARN_ON(1);
ebd6d357 752 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 753 } else {
4e4141a5
AV		 754 sdhci_writel(host, host->adma_addr,
755 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 756 }
757 } else {
c8b3e02e 758 int sg_cnt;
8f1934ce 759
c8b3e02e 760 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 761 data->sg, data->sg_len,
762 (data->flags & MMC_DATA_READ) ?
763 DMA_FROM_DEVICE :
764 DMA_TO_DEVICE);
c8b3e02e 765 if (sg_cnt == 0) {
8f1934ce
PO		 766 /*
767 * This only happens when someone fed
768 * us an invalid request.
769 */
770 WARN_ON(1);
ebd6d357 771 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 772 } else {
719a61b4 773 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 774 sdhci_writel(host, sg_dma_address(data->sg),
775 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 776 }
777 }
778 }
779
2134a922
PO		 780 /*
781 * Always adjust the DMA selection as some controllers
782 * (e.g. JMicron) can't do PIO properly when the selection
783 * is ADMA.
784 */
785 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 786 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 787 ctrl &= ~SDHCI_CTRL_DMA_MASK;
788 if ((host->flags & SDHCI_REQ_USE_DMA) &&
789 (host->flags & SDHCI_USE_ADMA))
790 ctrl |= SDHCI_CTRL_ADMA32;
791 else
792 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 793 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 794 }
795
8f1934ce 796 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 797 int flags;
798
799 flags = SG_MITER_ATOMIC;
800 if (host->data->flags & MMC_DATA_READ)
801 flags |= SG_MITER_TO_SG;
802 else
803 flags |= SG_MITER_FROM_SG;
804 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 805 host->blocks = data->blocks;
d129bceb 806 }
c7fa9963 807
6aa943ab
AV		 808 sdhci_set_transfer_irqs(host);
809
bab76961 810 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
4e4141a5
AV		 811 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
812 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 813}
814
815static void sdhci_set_transfer_mode(struct sdhci_host *host,
816 struct mmc_data *data)
817{
818 u16 mode;
819
c7fa9963
PO		 820 if (data == NULL)
821 return;
822
e538fbe8
PO		 823 WARN_ON(!host->data);
824
c7fa9963 825 mode = SDHCI_TRNS_BLK_CNT_EN;
c4512f79
JH		 826 if (data->blocks > 1) {
827 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
828 mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
829 else
830 mode |= SDHCI_TRNS_MULTI;
831 }
c7fa9963
PO		 832 if (data->flags & MMC_DATA_READ)
833 mode |= SDHCI_TRNS_READ;
c9fddbc4 834 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 835 mode |= SDHCI_TRNS_DMA;
836
4e4141a5 837 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 838}
839
840static void sdhci_finish_data(struct sdhci_host *host)
841{
842 struct mmc_data *data;
d129bceb
PO		 843
844 BUG_ON(!host->data);
845
846 data = host->data;
847 host->data = NULL;
848
c9fddbc4 849 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 850 if (host->flags & SDHCI_USE_ADMA)
851 sdhci_adma_table_post(host, data);
852 else {
853 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
854 data->sg_len, (data->flags & MMC_DATA_READ) ?
855 DMA_FROM_DEVICE : DMA_TO_DEVICE);
856 }
d129bceb
PO		 857 }
858
859 /*
c9b74c5b
PO		 860 * The specification states that the block count register must
861 * be updated, but it does not specify at what point in the
862 * data flow. That makes the register entirely useless to read
863 * back so we have to assume that nothing made it to the card
864 * in the event of an error.
d129bceb 865 */
c9b74c5b
PO		 866 if (data->error)
867 data->bytes_xfered = 0;
d129bceb 868 else
c9b74c5b 869 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 870
d129bceb
PO		 871 if (data->stop) {
872 /*
873 * The controller needs a reset of internal state machines
874 * upon error conditions.
875 */
17b0429d 876 if (data->error) {
d129bceb
PO		 877 sdhci_reset(host, SDHCI_RESET_CMD);
878 sdhci_reset(host, SDHCI_RESET_DATA);
879 }
880
881 sdhci_send_command(host, data->stop);
882 } else
883 tasklet_schedule(&host->finish_tasklet);
884}
885
886static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
887{
888 int flags;
fd2208d7 889 u32 mask;
7cb2c76f 890 unsigned long timeout;
d129bceb
PO		 891
892 WARN_ON(host->cmd);
893
d129bceb 894 /* Wait max 10 ms */
7cb2c76f 895 timeout = 10;
fd2208d7
PO		 896
897 mask = SDHCI_CMD_INHIBIT;
898 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
899 mask |= SDHCI_DATA_INHIBIT;
900
901 /* We shouldn't wait for data inihibit for stop commands, even
902 though they might use busy signaling */
903 if (host->mrq->data && (cmd == host->mrq->data->stop))
904 mask &= ~SDHCI_DATA_INHIBIT;
905
4e4141a5 906 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 907 if (timeout == 0) {
d129bceb 908 printk(KERN_ERR "%s: Controller never released "
acf1da45 909 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 910 sdhci_dumpregs(host);
17b0429d 911 cmd->error = -EIO;
d129bceb
PO		 912 tasklet_schedule(&host->finish_tasklet);
913 return;
914 }
7cb2c76f
PO		 915 timeout--;
916 mdelay(1);
917 }
d129bceb
PO		 918
919 mod_timer(&host->timer, jiffies + 10 * HZ);
920
921 host->cmd = cmd;
922
923 sdhci_prepare_data(host, cmd->data);
924
4e4141a5 925 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 926
c7fa9963
PO		 927 sdhci_set_transfer_mode(host, cmd->data);
928
d129bceb 929 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 930 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 931 mmc_hostname(host->mmc));
17b0429d 932 cmd->error = -EINVAL;
d129bceb
PO		 933 tasklet_schedule(&host->finish_tasklet);
934 return;
935 }
936
937 if (!(cmd->flags & MMC_RSP_PRESENT))
938 flags = SDHCI_CMD_RESP_NONE;
939 else if (cmd->flags & MMC_RSP_136)
940 flags = SDHCI_CMD_RESP_LONG;
941 else if (cmd->flags & MMC_RSP_BUSY)
942 flags = SDHCI_CMD_RESP_SHORT_BUSY;
943 else
944 flags = SDHCI_CMD_RESP_SHORT;
945
946 if (cmd->flags & MMC_RSP_CRC)
947 flags |= SDHCI_CMD_CRC;
948 if (cmd->flags & MMC_RSP_OPCODE)
949 flags |= SDHCI_CMD_INDEX;
950 if (cmd->data)
951 flags |= SDHCI_CMD_DATA;
952
4e4141a5 953 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 954}
955
956static void sdhci_finish_command(struct sdhci_host *host)
957{
958 int i;
959
960 BUG_ON(host->cmd == NULL);
961
962 if (host->cmd->flags & MMC_RSP_PRESENT) {
963 if (host->cmd->flags & MMC_RSP_136) {
964 /* CRC is stripped so we need to do some shifting. */
965 for (i = 0;i < 4;i++) {
4e4141a5 966 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 967 SDHCI_RESPONSE + (3-i)*4) << 8;
968 if (i != 3)
969 host->cmd->resp[i] |=
4e4141a5 970 sdhci_readb(host,
d129bceb
PO		 971 SDHCI_RESPONSE + (3-i)*4-1);
972 }
973 } else {
4e4141a5 974 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 975 }
976 }
977
17b0429d 978 host->cmd->error = 0;
d129bceb 979
e538fbe8
PO		 980 if (host->data && host->data_early)
981 sdhci_finish_data(host);
982
983 if (!host->cmd->data)
d129bceb
PO		 984 tasklet_schedule(&host->finish_tasklet);
985
986 host->cmd = NULL;
987}
988
989static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
990{
991 int div;
992 u16 clk;
7cb2c76f 993 unsigned long timeout;
d129bceb
PO		 994
995 if (clock == host->clock)
996 return;
997
8114634c
AV		 998 if (host->ops->set_clock) {
999 host->ops->set_clock(host, clock);
1000 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1001 return;
1002 }
1003
4e4141a5 1004 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1005
1006 if (clock == 0)
1007 goto out;
1008
85105c53
ZG		 1009 if (host->version >= SDHCI_SPEC_300) {
1010 /* Version 3.00 divisors must be a multiple of 2. */
1011 if (host->max_clk <= clock)
1012 div = 1;
1013 else {
0397526d 1014 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
85105c53
ZG		 1015 if ((host->max_clk / div) <= clock)
1016 break;
1017 }
1018 }
1019 } else {
1020 /* Version 2.00 divisors must be a power of 2. */
0397526d 1021 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1022 if ((host->max_clk / div) <= clock)
1023 break;
1024 }
d129bceb
PO		 1025 }
1026 div >>= 1;
1027
85105c53
ZG		 1028 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1029 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1030 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1031 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1032 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1033
27f6cb16
CB		 1034 /* Wait max 20 ms */
1035 timeout = 20;
4e4141a5 1036 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1037 & SDHCI_CLOCK_INT_STABLE)) {
1038 if (timeout == 0) {
acf1da45
PO		 1039 printk(KERN_ERR "%s: Internal clock never "
1040 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1041 sdhci_dumpregs(host);
1042 return;
1043 }
7cb2c76f
PO		 1044 timeout--;
1045 mdelay(1);
1046 }
d129bceb
PO		 1047
1048 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1049 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1050
1051out:
1052 host->clock = clock;
1053}
1054
146ad66e
PO		 1055static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1056{
8364248a 1057 u8 pwr = 0;
146ad66e 1058
8364248a 1059 if (power != (unsigned short)-1) {
ae628903
PO		 1060 switch (1 << power) {
1061 case MMC_VDD_165_195:
1062 pwr = SDHCI_POWER_180;
1063 break;
1064 case MMC_VDD_29_30:
1065 case MMC_VDD_30_31:
1066 pwr = SDHCI_POWER_300;
1067 break;
1068 case MMC_VDD_32_33:
1069 case MMC_VDD_33_34:
1070 pwr = SDHCI_POWER_330;
1071 break;
1072 default:
1073 BUG();
1074 }
1075 }
1076
1077 if (host->pwr == pwr)
146ad66e
PO		 1078 return;
1079
ae628903
PO		 1080 host->pwr = pwr;
1081
1082 if (pwr == 0) {
4e4141a5 1083 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ae628903 1084 return;
9e9dc5f2
DS		 1085 }
1086
1087 /*
1088 * Spec says that we should clear the power reg before setting
1089 * a new value. Some controllers don't seem to like this though.
1090 */
b8c86fc5 1091 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1092 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1093
e08c1694 1094 /*
c71f6512 1095 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1096 * and set turn on power at the same time, so set the voltage first.
1097 */
11a2f1b7 1098 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1099 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1100
ae628903 1101 pwr |= SDHCI_POWER_ON;
146ad66e 1102
ae628903 1103 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1104
1105 /*
1106 * Some controllers need an extra 10ms delay of 10ms before they
1107 * can apply clock after applying power
1108 */
11a2f1b7 1109 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1110 mdelay(10);
146ad66e
PO		 1111}
1112
d129bceb
PO		 1113/*****************************************************************************\
1114 * *
1115 * MMC callbacks *
1116 * *
1117\*****************************************************************************/
1118
1119static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1120{
1121 struct sdhci_host *host;
68d1fb7e 1122 bool present;
d129bceb
PO		 1123 unsigned long flags;
1124
1125 host = mmc_priv(mmc);
1126
1127 spin_lock_irqsave(&host->lock, flags);
1128
1129 WARN_ON(host->mrq != NULL);
1130
f9134319 1131#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1132 sdhci_activate_led(host);
2f730fec 1133#endif
c4512f79
JH		 1134 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
1135 if (mrq->stop) {
1136 mrq->data->stop = NULL;
1137 mrq->stop = NULL;
1138 }
1139 }
d129bceb
PO		 1140
1141 host->mrq = mrq;
1142
68d1fb7e
AV		 1143 /* If polling, assume that the card is always present. */
1144 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1145 present = true;
1146 else
1147 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1148 SDHCI_CARD_PRESENT;
1149
1150 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1151 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1152 tasklet_schedule(&host->finish_tasklet);
1153 } else
1154 sdhci_send_command(host, mrq->cmd);
1155
5f25a66f 1156 mmiowb();
d129bceb
PO		 1157 spin_unlock_irqrestore(&host->lock, flags);
1158}
1159
1160static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1161{
1162 struct sdhci_host *host;
1163 unsigned long flags;
1164 u8 ctrl;
1165
1166 host = mmc_priv(mmc);
1167
1168 spin_lock_irqsave(&host->lock, flags);
1169
1e72859e
PO		 1170 if (host->flags & SDHCI_DEVICE_DEAD)
1171 goto out;
1172
d129bceb
PO		 1173 /*
1174 * Reset the chip on each power off.
1175 * Should clear out any weird states.
1176 */
1177 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1178 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1179 sdhci_reinit(host);
d129bceb
PO		 1180 }
1181
1182 sdhci_set_clock(host, ios->clock);
1183
1184 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1185 sdhci_set_power(host, -1);
d129bceb 1186 else
146ad66e 1187 sdhci_set_power(host, ios->vdd);
d129bceb 1188
643a81ff
PR		 1189 if (host->ops->platform_send_init_74_clocks)
1190 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1191
15ec4461
PR		 1192 /*
1193 * If your platform has 8-bit width support but is not a v3 controller,
1194 * or if it requires special setup code, you should implement that in
1195 * platform_8bit_width().
1196 */
1197 if (host->ops->platform_8bit_width)
1198 host->ops->platform_8bit_width(host, ios->bus_width);
1199 else {
1200 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1201 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1202 ctrl &= ~SDHCI_CTRL_4BITBUS;
1203 if (host->version >= SDHCI_SPEC_300)
1204 ctrl |= SDHCI_CTRL_8BITBUS;
1205 } else {
1206 if (host->version >= SDHCI_SPEC_300)
1207 ctrl &= ~SDHCI_CTRL_8BITBUS;
1208 if (ios->bus_width == MMC_BUS_WIDTH_4)
1209 ctrl |= SDHCI_CTRL_4BITBUS;
1210 else
1211 ctrl &= ~SDHCI_CTRL_4BITBUS;
1212 }
1213 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1214 }
ae6d6c92 1215
15ec4461 1216 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1217
3ab9c8da
PR		 1218 if ((ios->timing == MMC_TIMING_SD_HS ||
1219 ios->timing == MMC_TIMING_MMC_HS)
1220 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1221 ctrl |= SDHCI_CTRL_HISPD;
1222 else
1223 ctrl &= ~SDHCI_CTRL_HISPD;
1224
4e4141a5 1225 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb 1226
b8352260
LD		 1227 /*
1228 * Some (ENE) controllers go apeshit on some ios operation,
1229 * signalling timeout and CRC errors even on CMD0. Resetting
1230 * it on each ios seems to solve the problem.
1231 */
b8c86fc5 1232 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1233 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1234
1e72859e 1235out:
5f25a66f 1236 mmiowb();
d129bceb
PO		 1237 spin_unlock_irqrestore(&host->lock, flags);
1238}
1239
1240static int sdhci_get_ro(struct mmc_host *mmc)
1241{
1242 struct sdhci_host *host;
1243 unsigned long flags;
2dfb579c 1244 int is_readonly;
d129bceb
PO		 1245
1246 host = mmc_priv(mmc);
1247
1248 spin_lock_irqsave(&host->lock, flags);
1249
1e72859e 1250 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1251 is_readonly = 0;
1252 else if (host->ops->get_ro)
1253 is_readonly = host->ops->get_ro(host);
1e72859e 1254 else
2dfb579c
WS		 1255 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1256 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1257
1258 spin_unlock_irqrestore(&host->lock, flags);
1259
2dfb579c
WS		 1260 /* This quirk needs to be replaced by a callback-function later */
1261 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1262 !is_readonly : is_readonly;
d129bceb
PO		 1263}
1264
f75979b7
PO		 1265static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1266{
1267 struct sdhci_host *host;
1268 unsigned long flags;
f75979b7
PO		 1269
1270 host = mmc_priv(mmc);
1271
1272 spin_lock_irqsave(&host->lock, flags);
1273
1e72859e
PO		 1274 if (host->flags & SDHCI_DEVICE_DEAD)
1275 goto out;
1276
f75979b7 1277 if (enable)
7260cf5e
AV		 1278 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1279 else
1280 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1281out:
f75979b7
PO		 1282 mmiowb();
1283
1284 spin_unlock_irqrestore(&host->lock, flags);
1285}
1286
ab7aefd0 1287static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1288 .request = sdhci_request,
1289 .set_ios = sdhci_set_ios,
1290 .get_ro = sdhci_get_ro,
f75979b7 1291 .enable_sdio_irq = sdhci_enable_sdio_irq,
d129bceb
PO		 1292};
1293
1294/*****************************************************************************\
1295 * *
1296 * Tasklets *
1297 * *
1298\*****************************************************************************/
1299
1300static void sdhci_tasklet_card(unsigned long param)
1301{
1302 struct sdhci_host *host;
1303 unsigned long flags;
1304
1305 host = (struct sdhci_host*)param;
1306
1307 spin_lock_irqsave(&host->lock, flags);
1308
4e4141a5 1309 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
d129bceb
PO		 1310 if (host->mrq) {
1311 printk(KERN_ERR "%s: Card removed during transfer!\n",
1312 mmc_hostname(host->mmc));
1313 printk(KERN_ERR "%s: Resetting controller.\n",
1314 mmc_hostname(host->mmc));
1315
1316 sdhci_reset(host, SDHCI_RESET_CMD);
1317 sdhci_reset(host, SDHCI_RESET_DATA);
1318
17b0429d 1319 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1320 tasklet_schedule(&host->finish_tasklet);
1321 }
1322 }
1323
1324 spin_unlock_irqrestore(&host->lock, flags);
1325
04cf585d 1326 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1327}
1328
1329static void sdhci_tasklet_finish(unsigned long param)
1330{
1331 struct sdhci_host *host;
1332 unsigned long flags;
1333 struct mmc_request *mrq;
1334
1335 host = (struct sdhci_host*)param;
1336
0c9c99a7
CB		 1337 /*
1338 * If this tasklet gets rescheduled while running, it will
1339 * be run again afterwards but without any active request.
1340 */
1341 if (!host->mrq)
1342 return;
1343
d129bceb
PO		 1344 spin_lock_irqsave(&host->lock, flags);
1345
1346 del_timer(&host->timer);
1347
1348 mrq = host->mrq;
1349
d129bceb
PO		 1350 /*
1351 * The controller needs a reset of internal state machines
1352 * upon error conditions.
1353 */
1e72859e 1354 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 1355 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 1356 (mrq->data && (mrq->data->error ||
1357 (mrq->data->stop && mrq->data->stop->error))) ||
1358 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1359
1360 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1361 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1362 unsigned int clock;
1363
1364 /* This is to force an update */
1365 clock = host->clock;
1366 host->clock = 0;
1367 sdhci_set_clock(host, clock);
1368 }
1369
1370 /* Spec says we should do both at the same time, but Ricoh
1371 controllers do not like that. */
d129bceb
PO		 1372 sdhci_reset(host, SDHCI_RESET_CMD);
1373 sdhci_reset(host, SDHCI_RESET_DATA);
1374 }
1375
1376 host->mrq = NULL;
1377 host->cmd = NULL;
1378 host->data = NULL;
1379
f9134319 1380#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1381 sdhci_deactivate_led(host);
2f730fec 1382#endif
d129bceb 1383
5f25a66f 1384 mmiowb();
d129bceb
PO		 1385 spin_unlock_irqrestore(&host->lock, flags);
1386
1387 mmc_request_done(host->mmc, mrq);
1388}
1389
1390static void sdhci_timeout_timer(unsigned long data)
1391{
1392 struct sdhci_host *host;
1393 unsigned long flags;
1394
1395 host = (struct sdhci_host*)data;
1396
1397 spin_lock_irqsave(&host->lock, flags);
1398
1399 if (host->mrq) {
acf1da45
PO		 1400 printk(KERN_ERR "%s: Timeout waiting for hardware "
1401 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1402 sdhci_dumpregs(host);
1403
1404 if (host->data) {
17b0429d 1405 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1406 sdhci_finish_data(host);
1407 } else {
1408 if (host->cmd)
17b0429d 1409 host->cmd->error = -ETIMEDOUT;
d129bceb 1410 else
17b0429d 1411 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1412
1413 tasklet_schedule(&host->finish_tasklet);
1414 }
1415 }
1416
5f25a66f 1417 mmiowb();
d129bceb
PO		 1418 spin_unlock_irqrestore(&host->lock, flags);
1419}
1420
1421/*****************************************************************************\
1422 * *
1423 * Interrupt handling *
1424 * *
1425\*****************************************************************************/
1426
1427static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1428{
1429 BUG_ON(intmask == 0);
1430
1431 if (!host->cmd) {
b67ac3f3
PO		 1432 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1433 "though no command operation was in progress.\n",
1434 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1435 sdhci_dumpregs(host);
1436 return;
1437 }
1438
43b58b36 1439 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1440 host->cmd->error = -ETIMEDOUT;
1441 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1442 SDHCI_INT_INDEX))
1443 host->cmd->error = -EILSEQ;
43b58b36 1444
e809517f 1445 if (host->cmd->error) {
d129bceb 1446 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 1447 return;
1448 }
1449
1450 /*
1451 * The host can send and interrupt when the busy state has
1452 * ended, allowing us to wait without wasting CPU cycles.
1453 * Unfortunately this is overloaded on the "data complete"
1454 * interrupt, so we need to take some care when handling
1455 * it.
1456 *
1457 * Note: The 1.0 specification is a bit ambiguous about this
1458 * feature so there might be some problems with older
1459 * controllers.
1460 */
1461 if (host->cmd->flags & MMC_RSP_BUSY) {
1462 if (host->cmd->data)
1463 DBG("Cannot wait for busy signal when also "
1464 "doing a data transfer");
f945405c 1465 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 1466 return;
f945405c
BD		 1467
1468 /* The controller does not support the end-of-busy IRQ,
1469 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 1470 }
1471
1472 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 1473 sdhci_finish_command(host);
d129bceb
PO		 1474}
1475
0957c333 1476#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 1477static void sdhci_show_adma_error(struct sdhci_host *host)
1478{
1479 const char *name = mmc_hostname(host->mmc);
1480 u8 *desc = host->adma_desc;
1481 __le32 *dma;
1482 __le16 *len;
1483 u8 attr;
1484
1485 sdhci_dumpregs(host);
1486
1487 while (true) {
1488 dma = (__le32 *)(desc + 4);
1489 len = (__le16 *)(desc + 2);
1490 attr = *desc;
1491
1492 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1493 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1494
1495 desc += 8;
1496
1497 if (attr & 2)
1498 break;
1499 }
1500}
1501#else
1502static void sdhci_show_adma_error(struct sdhci_host *host) { }
1503#endif
1504
d129bceb
PO		 1505static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1506{
1507 BUG_ON(intmask == 0);
1508
1509 if (!host->data) {
1510 /*
e809517f
PO		 1511 * The "data complete" interrupt is also used to
1512 * indicate that a busy state has ended. See comment
1513 * above in sdhci_cmd_irq().
d129bceb 1514 */
e809517f
PO		 1515 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1516 if (intmask & SDHCI_INT_DATA_END) {
1517 sdhci_finish_command(host);
1518 return;
1519 }
1520 }
d129bceb 1521
b67ac3f3
PO		 1522 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1523 "though no data operation was in progress.\n",
1524 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1525 sdhci_dumpregs(host);
1526
1527 return;
1528 }
1529
1530 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 1531 host->data->error = -ETIMEDOUT;
22113efd
AL		 1532 else if (intmask & SDHCI_INT_DATA_END_BIT)
1533 host->data->error = -EILSEQ;
1534 else if ((intmask & SDHCI_INT_DATA_CRC) &&
1535 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
1536 != MMC_BUS_TEST_R)
17b0429d 1537 host->data->error = -EILSEQ;
6882a8c0
BD		 1538 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1539 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1540 sdhci_show_adma_error(host);
2134a922 1541 host->data->error = -EIO;
6882a8c0 1542 }
d129bceb 1543
17b0429d 1544 if (host->data->error)
d129bceb
PO		 1545 sdhci_finish_data(host);
1546 else {
a406f5a3 1547 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1548 sdhci_transfer_pio(host);
1549
6ba736a1
PO		 1550 /*
1551 * We currently don't do anything fancy with DMA
1552 * boundaries, but as we can't disable the feature
1553 * we need to at least restart the transfer.
1554 */
1555 if (intmask & SDHCI_INT_DMA_END)
4e4141a5
AV		 1556 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1557 SDHCI_DMA_ADDRESS);
6ba736a1 1558
e538fbe8
PO		 1559 if (intmask & SDHCI_INT_DATA_END) {
1560 if (host->cmd) {
1561 /*
1562 * Data managed to finish before the
1563 * command completed. Make sure we do
1564 * things in the proper order.
1565 */
1566 host->data_early = 1;
1567 } else {
1568 sdhci_finish_data(host);
1569 }
1570 }
d129bceb
PO		 1571 }
1572}
1573
7d12e780 1574static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1575{
1576 irqreturn_t result;
1577 struct sdhci_host* host = dev_id;
1578 u32 intmask;
f75979b7 1579 int cardint = 0;
d129bceb
PO		 1580
1581 spin_lock(&host->lock);
1582
4e4141a5 1583 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 1584
62df67a5 1585 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1586 result = IRQ_NONE;
1587 goto out;
1588 }
1589
b69c9058
PO		 1590 DBG("*** %s got interrupt: 0x%08x\n",
1591 mmc_hostname(host->mmc), intmask);
d129bceb 1592
3192a28f 1593 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
4e4141a5
AV		 1594 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1595 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
d129bceb 1596 tasklet_schedule(&host->card_tasklet);
3192a28f 1597 }
d129bceb 1598
3192a28f 1599 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1600
3192a28f 1601 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 1602 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1603 SDHCI_INT_STATUS);
3192a28f 1604 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1605 }
1606
1607 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 1608 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1609 SDHCI_INT_STATUS);
3192a28f 1610 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1611 }
1612
1613 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1614
964f9ce2
PO		 1615 intmask &= ~SDHCI_INT_ERROR;
1616
d129bceb 1617 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1618 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1619 mmc_hostname(host->mmc));
4e4141a5 1620 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 1621 }
1622
9d26a5d3 1623 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 1624
f75979b7
PO		 1625 if (intmask & SDHCI_INT_CARD_INT)
1626 cardint = 1;
1627
1628 intmask &= ~SDHCI_INT_CARD_INT;
1629
3192a28f 1630 if (intmask) {
acf1da45 1631 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1632 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1633 sdhci_dumpregs(host);
1634
4e4141a5 1635 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 1636 }
d129bceb
PO		 1637
1638 result = IRQ_HANDLED;
1639
5f25a66f 1640 mmiowb();
d129bceb
PO		 1641out:
1642 spin_unlock(&host->lock);
1643
f75979b7
PO		 1644 /*
1645 * We have to delay this as it calls back into the driver.
1646 */
1647 if (cardint)
1648 mmc_signal_sdio_irq(host->mmc);
1649
d129bceb
PO		 1650 return result;
1651}
1652
1653/*****************************************************************************\
1654 * *
1655 * Suspend/resume *
1656 * *
1657\*****************************************************************************/
1658
1659#ifdef CONFIG_PM
1660
b8c86fc5 1661int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 1662{
b8c86fc5 1663 int ret;
a715dfc7 1664
7260cf5e
AV		 1665 sdhci_disable_card_detection(host);
1666
1a13f8fa 1667 ret = mmc_suspend_host(host->mmc);
b8c86fc5
PO		 1668 if (ret)
1669 return ret;
a715dfc7 1670
b8c86fc5 1671 free_irq(host->irq, host);
d129bceb 1672
9bea3c85
MS		 1673 if (host->vmmc)
1674 ret = regulator_disable(host->vmmc);
1675
1676 return ret;
d129bceb
PO		 1677}
1678
b8c86fc5 1679EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 1680
b8c86fc5
PO		 1681int sdhci_resume_host(struct sdhci_host *host)
1682{
1683 int ret;
d129bceb 1684
9bea3c85
MS		 1685 if (host->vmmc) {
1686 int ret = regulator_enable(host->vmmc);
1687 if (ret)
1688 return ret;
1689 }
1690
1691
a13abc7b 1692 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 1693 if (host->ops->enable_dma)
1694 host->ops->enable_dma(host);
1695 }
d129bceb 1696
b8c86fc5
PO		 1697 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1698 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 1699 if (ret)
1700 return ret;
d129bceb 1701
2f4cbb3d 1702 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 1703 mmiowb();
1704
1705 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 1706 sdhci_enable_card_detection(host);
1707
2f4cbb3d 1708 return ret;
d129bceb
PO		 1709}
1710
b8c86fc5 1711EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 1712
5f619704
DD		 1713void sdhci_enable_irq_wakeups(struct sdhci_host *host)
1714{
1715 u8 val;
1716 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
1717 val |= SDHCI_WAKE_ON_INT;
1718 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
1719}
1720
1721EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
1722
d129bceb
PO		 1723#endif /* CONFIG_PM */
1724
1725/*****************************************************************************\
1726 * *
b8c86fc5 1727 * Device allocation/registration *
d129bceb
PO		 1728 * *
1729\*****************************************************************************/
1730
b8c86fc5
PO		 1731struct sdhci_host *sdhci_alloc_host(struct device *dev,
1732 size_t priv_size)
d129bceb 1733{
d129bceb
PO		 1734 struct mmc_host *mmc;
1735 struct sdhci_host *host;
1736
b8c86fc5 1737 WARN_ON(dev == NULL);
d129bceb 1738
b8c86fc5 1739 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 1740 if (!mmc)
b8c86fc5 1741 return ERR_PTR(-ENOMEM);
d129bceb
PO		 1742
1743 host = mmc_priv(mmc);
1744 host->mmc = mmc;
1745
b8c86fc5
PO		 1746 return host;
1747}
8a4da143 1748
b8c86fc5 1749EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 1750
b8c86fc5
PO		 1751int sdhci_add_host(struct sdhci_host *host)
1752{
1753 struct mmc_host *mmc;
8f230f45 1754 unsigned int caps, ocr_avail;
b8c86fc5 1755 int ret;
d129bceb 1756
b8c86fc5
PO		 1757 WARN_ON(host == NULL);
1758 if (host == NULL)
1759 return -EINVAL;
d129bceb 1760
b8c86fc5 1761 mmc = host->mmc;
d129bceb 1762
b8c86fc5
PO		 1763 if (debug_quirks)
1764 host->quirks = debug_quirks;
d129bceb 1765
d96649ed
PO		 1766 sdhci_reset(host, SDHCI_RESET_ALL);
1767
4e4141a5 1768 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 1769 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1770 >> SDHCI_SPEC_VER_SHIFT;
85105c53 1771 if (host->version > SDHCI_SPEC_300) {
4a965505 1772 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 1773 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 1774 host->version);
4a965505
PO		 1775 }
1776
ccc92c23
ML		 1777 caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
1778 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 1779
b8c86fc5 1780 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b
RR		 1781 host->flags |= SDHCI_USE_SDMA;
1782 else if (!(caps & SDHCI_CAN_DO_SDMA))
1783 DBG("Controller doesn't have SDMA capability\n");
67435274 1784 else
a13abc7b 1785 host->flags |= SDHCI_USE_SDMA;
d129bceb 1786
b8c86fc5 1787 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 1788 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 1789 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 1790 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 1791 }
1792
a13abc7b
RR		 1793 if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1794 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 1795
1796 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1797 (host->flags & SDHCI_USE_ADMA)) {
1798 DBG("Disabling ADMA as it is marked broken\n");
1799 host->flags &= ~SDHCI_USE_ADMA;
1800 }
1801
a13abc7b 1802 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 1803 if (host->ops->enable_dma) {
1804 if (host->ops->enable_dma(host)) {
1805 printk(KERN_WARNING "%s: No suitable DMA "
1806 "available. Falling back to PIO.\n",
1807 mmc_hostname(mmc));
a13abc7b
RR		 1808 host->flags &=
1809 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 1810 }
d129bceb
PO		 1811 }
1812 }
1813
2134a922
PO		 1814 if (host->flags & SDHCI_USE_ADMA) {
1815 /*
1816 * We need to allocate descriptors for all sg entries
1817 * (128) and potentially one alignment transfer for
1818 * each of those entries.
1819 */
1820 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1821 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1822 if (!host->adma_desc || !host->align_buffer) {
1823 kfree(host->adma_desc);
1824 kfree(host->align_buffer);
1825 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1826 "buffers. Falling back to standard DMA.\n",
1827 mmc_hostname(mmc));
1828 host->flags &= ~SDHCI_USE_ADMA;
1829 }
1830 }
1831
7659150c
PO		 1832 /*
1833 * If we use DMA, then it's up to the caller to set the DMA
1834 * mask, but PIO does not need the hw shim so we set a new
1835 * mask here in that case.
1836 */
a13abc7b 1837 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 1838 host->dma_mask = DMA_BIT_MASK(64);
1839 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1840 }
d129bceb 1841
c4687d5f
ZG		 1842 if (host->version >= SDHCI_SPEC_300)
1843 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK)
1844 >> SDHCI_CLOCK_BASE_SHIFT;
1845 else
1846 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK)
1847 >> SDHCI_CLOCK_BASE_SHIFT;
1848
4240ff0a 1849 host->max_clk *= 1000000;
f27f47ef
AV		 1850 if (host->max_clk == 0 || host->quirks &
1851 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a
BD		 1852 if (!host->ops->get_max_clock) {
1853 printk(KERN_ERR
1854 "%s: Hardware doesn't specify base clock "
1855 "frequency.\n", mmc_hostname(mmc));
1856 return -ENODEV;
1857 }
1858 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 1859 }
d129bceb 1860
1c8cde92
PO		 1861 host->timeout_clk =
1862 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1863 if (host->timeout_clk == 0) {
81b39802
AV		 1864 if (host->ops->get_timeout_clock) {
1865 host->timeout_clk = host->ops->get_timeout_clock(host);
1866 } else if (!(host->quirks &
1867 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4240ff0a
BD		 1868 printk(KERN_ERR
1869 "%s: Hardware doesn't specify timeout clock "
1870 "frequency.\n", mmc_hostname(mmc));
1871 return -ENODEV;
1872 }
1c8cde92
PO		 1873 }
1874 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1875 host->timeout_clk *= 1000;
d129bceb
PO		 1876
1877 /*
1878 * Set host parameters.
1879 */
1880 mmc->ops = &sdhci_ops;
ce5f036b 1881 if (host->ops->get_min_clock)
a9e58f25 1882 mmc->f_min = host->ops->get_min_clock(host);
0397526d
ZG		 1883 else if (host->version >= SDHCI_SPEC_300)
1884 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
a9e58f25 1885 else
0397526d 1886 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 1887
d129bceb 1888 mmc->f_max = host->max_clk;
c1f5977c 1889 mmc->caps |= MMC_CAP_SDIO_IRQ;
5fe23c7f 1890
15ec4461
PR		 1891 /*
1892 * A controller may support 8-bit width, but the board itself
1893 * might not have the pins brought out. Boards that support
1894 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
1895 * their platform code before calling sdhci_add_host(), and we
1896 * won't assume 8-bit width for hosts without that CAP.
1897 */
5fe23c7f 1898 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 1899 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 1900
86a6a874 1901 if (caps & SDHCI_CAN_DO_HISPD)
a29e7e18 1902 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 1903
176d1ed4
JC		 1904 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
1905 mmc_card_is_removable(mmc))
68d1fb7e
AV		 1906 mmc->caps |= MMC_CAP_NEEDS_POLL;
1907
8f230f45 1908 ocr_avail = 0;
146ad66e 1909 if (caps & SDHCI_CAN_VDD_330)
8f230f45 1910 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
c70840e8 1911 if (caps & SDHCI_CAN_VDD_300)
8f230f45 1912 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
c70840e8 1913 if (caps & SDHCI_CAN_VDD_180)
8f230f45
TI		 1914 ocr_avail |= MMC_VDD_165_195;
1915
1916 mmc->ocr_avail = ocr_avail;
1917 mmc->ocr_avail_sdio = ocr_avail;
1918 if (host->ocr_avail_sdio)
1919 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
1920 mmc->ocr_avail_sd = ocr_avail;
1921 if (host->ocr_avail_sd)
1922 mmc->ocr_avail_sd &= host->ocr_avail_sd;
1923 else /* normal SD controllers don't support 1.8V */
1924 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
1925 mmc->ocr_avail_mmc = ocr_avail;
1926 if (host->ocr_avail_mmc)
1927 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 1928
1929 if (mmc->ocr_avail == 0) {
1930 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 1931 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 1932 return -ENODEV;
146ad66e
PO		 1933 }
1934
d129bceb
PO		 1935 spin_lock_init(&host->lock);
1936
1937 /*
2134a922
PO		 1938 * Maximum number of segments. Depends on if the hardware
1939 * can do scatter/gather or not.
d129bceb 1940 */
2134a922 1941 if (host->flags & SDHCI_USE_ADMA)
a36274e0 1942 mmc->max_segs = 128;
a13abc7b 1943 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 1944 mmc->max_segs = 1;
2134a922 1945 else /* PIO */
a36274e0 1946 mmc->max_segs = 128;
d129bceb
PO		 1947
1948 /*
bab76961 1949 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1950 * size (512KiB).
d129bceb 1951 */
55db890a 1952 mmc->max_req_size = 524288;
d129bceb
PO		 1953
1954 /*
1955 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 1956 * of bytes. When doing hardware scatter/gather, each entry cannot
1957 * be larger than 64 KiB though.
d129bceb 1958 */
30652aa3
OJ		 1959 if (host->flags & SDHCI_USE_ADMA) {
1960 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
1961 mmc->max_seg_size = 65535;
1962 else
1963 mmc->max_seg_size = 65536;
1964 } else {
2134a922 1965 mmc->max_seg_size = mmc->max_req_size;
30652aa3 1966 }
d129bceb 1967
fe4a3c7a
PO		 1968 /*
1969 * Maximum block size. This varies from controller to controller and
1970 * is specified in the capabilities register.
1971 */
0633f654
AV		 1972 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1973 mmc->max_blk_size = 2;
1974 } else {
1975 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1976 SDHCI_MAX_BLOCK_SHIFT;
1977 if (mmc->max_blk_size >= 3) {
1978 printk(KERN_WARNING "%s: Invalid maximum block size, "
1979 "assuming 512 bytes\n", mmc_hostname(mmc));
1980 mmc->max_blk_size = 0;
1981 }
1982 }
1983
1984 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 1985
55db890a
PO		 1986 /*
1987 * Maximum block count.
1988 */
1388eefd 1989 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 1990
d129bceb
PO		 1991 /*
1992 * Init tasklets.
1993 */
1994 tasklet_init(&host->card_tasklet,
1995 sdhci_tasklet_card, (unsigned long)host);
1996 tasklet_init(&host->finish_tasklet,
1997 sdhci_tasklet_finish, (unsigned long)host);
1998
e4cad1b5 1999 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 2000
dace1453 2001 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 2002 mmc_hostname(mmc), host);
d129bceb 2003 if (ret)
8ef1a143 2004 goto untasklet;
d129bceb 2005
9bea3c85
MS		 2006 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2007 if (IS_ERR(host->vmmc)) {
2008 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2009 host->vmmc = NULL;
2010 } else {
2011 regulator_enable(host->vmmc);
2012 }
2013
2f4cbb3d 2014 sdhci_init(host, 0);
d129bceb
PO		 2015
2016#ifdef CONFIG_MMC_DEBUG
2017 sdhci_dumpregs(host);
2018#endif
2019
f9134319 2020#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 2021 snprintf(host->led_name, sizeof(host->led_name),
2022 "%s::", mmc_hostname(mmc));
2023 host->led.name = host->led_name;
2f730fec
PO		 2024 host->led.brightness = LED_OFF;
2025 host->led.default_trigger = mmc_hostname(mmc);
2026 host->led.brightness_set = sdhci_led_control;
2027
b8c86fc5 2028 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 2029 if (ret)
2030 goto reset;
2031#endif
2032
5f25a66f
PO		 2033 mmiowb();
2034
d129bceb
PO		 2035 mmc_add_host(mmc);
2036
a13abc7b 2037 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 2038 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 2039 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2040 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 2041
7260cf5e
AV		 2042 sdhci_enable_card_detection(host);
2043
d129bceb
PO		 2044 return 0;
2045
f9134319 2046#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2047reset:
2048 sdhci_reset(host, SDHCI_RESET_ALL);
2049 free_irq(host->irq, host);
2050#endif
8ef1a143 2051untasklet:
d129bceb
PO		 2052 tasklet_kill(&host->card_tasklet);
2053 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 2054
2055 return ret;
2056}
2057
b8c86fc5 2058EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 2059
1e72859e 2060void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 2061{
1e72859e
PO		 2062 unsigned long flags;
2063
2064 if (dead) {
2065 spin_lock_irqsave(&host->lock, flags);
2066
2067 host->flags |= SDHCI_DEVICE_DEAD;
2068
2069 if (host->mrq) {
2070 printk(KERN_ERR "%s: Controller removed during "
2071 " transfer!\n", mmc_hostname(host->mmc));
2072
2073 host->mrq->cmd->error = -ENOMEDIUM;
2074 tasklet_schedule(&host->finish_tasklet);
2075 }
2076
2077 spin_unlock_irqrestore(&host->lock, flags);
2078 }
2079
7260cf5e
AV		 2080 sdhci_disable_card_detection(host);
2081
b8c86fc5 2082 mmc_remove_host(host->mmc);
d129bceb 2083
f9134319 2084#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2085 led_classdev_unregister(&host->led);
2086#endif
2087
1e72859e
PO		 2088 if (!dead)
2089 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 2090
2091 free_irq(host->irq, host);
2092
2093 del_timer_sync(&host->timer);
2094
2095 tasklet_kill(&host->card_tasklet);
2096 tasklet_kill(&host->finish_tasklet);
2134a922 2097
9bea3c85
MS		 2098 if (host->vmmc) {
2099 regulator_disable(host->vmmc);
2100 regulator_put(host->vmmc);
2101 }
2102
2134a922
PO		 2103 kfree(host->adma_desc);
2104 kfree(host->align_buffer);
2105
2106 host->adma_desc = NULL;
2107 host->align_buffer = NULL;
d129bceb
PO		 2108}
2109
b8c86fc5 2110EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 2111
b8c86fc5 2112void sdhci_free_host(struct sdhci_host *host)
d129bceb 2113{
b8c86fc5 2114 mmc_free_host(host->mmc);
d129bceb
PO		 2115}
2116
b8c86fc5 2117EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 2118
2119/*****************************************************************************\
2120 * *
2121 * Driver init/exit *
2122 * *
2123\*****************************************************************************/
2124
2125static int __init sdhci_drv_init(void)
2126{
2127 printk(KERN_INFO DRIVER_NAME
52fbf9c9 2128 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 2129 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2130
b8c86fc5 2131 return 0;
d129bceb
PO		 2132}
2133
2134static void __exit sdhci_drv_exit(void)
2135{
d129bceb
PO		 2136}
2137
2138module_init(sdhci_drv_init);
2139module_exit(sdhci_drv_exit);
2140
df673b22 2141module_param(debug_quirks, uint, 0444);
67435274 2142
32710e8f 2143MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 2144MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 2145MODULE_LICENSE("GPL");
67435274 2146
df673b22 2147MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux 6.x block layer and io_uring tree(s)