Commit | Line | Data |
---|---|---|
d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
b8c86fc5 | 18 | #include <linux/io.h> |
88b47679 | 19 | #include <linux/module.h> |
d129bceb | 20 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
11763609 | 22 | #include <linux/scatterlist.h> |
9bea3c85 | 23 | #include <linux/regulator/consumer.h> |
66fd8ad5 | 24 | #include <linux/pm_runtime.h> |
d129bceb | 25 | |
2f730fec PO |
26 | #include <linux/leds.h> |
27 | ||
22113efd | 28 | #include <linux/mmc/mmc.h> |
d129bceb | 29 | #include <linux/mmc/host.h> |
473b095a | 30 | #include <linux/mmc/card.h> |
bec9d4e5 | 31 | #include <linux/mmc/slot-gpio.h> |
d129bceb | 32 | |
d129bceb PO |
33 | #include "sdhci.h" |
34 | ||
35 | #define DRIVER_NAME "sdhci" | |
d129bceb | 36 | |
d129bceb | 37 | #define DBG(f, x...) \ |
c6563178 | 38 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 39 | |
f9134319 PO |
40 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
41 | defined(CONFIG_MMC_SDHCI_MODULE)) | |
42 | #define SDHCI_USE_LEDS_CLASS | |
43 | #endif | |
44 | ||
b513ea25 AN |
45 | #define MAX_TUNING_LOOP 40 |
46 | ||
df673b22 | 47 | static unsigned int debug_quirks = 0; |
66fd8ad5 | 48 | static unsigned int debug_quirks2; |
67435274 | 49 | |
d129bceb PO |
50 | static void sdhci_finish_data(struct sdhci_host *); |
51 | ||
d129bceb | 52 | static void sdhci_finish_command(struct sdhci_host *); |
069c9f14 | 53 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); |
cf2b5eea | 54 | static void sdhci_tuning_timer(unsigned long data); |
52983382 | 55 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); |
d129bceb | 56 | |
66fd8ad5 AH |
57 | #ifdef CONFIG_PM_RUNTIME |
58 | static int sdhci_runtime_pm_get(struct sdhci_host *host); | |
59 | static int sdhci_runtime_pm_put(struct sdhci_host *host); | |
f0710a55 AH |
60 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); |
61 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); | |
66fd8ad5 AH |
62 | #else |
63 | static inline int sdhci_runtime_pm_get(struct sdhci_host *host) | |
64 | { | |
65 | return 0; | |
66 | } | |
67 | static inline int sdhci_runtime_pm_put(struct sdhci_host *host) | |
68 | { | |
69 | return 0; | |
70 | } | |
f0710a55 AH |
71 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
72 | { | |
73 | } | |
74 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) | |
75 | { | |
76 | } | |
66fd8ad5 AH |
77 | #endif |
78 | ||
d129bceb PO |
79 | static void sdhci_dumpregs(struct sdhci_host *host) |
80 | { | |
a3c76eb9 | 81 | pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", |
412ab659 | 82 | mmc_hostname(host->mmc)); |
d129bceb | 83 | |
a3c76eb9 | 84 | pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", |
4e4141a5 AV |
85 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
86 | sdhci_readw(host, SDHCI_HOST_VERSION)); | |
a3c76eb9 | 87 | pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
4e4141a5 AV |
88 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
89 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); | |
a3c76eb9 | 90 | pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
4e4141a5 AV |
91 | sdhci_readl(host, SDHCI_ARGUMENT), |
92 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); | |
a3c76eb9 | 93 | pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
4e4141a5 AV |
94 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
95 | sdhci_readb(host, SDHCI_HOST_CONTROL)); | |
a3c76eb9 | 96 | pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
4e4141a5 AV |
97 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
98 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); | |
a3c76eb9 | 99 | pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
4e4141a5 AV |
100 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
101 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); | |
a3c76eb9 | 102 | pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
4e4141a5 AV |
103 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
104 | sdhci_readl(host, SDHCI_INT_STATUS)); | |
a3c76eb9 | 105 | pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
4e4141a5 AV |
106 | sdhci_readl(host, SDHCI_INT_ENABLE), |
107 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); | |
a3c76eb9 | 108 | pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
4e4141a5 AV |
109 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
110 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); | |
a3c76eb9 | 111 | pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", |
4e4141a5 | 112 | sdhci_readl(host, SDHCI_CAPABILITIES), |
e8120ad1 | 113 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
a3c76eb9 | 114 | pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", |
e8120ad1 | 115 | sdhci_readw(host, SDHCI_COMMAND), |
4e4141a5 | 116 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
a3c76eb9 | 117 | pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", |
f2119df6 | 118 | sdhci_readw(host, SDHCI_HOST_CONTROL2)); |
d129bceb | 119 | |
be3f4ae0 | 120 | if (host->flags & SDHCI_USE_ADMA) |
a3c76eb9 | 121 | pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", |
be3f4ae0 BD |
122 | readl(host->ioaddr + SDHCI_ADMA_ERROR), |
123 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
124 | ||
a3c76eb9 | 125 | pr_debug(DRIVER_NAME ": ===========================================\n"); |
d129bceb PO |
126 | } |
127 | ||
128 | /*****************************************************************************\ | |
129 | * * | |
130 | * Low level functions * | |
131 | * * | |
132 | \*****************************************************************************/ | |
133 | ||
7260cf5e AV |
134 | static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) |
135 | { | |
136 | u32 ier; | |
137 | ||
138 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
139 | ier &= ~clear; | |
140 | ier |= set; | |
141 | sdhci_writel(host, ier, SDHCI_INT_ENABLE); | |
142 | sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); | |
143 | } | |
144 | ||
145 | static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) | |
146 | { | |
147 | sdhci_clear_set_irqs(host, 0, irqs); | |
148 | } | |
149 | ||
150 | static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) | |
151 | { | |
152 | sdhci_clear_set_irqs(host, irqs, 0); | |
153 | } | |
154 | ||
155 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) | |
156 | { | |
d25928d1 | 157 | u32 present, irqs; |
7260cf5e | 158 | |
c79396c1 | 159 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || |
87b87a3f | 160 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) |
66fd8ad5 AH |
161 | return; |
162 | ||
d25928d1 SG |
163 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
164 | SDHCI_CARD_PRESENT; | |
165 | irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT; | |
166 | ||
7260cf5e AV |
167 | if (enable) |
168 | sdhci_unmask_irqs(host, irqs); | |
169 | else | |
170 | sdhci_mask_irqs(host, irqs); | |
171 | } | |
172 | ||
173 | static void sdhci_enable_card_detection(struct sdhci_host *host) | |
174 | { | |
175 | sdhci_set_card_detection(host, true); | |
176 | } | |
177 | ||
178 | static void sdhci_disable_card_detection(struct sdhci_host *host) | |
179 | { | |
180 | sdhci_set_card_detection(host, false); | |
181 | } | |
182 | ||
d129bceb PO |
183 | static void sdhci_reset(struct sdhci_host *host, u8 mask) |
184 | { | |
e16514d8 | 185 | unsigned long timeout; |
063a9dbb | 186 | u32 uninitialized_var(ier); |
e16514d8 | 187 | |
b8c86fc5 | 188 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
4e4141a5 | 189 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & |
8a4da143 PO |
190 | SDHCI_CARD_PRESENT)) |
191 | return; | |
192 | } | |
193 | ||
063a9dbb AV |
194 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) |
195 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
196 | ||
393c1a34 PR |
197 | if (host->ops->platform_reset_enter) |
198 | host->ops->platform_reset_enter(host, mask); | |
199 | ||
4e4141a5 | 200 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
d129bceb | 201 | |
f0710a55 | 202 | if (mask & SDHCI_RESET_ALL) { |
d129bceb | 203 | host->clock = 0; |
f0710a55 AH |
204 | /* Reset-all turns off SD Bus Power */ |
205 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) | |
206 | sdhci_runtime_pm_bus_off(host); | |
207 | } | |
d129bceb | 208 | |
e16514d8 PO |
209 | /* Wait max 100 ms */ |
210 | timeout = 100; | |
211 | ||
212 | /* hw clears the bit when it's done */ | |
4e4141a5 | 213 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
e16514d8 | 214 | if (timeout == 0) { |
a3c76eb9 | 215 | pr_err("%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
216 | mmc_hostname(host->mmc), (int)mask); |
217 | sdhci_dumpregs(host); | |
218 | return; | |
219 | } | |
220 | timeout--; | |
221 | mdelay(1); | |
d129bceb | 222 | } |
063a9dbb | 223 | |
393c1a34 PR |
224 | if (host->ops->platform_reset_exit) |
225 | host->ops->platform_reset_exit(host, mask); | |
226 | ||
063a9dbb AV |
227 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) |
228 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); | |
3abc1e80 SX |
229 | |
230 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { | |
231 | if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL)) | |
232 | host->ops->enable_dma(host); | |
233 | } | |
d129bceb PO |
234 | } |
235 | ||
2f4cbb3d NP |
236 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
237 | ||
238 | static void sdhci_init(struct sdhci_host *host, int soft) | |
d129bceb | 239 | { |
2f4cbb3d NP |
240 | if (soft) |
241 | sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); | |
242 | else | |
243 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb | 244 | |
7260cf5e AV |
245 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, |
246 | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | | |
3192a28f PO |
247 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | |
248 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | |
6aa943ab | 249 | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); |
2f4cbb3d NP |
250 | |
251 | if (soft) { | |
252 | /* force clock reconfiguration */ | |
253 | host->clock = 0; | |
254 | sdhci_set_ios(host->mmc, &host->mmc->ios); | |
255 | } | |
7260cf5e | 256 | } |
d129bceb | 257 | |
7260cf5e AV |
258 | static void sdhci_reinit(struct sdhci_host *host) |
259 | { | |
2f4cbb3d | 260 | sdhci_init(host, 0); |
b67c6b41 AL |
261 | /* |
262 | * Retuning stuffs are affected by different cards inserted and only | |
263 | * applicable to UHS-I cards. So reset these fields to their initial | |
264 | * value when card is removed. | |
265 | */ | |
973905fe AL |
266 | if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
267 | host->flags &= ~SDHCI_USING_RETUNING_TIMER; | |
268 | ||
b67c6b41 AL |
269 | del_timer_sync(&host->tuning_timer); |
270 | host->flags &= ~SDHCI_NEEDS_RETUNING; | |
271 | host->mmc->max_blk_count = | |
272 | (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; | |
273 | } | |
7260cf5e | 274 | sdhci_enable_card_detection(host); |
d129bceb PO |
275 | } |
276 | ||
277 | static void sdhci_activate_led(struct sdhci_host *host) | |
278 | { | |
279 | u8 ctrl; | |
280 | ||
4e4141a5 | 281 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 282 | ctrl |= SDHCI_CTRL_LED; |
4e4141a5 | 283 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
284 | } |
285 | ||
286 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
287 | { | |
288 | u8 ctrl; | |
289 | ||
4e4141a5 | 290 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 291 | ctrl &= ~SDHCI_CTRL_LED; |
4e4141a5 | 292 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
293 | } |
294 | ||
f9134319 | 295 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
296 | static void sdhci_led_control(struct led_classdev *led, |
297 | enum led_brightness brightness) | |
298 | { | |
299 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
300 | unsigned long flags; | |
301 | ||
302 | spin_lock_irqsave(&host->lock, flags); | |
303 | ||
66fd8ad5 AH |
304 | if (host->runtime_suspended) |
305 | goto out; | |
306 | ||
2f730fec PO |
307 | if (brightness == LED_OFF) |
308 | sdhci_deactivate_led(host); | |
309 | else | |
310 | sdhci_activate_led(host); | |
66fd8ad5 | 311 | out: |
2f730fec PO |
312 | spin_unlock_irqrestore(&host->lock, flags); |
313 | } | |
314 | #endif | |
315 | ||
d129bceb PO |
316 | /*****************************************************************************\ |
317 | * * | |
318 | * Core functions * | |
319 | * * | |
320 | \*****************************************************************************/ | |
321 | ||
a406f5a3 | 322 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 323 | { |
7659150c PO |
324 | unsigned long flags; |
325 | size_t blksize, len, chunk; | |
7244b85b | 326 | u32 uninitialized_var(scratch); |
7659150c | 327 | u8 *buf; |
d129bceb | 328 | |
a406f5a3 | 329 | DBG("PIO reading\n"); |
d129bceb | 330 | |
a406f5a3 | 331 | blksize = host->data->blksz; |
7659150c | 332 | chunk = 0; |
d129bceb | 333 | |
7659150c | 334 | local_irq_save(flags); |
d129bceb | 335 | |
a406f5a3 | 336 | while (blksize) { |
7659150c PO |
337 | if (!sg_miter_next(&host->sg_miter)) |
338 | BUG(); | |
d129bceb | 339 | |
7659150c | 340 | len = min(host->sg_miter.length, blksize); |
d129bceb | 341 | |
7659150c PO |
342 | blksize -= len; |
343 | host->sg_miter.consumed = len; | |
14d836e7 | 344 | |
7659150c | 345 | buf = host->sg_miter.addr; |
d129bceb | 346 | |
7659150c PO |
347 | while (len) { |
348 | if (chunk == 0) { | |
4e4141a5 | 349 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
7659150c | 350 | chunk = 4; |
a406f5a3 | 351 | } |
7659150c PO |
352 | |
353 | *buf = scratch & 0xFF; | |
354 | ||
355 | buf++; | |
356 | scratch >>= 8; | |
357 | chunk--; | |
358 | len--; | |
d129bceb | 359 | } |
a406f5a3 | 360 | } |
7659150c PO |
361 | |
362 | sg_miter_stop(&host->sg_miter); | |
363 | ||
364 | local_irq_restore(flags); | |
a406f5a3 | 365 | } |
d129bceb | 366 | |
a406f5a3 PO |
367 | static void sdhci_write_block_pio(struct sdhci_host *host) |
368 | { | |
7659150c PO |
369 | unsigned long flags; |
370 | size_t blksize, len, chunk; | |
371 | u32 scratch; | |
372 | u8 *buf; | |
d129bceb | 373 | |
a406f5a3 PO |
374 | DBG("PIO writing\n"); |
375 | ||
376 | blksize = host->data->blksz; | |
7659150c PO |
377 | chunk = 0; |
378 | scratch = 0; | |
d129bceb | 379 | |
7659150c | 380 | local_irq_save(flags); |
d129bceb | 381 | |
a406f5a3 | 382 | while (blksize) { |
7659150c PO |
383 | if (!sg_miter_next(&host->sg_miter)) |
384 | BUG(); | |
a406f5a3 | 385 | |
7659150c PO |
386 | len = min(host->sg_miter.length, blksize); |
387 | ||
388 | blksize -= len; | |
389 | host->sg_miter.consumed = len; | |
390 | ||
391 | buf = host->sg_miter.addr; | |
d129bceb | 392 | |
7659150c PO |
393 | while (len) { |
394 | scratch |= (u32)*buf << (chunk * 8); | |
395 | ||
396 | buf++; | |
397 | chunk++; | |
398 | len--; | |
399 | ||
400 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { | |
4e4141a5 | 401 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
7659150c PO |
402 | chunk = 0; |
403 | scratch = 0; | |
d129bceb | 404 | } |
d129bceb PO |
405 | } |
406 | } | |
7659150c PO |
407 | |
408 | sg_miter_stop(&host->sg_miter); | |
409 | ||
410 | local_irq_restore(flags); | |
a406f5a3 PO |
411 | } |
412 | ||
413 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
414 | { | |
415 | u32 mask; | |
416 | ||
417 | BUG_ON(!host->data); | |
418 | ||
7659150c | 419 | if (host->blocks == 0) |
a406f5a3 PO |
420 | return; |
421 | ||
422 | if (host->data->flags & MMC_DATA_READ) | |
423 | mask = SDHCI_DATA_AVAILABLE; | |
424 | else | |
425 | mask = SDHCI_SPACE_AVAILABLE; | |
426 | ||
4a3cba32 PO |
427 | /* |
428 | * Some controllers (JMicron JMB38x) mess up the buffer bits | |
429 | * for transfers < 4 bytes. As long as it is just one block, | |
430 | * we can ignore the bits. | |
431 | */ | |
432 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && | |
433 | (host->data->blocks == 1)) | |
434 | mask = ~0; | |
435 | ||
4e4141a5 | 436 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
3e3bf207 AV |
437 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
438 | udelay(100); | |
439 | ||
a406f5a3 PO |
440 | if (host->data->flags & MMC_DATA_READ) |
441 | sdhci_read_block_pio(host); | |
442 | else | |
443 | sdhci_write_block_pio(host); | |
d129bceb | 444 | |
7659150c PO |
445 | host->blocks--; |
446 | if (host->blocks == 0) | |
a406f5a3 | 447 | break; |
a406f5a3 | 448 | } |
d129bceb | 449 | |
a406f5a3 | 450 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
451 | } |
452 | ||
2134a922 PO |
453 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
454 | { | |
455 | local_irq_save(*flags); | |
482fce99 | 456 | return kmap_atomic(sg_page(sg)) + sg->offset; |
2134a922 PO |
457 | } |
458 | ||
459 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) | |
460 | { | |
482fce99 | 461 | kunmap_atomic(buffer); |
2134a922 PO |
462 | local_irq_restore(*flags); |
463 | } | |
464 | ||
118cd17d BD |
465 | static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) |
466 | { | |
9e506f35 BD |
467 | __le32 *dataddr = (__le32 __force *)(desc + 4); |
468 | __le16 *cmdlen = (__le16 __force *)desc; | |
118cd17d | 469 | |
9e506f35 BD |
470 | /* SDHCI specification says ADMA descriptors should be 4 byte |
471 | * aligned, so using 16 or 32bit operations should be safe. */ | |
118cd17d | 472 | |
9e506f35 BD |
473 | cmdlen[0] = cpu_to_le16(cmd); |
474 | cmdlen[1] = cpu_to_le16(len); | |
475 | ||
476 | dataddr[0] = cpu_to_le32(addr); | |
118cd17d BD |
477 | } |
478 | ||
8f1934ce | 479 | static int sdhci_adma_table_pre(struct sdhci_host *host, |
2134a922 PO |
480 | struct mmc_data *data) |
481 | { | |
482 | int direction; | |
483 | ||
484 | u8 *desc; | |
485 | u8 *align; | |
486 | dma_addr_t addr; | |
487 | dma_addr_t align_addr; | |
488 | int len, offset; | |
489 | ||
490 | struct scatterlist *sg; | |
491 | int i; | |
492 | char *buffer; | |
493 | unsigned long flags; | |
494 | ||
495 | /* | |
496 | * The spec does not specify endianness of descriptor table. | |
497 | * We currently guess that it is LE. | |
498 | */ | |
499 | ||
500 | if (data->flags & MMC_DATA_READ) | |
501 | direction = DMA_FROM_DEVICE; | |
502 | else | |
503 | direction = DMA_TO_DEVICE; | |
504 | ||
505 | /* | |
506 | * The ADMA descriptor table is mapped further down as we | |
507 | * need to fill it with data first. | |
508 | */ | |
509 | ||
510 | host->align_addr = dma_map_single(mmc_dev(host->mmc), | |
511 | host->align_buffer, 128 * 4, direction); | |
8d8bb39b | 512 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) |
8f1934ce | 513 | goto fail; |
2134a922 PO |
514 | BUG_ON(host->align_addr & 0x3); |
515 | ||
516 | host->sg_count = dma_map_sg(mmc_dev(host->mmc), | |
517 | data->sg, data->sg_len, direction); | |
8f1934ce PO |
518 | if (host->sg_count == 0) |
519 | goto unmap_align; | |
2134a922 PO |
520 | |
521 | desc = host->adma_desc; | |
522 | align = host->align_buffer; | |
523 | ||
524 | align_addr = host->align_addr; | |
525 | ||
526 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
527 | addr = sg_dma_address(sg); | |
528 | len = sg_dma_len(sg); | |
529 | ||
530 | /* | |
531 | * The SDHCI specification states that ADMA | |
532 | * addresses must be 32-bit aligned. If they | |
533 | * aren't, then we use a bounce buffer for | |
534 | * the (up to three) bytes that screw up the | |
535 | * alignment. | |
536 | */ | |
537 | offset = (4 - (addr & 0x3)) & 0x3; | |
538 | if (offset) { | |
539 | if (data->flags & MMC_DATA_WRITE) { | |
540 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 541 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
542 | memcpy(align, buffer, offset); |
543 | sdhci_kunmap_atomic(buffer, &flags); | |
544 | } | |
545 | ||
118cd17d BD |
546 | /* tran, valid */ |
547 | sdhci_set_adma_desc(desc, align_addr, offset, 0x21); | |
2134a922 PO |
548 | |
549 | BUG_ON(offset > 65536); | |
550 | ||
2134a922 PO |
551 | align += 4; |
552 | align_addr += 4; | |
553 | ||
554 | desc += 8; | |
555 | ||
556 | addr += offset; | |
557 | len -= offset; | |
558 | } | |
559 | ||
2134a922 PO |
560 | BUG_ON(len > 65536); |
561 | ||
118cd17d BD |
562 | /* tran, valid */ |
563 | sdhci_set_adma_desc(desc, addr, len, 0x21); | |
2134a922 PO |
564 | desc += 8; |
565 | ||
566 | /* | |
567 | * If this triggers then we have a calculation bug | |
568 | * somewhere. :/ | |
569 | */ | |
570 | WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); | |
571 | } | |
572 | ||
70764a90 TA |
573 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
574 | /* | |
575 | * Mark the last descriptor as the terminating descriptor | |
576 | */ | |
577 | if (desc != host->adma_desc) { | |
578 | desc -= 8; | |
579 | desc[0] |= 0x2; /* end */ | |
580 | } | |
581 | } else { | |
582 | /* | |
583 | * Add a terminating entry. | |
584 | */ | |
2134a922 | 585 | |
70764a90 TA |
586 | /* nop, end, valid */ |
587 | sdhci_set_adma_desc(desc, 0, 0, 0x3); | |
588 | } | |
2134a922 PO |
589 | |
590 | /* | |
591 | * Resync align buffer as we might have changed it. | |
592 | */ | |
593 | if (data->flags & MMC_DATA_WRITE) { | |
594 | dma_sync_single_for_device(mmc_dev(host->mmc), | |
595 | host->align_addr, 128 * 4, direction); | |
596 | } | |
597 | ||
598 | host->adma_addr = dma_map_single(mmc_dev(host->mmc), | |
599 | host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
980167b7 | 600 | if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) |
8f1934ce | 601 | goto unmap_entries; |
2134a922 | 602 | BUG_ON(host->adma_addr & 0x3); |
8f1934ce PO |
603 | |
604 | return 0; | |
605 | ||
606 | unmap_entries: | |
607 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
608 | data->sg_len, direction); | |
609 | unmap_align: | |
610 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
611 | 128 * 4, direction); | |
612 | fail: | |
613 | return -EINVAL; | |
2134a922 PO |
614 | } |
615 | ||
616 | static void sdhci_adma_table_post(struct sdhci_host *host, | |
617 | struct mmc_data *data) | |
618 | { | |
619 | int direction; | |
620 | ||
621 | struct scatterlist *sg; | |
622 | int i, size; | |
623 | u8 *align; | |
624 | char *buffer; | |
625 | unsigned long flags; | |
626 | ||
627 | if (data->flags & MMC_DATA_READ) | |
628 | direction = DMA_FROM_DEVICE; | |
629 | else | |
630 | direction = DMA_TO_DEVICE; | |
631 | ||
632 | dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, | |
633 | (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
634 | ||
635 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
636 | 128 * 4, direction); | |
637 | ||
638 | if (data->flags & MMC_DATA_READ) { | |
639 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, | |
640 | data->sg_len, direction); | |
641 | ||
642 | align = host->align_buffer; | |
643 | ||
644 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
645 | if (sg_dma_address(sg) & 0x3) { | |
646 | size = 4 - (sg_dma_address(sg) & 0x3); | |
647 | ||
648 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 649 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
650 | memcpy(buffer, align, size); |
651 | sdhci_kunmap_atomic(buffer, &flags); | |
652 | ||
653 | align += 4; | |
654 | } | |
655 | } | |
656 | } | |
657 | ||
658 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
659 | data->sg_len, direction); | |
660 | } | |
661 | ||
a3c7778f | 662 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb | 663 | { |
1c8cde92 | 664 | u8 count; |
a3c7778f | 665 | struct mmc_data *data = cmd->data; |
1c8cde92 | 666 | unsigned target_timeout, current_timeout; |
d129bceb | 667 | |
ee53ab5d PO |
668 | /* |
669 | * If the host controller provides us with an incorrect timeout | |
670 | * value, just skip the check and use 0xE. The hardware may take | |
671 | * longer to time out, but that's much better than having a too-short | |
672 | * timeout value. | |
673 | */ | |
11a2f1b7 | 674 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
ee53ab5d | 675 | return 0xE; |
e538fbe8 | 676 | |
a3c7778f AW |
677 | /* Unspecified timeout, assume max */ |
678 | if (!data && !cmd->cmd_timeout_ms) | |
679 | return 0xE; | |
d129bceb | 680 | |
a3c7778f AW |
681 | /* timeout in us */ |
682 | if (!data) | |
683 | target_timeout = cmd->cmd_timeout_ms * 1000; | |
78a2ca27 AS |
684 | else { |
685 | target_timeout = data->timeout_ns / 1000; | |
686 | if (host->clock) | |
687 | target_timeout += data->timeout_clks / host->clock; | |
688 | } | |
81b39802 | 689 | |
1c8cde92 PO |
690 | /* |
691 | * Figure out needed cycles. | |
692 | * We do this in steps in order to fit inside a 32 bit int. | |
693 | * The first step is the minimum timeout, which will have a | |
694 | * minimum resolution of 6 bits: | |
695 | * (1) 2^13*1000 > 2^22, | |
696 | * (2) host->timeout_clk < 2^16 | |
697 | * => | |
698 | * (1) / (2) > 2^6 | |
699 | */ | |
700 | count = 0; | |
701 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
702 | while (current_timeout < target_timeout) { | |
703 | count++; | |
704 | current_timeout <<= 1; | |
705 | if (count >= 0xF) | |
706 | break; | |
707 | } | |
708 | ||
709 | if (count >= 0xF) { | |
09eeff52 CB |
710 | DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", |
711 | mmc_hostname(host->mmc), count, cmd->opcode); | |
1c8cde92 PO |
712 | count = 0xE; |
713 | } | |
714 | ||
ee53ab5d PO |
715 | return count; |
716 | } | |
717 | ||
6aa943ab AV |
718 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
719 | { | |
720 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; | |
721 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; | |
722 | ||
723 | if (host->flags & SDHCI_REQ_USE_DMA) | |
724 | sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); | |
725 | else | |
726 | sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); | |
727 | } | |
728 | ||
a3c7778f | 729 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) |
ee53ab5d PO |
730 | { |
731 | u8 count; | |
2134a922 | 732 | u8 ctrl; |
a3c7778f | 733 | struct mmc_data *data = cmd->data; |
8f1934ce | 734 | int ret; |
ee53ab5d PO |
735 | |
736 | WARN_ON(host->data); | |
737 | ||
a3c7778f AW |
738 | if (data || (cmd->flags & MMC_RSP_BUSY)) { |
739 | count = sdhci_calc_timeout(host, cmd); | |
740 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); | |
741 | } | |
742 | ||
743 | if (!data) | |
ee53ab5d PO |
744 | return; |
745 | ||
746 | /* Sanity checks */ | |
747 | BUG_ON(data->blksz * data->blocks > 524288); | |
748 | BUG_ON(data->blksz > host->mmc->max_blk_size); | |
749 | BUG_ON(data->blocks > 65535); | |
750 | ||
751 | host->data = data; | |
752 | host->data_early = 0; | |
f6a03cbf | 753 | host->data->bytes_xfered = 0; |
ee53ab5d | 754 | |
a13abc7b | 755 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) |
c9fddbc4 PO |
756 | host->flags |= SDHCI_REQ_USE_DMA; |
757 | ||
2134a922 PO |
758 | /* |
759 | * FIXME: This doesn't account for merging when mapping the | |
760 | * scatterlist. | |
761 | */ | |
762 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
763 | int broken, i; | |
764 | struct scatterlist *sg; | |
765 | ||
766 | broken = 0; | |
767 | if (host->flags & SDHCI_USE_ADMA) { | |
768 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
769 | broken = 1; | |
770 | } else { | |
771 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) | |
772 | broken = 1; | |
773 | } | |
774 | ||
775 | if (unlikely(broken)) { | |
776 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
777 | if (sg->length & 0x3) { | |
778 | DBG("Reverting to PIO because of " | |
779 | "transfer size (%d)\n", | |
780 | sg->length); | |
781 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
782 | break; | |
783 | } | |
784 | } | |
785 | } | |
c9fddbc4 PO |
786 | } |
787 | ||
788 | /* | |
789 | * The assumption here being that alignment is the same after | |
790 | * translation to device address space. | |
791 | */ | |
2134a922 PO |
792 | if (host->flags & SDHCI_REQ_USE_DMA) { |
793 | int broken, i; | |
794 | struct scatterlist *sg; | |
795 | ||
796 | broken = 0; | |
797 | if (host->flags & SDHCI_USE_ADMA) { | |
798 | /* | |
799 | * As we use 3 byte chunks to work around | |
800 | * alignment problems, we need to check this | |
801 | * quirk. | |
802 | */ | |
803 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
804 | broken = 1; | |
805 | } else { | |
806 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) | |
807 | broken = 1; | |
808 | } | |
809 | ||
810 | if (unlikely(broken)) { | |
811 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
812 | if (sg->offset & 0x3) { | |
813 | DBG("Reverting to PIO because of " | |
814 | "bad alignment\n"); | |
815 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
816 | break; | |
817 | } | |
818 | } | |
819 | } | |
820 | } | |
821 | ||
8f1934ce PO |
822 | if (host->flags & SDHCI_REQ_USE_DMA) { |
823 | if (host->flags & SDHCI_USE_ADMA) { | |
824 | ret = sdhci_adma_table_pre(host, data); | |
825 | if (ret) { | |
826 | /* | |
827 | * This only happens when someone fed | |
828 | * us an invalid request. | |
829 | */ | |
830 | WARN_ON(1); | |
ebd6d357 | 831 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 832 | } else { |
4e4141a5 AV |
833 | sdhci_writel(host, host->adma_addr, |
834 | SDHCI_ADMA_ADDRESS); | |
8f1934ce PO |
835 | } |
836 | } else { | |
c8b3e02e | 837 | int sg_cnt; |
8f1934ce | 838 | |
c8b3e02e | 839 | sg_cnt = dma_map_sg(mmc_dev(host->mmc), |
8f1934ce PO |
840 | data->sg, data->sg_len, |
841 | (data->flags & MMC_DATA_READ) ? | |
842 | DMA_FROM_DEVICE : | |
843 | DMA_TO_DEVICE); | |
c8b3e02e | 844 | if (sg_cnt == 0) { |
8f1934ce PO |
845 | /* |
846 | * This only happens when someone fed | |
847 | * us an invalid request. | |
848 | */ | |
849 | WARN_ON(1); | |
ebd6d357 | 850 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 851 | } else { |
719a61b4 | 852 | WARN_ON(sg_cnt != 1); |
4e4141a5 AV |
853 | sdhci_writel(host, sg_dma_address(data->sg), |
854 | SDHCI_DMA_ADDRESS); | |
8f1934ce PO |
855 | } |
856 | } | |
857 | } | |
858 | ||
2134a922 PO |
859 | /* |
860 | * Always adjust the DMA selection as some controllers | |
861 | * (e.g. JMicron) can't do PIO properly when the selection | |
862 | * is ADMA. | |
863 | */ | |
864 | if (host->version >= SDHCI_SPEC_200) { | |
4e4141a5 | 865 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
2134a922 PO |
866 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
867 | if ((host->flags & SDHCI_REQ_USE_DMA) && | |
868 | (host->flags & SDHCI_USE_ADMA)) | |
869 | ctrl |= SDHCI_CTRL_ADMA32; | |
870 | else | |
871 | ctrl |= SDHCI_CTRL_SDMA; | |
4e4141a5 | 872 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
c9fddbc4 PO |
873 | } |
874 | ||
8f1934ce | 875 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
da60a91d SAS |
876 | int flags; |
877 | ||
878 | flags = SG_MITER_ATOMIC; | |
879 | if (host->data->flags & MMC_DATA_READ) | |
880 | flags |= SG_MITER_TO_SG; | |
881 | else | |
882 | flags |= SG_MITER_FROM_SG; | |
883 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
7659150c | 884 | host->blocks = data->blocks; |
d129bceb | 885 | } |
c7fa9963 | 886 | |
6aa943ab AV |
887 | sdhci_set_transfer_irqs(host); |
888 | ||
f6a03cbf MV |
889 | /* Set the DMA boundary value and block size */ |
890 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, | |
891 | data->blksz), SDHCI_BLOCK_SIZE); | |
4e4141a5 | 892 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
c7fa9963 PO |
893 | } |
894 | ||
895 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
e89d456f | 896 | struct mmc_command *cmd) |
c7fa9963 PO |
897 | { |
898 | u16 mode; | |
e89d456f | 899 | struct mmc_data *data = cmd->data; |
c7fa9963 | 900 | |
2b558c13 DA |
901 | if (data == NULL) { |
902 | /* clear Auto CMD settings for no data CMDs */ | |
903 | mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); | |
904 | sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | | |
905 | SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); | |
c7fa9963 | 906 | return; |
2b558c13 | 907 | } |
c7fa9963 | 908 | |
e538fbe8 PO |
909 | WARN_ON(!host->data); |
910 | ||
c7fa9963 | 911 | mode = SDHCI_TRNS_BLK_CNT_EN; |
e89d456f AW |
912 | if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { |
913 | mode |= SDHCI_TRNS_MULTI; | |
914 | /* | |
915 | * If we are sending CMD23, CMD12 never gets sent | |
916 | * on successful completion (so no Auto-CMD12). | |
917 | */ | |
918 | if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) | |
919 | mode |= SDHCI_TRNS_AUTO_CMD12; | |
8edf6371 AW |
920 | else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { |
921 | mode |= SDHCI_TRNS_AUTO_CMD23; | |
922 | sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); | |
923 | } | |
c4512f79 | 924 | } |
8edf6371 | 925 | |
c7fa9963 PO |
926 | if (data->flags & MMC_DATA_READ) |
927 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 928 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
929 | mode |= SDHCI_TRNS_DMA; |
930 | ||
4e4141a5 | 931 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
d129bceb PO |
932 | } |
933 | ||
934 | static void sdhci_finish_data(struct sdhci_host *host) | |
935 | { | |
936 | struct mmc_data *data; | |
d129bceb PO |
937 | |
938 | BUG_ON(!host->data); | |
939 | ||
940 | data = host->data; | |
941 | host->data = NULL; | |
942 | ||
c9fddbc4 | 943 | if (host->flags & SDHCI_REQ_USE_DMA) { |
2134a922 PO |
944 | if (host->flags & SDHCI_USE_ADMA) |
945 | sdhci_adma_table_post(host, data); | |
946 | else { | |
947 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
948 | data->sg_len, (data->flags & MMC_DATA_READ) ? | |
949 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
950 | } | |
d129bceb PO |
951 | } |
952 | ||
953 | /* | |
c9b74c5b PO |
954 | * The specification states that the block count register must |
955 | * be updated, but it does not specify at what point in the | |
956 | * data flow. That makes the register entirely useless to read | |
957 | * back so we have to assume that nothing made it to the card | |
958 | * in the event of an error. | |
d129bceb | 959 | */ |
c9b74c5b PO |
960 | if (data->error) |
961 | data->bytes_xfered = 0; | |
d129bceb | 962 | else |
c9b74c5b | 963 | data->bytes_xfered = data->blksz * data->blocks; |
d129bceb | 964 | |
e89d456f AW |
965 | /* |
966 | * Need to send CMD12 if - | |
967 | * a) open-ended multiblock transfer (no CMD23) | |
968 | * b) error in multiblock transfer | |
969 | */ | |
970 | if (data->stop && | |
971 | (data->error || | |
972 | !host->mrq->sbc)) { | |
973 | ||
d129bceb PO |
974 | /* |
975 | * The controller needs a reset of internal state machines | |
976 | * upon error conditions. | |
977 | */ | |
17b0429d | 978 | if (data->error) { |
d129bceb PO |
979 | sdhci_reset(host, SDHCI_RESET_CMD); |
980 | sdhci_reset(host, SDHCI_RESET_DATA); | |
981 | } | |
982 | ||
983 | sdhci_send_command(host, data->stop); | |
984 | } else | |
985 | tasklet_schedule(&host->finish_tasklet); | |
986 | } | |
987 | ||
c0e55129 | 988 | void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb PO |
989 | { |
990 | int flags; | |
fd2208d7 | 991 | u32 mask; |
7cb2c76f | 992 | unsigned long timeout; |
d129bceb PO |
993 | |
994 | WARN_ON(host->cmd); | |
995 | ||
d129bceb | 996 | /* Wait max 10 ms */ |
7cb2c76f | 997 | timeout = 10; |
fd2208d7 PO |
998 | |
999 | mask = SDHCI_CMD_INHIBIT; | |
1000 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
1001 | mask |= SDHCI_DATA_INHIBIT; | |
1002 | ||
1003 | /* We shouldn't wait for data inihibit for stop commands, even | |
1004 | though they might use busy signaling */ | |
1005 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
1006 | mask &= ~SDHCI_DATA_INHIBIT; | |
1007 | ||
4e4141a5 | 1008 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
7cb2c76f | 1009 | if (timeout == 0) { |
a3c76eb9 | 1010 | pr_err("%s: Controller never released " |
acf1da45 | 1011 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb | 1012 | sdhci_dumpregs(host); |
17b0429d | 1013 | cmd->error = -EIO; |
d129bceb PO |
1014 | tasklet_schedule(&host->finish_tasklet); |
1015 | return; | |
1016 | } | |
7cb2c76f PO |
1017 | timeout--; |
1018 | mdelay(1); | |
1019 | } | |
d129bceb PO |
1020 | |
1021 | mod_timer(&host->timer, jiffies + 10 * HZ); | |
1022 | ||
1023 | host->cmd = cmd; | |
1024 | ||
a3c7778f | 1025 | sdhci_prepare_data(host, cmd); |
d129bceb | 1026 | |
4e4141a5 | 1027 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
d129bceb | 1028 | |
e89d456f | 1029 | sdhci_set_transfer_mode(host, cmd); |
c7fa9963 | 1030 | |
d129bceb | 1031 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
a3c76eb9 | 1032 | pr_err("%s: Unsupported response type!\n", |
d129bceb | 1033 | mmc_hostname(host->mmc)); |
17b0429d | 1034 | cmd->error = -EINVAL; |
d129bceb PO |
1035 | tasklet_schedule(&host->finish_tasklet); |
1036 | return; | |
1037 | } | |
1038 | ||
1039 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
1040 | flags = SDHCI_CMD_RESP_NONE; | |
1041 | else if (cmd->flags & MMC_RSP_136) | |
1042 | flags = SDHCI_CMD_RESP_LONG; | |
1043 | else if (cmd->flags & MMC_RSP_BUSY) | |
1044 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
1045 | else | |
1046 | flags = SDHCI_CMD_RESP_SHORT; | |
1047 | ||
1048 | if (cmd->flags & MMC_RSP_CRC) | |
1049 | flags |= SDHCI_CMD_CRC; | |
1050 | if (cmd->flags & MMC_RSP_OPCODE) | |
1051 | flags |= SDHCI_CMD_INDEX; | |
b513ea25 AN |
1052 | |
1053 | /* CMD19 is special in that the Data Present Select should be set */ | |
069c9f14 G |
1054 | if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || |
1055 | cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) | |
d129bceb PO |
1056 | flags |= SDHCI_CMD_DATA; |
1057 | ||
4e4141a5 | 1058 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
d129bceb | 1059 | } |
c0e55129 | 1060 | EXPORT_SYMBOL_GPL(sdhci_send_command); |
d129bceb PO |
1061 | |
1062 | static void sdhci_finish_command(struct sdhci_host *host) | |
1063 | { | |
1064 | int i; | |
1065 | ||
1066 | BUG_ON(host->cmd == NULL); | |
1067 | ||
1068 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
1069 | if (host->cmd->flags & MMC_RSP_136) { | |
1070 | /* CRC is stripped so we need to do some shifting. */ | |
1071 | for (i = 0;i < 4;i++) { | |
4e4141a5 | 1072 | host->cmd->resp[i] = sdhci_readl(host, |
d129bceb PO |
1073 | SDHCI_RESPONSE + (3-i)*4) << 8; |
1074 | if (i != 3) | |
1075 | host->cmd->resp[i] |= | |
4e4141a5 | 1076 | sdhci_readb(host, |
d129bceb PO |
1077 | SDHCI_RESPONSE + (3-i)*4-1); |
1078 | } | |
1079 | } else { | |
4e4141a5 | 1080 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
d129bceb PO |
1081 | } |
1082 | } | |
1083 | ||
17b0429d | 1084 | host->cmd->error = 0; |
d129bceb | 1085 | |
e89d456f AW |
1086 | /* Finished CMD23, now send actual command. */ |
1087 | if (host->cmd == host->mrq->sbc) { | |
1088 | host->cmd = NULL; | |
1089 | sdhci_send_command(host, host->mrq->cmd); | |
1090 | } else { | |
e538fbe8 | 1091 | |
e89d456f AW |
1092 | /* Processed actual command. */ |
1093 | if (host->data && host->data_early) | |
1094 | sdhci_finish_data(host); | |
d129bceb | 1095 | |
e89d456f AW |
1096 | if (!host->cmd->data) |
1097 | tasklet_schedule(&host->finish_tasklet); | |
1098 | ||
1099 | host->cmd = NULL; | |
1100 | } | |
d129bceb PO |
1101 | } |
1102 | ||
52983382 KL |
1103 | static u16 sdhci_get_preset_value(struct sdhci_host *host) |
1104 | { | |
1105 | u16 ctrl, preset = 0; | |
1106 | ||
1107 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1108 | ||
1109 | switch (ctrl & SDHCI_CTRL_UHS_MASK) { | |
1110 | case SDHCI_CTRL_UHS_SDR12: | |
1111 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); | |
1112 | break; | |
1113 | case SDHCI_CTRL_UHS_SDR25: | |
1114 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); | |
1115 | break; | |
1116 | case SDHCI_CTRL_UHS_SDR50: | |
1117 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); | |
1118 | break; | |
1119 | case SDHCI_CTRL_UHS_SDR104: | |
1120 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); | |
1121 | break; | |
1122 | case SDHCI_CTRL_UHS_DDR50: | |
1123 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); | |
1124 | break; | |
1125 | default: | |
1126 | pr_warn("%s: Invalid UHS-I mode selected\n", | |
1127 | mmc_hostname(host->mmc)); | |
1128 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); | |
1129 | break; | |
1130 | } | |
1131 | return preset; | |
1132 | } | |
1133 | ||
d129bceb PO |
1134 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
1135 | { | |
c3ed3877 | 1136 | int div = 0; /* Initialized for compiler warning */ |
df16219f | 1137 | int real_div = div, clk_mul = 1; |
c3ed3877 | 1138 | u16 clk = 0; |
7cb2c76f | 1139 | unsigned long timeout; |
d129bceb | 1140 | |
30832ab5 | 1141 | if (clock && clock == host->clock) |
d129bceb PO |
1142 | return; |
1143 | ||
df16219f GC |
1144 | host->mmc->actual_clock = 0; |
1145 | ||
8114634c AV |
1146 | if (host->ops->set_clock) { |
1147 | host->ops->set_clock(host, clock); | |
1148 | if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) | |
1149 | return; | |
1150 | } | |
1151 | ||
4e4141a5 | 1152 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1153 | |
1154 | if (clock == 0) | |
1155 | goto out; | |
1156 | ||
85105c53 | 1157 | if (host->version >= SDHCI_SPEC_300) { |
52983382 KL |
1158 | if (sdhci_readw(host, SDHCI_HOST_CONTROL2) & |
1159 | SDHCI_CTRL_PRESET_VAL_ENABLE) { | |
1160 | u16 pre_val; | |
1161 | ||
1162 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1163 | pre_val = sdhci_get_preset_value(host); | |
1164 | div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) | |
1165 | >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; | |
1166 | if (host->clk_mul && | |
1167 | (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { | |
1168 | clk = SDHCI_PROG_CLOCK_MODE; | |
1169 | real_div = div + 1; | |
1170 | clk_mul = host->clk_mul; | |
1171 | } else { | |
1172 | real_div = max_t(int, 1, div << 1); | |
1173 | } | |
1174 | goto clock_set; | |
1175 | } | |
1176 | ||
c3ed3877 AN |
1177 | /* |
1178 | * Check if the Host Controller supports Programmable Clock | |
1179 | * Mode. | |
1180 | */ | |
1181 | if (host->clk_mul) { | |
52983382 KL |
1182 | for (div = 1; div <= 1024; div++) { |
1183 | if ((host->max_clk * host->clk_mul / div) | |
1184 | <= clock) | |
1185 | break; | |
1186 | } | |
c3ed3877 | 1187 | /* |
52983382 KL |
1188 | * Set Programmable Clock Mode in the Clock |
1189 | * Control register. | |
c3ed3877 | 1190 | */ |
52983382 KL |
1191 | clk = SDHCI_PROG_CLOCK_MODE; |
1192 | real_div = div; | |
1193 | clk_mul = host->clk_mul; | |
1194 | div--; | |
c3ed3877 AN |
1195 | } else { |
1196 | /* Version 3.00 divisors must be a multiple of 2. */ | |
1197 | if (host->max_clk <= clock) | |
1198 | div = 1; | |
1199 | else { | |
1200 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; | |
1201 | div += 2) { | |
1202 | if ((host->max_clk / div) <= clock) | |
1203 | break; | |
1204 | } | |
85105c53 | 1205 | } |
df16219f | 1206 | real_div = div; |
c3ed3877 | 1207 | div >>= 1; |
85105c53 ZG |
1208 | } |
1209 | } else { | |
1210 | /* Version 2.00 divisors must be a power of 2. */ | |
0397526d | 1211 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
85105c53 ZG |
1212 | if ((host->max_clk / div) <= clock) |
1213 | break; | |
1214 | } | |
df16219f | 1215 | real_div = div; |
c3ed3877 | 1216 | div >>= 1; |
d129bceb | 1217 | } |
d129bceb | 1218 | |
52983382 | 1219 | clock_set: |
df16219f GC |
1220 | if (real_div) |
1221 | host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; | |
1222 | ||
c3ed3877 | 1223 | clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
85105c53 ZG |
1224 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
1225 | << SDHCI_DIVIDER_HI_SHIFT; | |
d129bceb | 1226 | clk |= SDHCI_CLOCK_INT_EN; |
4e4141a5 | 1227 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1228 | |
27f6cb16 CB |
1229 | /* Wait max 20 ms */ |
1230 | timeout = 20; | |
4e4141a5 | 1231 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
7cb2c76f PO |
1232 | & SDHCI_CLOCK_INT_STABLE)) { |
1233 | if (timeout == 0) { | |
a3c76eb9 | 1234 | pr_err("%s: Internal clock never " |
acf1da45 | 1235 | "stabilised.\n", mmc_hostname(host->mmc)); |
d129bceb PO |
1236 | sdhci_dumpregs(host); |
1237 | return; | |
1238 | } | |
7cb2c76f PO |
1239 | timeout--; |
1240 | mdelay(1); | |
1241 | } | |
d129bceb PO |
1242 | |
1243 | clk |= SDHCI_CLOCK_CARD_EN; | |
4e4141a5 | 1244 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1245 | |
1246 | out: | |
1247 | host->clock = clock; | |
1248 | } | |
1249 | ||
8213af3b AS |
1250 | static inline void sdhci_update_clock(struct sdhci_host *host) |
1251 | { | |
1252 | unsigned int clock; | |
1253 | ||
1254 | clock = host->clock; | |
1255 | host->clock = 0; | |
1256 | sdhci_set_clock(host, clock); | |
1257 | } | |
1258 | ||
ceb6143b | 1259 | static int sdhci_set_power(struct sdhci_host *host, unsigned short power) |
146ad66e | 1260 | { |
8364248a | 1261 | u8 pwr = 0; |
146ad66e | 1262 | |
8364248a | 1263 | if (power != (unsigned short)-1) { |
ae628903 PO |
1264 | switch (1 << power) { |
1265 | case MMC_VDD_165_195: | |
1266 | pwr = SDHCI_POWER_180; | |
1267 | break; | |
1268 | case MMC_VDD_29_30: | |
1269 | case MMC_VDD_30_31: | |
1270 | pwr = SDHCI_POWER_300; | |
1271 | break; | |
1272 | case MMC_VDD_32_33: | |
1273 | case MMC_VDD_33_34: | |
1274 | pwr = SDHCI_POWER_330; | |
1275 | break; | |
1276 | default: | |
1277 | BUG(); | |
1278 | } | |
1279 | } | |
1280 | ||
1281 | if (host->pwr == pwr) | |
ceb6143b | 1282 | return -1; |
146ad66e | 1283 | |
ae628903 PO |
1284 | host->pwr = pwr; |
1285 | ||
1286 | if (pwr == 0) { | |
4e4141a5 | 1287 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
f0710a55 AH |
1288 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1289 | sdhci_runtime_pm_bus_off(host); | |
ceb6143b | 1290 | return 0; |
9e9dc5f2 DS |
1291 | } |
1292 | ||
1293 | /* | |
1294 | * Spec says that we should clear the power reg before setting | |
1295 | * a new value. Some controllers don't seem to like this though. | |
1296 | */ | |
b8c86fc5 | 1297 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
4e4141a5 | 1298 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
146ad66e | 1299 | |
e08c1694 | 1300 | /* |
c71f6512 | 1301 | * At least the Marvell CaFe chip gets confused if we set the voltage |
e08c1694 AS |
1302 | * and set turn on power at the same time, so set the voltage first. |
1303 | */ | |
11a2f1b7 | 1304 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) |
ae628903 | 1305 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
e08c1694 | 1306 | |
ae628903 | 1307 | pwr |= SDHCI_POWER_ON; |
146ad66e | 1308 | |
ae628903 | 1309 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
557b0697 | 1310 | |
f0710a55 AH |
1311 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1312 | sdhci_runtime_pm_bus_on(host); | |
1313 | ||
557b0697 HW |
1314 | /* |
1315 | * Some controllers need an extra 10ms delay of 10ms before they | |
1316 | * can apply clock after applying power | |
1317 | */ | |
11a2f1b7 | 1318 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) |
557b0697 | 1319 | mdelay(10); |
ceb6143b AH |
1320 | |
1321 | return power; | |
146ad66e PO |
1322 | } |
1323 | ||
d129bceb PO |
1324 | /*****************************************************************************\ |
1325 | * * | |
1326 | * MMC callbacks * | |
1327 | * * | |
1328 | \*****************************************************************************/ | |
1329 | ||
1330 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1331 | { | |
1332 | struct sdhci_host *host; | |
505a8680 | 1333 | int present; |
d129bceb | 1334 | unsigned long flags; |
473b095a | 1335 | u32 tuning_opcode; |
d129bceb PO |
1336 | |
1337 | host = mmc_priv(mmc); | |
1338 | ||
66fd8ad5 AH |
1339 | sdhci_runtime_pm_get(host); |
1340 | ||
d129bceb PO |
1341 | spin_lock_irqsave(&host->lock, flags); |
1342 | ||
1343 | WARN_ON(host->mrq != NULL); | |
1344 | ||
f9134319 | 1345 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1346 | sdhci_activate_led(host); |
2f730fec | 1347 | #endif |
e89d456f AW |
1348 | |
1349 | /* | |
1350 | * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED | |
1351 | * requests if Auto-CMD12 is enabled. | |
1352 | */ | |
1353 | if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { | |
c4512f79 JH |
1354 | if (mrq->stop) { |
1355 | mrq->data->stop = NULL; | |
1356 | mrq->stop = NULL; | |
1357 | } | |
1358 | } | |
d129bceb PO |
1359 | |
1360 | host->mrq = mrq; | |
1361 | ||
505a8680 SG |
1362 | /* |
1363 | * Firstly check card presence from cd-gpio. The return could | |
1364 | * be one of the following possibilities: | |
1365 | * negative: cd-gpio is not available | |
1366 | * zero: cd-gpio is used, and card is removed | |
1367 | * one: cd-gpio is used, and card is present | |
1368 | */ | |
1369 | present = mmc_gpio_get_cd(host->mmc); | |
1370 | if (present < 0) { | |
1371 | /* If polling, assume that the card is always present. */ | |
1372 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
1373 | present = 1; | |
1374 | else | |
1375 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
1376 | SDHCI_CARD_PRESENT; | |
bec9d4e5 GL |
1377 | } |
1378 | ||
68d1fb7e | 1379 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { |
17b0429d | 1380 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb | 1381 | tasklet_schedule(&host->finish_tasklet); |
cf2b5eea AN |
1382 | } else { |
1383 | u32 present_state; | |
1384 | ||
1385 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
1386 | /* | |
1387 | * Check if the re-tuning timer has already expired and there | |
1388 | * is no on-going data transfer. If so, we need to execute | |
1389 | * tuning procedure before sending command. | |
1390 | */ | |
1391 | if ((host->flags & SDHCI_NEEDS_RETUNING) && | |
1392 | !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { | |
14efd957 CB |
1393 | if (mmc->card) { |
1394 | /* eMMC uses cmd21 but sd and sdio use cmd19 */ | |
1395 | tuning_opcode = | |
1396 | mmc->card->type == MMC_TYPE_MMC ? | |
1397 | MMC_SEND_TUNING_BLOCK_HS200 : | |
1398 | MMC_SEND_TUNING_BLOCK; | |
63c21180 CL |
1399 | |
1400 | /* Here we need to set the host->mrq to NULL, | |
1401 | * in case the pending finish_tasklet | |
1402 | * finishes it incorrectly. | |
1403 | */ | |
1404 | host->mrq = NULL; | |
1405 | ||
14efd957 CB |
1406 | spin_unlock_irqrestore(&host->lock, flags); |
1407 | sdhci_execute_tuning(mmc, tuning_opcode); | |
1408 | spin_lock_irqsave(&host->lock, flags); | |
1409 | ||
1410 | /* Restore original mmc_request structure */ | |
1411 | host->mrq = mrq; | |
1412 | } | |
cf2b5eea AN |
1413 | } |
1414 | ||
8edf6371 | 1415 | if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) |
e89d456f AW |
1416 | sdhci_send_command(host, mrq->sbc); |
1417 | else | |
1418 | sdhci_send_command(host, mrq->cmd); | |
cf2b5eea | 1419 | } |
d129bceb | 1420 | |
5f25a66f | 1421 | mmiowb(); |
d129bceb PO |
1422 | spin_unlock_irqrestore(&host->lock, flags); |
1423 | } | |
1424 | ||
66fd8ad5 | 1425 | static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) |
d129bceb | 1426 | { |
d129bceb | 1427 | unsigned long flags; |
ceb6143b | 1428 | int vdd_bit = -1; |
d129bceb PO |
1429 | u8 ctrl; |
1430 | ||
d129bceb PO |
1431 | spin_lock_irqsave(&host->lock, flags); |
1432 | ||
ceb6143b AH |
1433 | if (host->flags & SDHCI_DEVICE_DEAD) { |
1434 | spin_unlock_irqrestore(&host->lock, flags); | |
1435 | if (host->vmmc && ios->power_mode == MMC_POWER_OFF) | |
1436 | mmc_regulator_set_ocr(host->mmc, host->vmmc, 0); | |
1437 | return; | |
1438 | } | |
1e72859e | 1439 | |
d129bceb PO |
1440 | /* |
1441 | * Reset the chip on each power off. | |
1442 | * Should clear out any weird states. | |
1443 | */ | |
1444 | if (ios->power_mode == MMC_POWER_OFF) { | |
4e4141a5 | 1445 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
7260cf5e | 1446 | sdhci_reinit(host); |
d129bceb PO |
1447 | } |
1448 | ||
52983382 | 1449 | if (host->version >= SDHCI_SPEC_300 && |
372c4634 DA |
1450 | (ios->power_mode == MMC_POWER_UP) && |
1451 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) | |
52983382 KL |
1452 | sdhci_enable_preset_value(host, false); |
1453 | ||
d129bceb PO |
1454 | sdhci_set_clock(host, ios->clock); |
1455 | ||
1456 | if (ios->power_mode == MMC_POWER_OFF) | |
ceb6143b | 1457 | vdd_bit = sdhci_set_power(host, -1); |
d129bceb | 1458 | else |
ceb6143b AH |
1459 | vdd_bit = sdhci_set_power(host, ios->vdd); |
1460 | ||
1461 | if (host->vmmc && vdd_bit != -1) { | |
1462 | spin_unlock_irqrestore(&host->lock, flags); | |
1463 | mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit); | |
1464 | spin_lock_irqsave(&host->lock, flags); | |
1465 | } | |
d129bceb | 1466 | |
643a81ff PR |
1467 | if (host->ops->platform_send_init_74_clocks) |
1468 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); | |
1469 | ||
15ec4461 PR |
1470 | /* |
1471 | * If your platform has 8-bit width support but is not a v3 controller, | |
1472 | * or if it requires special setup code, you should implement that in | |
7bc088d3 | 1473 | * platform_bus_width(). |
15ec4461 | 1474 | */ |
7bc088d3 SH |
1475 | if (host->ops->platform_bus_width) { |
1476 | host->ops->platform_bus_width(host, ios->bus_width); | |
1477 | } else { | |
15ec4461 PR |
1478 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
1479 | if (ios->bus_width == MMC_BUS_WIDTH_8) { | |
1480 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1481 | if (host->version >= SDHCI_SPEC_300) | |
1482 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1483 | } else { | |
1484 | if (host->version >= SDHCI_SPEC_300) | |
1485 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1486 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
1487 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1488 | else | |
1489 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1490 | } | |
1491 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1492 | } | |
ae6d6c92 | 1493 | |
15ec4461 | 1494 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
cd9277c0 | 1495 | |
3ab9c8da PR |
1496 | if ((ios->timing == MMC_TIMING_SD_HS || |
1497 | ios->timing == MMC_TIMING_MMC_HS) | |
1498 | && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) | |
cd9277c0 PO |
1499 | ctrl |= SDHCI_CTRL_HISPD; |
1500 | else | |
1501 | ctrl &= ~SDHCI_CTRL_HISPD; | |
1502 | ||
d6d50a15 | 1503 | if (host->version >= SDHCI_SPEC_300) { |
49c468fc | 1504 | u16 clk, ctrl_2; |
49c468fc AN |
1505 | |
1506 | /* In case of UHS-I modes, set High Speed Enable */ | |
069c9f14 G |
1507 | if ((ios->timing == MMC_TIMING_MMC_HS200) || |
1508 | (ios->timing == MMC_TIMING_UHS_SDR50) || | |
49c468fc AN |
1509 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
1510 | (ios->timing == MMC_TIMING_UHS_DDR50) || | |
dd8df17f | 1511 | (ios->timing == MMC_TIMING_UHS_SDR25)) |
49c468fc | 1512 | ctrl |= SDHCI_CTRL_HISPD; |
d6d50a15 AN |
1513 | |
1514 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1515 | if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { | |
758535c4 | 1516 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d6d50a15 AN |
1517 | /* |
1518 | * We only need to set Driver Strength if the | |
1519 | * preset value enable is not set. | |
1520 | */ | |
1521 | ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; | |
1522 | if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) | |
1523 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; | |
1524 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) | |
1525 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; | |
1526 | ||
1527 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
758535c4 AN |
1528 | } else { |
1529 | /* | |
1530 | * According to SDHC Spec v3.00, if the Preset Value | |
1531 | * Enable in the Host Control 2 register is set, we | |
1532 | * need to reset SD Clock Enable before changing High | |
1533 | * Speed Enable to avoid generating clock gliches. | |
1534 | */ | |
758535c4 AN |
1535 | |
1536 | /* Reset SD Clock Enable */ | |
1537 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1538 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
1539 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1540 | ||
1541 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1542 | ||
1543 | /* Re-enable SD Clock */ | |
8213af3b | 1544 | sdhci_update_clock(host); |
d6d50a15 | 1545 | } |
49c468fc | 1546 | |
49c468fc AN |
1547 | |
1548 | /* Reset SD Clock Enable */ | |
1549 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1550 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
1551 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1552 | ||
6322cdd0 PR |
1553 | if (host->ops->set_uhs_signaling) |
1554 | host->ops->set_uhs_signaling(host, ios->timing); | |
1555 | else { | |
1556 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1557 | /* Select Bus Speed Mode for host */ | |
1558 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
59911568 GC |
1559 | if ((ios->timing == MMC_TIMING_MMC_HS200) || |
1560 | (ios->timing == MMC_TIMING_UHS_SDR104)) | |
1561 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | |
069c9f14 | 1562 | else if (ios->timing == MMC_TIMING_UHS_SDR12) |
6322cdd0 PR |
1563 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; |
1564 | else if (ios->timing == MMC_TIMING_UHS_SDR25) | |
1565 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
1566 | else if (ios->timing == MMC_TIMING_UHS_SDR50) | |
1567 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | |
6322cdd0 PR |
1568 | else if (ios->timing == MMC_TIMING_UHS_DDR50) |
1569 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; | |
1570 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
1571 | } | |
49c468fc | 1572 | |
52983382 KL |
1573 | if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && |
1574 | ((ios->timing == MMC_TIMING_UHS_SDR12) || | |
1575 | (ios->timing == MMC_TIMING_UHS_SDR25) || | |
1576 | (ios->timing == MMC_TIMING_UHS_SDR50) || | |
1577 | (ios->timing == MMC_TIMING_UHS_SDR104) || | |
1578 | (ios->timing == MMC_TIMING_UHS_DDR50))) { | |
1579 | u16 preset; | |
1580 | ||
1581 | sdhci_enable_preset_value(host, true); | |
1582 | preset = sdhci_get_preset_value(host); | |
1583 | ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) | |
1584 | >> SDHCI_PRESET_DRV_SHIFT; | |
1585 | } | |
1586 | ||
49c468fc | 1587 | /* Re-enable SD Clock */ |
8213af3b | 1588 | sdhci_update_clock(host); |
758535c4 AN |
1589 | } else |
1590 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
d6d50a15 | 1591 | |
b8352260 LD |
1592 | /* |
1593 | * Some (ENE) controllers go apeshit on some ios operation, | |
1594 | * signalling timeout and CRC errors even on CMD0. Resetting | |
1595 | * it on each ios seems to solve the problem. | |
1596 | */ | |
b8c86fc5 | 1597 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
b8352260 LD |
1598 | sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
1599 | ||
5f25a66f | 1600 | mmiowb(); |
d129bceb PO |
1601 | spin_unlock_irqrestore(&host->lock, flags); |
1602 | } | |
1603 | ||
66fd8ad5 AH |
1604 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
1605 | { | |
1606 | struct sdhci_host *host = mmc_priv(mmc); | |
1607 | ||
1608 | sdhci_runtime_pm_get(host); | |
1609 | sdhci_do_set_ios(host, ios); | |
1610 | sdhci_runtime_pm_put(host); | |
1611 | } | |
1612 | ||
94144a46 KL |
1613 | static int sdhci_do_get_cd(struct sdhci_host *host) |
1614 | { | |
1615 | int gpio_cd = mmc_gpio_get_cd(host->mmc); | |
1616 | ||
1617 | if (host->flags & SDHCI_DEVICE_DEAD) | |
1618 | return 0; | |
1619 | ||
1620 | /* If polling/nonremovable, assume that the card is always present. */ | |
1621 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || | |
1622 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) | |
1623 | return 1; | |
1624 | ||
1625 | /* Try slot gpio detect */ | |
1626 | if (!IS_ERR_VALUE(gpio_cd)) | |
1627 | return !!gpio_cd; | |
1628 | ||
1629 | /* Host native card detect */ | |
1630 | return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); | |
1631 | } | |
1632 | ||
1633 | static int sdhci_get_cd(struct mmc_host *mmc) | |
1634 | { | |
1635 | struct sdhci_host *host = mmc_priv(mmc); | |
1636 | int ret; | |
1637 | ||
1638 | sdhci_runtime_pm_get(host); | |
1639 | ret = sdhci_do_get_cd(host); | |
1640 | sdhci_runtime_pm_put(host); | |
1641 | return ret; | |
1642 | } | |
1643 | ||
66fd8ad5 | 1644 | static int sdhci_check_ro(struct sdhci_host *host) |
d129bceb | 1645 | { |
d129bceb | 1646 | unsigned long flags; |
2dfb579c | 1647 | int is_readonly; |
d129bceb | 1648 | |
d129bceb PO |
1649 | spin_lock_irqsave(&host->lock, flags); |
1650 | ||
1e72859e | 1651 | if (host->flags & SDHCI_DEVICE_DEAD) |
2dfb579c WS |
1652 | is_readonly = 0; |
1653 | else if (host->ops->get_ro) | |
1654 | is_readonly = host->ops->get_ro(host); | |
1e72859e | 1655 | else |
2dfb579c WS |
1656 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
1657 | & SDHCI_WRITE_PROTECT); | |
d129bceb PO |
1658 | |
1659 | spin_unlock_irqrestore(&host->lock, flags); | |
1660 | ||
2dfb579c WS |
1661 | /* This quirk needs to be replaced by a callback-function later */ |
1662 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? | |
1663 | !is_readonly : is_readonly; | |
d129bceb PO |
1664 | } |
1665 | ||
82b0e23a TI |
1666 | #define SAMPLE_COUNT 5 |
1667 | ||
66fd8ad5 | 1668 | static int sdhci_do_get_ro(struct sdhci_host *host) |
82b0e23a | 1669 | { |
82b0e23a TI |
1670 | int i, ro_count; |
1671 | ||
82b0e23a | 1672 | if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) |
66fd8ad5 | 1673 | return sdhci_check_ro(host); |
82b0e23a TI |
1674 | |
1675 | ro_count = 0; | |
1676 | for (i = 0; i < SAMPLE_COUNT; i++) { | |
66fd8ad5 | 1677 | if (sdhci_check_ro(host)) { |
82b0e23a TI |
1678 | if (++ro_count > SAMPLE_COUNT / 2) |
1679 | return 1; | |
1680 | } | |
1681 | msleep(30); | |
1682 | } | |
1683 | return 0; | |
1684 | } | |
1685 | ||
20758b66 AH |
1686 | static void sdhci_hw_reset(struct mmc_host *mmc) |
1687 | { | |
1688 | struct sdhci_host *host = mmc_priv(mmc); | |
1689 | ||
1690 | if (host->ops && host->ops->hw_reset) | |
1691 | host->ops->hw_reset(host); | |
1692 | } | |
1693 | ||
66fd8ad5 | 1694 | static int sdhci_get_ro(struct mmc_host *mmc) |
f75979b7 | 1695 | { |
66fd8ad5 AH |
1696 | struct sdhci_host *host = mmc_priv(mmc); |
1697 | int ret; | |
f75979b7 | 1698 | |
66fd8ad5 AH |
1699 | sdhci_runtime_pm_get(host); |
1700 | ret = sdhci_do_get_ro(host); | |
1701 | sdhci_runtime_pm_put(host); | |
1702 | return ret; | |
1703 | } | |
f75979b7 | 1704 | |
66fd8ad5 AH |
1705 | static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) |
1706 | { | |
1e72859e PO |
1707 | if (host->flags & SDHCI_DEVICE_DEAD) |
1708 | goto out; | |
1709 | ||
66fd8ad5 AH |
1710 | if (enable) |
1711 | host->flags |= SDHCI_SDIO_IRQ_ENABLED; | |
1712 | else | |
1713 | host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; | |
1714 | ||
1715 | /* SDIO IRQ will be enabled as appropriate in runtime resume */ | |
1716 | if (host->runtime_suspended) | |
1717 | goto out; | |
1718 | ||
f75979b7 | 1719 | if (enable) |
7260cf5e AV |
1720 | sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); |
1721 | else | |
1722 | sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); | |
1e72859e | 1723 | out: |
f75979b7 | 1724 | mmiowb(); |
66fd8ad5 AH |
1725 | } |
1726 | ||
1727 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) | |
1728 | { | |
1729 | struct sdhci_host *host = mmc_priv(mmc); | |
1730 | unsigned long flags; | |
f75979b7 | 1731 | |
66fd8ad5 AH |
1732 | spin_lock_irqsave(&host->lock, flags); |
1733 | sdhci_enable_sdio_irq_nolock(host, enable); | |
f75979b7 PO |
1734 | spin_unlock_irqrestore(&host->lock, flags); |
1735 | } | |
1736 | ||
20b92a30 | 1737 | static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, |
21f5998f | 1738 | struct mmc_ios *ios) |
f2119df6 | 1739 | { |
20b92a30 | 1740 | u16 ctrl; |
6231f3de | 1741 | int ret; |
f2119df6 | 1742 | |
20b92a30 KL |
1743 | /* |
1744 | * Signal Voltage Switching is only applicable for Host Controllers | |
1745 | * v3.00 and above. | |
1746 | */ | |
1747 | if (host->version < SDHCI_SPEC_300) | |
1748 | return 0; | |
6231f3de | 1749 | |
f2119df6 | 1750 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
f2119df6 | 1751 | |
21f5998f | 1752 | switch (ios->signal_voltage) { |
20b92a30 KL |
1753 | case MMC_SIGNAL_VOLTAGE_330: |
1754 | /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ | |
1755 | ctrl &= ~SDHCI_CTRL_VDD_180; | |
1756 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
f2119df6 | 1757 | |
20b92a30 KL |
1758 | if (host->vqmmc) { |
1759 | ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000); | |
1760 | if (ret) { | |
1761 | pr_warning("%s: Switching to 3.3V signalling voltage " | |
1762 | " failed\n", mmc_hostname(host->mmc)); | |
1763 | return -EIO; | |
1764 | } | |
1765 | } | |
1766 | /* Wait for 5ms */ | |
1767 | usleep_range(5000, 5500); | |
f2119df6 | 1768 | |
20b92a30 KL |
1769 | /* 3.3V regulator output should be stable within 5 ms */ |
1770 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1771 | if (!(ctrl & SDHCI_CTRL_VDD_180)) | |
1772 | return 0; | |
6231f3de | 1773 | |
20b92a30 KL |
1774 | pr_warning("%s: 3.3V regulator output did not became stable\n", |
1775 | mmc_hostname(host->mmc)); | |
1776 | ||
1777 | return -EAGAIN; | |
1778 | case MMC_SIGNAL_VOLTAGE_180: | |
1779 | if (host->vqmmc) { | |
1780 | ret = regulator_set_voltage(host->vqmmc, | |
1781 | 1700000, 1950000); | |
1782 | if (ret) { | |
1783 | pr_warning("%s: Switching to 1.8V signalling voltage " | |
1784 | " failed\n", mmc_hostname(host->mmc)); | |
1785 | return -EIO; | |
1786 | } | |
1787 | } | |
6231f3de | 1788 | |
6231f3de PR |
1789 | /* |
1790 | * Enable 1.8V Signal Enable in the Host Control2 | |
1791 | * register | |
1792 | */ | |
20b92a30 KL |
1793 | ctrl |= SDHCI_CTRL_VDD_180; |
1794 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
6231f3de | 1795 | |
20b92a30 KL |
1796 | /* Wait for 5ms */ |
1797 | usleep_range(5000, 5500); | |
f2119df6 | 1798 | |
20b92a30 KL |
1799 | /* 1.8V regulator output should be stable within 5 ms */ |
1800 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1801 | if (ctrl & SDHCI_CTRL_VDD_180) | |
1802 | return 0; | |
f2119df6 | 1803 | |
20b92a30 KL |
1804 | pr_warning("%s: 1.8V regulator output did not became stable\n", |
1805 | mmc_hostname(host->mmc)); | |
f2119df6 | 1806 | |
20b92a30 KL |
1807 | return -EAGAIN; |
1808 | case MMC_SIGNAL_VOLTAGE_120: | |
1809 | if (host->vqmmc) { | |
1810 | ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000); | |
1811 | if (ret) { | |
1812 | pr_warning("%s: Switching to 1.2V signalling voltage " | |
1813 | " failed\n", mmc_hostname(host->mmc)); | |
1814 | return -EIO; | |
f2119df6 AN |
1815 | } |
1816 | } | |
6231f3de | 1817 | return 0; |
20b92a30 | 1818 | default: |
f2119df6 AN |
1819 | /* No signal voltage switch required */ |
1820 | return 0; | |
20b92a30 | 1821 | } |
f2119df6 AN |
1822 | } |
1823 | ||
66fd8ad5 | 1824 | static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
21f5998f | 1825 | struct mmc_ios *ios) |
66fd8ad5 AH |
1826 | { |
1827 | struct sdhci_host *host = mmc_priv(mmc); | |
1828 | int err; | |
1829 | ||
1830 | if (host->version < SDHCI_SPEC_300) | |
1831 | return 0; | |
1832 | sdhci_runtime_pm_get(host); | |
21f5998f | 1833 | err = sdhci_do_start_signal_voltage_switch(host, ios); |
66fd8ad5 AH |
1834 | sdhci_runtime_pm_put(host); |
1835 | return err; | |
1836 | } | |
1837 | ||
20b92a30 KL |
1838 | static int sdhci_card_busy(struct mmc_host *mmc) |
1839 | { | |
1840 | struct sdhci_host *host = mmc_priv(mmc); | |
1841 | u32 present_state; | |
1842 | ||
1843 | sdhci_runtime_pm_get(host); | |
1844 | /* Check whether DAT[3:0] is 0000 */ | |
1845 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
1846 | sdhci_runtime_pm_put(host); | |
1847 | ||
1848 | return !(present_state & SDHCI_DATA_LVL_MASK); | |
1849 | } | |
1850 | ||
069c9f14 | 1851 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) |
b513ea25 AN |
1852 | { |
1853 | struct sdhci_host *host; | |
1854 | u16 ctrl; | |
1855 | u32 ier; | |
1856 | int tuning_loop_counter = MAX_TUNING_LOOP; | |
1857 | unsigned long timeout; | |
1858 | int err = 0; | |
069c9f14 | 1859 | bool requires_tuning_nonuhs = false; |
b513ea25 AN |
1860 | |
1861 | host = mmc_priv(mmc); | |
1862 | ||
66fd8ad5 | 1863 | sdhci_runtime_pm_get(host); |
b513ea25 AN |
1864 | disable_irq(host->irq); |
1865 | spin_lock(&host->lock); | |
1866 | ||
1867 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1868 | ||
1869 | /* | |
069c9f14 G |
1870 | * The Host Controller needs tuning only in case of SDR104 mode |
1871 | * and for SDR50 mode when Use Tuning for SDR50 is set in the | |
b513ea25 | 1872 | * Capabilities register. |
069c9f14 G |
1873 | * If the Host Controller supports the HS200 mode then the |
1874 | * tuning function has to be executed. | |
b513ea25 | 1875 | */ |
069c9f14 G |
1876 | if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) && |
1877 | (host->flags & SDHCI_SDR50_NEEDS_TUNING || | |
156e14b1 | 1878 | host->flags & SDHCI_SDR104_NEEDS_TUNING)) |
069c9f14 G |
1879 | requires_tuning_nonuhs = true; |
1880 | ||
b513ea25 | 1881 | if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) || |
069c9f14 | 1882 | requires_tuning_nonuhs) |
b513ea25 AN |
1883 | ctrl |= SDHCI_CTRL_EXEC_TUNING; |
1884 | else { | |
1885 | spin_unlock(&host->lock); | |
1886 | enable_irq(host->irq); | |
66fd8ad5 | 1887 | sdhci_runtime_pm_put(host); |
b513ea25 AN |
1888 | return 0; |
1889 | } | |
1890 | ||
45251812 DA |
1891 | if (host->ops->platform_execute_tuning) { |
1892 | spin_unlock(&host->lock); | |
1893 | enable_irq(host->irq); | |
1894 | err = host->ops->platform_execute_tuning(host, opcode); | |
1895 | sdhci_runtime_pm_put(host); | |
1896 | return err; | |
1897 | } | |
1898 | ||
b513ea25 AN |
1899 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
1900 | ||
1901 | /* | |
1902 | * As per the Host Controller spec v3.00, tuning command | |
1903 | * generates Buffer Read Ready interrupt, so enable that. | |
1904 | * | |
1905 | * Note: The spec clearly says that when tuning sequence | |
1906 | * is being performed, the controller does not generate | |
1907 | * interrupts other than Buffer Read Ready interrupt. But | |
1908 | * to make sure we don't hit a controller bug, we _only_ | |
1909 | * enable Buffer Read Ready interrupt here. | |
1910 | */ | |
1911 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
1912 | sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL); | |
1913 | ||
1914 | /* | |
1915 | * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number | |
1916 | * of loops reaches 40 times or a timeout of 150ms occurs. | |
1917 | */ | |
1918 | timeout = 150; | |
1919 | do { | |
1920 | struct mmc_command cmd = {0}; | |
66fd8ad5 | 1921 | struct mmc_request mrq = {NULL}; |
b513ea25 AN |
1922 | |
1923 | if (!tuning_loop_counter && !timeout) | |
1924 | break; | |
1925 | ||
069c9f14 | 1926 | cmd.opcode = opcode; |
b513ea25 AN |
1927 | cmd.arg = 0; |
1928 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; | |
1929 | cmd.retries = 0; | |
1930 | cmd.data = NULL; | |
1931 | cmd.error = 0; | |
1932 | ||
1933 | mrq.cmd = &cmd; | |
1934 | host->mrq = &mrq; | |
1935 | ||
1936 | /* | |
1937 | * In response to CMD19, the card sends 64 bytes of tuning | |
1938 | * block to the Host Controller. So we set the block size | |
1939 | * to 64 here. | |
1940 | */ | |
069c9f14 G |
1941 | if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { |
1942 | if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
1943 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), | |
1944 | SDHCI_BLOCK_SIZE); | |
1945 | else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) | |
1946 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), | |
1947 | SDHCI_BLOCK_SIZE); | |
1948 | } else { | |
1949 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), | |
1950 | SDHCI_BLOCK_SIZE); | |
1951 | } | |
b513ea25 AN |
1952 | |
1953 | /* | |
1954 | * The tuning block is sent by the card to the host controller. | |
1955 | * So we set the TRNS_READ bit in the Transfer Mode register. | |
1956 | * This also takes care of setting DMA Enable and Multi Block | |
1957 | * Select in the same register to 0. | |
1958 | */ | |
1959 | sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); | |
1960 | ||
1961 | sdhci_send_command(host, &cmd); | |
1962 | ||
1963 | host->cmd = NULL; | |
1964 | host->mrq = NULL; | |
1965 | ||
1966 | spin_unlock(&host->lock); | |
1967 | enable_irq(host->irq); | |
1968 | ||
1969 | /* Wait for Buffer Read Ready interrupt */ | |
1970 | wait_event_interruptible_timeout(host->buf_ready_int, | |
1971 | (host->tuning_done == 1), | |
1972 | msecs_to_jiffies(50)); | |
1973 | disable_irq(host->irq); | |
1974 | spin_lock(&host->lock); | |
1975 | ||
1976 | if (!host->tuning_done) { | |
a3c76eb9 | 1977 | pr_info(DRIVER_NAME ": Timeout waiting for " |
b513ea25 AN |
1978 | "Buffer Read Ready interrupt during tuning " |
1979 | "procedure, falling back to fixed sampling " | |
1980 | "clock\n"); | |
1981 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1982 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; | |
1983 | ctrl &= ~SDHCI_CTRL_EXEC_TUNING; | |
1984 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
1985 | ||
1986 | err = -EIO; | |
1987 | goto out; | |
1988 | } | |
1989 | ||
1990 | host->tuning_done = 0; | |
1991 | ||
1992 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1993 | tuning_loop_counter--; | |
1994 | timeout--; | |
1995 | mdelay(1); | |
1996 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); | |
1997 | ||
1998 | /* | |
1999 | * The Host Driver has exhausted the maximum number of loops allowed, | |
2000 | * so use fixed sampling frequency. | |
2001 | */ | |
2002 | if (!tuning_loop_counter || !timeout) { | |
2003 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; | |
2004 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
114f2bf6 | 2005 | err = -EIO; |
b513ea25 AN |
2006 | } else { |
2007 | if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { | |
a3c76eb9 | 2008 | pr_info(DRIVER_NAME ": Tuning procedure" |
b513ea25 AN |
2009 | " failed, falling back to fixed sampling" |
2010 | " clock\n"); | |
2011 | err = -EIO; | |
2012 | } | |
2013 | } | |
2014 | ||
2015 | out: | |
cf2b5eea AN |
2016 | /* |
2017 | * If this is the very first time we are here, we start the retuning | |
2018 | * timer. Since only during the first time, SDHCI_NEEDS_RETUNING | |
2019 | * flag won't be set, we check this condition before actually starting | |
2020 | * the timer. | |
2021 | */ | |
2022 | if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && | |
2023 | (host->tuning_mode == SDHCI_TUNING_MODE_1)) { | |
973905fe | 2024 | host->flags |= SDHCI_USING_RETUNING_TIMER; |
cf2b5eea AN |
2025 | mod_timer(&host->tuning_timer, jiffies + |
2026 | host->tuning_count * HZ); | |
2027 | /* Tuning mode 1 limits the maximum data length to 4MB */ | |
2028 | mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; | |
2029 | } else { | |
2030 | host->flags &= ~SDHCI_NEEDS_RETUNING; | |
2031 | /* Reload the new initial value for timer */ | |
2032 | if (host->tuning_mode == SDHCI_TUNING_MODE_1) | |
2033 | mod_timer(&host->tuning_timer, jiffies + | |
2034 | host->tuning_count * HZ); | |
2035 | } | |
2036 | ||
2037 | /* | |
2038 | * In case tuning fails, host controllers which support re-tuning can | |
2039 | * try tuning again at a later time, when the re-tuning timer expires. | |
2040 | * So for these controllers, we return 0. Since there might be other | |
2041 | * controllers who do not have this capability, we return error for | |
973905fe AL |
2042 | * them. SDHCI_USING_RETUNING_TIMER means the host is currently using |
2043 | * a retuning timer to do the retuning for the card. | |
cf2b5eea | 2044 | */ |
973905fe | 2045 | if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) |
cf2b5eea AN |
2046 | err = 0; |
2047 | ||
b513ea25 AN |
2048 | sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier); |
2049 | spin_unlock(&host->lock); | |
2050 | enable_irq(host->irq); | |
66fd8ad5 | 2051 | sdhci_runtime_pm_put(host); |
b513ea25 AN |
2052 | |
2053 | return err; | |
2054 | } | |
2055 | ||
52983382 KL |
2056 | |
2057 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) | |
4d55c5a1 | 2058 | { |
4d55c5a1 | 2059 | u16 ctrl; |
4d55c5a1 | 2060 | |
4d55c5a1 AN |
2061 | /* Host Controller v3.00 defines preset value registers */ |
2062 | if (host->version < SDHCI_SPEC_300) | |
2063 | return; | |
2064 | ||
4d55c5a1 AN |
2065 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
2066 | ||
2067 | /* | |
2068 | * We only enable or disable Preset Value if they are not already | |
2069 | * enabled or disabled respectively. Otherwise, we bail out. | |
2070 | */ | |
2071 | if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { | |
2072 | ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; | |
2073 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
66fd8ad5 | 2074 | host->flags |= SDHCI_PV_ENABLED; |
4d55c5a1 AN |
2075 | } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { |
2076 | ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; | |
2077 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
66fd8ad5 | 2078 | host->flags &= ~SDHCI_PV_ENABLED; |
4d55c5a1 | 2079 | } |
66fd8ad5 AH |
2080 | } |
2081 | ||
71e69211 | 2082 | static void sdhci_card_event(struct mmc_host *mmc) |
d129bceb | 2083 | { |
71e69211 | 2084 | struct sdhci_host *host = mmc_priv(mmc); |
d129bceb PO |
2085 | unsigned long flags; |
2086 | ||
722e1280 CD |
2087 | /* First check if client has provided their own card event */ |
2088 | if (host->ops->card_event) | |
2089 | host->ops->card_event(host); | |
2090 | ||
d129bceb PO |
2091 | spin_lock_irqsave(&host->lock, flags); |
2092 | ||
66fd8ad5 | 2093 | /* Check host->mrq first in case we are runtime suspended */ |
9668d765 | 2094 | if (host->mrq && !sdhci_do_get_cd(host)) { |
a3c76eb9 | 2095 | pr_err("%s: Card removed during transfer!\n", |
66fd8ad5 | 2096 | mmc_hostname(host->mmc)); |
a3c76eb9 | 2097 | pr_err("%s: Resetting controller.\n", |
66fd8ad5 | 2098 | mmc_hostname(host->mmc)); |
d129bceb | 2099 | |
66fd8ad5 AH |
2100 | sdhci_reset(host, SDHCI_RESET_CMD); |
2101 | sdhci_reset(host, SDHCI_RESET_DATA); | |
d129bceb | 2102 | |
66fd8ad5 AH |
2103 | host->mrq->cmd->error = -ENOMEDIUM; |
2104 | tasklet_schedule(&host->finish_tasklet); | |
d129bceb PO |
2105 | } |
2106 | ||
2107 | spin_unlock_irqrestore(&host->lock, flags); | |
71e69211 GL |
2108 | } |
2109 | ||
2110 | static const struct mmc_host_ops sdhci_ops = { | |
2111 | .request = sdhci_request, | |
2112 | .set_ios = sdhci_set_ios, | |
94144a46 | 2113 | .get_cd = sdhci_get_cd, |
71e69211 GL |
2114 | .get_ro = sdhci_get_ro, |
2115 | .hw_reset = sdhci_hw_reset, | |
2116 | .enable_sdio_irq = sdhci_enable_sdio_irq, | |
2117 | .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, | |
2118 | .execute_tuning = sdhci_execute_tuning, | |
71e69211 | 2119 | .card_event = sdhci_card_event, |
20b92a30 | 2120 | .card_busy = sdhci_card_busy, |
71e69211 GL |
2121 | }; |
2122 | ||
2123 | /*****************************************************************************\ | |
2124 | * * | |
2125 | * Tasklets * | |
2126 | * * | |
2127 | \*****************************************************************************/ | |
2128 | ||
2129 | static void sdhci_tasklet_card(unsigned long param) | |
2130 | { | |
2131 | struct sdhci_host *host = (struct sdhci_host*)param; | |
2132 | ||
2133 | sdhci_card_event(host->mmc); | |
d129bceb | 2134 | |
04cf585d | 2135 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); |
d129bceb PO |
2136 | } |
2137 | ||
2138 | static void sdhci_tasklet_finish(unsigned long param) | |
2139 | { | |
2140 | struct sdhci_host *host; | |
2141 | unsigned long flags; | |
2142 | struct mmc_request *mrq; | |
2143 | ||
2144 | host = (struct sdhci_host*)param; | |
2145 | ||
66fd8ad5 AH |
2146 | spin_lock_irqsave(&host->lock, flags); |
2147 | ||
0c9c99a7 CB |
2148 | /* |
2149 | * If this tasklet gets rescheduled while running, it will | |
2150 | * be run again afterwards but without any active request. | |
2151 | */ | |
66fd8ad5 AH |
2152 | if (!host->mrq) { |
2153 | spin_unlock_irqrestore(&host->lock, flags); | |
0c9c99a7 | 2154 | return; |
66fd8ad5 | 2155 | } |
d129bceb PO |
2156 | |
2157 | del_timer(&host->timer); | |
2158 | ||
2159 | mrq = host->mrq; | |
2160 | ||
d129bceb PO |
2161 | /* |
2162 | * The controller needs a reset of internal state machines | |
2163 | * upon error conditions. | |
2164 | */ | |
1e72859e | 2165 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
b7b4d342 | 2166 | ((mrq->cmd && mrq->cmd->error) || |
1e72859e PO |
2167 | (mrq->data && (mrq->data->error || |
2168 | (mrq->data->stop && mrq->data->stop->error))) || | |
2169 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { | |
645289dc PO |
2170 | |
2171 | /* Some controllers need this kick or reset won't work here */ | |
8213af3b | 2172 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) |
645289dc | 2173 | /* This is to force an update */ |
8213af3b | 2174 | sdhci_update_clock(host); |
645289dc PO |
2175 | |
2176 | /* Spec says we should do both at the same time, but Ricoh | |
2177 | controllers do not like that. */ | |
d129bceb PO |
2178 | sdhci_reset(host, SDHCI_RESET_CMD); |
2179 | sdhci_reset(host, SDHCI_RESET_DATA); | |
2180 | } | |
2181 | ||
2182 | host->mrq = NULL; | |
2183 | host->cmd = NULL; | |
2184 | host->data = NULL; | |
2185 | ||
f9134319 | 2186 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 2187 | sdhci_deactivate_led(host); |
2f730fec | 2188 | #endif |
d129bceb | 2189 | |
5f25a66f | 2190 | mmiowb(); |
d129bceb PO |
2191 | spin_unlock_irqrestore(&host->lock, flags); |
2192 | ||
2193 | mmc_request_done(host->mmc, mrq); | |
66fd8ad5 | 2194 | sdhci_runtime_pm_put(host); |
d129bceb PO |
2195 | } |
2196 | ||
2197 | static void sdhci_timeout_timer(unsigned long data) | |
2198 | { | |
2199 | struct sdhci_host *host; | |
2200 | unsigned long flags; | |
2201 | ||
2202 | host = (struct sdhci_host*)data; | |
2203 | ||
2204 | spin_lock_irqsave(&host->lock, flags); | |
2205 | ||
2206 | if (host->mrq) { | |
a3c76eb9 | 2207 | pr_err("%s: Timeout waiting for hardware " |
acf1da45 | 2208 | "interrupt.\n", mmc_hostname(host->mmc)); |
d129bceb PO |
2209 | sdhci_dumpregs(host); |
2210 | ||
2211 | if (host->data) { | |
17b0429d | 2212 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
2213 | sdhci_finish_data(host); |
2214 | } else { | |
2215 | if (host->cmd) | |
17b0429d | 2216 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 2217 | else |
17b0429d | 2218 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
2219 | |
2220 | tasklet_schedule(&host->finish_tasklet); | |
2221 | } | |
2222 | } | |
2223 | ||
5f25a66f | 2224 | mmiowb(); |
d129bceb PO |
2225 | spin_unlock_irqrestore(&host->lock, flags); |
2226 | } | |
2227 | ||
cf2b5eea AN |
2228 | static void sdhci_tuning_timer(unsigned long data) |
2229 | { | |
2230 | struct sdhci_host *host; | |
2231 | unsigned long flags; | |
2232 | ||
2233 | host = (struct sdhci_host *)data; | |
2234 | ||
2235 | spin_lock_irqsave(&host->lock, flags); | |
2236 | ||
2237 | host->flags |= SDHCI_NEEDS_RETUNING; | |
2238 | ||
2239 | spin_unlock_irqrestore(&host->lock, flags); | |
2240 | } | |
2241 | ||
d129bceb PO |
2242 | /*****************************************************************************\ |
2243 | * * | |
2244 | * Interrupt handling * | |
2245 | * * | |
2246 | \*****************************************************************************/ | |
2247 | ||
2248 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
2249 | { | |
2250 | BUG_ON(intmask == 0); | |
2251 | ||
2252 | if (!host->cmd) { | |
a3c76eb9 | 2253 | pr_err("%s: Got command interrupt 0x%08x even " |
b67ac3f3 PO |
2254 | "though no command operation was in progress.\n", |
2255 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
2256 | sdhci_dumpregs(host); |
2257 | return; | |
2258 | } | |
2259 | ||
43b58b36 | 2260 | if (intmask & SDHCI_INT_TIMEOUT) |
17b0429d PO |
2261 | host->cmd->error = -ETIMEDOUT; |
2262 | else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | | |
2263 | SDHCI_INT_INDEX)) | |
2264 | host->cmd->error = -EILSEQ; | |
43b58b36 | 2265 | |
e809517f | 2266 | if (host->cmd->error) { |
d129bceb | 2267 | tasklet_schedule(&host->finish_tasklet); |
e809517f PO |
2268 | return; |
2269 | } | |
2270 | ||
2271 | /* | |
2272 | * The host can send and interrupt when the busy state has | |
2273 | * ended, allowing us to wait without wasting CPU cycles. | |
2274 | * Unfortunately this is overloaded on the "data complete" | |
2275 | * interrupt, so we need to take some care when handling | |
2276 | * it. | |
2277 | * | |
2278 | * Note: The 1.0 specification is a bit ambiguous about this | |
2279 | * feature so there might be some problems with older | |
2280 | * controllers. | |
2281 | */ | |
2282 | if (host->cmd->flags & MMC_RSP_BUSY) { | |
2283 | if (host->cmd->data) | |
2284 | DBG("Cannot wait for busy signal when also " | |
2285 | "doing a data transfer"); | |
f945405c | 2286 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) |
e809517f | 2287 | return; |
f945405c BD |
2288 | |
2289 | /* The controller does not support the end-of-busy IRQ, | |
2290 | * fall through and take the SDHCI_INT_RESPONSE */ | |
e809517f PO |
2291 | } |
2292 | ||
2293 | if (intmask & SDHCI_INT_RESPONSE) | |
43b58b36 | 2294 | sdhci_finish_command(host); |
d129bceb PO |
2295 | } |
2296 | ||
0957c333 | 2297 | #ifdef CONFIG_MMC_DEBUG |
6882a8c0 BD |
2298 | static void sdhci_show_adma_error(struct sdhci_host *host) |
2299 | { | |
2300 | const char *name = mmc_hostname(host->mmc); | |
2301 | u8 *desc = host->adma_desc; | |
2302 | __le32 *dma; | |
2303 | __le16 *len; | |
2304 | u8 attr; | |
2305 | ||
2306 | sdhci_dumpregs(host); | |
2307 | ||
2308 | while (true) { | |
2309 | dma = (__le32 *)(desc + 4); | |
2310 | len = (__le16 *)(desc + 2); | |
2311 | attr = *desc; | |
2312 | ||
2313 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
2314 | name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); | |
2315 | ||
2316 | desc += 8; | |
2317 | ||
2318 | if (attr & 2) | |
2319 | break; | |
2320 | } | |
2321 | } | |
2322 | #else | |
2323 | static void sdhci_show_adma_error(struct sdhci_host *host) { } | |
2324 | #endif | |
2325 | ||
d129bceb PO |
2326 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
2327 | { | |
069c9f14 | 2328 | u32 command; |
d129bceb PO |
2329 | BUG_ON(intmask == 0); |
2330 | ||
b513ea25 AN |
2331 | /* CMD19 generates _only_ Buffer Read Ready interrupt */ |
2332 | if (intmask & SDHCI_INT_DATA_AVAIL) { | |
069c9f14 G |
2333 | command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); |
2334 | if (command == MMC_SEND_TUNING_BLOCK || | |
2335 | command == MMC_SEND_TUNING_BLOCK_HS200) { | |
b513ea25 AN |
2336 | host->tuning_done = 1; |
2337 | wake_up(&host->buf_ready_int); | |
2338 | return; | |
2339 | } | |
2340 | } | |
2341 | ||
d129bceb PO |
2342 | if (!host->data) { |
2343 | /* | |
e809517f PO |
2344 | * The "data complete" interrupt is also used to |
2345 | * indicate that a busy state has ended. See comment | |
2346 | * above in sdhci_cmd_irq(). | |
d129bceb | 2347 | */ |
e809517f PO |
2348 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
2349 | if (intmask & SDHCI_INT_DATA_END) { | |
2350 | sdhci_finish_command(host); | |
2351 | return; | |
2352 | } | |
2353 | } | |
d129bceb | 2354 | |
a3c76eb9 | 2355 | pr_err("%s: Got data interrupt 0x%08x even " |
b67ac3f3 PO |
2356 | "though no data operation was in progress.\n", |
2357 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
2358 | sdhci_dumpregs(host); |
2359 | ||
2360 | return; | |
2361 | } | |
2362 | ||
2363 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d | 2364 | host->data->error = -ETIMEDOUT; |
22113efd AL |
2365 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
2366 | host->data->error = -EILSEQ; | |
2367 | else if ((intmask & SDHCI_INT_DATA_CRC) && | |
2368 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) | |
2369 | != MMC_BUS_TEST_R) | |
17b0429d | 2370 | host->data->error = -EILSEQ; |
6882a8c0 | 2371 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
a3c76eb9 | 2372 | pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); |
6882a8c0 | 2373 | sdhci_show_adma_error(host); |
2134a922 | 2374 | host->data->error = -EIO; |
a4071fbb HZ |
2375 | if (host->ops->adma_workaround) |
2376 | host->ops->adma_workaround(host, intmask); | |
6882a8c0 | 2377 | } |
d129bceb | 2378 | |
17b0429d | 2379 | if (host->data->error) |
d129bceb PO |
2380 | sdhci_finish_data(host); |
2381 | else { | |
a406f5a3 | 2382 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
2383 | sdhci_transfer_pio(host); |
2384 | ||
6ba736a1 PO |
2385 | /* |
2386 | * We currently don't do anything fancy with DMA | |
2387 | * boundaries, but as we can't disable the feature | |
2388 | * we need to at least restart the transfer. | |
f6a03cbf MV |
2389 | * |
2390 | * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) | |
2391 | * should return a valid address to continue from, but as | |
2392 | * some controllers are faulty, don't trust them. | |
6ba736a1 | 2393 | */ |
f6a03cbf MV |
2394 | if (intmask & SDHCI_INT_DMA_END) { |
2395 | u32 dmastart, dmanow; | |
2396 | dmastart = sg_dma_address(host->data->sg); | |
2397 | dmanow = dmastart + host->data->bytes_xfered; | |
2398 | /* | |
2399 | * Force update to the next DMA block boundary. | |
2400 | */ | |
2401 | dmanow = (dmanow & | |
2402 | ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + | |
2403 | SDHCI_DEFAULT_BOUNDARY_SIZE; | |
2404 | host->data->bytes_xfered = dmanow - dmastart; | |
2405 | DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," | |
2406 | " next 0x%08x\n", | |
2407 | mmc_hostname(host->mmc), dmastart, | |
2408 | host->data->bytes_xfered, dmanow); | |
2409 | sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); | |
2410 | } | |
6ba736a1 | 2411 | |
e538fbe8 PO |
2412 | if (intmask & SDHCI_INT_DATA_END) { |
2413 | if (host->cmd) { | |
2414 | /* | |
2415 | * Data managed to finish before the | |
2416 | * command completed. Make sure we do | |
2417 | * things in the proper order. | |
2418 | */ | |
2419 | host->data_early = 1; | |
2420 | } else { | |
2421 | sdhci_finish_data(host); | |
2422 | } | |
2423 | } | |
d129bceb PO |
2424 | } |
2425 | } | |
2426 | ||
7d12e780 | 2427 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb PO |
2428 | { |
2429 | irqreturn_t result; | |
66fd8ad5 | 2430 | struct sdhci_host *host = dev_id; |
6379b237 AS |
2431 | u32 intmask, unexpected = 0; |
2432 | int cardint = 0, max_loops = 16; | |
d129bceb PO |
2433 | |
2434 | spin_lock(&host->lock); | |
2435 | ||
66fd8ad5 AH |
2436 | if (host->runtime_suspended) { |
2437 | spin_unlock(&host->lock); | |
a3c76eb9 | 2438 | pr_warning("%s: got irq while runtime suspended\n", |
66fd8ad5 AH |
2439 | mmc_hostname(host->mmc)); |
2440 | return IRQ_HANDLED; | |
2441 | } | |
2442 | ||
4e4141a5 | 2443 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
d129bceb | 2444 | |
62df67a5 | 2445 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
2446 | result = IRQ_NONE; |
2447 | goto out; | |
2448 | } | |
2449 | ||
6379b237 | 2450 | again: |
b69c9058 PO |
2451 | DBG("*** %s got interrupt: 0x%08x\n", |
2452 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 2453 | |
3192a28f | 2454 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
d25928d1 SG |
2455 | u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
2456 | SDHCI_CARD_PRESENT; | |
2457 | ||
2458 | /* | |
2459 | * There is a observation on i.mx esdhc. INSERT bit will be | |
2460 | * immediately set again when it gets cleared, if a card is | |
2461 | * inserted. We have to mask the irq to prevent interrupt | |
2462 | * storm which will freeze the system. And the REMOVE gets | |
2463 | * the same situation. | |
2464 | * | |
2465 | * More testing are needed here to ensure it works for other | |
2466 | * platforms though. | |
2467 | */ | |
2468 | sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT : | |
2469 | SDHCI_INT_CARD_REMOVE); | |
2470 | sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE : | |
2471 | SDHCI_INT_CARD_INSERT); | |
2472 | ||
4e4141a5 | 2473 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | |
d25928d1 SG |
2474 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); |
2475 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); | |
d129bceb | 2476 | tasklet_schedule(&host->card_tasklet); |
3192a28f | 2477 | } |
d129bceb | 2478 | |
3192a28f | 2479 | if (intmask & SDHCI_INT_CMD_MASK) { |
4e4141a5 AV |
2480 | sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, |
2481 | SDHCI_INT_STATUS); | |
3192a28f | 2482 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
d129bceb PO |
2483 | } |
2484 | ||
2485 | if (intmask & SDHCI_INT_DATA_MASK) { | |
4e4141a5 AV |
2486 | sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, |
2487 | SDHCI_INT_STATUS); | |
3192a28f | 2488 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
d129bceb PO |
2489 | } |
2490 | ||
2491 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | |
2492 | ||
964f9ce2 PO |
2493 | intmask &= ~SDHCI_INT_ERROR; |
2494 | ||
d129bceb | 2495 | if (intmask & SDHCI_INT_BUS_POWER) { |
a3c76eb9 | 2496 | pr_err("%s: Card is consuming too much power!\n", |
d129bceb | 2497 | mmc_hostname(host->mmc)); |
4e4141a5 | 2498 | sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); |
d129bceb PO |
2499 | } |
2500 | ||
9d26a5d3 | 2501 | intmask &= ~SDHCI_INT_BUS_POWER; |
3192a28f | 2502 | |
f75979b7 PO |
2503 | if (intmask & SDHCI_INT_CARD_INT) |
2504 | cardint = 1; | |
2505 | ||
2506 | intmask &= ~SDHCI_INT_CARD_INT; | |
2507 | ||
3192a28f | 2508 | if (intmask) { |
6379b237 | 2509 | unexpected |= intmask; |
4e4141a5 | 2510 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); |
3192a28f | 2511 | } |
d129bceb PO |
2512 | |
2513 | result = IRQ_HANDLED; | |
2514 | ||
6379b237 | 2515 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
0a8fd09c AN |
2516 | |
2517 | /* | |
2518 | * If we know we'll call the driver to signal SDIO IRQ, disregard | |
2519 | * further indications of Card Interrupt in the status to avoid a | |
2520 | * needless loop. | |
2521 | */ | |
2522 | if (cardint) | |
2523 | intmask &= ~SDHCI_INT_CARD_INT; | |
6379b237 AS |
2524 | if (intmask && --max_loops) |
2525 | goto again; | |
d129bceb PO |
2526 | out: |
2527 | spin_unlock(&host->lock); | |
2528 | ||
6379b237 AS |
2529 | if (unexpected) { |
2530 | pr_err("%s: Unexpected interrupt 0x%08x.\n", | |
2531 | mmc_hostname(host->mmc), unexpected); | |
2532 | sdhci_dumpregs(host); | |
2533 | } | |
f75979b7 PO |
2534 | /* |
2535 | * We have to delay this as it calls back into the driver. | |
2536 | */ | |
2537 | if (cardint) | |
2538 | mmc_signal_sdio_irq(host->mmc); | |
2539 | ||
d129bceb PO |
2540 | return result; |
2541 | } | |
2542 | ||
2543 | /*****************************************************************************\ | |
2544 | * * | |
2545 | * Suspend/resume * | |
2546 | * * | |
2547 | \*****************************************************************************/ | |
2548 | ||
2549 | #ifdef CONFIG_PM | |
ad080d79 KL |
2550 | void sdhci_enable_irq_wakeups(struct sdhci_host *host) |
2551 | { | |
2552 | u8 val; | |
2553 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | |
2554 | | SDHCI_WAKE_ON_INT; | |
2555 | ||
2556 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
2557 | val |= mask ; | |
2558 | /* Avoid fake wake up */ | |
2559 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
2560 | val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); | |
2561 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
2562 | } | |
2563 | EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); | |
2564 | ||
2565 | void sdhci_disable_irq_wakeups(struct sdhci_host *host) | |
2566 | { | |
2567 | u8 val; | |
2568 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | |
2569 | | SDHCI_WAKE_ON_INT; | |
2570 | ||
2571 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
2572 | val &= ~mask; | |
2573 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
2574 | } | |
2575 | EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups); | |
d129bceb | 2576 | |
29495aa0 | 2577 | int sdhci_suspend_host(struct sdhci_host *host) |
d129bceb | 2578 | { |
a1b13b4e CB |
2579 | if (host->ops->platform_suspend) |
2580 | host->ops->platform_suspend(host); | |
2581 | ||
7260cf5e AV |
2582 | sdhci_disable_card_detection(host); |
2583 | ||
cf2b5eea | 2584 | /* Disable tuning since we are suspending */ |
973905fe | 2585 | if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
c6ced0db | 2586 | del_timer_sync(&host->tuning_timer); |
cf2b5eea | 2587 | host->flags &= ~SDHCI_NEEDS_RETUNING; |
cf2b5eea AN |
2588 | } |
2589 | ||
ad080d79 KL |
2590 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
2591 | sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); | |
2592 | free_irq(host->irq, host); | |
2593 | } else { | |
2594 | sdhci_enable_irq_wakeups(host); | |
2595 | enable_irq_wake(host->irq); | |
2596 | } | |
4ee14ec6 | 2597 | return 0; |
d129bceb PO |
2598 | } |
2599 | ||
b8c86fc5 | 2600 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
d129bceb | 2601 | |
b8c86fc5 PO |
2602 | int sdhci_resume_host(struct sdhci_host *host) |
2603 | { | |
4ee14ec6 | 2604 | int ret = 0; |
d129bceb | 2605 | |
a13abc7b | 2606 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
2607 | if (host->ops->enable_dma) |
2608 | host->ops->enable_dma(host); | |
2609 | } | |
d129bceb | 2610 | |
ad080d79 KL |
2611 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
2612 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, | |
2613 | mmc_hostname(host->mmc), host); | |
2614 | if (ret) | |
2615 | return ret; | |
2616 | } else { | |
2617 | sdhci_disable_irq_wakeups(host); | |
2618 | disable_irq_wake(host->irq); | |
2619 | } | |
d129bceb | 2620 | |
6308d290 AH |
2621 | if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && |
2622 | (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { | |
2623 | /* Card keeps power but host controller does not */ | |
2624 | sdhci_init(host, 0); | |
2625 | host->pwr = 0; | |
2626 | host->clock = 0; | |
2627 | sdhci_do_set_ios(host, &host->mmc->ios); | |
2628 | } else { | |
2629 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); | |
2630 | mmiowb(); | |
2631 | } | |
b8c86fc5 | 2632 | |
7260cf5e AV |
2633 | sdhci_enable_card_detection(host); |
2634 | ||
a1b13b4e CB |
2635 | if (host->ops->platform_resume) |
2636 | host->ops->platform_resume(host); | |
2637 | ||
cf2b5eea | 2638 | /* Set the re-tuning expiration flag */ |
973905fe | 2639 | if (host->flags & SDHCI_USING_RETUNING_TIMER) |
cf2b5eea AN |
2640 | host->flags |= SDHCI_NEEDS_RETUNING; |
2641 | ||
2f4cbb3d | 2642 | return ret; |
d129bceb PO |
2643 | } |
2644 | ||
b8c86fc5 | 2645 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
d129bceb PO |
2646 | #endif /* CONFIG_PM */ |
2647 | ||
66fd8ad5 AH |
2648 | #ifdef CONFIG_PM_RUNTIME |
2649 | ||
2650 | static int sdhci_runtime_pm_get(struct sdhci_host *host) | |
2651 | { | |
2652 | return pm_runtime_get_sync(host->mmc->parent); | |
2653 | } | |
2654 | ||
2655 | static int sdhci_runtime_pm_put(struct sdhci_host *host) | |
2656 | { | |
2657 | pm_runtime_mark_last_busy(host->mmc->parent); | |
2658 | return pm_runtime_put_autosuspend(host->mmc->parent); | |
2659 | } | |
2660 | ||
f0710a55 AH |
2661 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
2662 | { | |
2663 | if (host->runtime_suspended || host->bus_on) | |
2664 | return; | |
2665 | host->bus_on = true; | |
2666 | pm_runtime_get_noresume(host->mmc->parent); | |
2667 | } | |
2668 | ||
2669 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) | |
2670 | { | |
2671 | if (host->runtime_suspended || !host->bus_on) | |
2672 | return; | |
2673 | host->bus_on = false; | |
2674 | pm_runtime_put_noidle(host->mmc->parent); | |
2675 | } | |
2676 | ||
66fd8ad5 AH |
2677 | int sdhci_runtime_suspend_host(struct sdhci_host *host) |
2678 | { | |
2679 | unsigned long flags; | |
2680 | int ret = 0; | |
2681 | ||
2682 | /* Disable tuning since we are suspending */ | |
973905fe | 2683 | if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
66fd8ad5 AH |
2684 | del_timer_sync(&host->tuning_timer); |
2685 | host->flags &= ~SDHCI_NEEDS_RETUNING; | |
2686 | } | |
2687 | ||
2688 | spin_lock_irqsave(&host->lock, flags); | |
2689 | sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); | |
2690 | spin_unlock_irqrestore(&host->lock, flags); | |
2691 | ||
2692 | synchronize_irq(host->irq); | |
2693 | ||
2694 | spin_lock_irqsave(&host->lock, flags); | |
2695 | host->runtime_suspended = true; | |
2696 | spin_unlock_irqrestore(&host->lock, flags); | |
2697 | ||
2698 | return ret; | |
2699 | } | |
2700 | EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); | |
2701 | ||
2702 | int sdhci_runtime_resume_host(struct sdhci_host *host) | |
2703 | { | |
2704 | unsigned long flags; | |
2705 | int ret = 0, host_flags = host->flags; | |
2706 | ||
2707 | if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { | |
2708 | if (host->ops->enable_dma) | |
2709 | host->ops->enable_dma(host); | |
2710 | } | |
2711 | ||
2712 | sdhci_init(host, 0); | |
2713 | ||
2714 | /* Force clock and power re-program */ | |
2715 | host->pwr = 0; | |
2716 | host->clock = 0; | |
2717 | sdhci_do_set_ios(host, &host->mmc->ios); | |
2718 | ||
2719 | sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); | |
52983382 KL |
2720 | if ((host_flags & SDHCI_PV_ENABLED) && |
2721 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { | |
2722 | spin_lock_irqsave(&host->lock, flags); | |
2723 | sdhci_enable_preset_value(host, true); | |
2724 | spin_unlock_irqrestore(&host->lock, flags); | |
2725 | } | |
66fd8ad5 AH |
2726 | |
2727 | /* Set the re-tuning expiration flag */ | |
973905fe | 2728 | if (host->flags & SDHCI_USING_RETUNING_TIMER) |
66fd8ad5 AH |
2729 | host->flags |= SDHCI_NEEDS_RETUNING; |
2730 | ||
2731 | spin_lock_irqsave(&host->lock, flags); | |
2732 | ||
2733 | host->runtime_suspended = false; | |
2734 | ||
2735 | /* Enable SDIO IRQ */ | |
2736 | if ((host->flags & SDHCI_SDIO_IRQ_ENABLED)) | |
2737 | sdhci_enable_sdio_irq_nolock(host, true); | |
2738 | ||
2739 | /* Enable Card Detection */ | |
2740 | sdhci_enable_card_detection(host); | |
2741 | ||
2742 | spin_unlock_irqrestore(&host->lock, flags); | |
2743 | ||
2744 | return ret; | |
2745 | } | |
2746 | EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); | |
2747 | ||
2748 | #endif | |
2749 | ||
d129bceb PO |
2750 | /*****************************************************************************\ |
2751 | * * | |
b8c86fc5 | 2752 | * Device allocation/registration * |
d129bceb PO |
2753 | * * |
2754 | \*****************************************************************************/ | |
2755 | ||
b8c86fc5 PO |
2756 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
2757 | size_t priv_size) | |
d129bceb | 2758 | { |
d129bceb PO |
2759 | struct mmc_host *mmc; |
2760 | struct sdhci_host *host; | |
2761 | ||
b8c86fc5 | 2762 | WARN_ON(dev == NULL); |
d129bceb | 2763 | |
b8c86fc5 | 2764 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
d129bceb | 2765 | if (!mmc) |
b8c86fc5 | 2766 | return ERR_PTR(-ENOMEM); |
d129bceb PO |
2767 | |
2768 | host = mmc_priv(mmc); | |
2769 | host->mmc = mmc; | |
2770 | ||
b8c86fc5 PO |
2771 | return host; |
2772 | } | |
8a4da143 | 2773 | |
b8c86fc5 | 2774 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
d129bceb | 2775 | |
b8c86fc5 PO |
2776 | int sdhci_add_host(struct sdhci_host *host) |
2777 | { | |
2778 | struct mmc_host *mmc; | |
bd6a8c30 | 2779 | u32 caps[2] = {0, 0}; |
f2119df6 AN |
2780 | u32 max_current_caps; |
2781 | unsigned int ocr_avail; | |
b8c86fc5 | 2782 | int ret; |
d129bceb | 2783 | |
b8c86fc5 PO |
2784 | WARN_ON(host == NULL); |
2785 | if (host == NULL) | |
2786 | return -EINVAL; | |
d129bceb | 2787 | |
b8c86fc5 | 2788 | mmc = host->mmc; |
d129bceb | 2789 | |
b8c86fc5 PO |
2790 | if (debug_quirks) |
2791 | host->quirks = debug_quirks; | |
66fd8ad5 AH |
2792 | if (debug_quirks2) |
2793 | host->quirks2 = debug_quirks2; | |
d129bceb | 2794 | |
d96649ed PO |
2795 | sdhci_reset(host, SDHCI_RESET_ALL); |
2796 | ||
4e4141a5 | 2797 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
2134a922 PO |
2798 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
2799 | >> SDHCI_SPEC_VER_SHIFT; | |
85105c53 | 2800 | if (host->version > SDHCI_SPEC_300) { |
a3c76eb9 | 2801 | pr_err("%s: Unknown controller version (%d). " |
b69c9058 | 2802 | "You may experience problems.\n", mmc_hostname(mmc), |
2134a922 | 2803 | host->version); |
4a965505 PO |
2804 | } |
2805 | ||
f2119df6 | 2806 | caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : |
ccc92c23 | 2807 | sdhci_readl(host, SDHCI_CAPABILITIES); |
d129bceb | 2808 | |
bd6a8c30 PR |
2809 | if (host->version >= SDHCI_SPEC_300) |
2810 | caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? | |
2811 | host->caps1 : | |
2812 | sdhci_readl(host, SDHCI_CAPABILITIES_1); | |
f2119df6 | 2813 | |
b8c86fc5 | 2814 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
a13abc7b | 2815 | host->flags |= SDHCI_USE_SDMA; |
f2119df6 | 2816 | else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) |
a13abc7b | 2817 | DBG("Controller doesn't have SDMA capability\n"); |
67435274 | 2818 | else |
a13abc7b | 2819 | host->flags |= SDHCI_USE_SDMA; |
d129bceb | 2820 | |
b8c86fc5 | 2821 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
a13abc7b | 2822 | (host->flags & SDHCI_USE_SDMA)) { |
cee687ce | 2823 | DBG("Disabling DMA as it is marked broken\n"); |
a13abc7b | 2824 | host->flags &= ~SDHCI_USE_SDMA; |
7c168e3d FT |
2825 | } |
2826 | ||
f2119df6 AN |
2827 | if ((host->version >= SDHCI_SPEC_200) && |
2828 | (caps[0] & SDHCI_CAN_DO_ADMA2)) | |
a13abc7b | 2829 | host->flags |= SDHCI_USE_ADMA; |
2134a922 PO |
2830 | |
2831 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && | |
2832 | (host->flags & SDHCI_USE_ADMA)) { | |
2833 | DBG("Disabling ADMA as it is marked broken\n"); | |
2834 | host->flags &= ~SDHCI_USE_ADMA; | |
2835 | } | |
2836 | ||
a13abc7b | 2837 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
2838 | if (host->ops->enable_dma) { |
2839 | if (host->ops->enable_dma(host)) { | |
a3c76eb9 | 2840 | pr_warning("%s: No suitable DMA " |
b8c86fc5 PO |
2841 | "available. Falling back to PIO.\n", |
2842 | mmc_hostname(mmc)); | |
a13abc7b RR |
2843 | host->flags &= |
2844 | ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); | |
b8c86fc5 | 2845 | } |
d129bceb PO |
2846 | } |
2847 | } | |
2848 | ||
2134a922 PO |
2849 | if (host->flags & SDHCI_USE_ADMA) { |
2850 | /* | |
2851 | * We need to allocate descriptors for all sg entries | |
2852 | * (128) and potentially one alignment transfer for | |
2853 | * each of those entries. | |
2854 | */ | |
2855 | host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); | |
2856 | host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); | |
2857 | if (!host->adma_desc || !host->align_buffer) { | |
2858 | kfree(host->adma_desc); | |
2859 | kfree(host->align_buffer); | |
a3c76eb9 | 2860 | pr_warning("%s: Unable to allocate ADMA " |
2134a922 PO |
2861 | "buffers. Falling back to standard DMA.\n", |
2862 | mmc_hostname(mmc)); | |
2863 | host->flags &= ~SDHCI_USE_ADMA; | |
2864 | } | |
2865 | } | |
2866 | ||
7659150c PO |
2867 | /* |
2868 | * If we use DMA, then it's up to the caller to set the DMA | |
2869 | * mask, but PIO does not need the hw shim so we set a new | |
2870 | * mask here in that case. | |
2871 | */ | |
a13abc7b | 2872 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
7659150c PO |
2873 | host->dma_mask = DMA_BIT_MASK(64); |
2874 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; | |
2875 | } | |
d129bceb | 2876 | |
c4687d5f | 2877 | if (host->version >= SDHCI_SPEC_300) |
f2119df6 | 2878 | host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) |
c4687d5f ZG |
2879 | >> SDHCI_CLOCK_BASE_SHIFT; |
2880 | else | |
f2119df6 | 2881 | host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) |
c4687d5f ZG |
2882 | >> SDHCI_CLOCK_BASE_SHIFT; |
2883 | ||
4240ff0a | 2884 | host->max_clk *= 1000000; |
f27f47ef AV |
2885 | if (host->max_clk == 0 || host->quirks & |
2886 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { | |
4240ff0a | 2887 | if (!host->ops->get_max_clock) { |
a3c76eb9 | 2888 | pr_err("%s: Hardware doesn't specify base clock " |
4240ff0a BD |
2889 | "frequency.\n", mmc_hostname(mmc)); |
2890 | return -ENODEV; | |
2891 | } | |
2892 | host->max_clk = host->ops->get_max_clock(host); | |
8ef1a143 | 2893 | } |
d129bceb | 2894 | |
c3ed3877 AN |
2895 | /* |
2896 | * In case of Host Controller v3.00, find out whether clock | |
2897 | * multiplier is supported. | |
2898 | */ | |
2899 | host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> | |
2900 | SDHCI_CLOCK_MUL_SHIFT; | |
2901 | ||
2902 | /* | |
2903 | * In case the value in Clock Multiplier is 0, then programmable | |
2904 | * clock mode is not supported, otherwise the actual clock | |
2905 | * multiplier is one more than the value of Clock Multiplier | |
2906 | * in the Capabilities Register. | |
2907 | */ | |
2908 | if (host->clk_mul) | |
2909 | host->clk_mul += 1; | |
2910 | ||
d129bceb PO |
2911 | /* |
2912 | * Set host parameters. | |
2913 | */ | |
2914 | mmc->ops = &sdhci_ops; | |
c3ed3877 | 2915 | mmc->f_max = host->max_clk; |
ce5f036b | 2916 | if (host->ops->get_min_clock) |
a9e58f25 | 2917 | mmc->f_min = host->ops->get_min_clock(host); |
c3ed3877 AN |
2918 | else if (host->version >= SDHCI_SPEC_300) { |
2919 | if (host->clk_mul) { | |
2920 | mmc->f_min = (host->max_clk * host->clk_mul) / 1024; | |
2921 | mmc->f_max = host->max_clk * host->clk_mul; | |
2922 | } else | |
2923 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; | |
2924 | } else | |
0397526d | 2925 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
15ec4461 | 2926 | |
272308ca AS |
2927 | host->timeout_clk = |
2928 | (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
2929 | if (host->timeout_clk == 0) { | |
2930 | if (host->ops->get_timeout_clock) { | |
2931 | host->timeout_clk = host->ops->get_timeout_clock(host); | |
2932 | } else if (!(host->quirks & | |
2933 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { | |
a3c76eb9 | 2934 | pr_err("%s: Hardware doesn't specify timeout clock " |
272308ca AS |
2935 | "frequency.\n", mmc_hostname(mmc)); |
2936 | return -ENODEV; | |
2937 | } | |
2938 | } | |
2939 | if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) | |
2940 | host->timeout_clk *= 1000; | |
2941 | ||
2942 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) | |
65be3fef | 2943 | host->timeout_clk = mmc->f_max / 1000; |
272308ca | 2944 | |
65be3fef | 2945 | mmc->max_discard_to = (1 << 27) / host->timeout_clk; |
58d1246d | 2946 | |
e89d456f AW |
2947 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; |
2948 | ||
2949 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) | |
2950 | host->flags |= SDHCI_AUTO_CMD12; | |
5fe23c7f | 2951 | |
8edf6371 | 2952 | /* Auto-CMD23 stuff only works in ADMA or PIO. */ |
4f3d3e9b | 2953 | if ((host->version >= SDHCI_SPEC_300) && |
8edf6371 | 2954 | ((host->flags & SDHCI_USE_ADMA) || |
4f3d3e9b | 2955 | !(host->flags & SDHCI_USE_SDMA))) { |
8edf6371 AW |
2956 | host->flags |= SDHCI_AUTO_CMD23; |
2957 | DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); | |
2958 | } else { | |
2959 | DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); | |
2960 | } | |
2961 | ||
15ec4461 PR |
2962 | /* |
2963 | * A controller may support 8-bit width, but the board itself | |
2964 | * might not have the pins brought out. Boards that support | |
2965 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in | |
2966 | * their platform code before calling sdhci_add_host(), and we | |
2967 | * won't assume 8-bit width for hosts without that CAP. | |
2968 | */ | |
5fe23c7f | 2969 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
15ec4461 | 2970 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
d129bceb | 2971 | |
63ef5d8c JH |
2972 | if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) |
2973 | mmc->caps &= ~MMC_CAP_CMD23; | |
2974 | ||
f2119df6 | 2975 | if (caps[0] & SDHCI_CAN_DO_HISPD) |
a29e7e18 | 2976 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
cd9277c0 | 2977 | |
176d1ed4 | 2978 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
eb6d5ae1 | 2979 | !(host->mmc->caps & MMC_CAP_NONREMOVABLE)) |
68d1fb7e AV |
2980 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
2981 | ||
6231f3de | 2982 | /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ |
462849aa | 2983 | host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc"); |
657d5982 KL |
2984 | if (IS_ERR_OR_NULL(host->vqmmc)) { |
2985 | if (PTR_ERR(host->vqmmc) < 0) { | |
2986 | pr_info("%s: no vqmmc regulator found\n", | |
2987 | mmc_hostname(mmc)); | |
2988 | host->vqmmc = NULL; | |
2989 | } | |
8363c374 | 2990 | } else { |
a3361aba | 2991 | ret = regulator_enable(host->vqmmc); |
cec2e216 KL |
2992 | if (!regulator_is_supported_voltage(host->vqmmc, 1700000, |
2993 | 1950000)) | |
8363c374 KL |
2994 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | |
2995 | SDHCI_SUPPORT_SDR50 | | |
2996 | SDHCI_SUPPORT_DDR50); | |
a3361aba CB |
2997 | if (ret) { |
2998 | pr_warn("%s: Failed to enable vqmmc regulator: %d\n", | |
2999 | mmc_hostname(mmc), ret); | |
3000 | host->vqmmc = NULL; | |
3001 | } | |
8363c374 | 3002 | } |
6231f3de | 3003 | |
6a66180a DD |
3004 | if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) |
3005 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | | |
3006 | SDHCI_SUPPORT_DDR50); | |
3007 | ||
4188bba0 AC |
3008 | /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ |
3009 | if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | | |
3010 | SDHCI_SUPPORT_DDR50)) | |
f2119df6 AN |
3011 | mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; |
3012 | ||
3013 | /* SDR104 supports also implies SDR50 support */ | |
156e14b1 | 3014 | if (caps[1] & SDHCI_SUPPORT_SDR104) { |
f2119df6 | 3015 | mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; |
156e14b1 GC |
3016 | /* SD3.0: SDR104 is supported so (for eMMC) the caps2 |
3017 | * field can be promoted to support HS200. | |
3018 | */ | |
3019 | mmc->caps2 |= MMC_CAP2_HS200; | |
3020 | } else if (caps[1] & SDHCI_SUPPORT_SDR50) | |
f2119df6 AN |
3021 | mmc->caps |= MMC_CAP_UHS_SDR50; |
3022 | ||
3023 | if (caps[1] & SDHCI_SUPPORT_DDR50) | |
3024 | mmc->caps |= MMC_CAP_UHS_DDR50; | |
3025 | ||
069c9f14 | 3026 | /* Does the host need tuning for SDR50? */ |
b513ea25 AN |
3027 | if (caps[1] & SDHCI_USE_SDR50_TUNING) |
3028 | host->flags |= SDHCI_SDR50_NEEDS_TUNING; | |
3029 | ||
156e14b1 | 3030 | /* Does the host need tuning for SDR104 / HS200? */ |
069c9f14 | 3031 | if (mmc->caps2 & MMC_CAP2_HS200) |
156e14b1 | 3032 | host->flags |= SDHCI_SDR104_NEEDS_TUNING; |
069c9f14 | 3033 | |
d6d50a15 AN |
3034 | /* Driver Type(s) (A, C, D) supported by the host */ |
3035 | if (caps[1] & SDHCI_DRIVER_TYPE_A) | |
3036 | mmc->caps |= MMC_CAP_DRIVER_TYPE_A; | |
3037 | if (caps[1] & SDHCI_DRIVER_TYPE_C) | |
3038 | mmc->caps |= MMC_CAP_DRIVER_TYPE_C; | |
3039 | if (caps[1] & SDHCI_DRIVER_TYPE_D) | |
3040 | mmc->caps |= MMC_CAP_DRIVER_TYPE_D; | |
3041 | ||
cf2b5eea AN |
3042 | /* Initial value for re-tuning timer count */ |
3043 | host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> | |
3044 | SDHCI_RETUNING_TIMER_COUNT_SHIFT; | |
3045 | ||
3046 | /* | |
3047 | * In case Re-tuning Timer is not disabled, the actual value of | |
3048 | * re-tuning timer will be 2 ^ (n - 1). | |
3049 | */ | |
3050 | if (host->tuning_count) | |
3051 | host->tuning_count = 1 << (host->tuning_count - 1); | |
3052 | ||
3053 | /* Re-tuning mode supported by the Host Controller */ | |
3054 | host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> | |
3055 | SDHCI_RETUNING_MODE_SHIFT; | |
3056 | ||
8f230f45 | 3057 | ocr_avail = 0; |
bad37e1a | 3058 | |
462849aa | 3059 | host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc"); |
657d5982 KL |
3060 | if (IS_ERR_OR_NULL(host->vmmc)) { |
3061 | if (PTR_ERR(host->vmmc) < 0) { | |
3062 | pr_info("%s: no vmmc regulator found\n", | |
3063 | mmc_hostname(mmc)); | |
3064 | host->vmmc = NULL; | |
3065 | } | |
8363c374 | 3066 | } |
bad37e1a | 3067 | |
68737043 | 3068 | #ifdef CONFIG_REGULATOR |
a4f8f257 MS |
3069 | /* |
3070 | * Voltage range check makes sense only if regulator reports | |
3071 | * any voltage value. | |
3072 | */ | |
3073 | if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) { | |
cec2e216 KL |
3074 | ret = regulator_is_supported_voltage(host->vmmc, 2700000, |
3075 | 3600000); | |
68737043 PR |
3076 | if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330))) |
3077 | caps[0] &= ~SDHCI_CAN_VDD_330; | |
68737043 PR |
3078 | if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300))) |
3079 | caps[0] &= ~SDHCI_CAN_VDD_300; | |
cec2e216 KL |
3080 | ret = regulator_is_supported_voltage(host->vmmc, 1700000, |
3081 | 1950000); | |
68737043 PR |
3082 | if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180))) |
3083 | caps[0] &= ~SDHCI_CAN_VDD_180; | |
3084 | } | |
3085 | #endif /* CONFIG_REGULATOR */ | |
3086 | ||
f2119df6 AN |
3087 | /* |
3088 | * According to SD Host Controller spec v3.00, if the Host System | |
3089 | * can afford more than 150mA, Host Driver should set XPC to 1. Also | |
3090 | * the value is meaningful only if Voltage Support in the Capabilities | |
3091 | * register is set. The actual current value is 4 times the register | |
3092 | * value. | |
3093 | */ | |
3094 | max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); | |
bad37e1a PR |
3095 | if (!max_current_caps && host->vmmc) { |
3096 | u32 curr = regulator_get_current_limit(host->vmmc); | |
3097 | if (curr > 0) { | |
3098 | ||
3099 | /* convert to SDHCI_MAX_CURRENT format */ | |
3100 | curr = curr/1000; /* convert to mA */ | |
3101 | curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; | |
3102 | ||
3103 | curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); | |
3104 | max_current_caps = | |
3105 | (curr << SDHCI_MAX_CURRENT_330_SHIFT) | | |
3106 | (curr << SDHCI_MAX_CURRENT_300_SHIFT) | | |
3107 | (curr << SDHCI_MAX_CURRENT_180_SHIFT); | |
3108 | } | |
3109 | } | |
f2119df6 AN |
3110 | |
3111 | if (caps[0] & SDHCI_CAN_VDD_330) { | |
8f230f45 | 3112 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
f2119df6 | 3113 | |
55c4665e | 3114 | mmc->max_current_330 = ((max_current_caps & |
f2119df6 AN |
3115 | SDHCI_MAX_CURRENT_330_MASK) >> |
3116 | SDHCI_MAX_CURRENT_330_SHIFT) * | |
3117 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3118 | } |
3119 | if (caps[0] & SDHCI_CAN_VDD_300) { | |
8f230f45 | 3120 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
f2119df6 | 3121 | |
55c4665e | 3122 | mmc->max_current_300 = ((max_current_caps & |
f2119df6 AN |
3123 | SDHCI_MAX_CURRENT_300_MASK) >> |
3124 | SDHCI_MAX_CURRENT_300_SHIFT) * | |
3125 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3126 | } |
3127 | if (caps[0] & SDHCI_CAN_VDD_180) { | |
8f230f45 TI |
3128 | ocr_avail |= MMC_VDD_165_195; |
3129 | ||
55c4665e | 3130 | mmc->max_current_180 = ((max_current_caps & |
f2119df6 AN |
3131 | SDHCI_MAX_CURRENT_180_MASK) >> |
3132 | SDHCI_MAX_CURRENT_180_SHIFT) * | |
3133 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3134 | } |
3135 | ||
c0b887b6 HZ |
3136 | if (host->ocr_mask) |
3137 | ocr_avail = host->ocr_mask; | |
3138 | ||
8f230f45 TI |
3139 | mmc->ocr_avail = ocr_avail; |
3140 | mmc->ocr_avail_sdio = ocr_avail; | |
3141 | if (host->ocr_avail_sdio) | |
3142 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; | |
3143 | mmc->ocr_avail_sd = ocr_avail; | |
3144 | if (host->ocr_avail_sd) | |
3145 | mmc->ocr_avail_sd &= host->ocr_avail_sd; | |
3146 | else /* normal SD controllers don't support 1.8V */ | |
3147 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; | |
3148 | mmc->ocr_avail_mmc = ocr_avail; | |
3149 | if (host->ocr_avail_mmc) | |
3150 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; | |
146ad66e PO |
3151 | |
3152 | if (mmc->ocr_avail == 0) { | |
a3c76eb9 | 3153 | pr_err("%s: Hardware doesn't report any " |
b69c9058 | 3154 | "support voltages.\n", mmc_hostname(mmc)); |
b8c86fc5 | 3155 | return -ENODEV; |
146ad66e PO |
3156 | } |
3157 | ||
d129bceb PO |
3158 | spin_lock_init(&host->lock); |
3159 | ||
3160 | /* | |
2134a922 PO |
3161 | * Maximum number of segments. Depends on if the hardware |
3162 | * can do scatter/gather or not. | |
d129bceb | 3163 | */ |
2134a922 | 3164 | if (host->flags & SDHCI_USE_ADMA) |
a36274e0 | 3165 | mmc->max_segs = 128; |
a13abc7b | 3166 | else if (host->flags & SDHCI_USE_SDMA) |
a36274e0 | 3167 | mmc->max_segs = 1; |
2134a922 | 3168 | else /* PIO */ |
a36274e0 | 3169 | mmc->max_segs = 128; |
d129bceb PO |
3170 | |
3171 | /* | |
bab76961 | 3172 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 3173 | * size (512KiB). |
d129bceb | 3174 | */ |
55db890a | 3175 | mmc->max_req_size = 524288; |
d129bceb PO |
3176 | |
3177 | /* | |
3178 | * Maximum segment size. Could be one segment with the maximum number | |
2134a922 PO |
3179 | * of bytes. When doing hardware scatter/gather, each entry cannot |
3180 | * be larger than 64 KiB though. | |
d129bceb | 3181 | */ |
30652aa3 OJ |
3182 | if (host->flags & SDHCI_USE_ADMA) { |
3183 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) | |
3184 | mmc->max_seg_size = 65535; | |
3185 | else | |
3186 | mmc->max_seg_size = 65536; | |
3187 | } else { | |
2134a922 | 3188 | mmc->max_seg_size = mmc->max_req_size; |
30652aa3 | 3189 | } |
d129bceb | 3190 | |
fe4a3c7a PO |
3191 | /* |
3192 | * Maximum block size. This varies from controller to controller and | |
3193 | * is specified in the capabilities register. | |
3194 | */ | |
0633f654 AV |
3195 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
3196 | mmc->max_blk_size = 2; | |
3197 | } else { | |
f2119df6 | 3198 | mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> |
0633f654 AV |
3199 | SDHCI_MAX_BLOCK_SHIFT; |
3200 | if (mmc->max_blk_size >= 3) { | |
a3c76eb9 | 3201 | pr_warning("%s: Invalid maximum block size, " |
0633f654 AV |
3202 | "assuming 512 bytes\n", mmc_hostname(mmc)); |
3203 | mmc->max_blk_size = 0; | |
3204 | } | |
3205 | } | |
3206 | ||
3207 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 3208 | |
55db890a PO |
3209 | /* |
3210 | * Maximum block count. | |
3211 | */ | |
1388eefd | 3212 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
55db890a | 3213 | |
d129bceb PO |
3214 | /* |
3215 | * Init tasklets. | |
3216 | */ | |
3217 | tasklet_init(&host->card_tasklet, | |
3218 | sdhci_tasklet_card, (unsigned long)host); | |
3219 | tasklet_init(&host->finish_tasklet, | |
3220 | sdhci_tasklet_finish, (unsigned long)host); | |
3221 | ||
e4cad1b5 | 3222 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 3223 | |
cf2b5eea | 3224 | if (host->version >= SDHCI_SPEC_300) { |
b513ea25 AN |
3225 | init_waitqueue_head(&host->buf_ready_int); |
3226 | ||
cf2b5eea AN |
3227 | /* Initialize re-tuning timer */ |
3228 | init_timer(&host->tuning_timer); | |
3229 | host->tuning_timer.data = (unsigned long)host; | |
3230 | host->tuning_timer.function = sdhci_tuning_timer; | |
3231 | } | |
3232 | ||
2af502ca SG |
3233 | sdhci_init(host, 0); |
3234 | ||
dace1453 | 3235 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
b69c9058 | 3236 | mmc_hostname(mmc), host); |
0fc81ee3 MB |
3237 | if (ret) { |
3238 | pr_err("%s: Failed to request IRQ %d: %d\n", | |
3239 | mmc_hostname(mmc), host->irq, ret); | |
8ef1a143 | 3240 | goto untasklet; |
0fc81ee3 | 3241 | } |
d129bceb | 3242 | |
d129bceb PO |
3243 | #ifdef CONFIG_MMC_DEBUG |
3244 | sdhci_dumpregs(host); | |
3245 | #endif | |
3246 | ||
f9134319 | 3247 | #ifdef SDHCI_USE_LEDS_CLASS |
5dbace0c HS |
3248 | snprintf(host->led_name, sizeof(host->led_name), |
3249 | "%s::", mmc_hostname(mmc)); | |
3250 | host->led.name = host->led_name; | |
2f730fec PO |
3251 | host->led.brightness = LED_OFF; |
3252 | host->led.default_trigger = mmc_hostname(mmc); | |
3253 | host->led.brightness_set = sdhci_led_control; | |
3254 | ||
b8c86fc5 | 3255 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
0fc81ee3 MB |
3256 | if (ret) { |
3257 | pr_err("%s: Failed to register LED device: %d\n", | |
3258 | mmc_hostname(mmc), ret); | |
2f730fec | 3259 | goto reset; |
0fc81ee3 | 3260 | } |
2f730fec PO |
3261 | #endif |
3262 | ||
5f25a66f PO |
3263 | mmiowb(); |
3264 | ||
d129bceb PO |
3265 | mmc_add_host(mmc); |
3266 | ||
a3c76eb9 | 3267 | pr_info("%s: SDHCI controller on %s [%s] using %s\n", |
d1b26863 | 3268 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
a13abc7b RR |
3269 | (host->flags & SDHCI_USE_ADMA) ? "ADMA" : |
3270 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); | |
d129bceb | 3271 | |
7260cf5e AV |
3272 | sdhci_enable_card_detection(host); |
3273 | ||
d129bceb PO |
3274 | return 0; |
3275 | ||
f9134319 | 3276 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
3277 | reset: |
3278 | sdhci_reset(host, SDHCI_RESET_ALL); | |
b0a8dece | 3279 | sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); |
2f730fec PO |
3280 | free_irq(host->irq, host); |
3281 | #endif | |
8ef1a143 | 3282 | untasklet: |
d129bceb PO |
3283 | tasklet_kill(&host->card_tasklet); |
3284 | tasklet_kill(&host->finish_tasklet); | |
d129bceb PO |
3285 | |
3286 | return ret; | |
3287 | } | |
3288 | ||
b8c86fc5 | 3289 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
d129bceb | 3290 | |
1e72859e | 3291 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
b8c86fc5 | 3292 | { |
1e72859e PO |
3293 | unsigned long flags; |
3294 | ||
3295 | if (dead) { | |
3296 | spin_lock_irqsave(&host->lock, flags); | |
3297 | ||
3298 | host->flags |= SDHCI_DEVICE_DEAD; | |
3299 | ||
3300 | if (host->mrq) { | |
a3c76eb9 | 3301 | pr_err("%s: Controller removed during " |
1e72859e PO |
3302 | " transfer!\n", mmc_hostname(host->mmc)); |
3303 | ||
3304 | host->mrq->cmd->error = -ENOMEDIUM; | |
3305 | tasklet_schedule(&host->finish_tasklet); | |
3306 | } | |
3307 | ||
3308 | spin_unlock_irqrestore(&host->lock, flags); | |
3309 | } | |
3310 | ||
7260cf5e AV |
3311 | sdhci_disable_card_detection(host); |
3312 | ||
b8c86fc5 | 3313 | mmc_remove_host(host->mmc); |
d129bceb | 3314 | |
f9134319 | 3315 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
3316 | led_classdev_unregister(&host->led); |
3317 | #endif | |
3318 | ||
1e72859e PO |
3319 | if (!dead) |
3320 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb | 3321 | |
b0a8dece | 3322 | sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); |
d129bceb PO |
3323 | free_irq(host->irq, host); |
3324 | ||
3325 | del_timer_sync(&host->timer); | |
3326 | ||
3327 | tasklet_kill(&host->card_tasklet); | |
3328 | tasklet_kill(&host->finish_tasklet); | |
2134a922 | 3329 | |
77dcb3f4 PR |
3330 | if (host->vmmc) { |
3331 | regulator_disable(host->vmmc); | |
9bea3c85 | 3332 | regulator_put(host->vmmc); |
77dcb3f4 | 3333 | } |
9bea3c85 | 3334 | |
6231f3de PR |
3335 | if (host->vqmmc) { |
3336 | regulator_disable(host->vqmmc); | |
3337 | regulator_put(host->vqmmc); | |
3338 | } | |
3339 | ||
2134a922 PO |
3340 | kfree(host->adma_desc); |
3341 | kfree(host->align_buffer); | |
3342 | ||
3343 | host->adma_desc = NULL; | |
3344 | host->align_buffer = NULL; | |
d129bceb PO |
3345 | } |
3346 | ||
b8c86fc5 | 3347 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
d129bceb | 3348 | |
b8c86fc5 | 3349 | void sdhci_free_host(struct sdhci_host *host) |
d129bceb | 3350 | { |
b8c86fc5 | 3351 | mmc_free_host(host->mmc); |
d129bceb PO |
3352 | } |
3353 | ||
b8c86fc5 | 3354 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
d129bceb PO |
3355 | |
3356 | /*****************************************************************************\ | |
3357 | * * | |
3358 | * Driver init/exit * | |
3359 | * * | |
3360 | \*****************************************************************************/ | |
3361 | ||
3362 | static int __init sdhci_drv_init(void) | |
3363 | { | |
a3c76eb9 | 3364 | pr_info(DRIVER_NAME |
52fbf9c9 | 3365 | ": Secure Digital Host Controller Interface driver\n"); |
a3c76eb9 | 3366 | pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
d129bceb | 3367 | |
b8c86fc5 | 3368 | return 0; |
d129bceb PO |
3369 | } |
3370 | ||
3371 | static void __exit sdhci_drv_exit(void) | |
3372 | { | |
d129bceb PO |
3373 | } |
3374 | ||
3375 | module_init(sdhci_drv_init); | |
3376 | module_exit(sdhci_drv_exit); | |
3377 | ||
df673b22 | 3378 | module_param(debug_quirks, uint, 0444); |
66fd8ad5 | 3379 | module_param(debug_quirks2, uint, 0444); |
67435274 | 3380 | |
32710e8f | 3381 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 | 3382 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
d129bceb | 3383 | MODULE_LICENSE("GPL"); |
67435274 | 3384 | |
df673b22 | 3385 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |
66fd8ad5 | 3386 | MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); |