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mmc: sdhci: avoid sync'ing the SG if there's no misalignment
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
d129bceb 52static void sdhci_finish_command(struct sdhci_host *);
069c9f14 53static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 54static void sdhci_tuning_timer(unsigned long data);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 56
66fd8ad5
AH		 57#ifdef CONFIG_PM_RUNTIME
58static int sdhci_runtime_pm_get(struct sdhci_host *host);
59static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 60static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
61static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 62#else
63static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
64{
65 return 0;
66}
67static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
68{
69 return 0;
70}
f0710a55
AH		 71static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
72{
73}
74static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
75{
76}
66fd8ad5
AH		 77#endif
78
d129bceb
PO		 79static void sdhci_dumpregs(struct sdhci_host *host)
80{
a3c76eb9 81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 82 mmc_hostname(host->mmc));
d129bceb 83
a3c76eb9 84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 85 sdhci_readl(host, SDHCI_DMA_ADDRESS),
86 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readw(host, SDHCI_BLOCK_SIZE),
89 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readl(host, SDHCI_ARGUMENT),
92 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readl(host, SDHCI_PRESENT_STATE),
95 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readb(host, SDHCI_POWER_CONTROL),
98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
101 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
104 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 106 sdhci_readl(host, SDHCI_INT_ENABLE),
107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 109 sdhci_readw(host, SDHCI_ACMD12_ERR),
110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 112 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 113 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 115 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 116 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 118 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 119
be3f4ae0 120 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 121 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 122 readl(host->ioaddr + SDHCI_ADMA_ERROR),
123 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
124
a3c76eb9 125 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 126}
127
128/*****************************************************************************\
129 * *
130 * Low level functions *
131 * *
132\*****************************************************************************/
133
7260cf5e
AV		 134static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
135{
5b4f1f6c 136 u32 present;
7260cf5e 137
c79396c1 138 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 139 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 140 return;
141
5b4f1f6c
RK		 142 if (enable) {
143 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
144 SDHCI_CARD_PRESENT;
d25928d1 145
5b4f1f6c
RK		 146 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
147 SDHCI_INT_CARD_INSERT;
148 } else {
149 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
150 }
b537f94c
RK		 151
152 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
153 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 154}
155
156static void sdhci_enable_card_detection(struct sdhci_host *host)
157{
158 sdhci_set_card_detection(host, true);
159}
160
161static void sdhci_disable_card_detection(struct sdhci_host *host)
162{
163 sdhci_set_card_detection(host, false);
164}
165
03231f9b 166void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 167{
e16514d8 168 unsigned long timeout;
393c1a34 169
4e4141a5 170 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 171
f0710a55 172 if (mask & SDHCI_RESET_ALL) {
d129bceb 173 host->clock = 0;
f0710a55
AH		 174 /* Reset-all turns off SD Bus Power */
175 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
176 sdhci_runtime_pm_bus_off(host);
177 }
d129bceb 178
e16514d8
PO		 179 /* Wait max 100 ms */
180 timeout = 100;
181
182 /* hw clears the bit when it's done */
4e4141a5 183 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 184 if (timeout == 0) {
a3c76eb9 185 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 186 mmc_hostname(host->mmc), (int)mask);
187 sdhci_dumpregs(host);
188 return;
189 }
190 timeout--;
191 mdelay(1);
d129bceb 192 }
03231f9b
RK		 193}
194EXPORT_SYMBOL_GPL(sdhci_reset);
195
196static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
197{
198 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
199 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
200 SDHCI_CARD_PRESENT))
201 return;
202 }
063a9dbb 203
03231f9b 204 host->ops->reset(host, mask);
393c1a34 205
3abc1e80
SX		 206 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
207 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
208 host->ops->enable_dma(host);
209 }
d129bceb
PO		 210}
211
2f4cbb3d
NP		 212static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
213
214static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 215{
2f4cbb3d 216 if (soft)
03231f9b 217 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 218 else
03231f9b 219 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 220
b537f94c
RK		 221 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
222 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
223 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
224 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
225 SDHCI_INT_RESPONSE;
226
227 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
228 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 229
230 if (soft) {
231 /* force clock reconfiguration */
232 host->clock = 0;
233 sdhci_set_ios(host->mmc, &host->mmc->ios);
234 }
7260cf5e 235}
d129bceb 236
7260cf5e
AV		 237static void sdhci_reinit(struct sdhci_host *host)
238{
2f4cbb3d 239 sdhci_init(host, 0);
b67c6b41
AL		 240 /*
241 * Retuning stuffs are affected by different cards inserted and only
242 * applicable to UHS-I cards. So reset these fields to their initial
243 * value when card is removed.
244 */
973905fe
AL		 245 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
246 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
247
b67c6b41
AL		 248 del_timer_sync(&host->tuning_timer);
249 host->flags &= ~SDHCI_NEEDS_RETUNING;
250 host->mmc->max_blk_count =
251 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
252 }
7260cf5e 253 sdhci_enable_card_detection(host);
d129bceb
PO		 254}
255
256static void sdhci_activate_led(struct sdhci_host *host)
257{
258 u8 ctrl;
259
4e4141a5 260 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 261 ctrl |= SDHCI_CTRL_LED;
4e4141a5 262 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 263}
264
265static void sdhci_deactivate_led(struct sdhci_host *host)
266{
267 u8 ctrl;
268
4e4141a5 269 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 270 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 271 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 272}
273
f9134319 274#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 275static void sdhci_led_control(struct led_classdev *led,
276 enum led_brightness brightness)
277{
278 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
279 unsigned long flags;
280
281 spin_lock_irqsave(&host->lock, flags);
282
66fd8ad5
AH		 283 if (host->runtime_suspended)
284 goto out;
285
2f730fec
PO		 286 if (brightness == LED_OFF)
287 sdhci_deactivate_led(host);
288 else
289 sdhci_activate_led(host);
66fd8ad5 290out:
2f730fec
PO		 291 spin_unlock_irqrestore(&host->lock, flags);
292}
293#endif
294
d129bceb
PO		 295/*****************************************************************************\
296 * *
297 * Core functions *
298 * *
299\*****************************************************************************/
300
a406f5a3 301static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 302{
7659150c
PO		 303 unsigned long flags;
304 size_t blksize, len, chunk;
7244b85b 305 u32 uninitialized_var(scratch);
7659150c 306 u8 *buf;
d129bceb 307
a406f5a3 308 DBG("PIO reading\n");
d129bceb 309
a406f5a3 310 blksize = host->data->blksz;
7659150c 311 chunk = 0;
d129bceb 312
7659150c 313 local_irq_save(flags);
d129bceb 314
a406f5a3 315 while (blksize) {
7659150c
PO		 316 if (!sg_miter_next(&host->sg_miter))
317 BUG();
d129bceb 318
7659150c 319 len = min(host->sg_miter.length, blksize);
d129bceb 320
7659150c
PO		 321 blksize -= len;
322 host->sg_miter.consumed = len;
14d836e7 323
7659150c 324 buf = host->sg_miter.addr;
d129bceb 325
7659150c
PO		 326 while (len) {
327 if (chunk == 0) {
4e4141a5 328 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 329 chunk = 4;
a406f5a3 330 }
7659150c
PO		 331
332 *buf = scratch & 0xFF;
333
334 buf++;
335 scratch >>= 8;
336 chunk--;
337 len--;
d129bceb 338 }
a406f5a3 339 }
7659150c
PO		 340
341 sg_miter_stop(&host->sg_miter);
342
343 local_irq_restore(flags);
a406f5a3 344}
d129bceb 345
a406f5a3
PO		 346static void sdhci_write_block_pio(struct sdhci_host *host)
347{
7659150c
PO		 348 unsigned long flags;
349 size_t blksize, len, chunk;
350 u32 scratch;
351 u8 *buf;
d129bceb 352
a406f5a3
PO		 353 DBG("PIO writing\n");
354
355 blksize = host->data->blksz;
7659150c
PO		 356 chunk = 0;
357 scratch = 0;
d129bceb 358
7659150c 359 local_irq_save(flags);
d129bceb 360
a406f5a3 361 while (blksize) {
7659150c
PO		 362 if (!sg_miter_next(&host->sg_miter))
363 BUG();
a406f5a3 364
7659150c
PO		 365 len = min(host->sg_miter.length, blksize);
366
367 blksize -= len;
368 host->sg_miter.consumed = len;
369
370 buf = host->sg_miter.addr;
d129bceb 371
7659150c
PO		 372 while (len) {
373 scratch |= (u32)*buf << (chunk * 8);
374
375 buf++;
376 chunk++;
377 len--;
378
379 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 380 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 381 chunk = 0;
382 scratch = 0;
d129bceb 383 }
d129bceb
PO		 384 }
385 }
7659150c
PO		 386
387 sg_miter_stop(&host->sg_miter);
388
389 local_irq_restore(flags);
a406f5a3
PO		 390}
391
392static void sdhci_transfer_pio(struct sdhci_host *host)
393{
394 u32 mask;
395
396 BUG_ON(!host->data);
397
7659150c 398 if (host->blocks == 0)
a406f5a3
PO		 399 return;
400
401 if (host->data->flags & MMC_DATA_READ)
402 mask = SDHCI_DATA_AVAILABLE;
403 else
404 mask = SDHCI_SPACE_AVAILABLE;
405
4a3cba32
PO		 406 /*
407 * Some controllers (JMicron JMB38x) mess up the buffer bits
408 * for transfers < 4 bytes. As long as it is just one block,
409 * we can ignore the bits.
410 */
411 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
412 (host->data->blocks == 1))
413 mask = ~0;
414
4e4141a5 415 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 416 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
417 udelay(100);
418
a406f5a3
PO		 419 if (host->data->flags & MMC_DATA_READ)
420 sdhci_read_block_pio(host);
421 else
422 sdhci_write_block_pio(host);
d129bceb 423
7659150c
PO		 424 host->blocks--;
425 if (host->blocks == 0)
a406f5a3 426 break;
a406f5a3 427 }
d129bceb 428
a406f5a3 429 DBG("PIO transfer complete.\n");
d129bceb
PO		 430}
431
2134a922
PO		 432static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
433{
434 local_irq_save(*flags);
482fce99 435 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 436}
437
438static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
439{
482fce99 440 kunmap_atomic(buffer);
2134a922
PO		 441 local_irq_restore(*flags);
442}
443
118cd17d
BD		 444static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
445{
9e506f35
BD		 446 __le32 *dataddr = (__le32 __force *)(desc + 4);
447 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 448
9e506f35
BD		 449 /* SDHCI specification says ADMA descriptors should be 4 byte
450 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 451
9e506f35
BD		 452 cmdlen[0] = cpu_to_le16(cmd);
453 cmdlen[1] = cpu_to_le16(len);
454
455 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 456}
457
8f1934ce 458static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 459 struct mmc_data *data)
460{
461 int direction;
462
463 u8 *desc;
464 u8 *align;
465 dma_addr_t addr;
466 dma_addr_t align_addr;
467 int len, offset;
468
469 struct scatterlist *sg;
470 int i;
471 char *buffer;
472 unsigned long flags;
473
474 /*
475 * The spec does not specify endianness of descriptor table.
476 * We currently guess that it is LE.
477 */
478
479 if (data->flags & MMC_DATA_READ)
480 direction = DMA_FROM_DEVICE;
481 else
482 direction = DMA_TO_DEVICE;
483
484 /*
485 * The ADMA descriptor table is mapped further down as we
486 * need to fill it with data first.
487 */
488
489 host->align_addr = dma_map_single(mmc_dev(host->mmc),
490 host->align_buffer, 128 * 4, direction);
8d8bb39b 491 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 492 goto fail;
2134a922
PO		 493 BUG_ON(host->align_addr & 0x3);
494
495 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
496 data->sg, data->sg_len, direction);
8f1934ce
PO		 497 if (host->sg_count == 0)
498 goto unmap_align;
2134a922
PO		 499
500 desc = host->adma_desc;
501 align = host->align_buffer;
502
503 align_addr = host->align_addr;
504
505 for_each_sg(data->sg, sg, host->sg_count, i) {
506 addr = sg_dma_address(sg);
507 len = sg_dma_len(sg);
508
509 /*
510 * The SDHCI specification states that ADMA
511 * addresses must be 32-bit aligned. If they
512 * aren't, then we use a bounce buffer for
513 * the (up to three) bytes that screw up the
514 * alignment.
515 */
516 offset = (4 - (addr & 0x3)) & 0x3;
517 if (offset) {
518 if (data->flags & MMC_DATA_WRITE) {
519 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 520 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 521 memcpy(align, buffer, offset);
522 sdhci_kunmap_atomic(buffer, &flags);
523 }
524
118cd17d
BD		 525 /* tran, valid */
526 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 527
528 BUG_ON(offset > 65536);
529
2134a922
PO		 530 align += 4;
531 align_addr += 4;
532
533 desc += 8;
534
535 addr += offset;
536 len -= offset;
537 }
538
2134a922
PO		 539 BUG_ON(len > 65536);
540
118cd17d
BD		 541 /* tran, valid */
542 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 543 desc += 8;
544
545 /*
546 * If this triggers then we have a calculation bug
547 * somewhere. :/
548 */
549 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
550 }
551
70764a90
TA		 552 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
553 /*
554 * Mark the last descriptor as the terminating descriptor
555 */
556 if (desc != host->adma_desc) {
557 desc -= 8;
558 desc[0] |= 0x2; /* end */
559 }
560 } else {
561 /*
562 * Add a terminating entry.
563 */
2134a922 564
70764a90
TA		 565 /* nop, end, valid */
566 sdhci_set_adma_desc(desc, 0, 0, 0x3);
567 }
2134a922
PO		 568
569 /*
570 * Resync align buffer as we might have changed it.
571 */
572 if (data->flags & MMC_DATA_WRITE) {
573 dma_sync_single_for_device(mmc_dev(host->mmc),
574 host->align_addr, 128 * 4, direction);
575 }
576
577 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
578 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 579 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 580 goto unmap_entries;
2134a922 581 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 582
583 return 0;
584
585unmap_entries:
586 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
587 data->sg_len, direction);
588unmap_align:
589 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
590 128 * 4, direction);
591fail:
592 return -EINVAL;
2134a922
PO		 593}
594
595static void sdhci_adma_table_post(struct sdhci_host *host,
596 struct mmc_data *data)
597{
598 int direction;
599
600 struct scatterlist *sg;
601 int i, size;
602 u8 *align;
603 char *buffer;
604 unsigned long flags;
de0b65a7 605 bool has_unaligned;
2134a922
PO		 606
607 if (data->flags & MMC_DATA_READ)
608 direction = DMA_FROM_DEVICE;
609 else
610 direction = DMA_TO_DEVICE;
611
612 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
613 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
614
615 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
616 128 * 4, direction);
617
de0b65a7
RK		 618 /* Do a quick scan of the SG list for any unaligned mappings */
619 has_unaligned = false;
620 for_each_sg(data->sg, sg, host->sg_count, i)
621 if (sg_dma_address(sg) & 3) {
622 has_unaligned = true;
623 break;
624 }
625
626 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 627 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
628 data->sg_len, direction);
629
630 align = host->align_buffer;
631
632 for_each_sg(data->sg, sg, host->sg_count, i) {
633 if (sg_dma_address(sg) & 0x3) {
634 size = 4 - (sg_dma_address(sg) & 0x3);
635
636 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 637 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 638 memcpy(buffer, align, size);
639 sdhci_kunmap_atomic(buffer, &flags);
640
641 align += 4;
642 }
643 }
644 }
645
646 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
647 data->sg_len, direction);
648}
649
a3c7778f 650static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 651{
1c8cde92 652 u8 count;
a3c7778f 653 struct mmc_data *data = cmd->data;
1c8cde92 654 unsigned target_timeout, current_timeout;
d129bceb 655
ee53ab5d
PO		 656 /*
657 * If the host controller provides us with an incorrect timeout
658 * value, just skip the check and use 0xE. The hardware may take
659 * longer to time out, but that's much better than having a too-short
660 * timeout value.
661 */
11a2f1b7 662 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 663 return 0xE;
e538fbe8 664
a3c7778f 665 /* Unspecified timeout, assume max */
1d4d7744 666 if (!data && !cmd->busy_timeout)
a3c7778f 667 return 0xE;
d129bceb 668
a3c7778f
AW		 669 /* timeout in us */
670 if (!data)
1d4d7744 671 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 672 else {
673 target_timeout = data->timeout_ns / 1000;
674 if (host->clock)
675 target_timeout += data->timeout_clks / host->clock;
676 }
81b39802 677
1c8cde92
PO		 678 /*
679 * Figure out needed cycles.
680 * We do this in steps in order to fit inside a 32 bit int.
681 * The first step is the minimum timeout, which will have a
682 * minimum resolution of 6 bits:
683 * (1) 2^13*1000 > 2^22,
684 * (2) host->timeout_clk < 2^16
685 * =>
686 * (1) / (2) > 2^6
687 */
688 count = 0;
689 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
690 while (current_timeout < target_timeout) {
691 count++;
692 current_timeout <<= 1;
693 if (count >= 0xF)
694 break;
695 }
696
697 if (count >= 0xF) {
09eeff52
CB		 698 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
699 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 700 count = 0xE;
701 }
702
ee53ab5d
PO		 703 return count;
704}
705
6aa943ab
AV		 706static void sdhci_set_transfer_irqs(struct sdhci_host *host)
707{
708 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
709 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
710
711 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 712 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 713 else
b537f94c
RK		 714 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
715
716 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
717 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 718}
719
a3c7778f 720static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 721{
722 u8 count;
2134a922 723 u8 ctrl;
a3c7778f 724 struct mmc_data *data = cmd->data;
8f1934ce 725 int ret;
ee53ab5d
PO		 726
727 WARN_ON(host->data);
728
a3c7778f
AW		 729 if (data || (cmd->flags & MMC_RSP_BUSY)) {
730 count = sdhci_calc_timeout(host, cmd);
731 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
732 }
733
734 if (!data)
ee53ab5d
PO		 735 return;
736
737 /* Sanity checks */
738 BUG_ON(data->blksz * data->blocks > 524288);
739 BUG_ON(data->blksz > host->mmc->max_blk_size);
740 BUG_ON(data->blocks > 65535);
741
742 host->data = data;
743 host->data_early = 0;
f6a03cbf 744 host->data->bytes_xfered = 0;
ee53ab5d 745
a13abc7b 746 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 747 host->flags |= SDHCI_REQ_USE_DMA;
748
2134a922
PO		 749 /*
750 * FIXME: This doesn't account for merging when mapping the
751 * scatterlist.
752 */
753 if (host->flags & SDHCI_REQ_USE_DMA) {
754 int broken, i;
755 struct scatterlist *sg;
756
757 broken = 0;
758 if (host->flags & SDHCI_USE_ADMA) {
759 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
760 broken = 1;
761 } else {
762 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
763 broken = 1;
764 }
765
766 if (unlikely(broken)) {
767 for_each_sg(data->sg, sg, data->sg_len, i) {
768 if (sg->length & 0x3) {
769 DBG("Reverting to PIO because of "
770 "transfer size (%d)\n",
771 sg->length);
772 host->flags &= ~SDHCI_REQ_USE_DMA;
773 break;
774 }
775 }
776 }
c9fddbc4
PO		 777 }
778
779 /*
780 * The assumption here being that alignment is the same after
781 * translation to device address space.
782 */
2134a922
PO		 783 if (host->flags & SDHCI_REQ_USE_DMA) {
784 int broken, i;
785 struct scatterlist *sg;
786
787 broken = 0;
788 if (host->flags & SDHCI_USE_ADMA) {
789 /*
790 * As we use 3 byte chunks to work around
791 * alignment problems, we need to check this
792 * quirk.
793 */
794 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
795 broken = 1;
796 } else {
797 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
798 broken = 1;
799 }
800
801 if (unlikely(broken)) {
802 for_each_sg(data->sg, sg, data->sg_len, i) {
803 if (sg->offset & 0x3) {
804 DBG("Reverting to PIO because of "
805 "bad alignment\n");
806 host->flags &= ~SDHCI_REQ_USE_DMA;
807 break;
808 }
809 }
810 }
811 }
812
8f1934ce
PO		 813 if (host->flags & SDHCI_REQ_USE_DMA) {
814 if (host->flags & SDHCI_USE_ADMA) {
815 ret = sdhci_adma_table_pre(host, data);
816 if (ret) {
817 /*
818 * This only happens when someone fed
819 * us an invalid request.
820 */
821 WARN_ON(1);
ebd6d357 822 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 823 } else {
4e4141a5
AV		 824 sdhci_writel(host, host->adma_addr,
825 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 826 }
827 } else {
c8b3e02e 828 int sg_cnt;
8f1934ce 829
c8b3e02e 830 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 831 data->sg, data->sg_len,
832 (data->flags & MMC_DATA_READ) ?
833 DMA_FROM_DEVICE :
834 DMA_TO_DEVICE);
c8b3e02e 835 if (sg_cnt == 0) {
8f1934ce
PO		 836 /*
837 * This only happens when someone fed
838 * us an invalid request.
839 */
840 WARN_ON(1);
ebd6d357 841 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 842 } else {
719a61b4 843 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 844 sdhci_writel(host, sg_dma_address(data->sg),
845 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 846 }
847 }
848 }
849
2134a922
PO		 850 /*
851 * Always adjust the DMA selection as some controllers
852 * (e.g. JMicron) can't do PIO properly when the selection
853 * is ADMA.
854 */
855 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 856 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 857 ctrl &= ~SDHCI_CTRL_DMA_MASK;
858 if ((host->flags & SDHCI_REQ_USE_DMA) &&
859 (host->flags & SDHCI_USE_ADMA))
860 ctrl |= SDHCI_CTRL_ADMA32;
861 else
862 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 863 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 864 }
865
8f1934ce 866 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 867 int flags;
868
869 flags = SG_MITER_ATOMIC;
870 if (host->data->flags & MMC_DATA_READ)
871 flags |= SG_MITER_TO_SG;
872 else
873 flags |= SG_MITER_FROM_SG;
874 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 875 host->blocks = data->blocks;
d129bceb 876 }
c7fa9963 877
6aa943ab
AV		 878 sdhci_set_transfer_irqs(host);
879
f6a03cbf
MV		 880 /* Set the DMA boundary value and block size */
881 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
882 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 883 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 884}
885
886static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 887 struct mmc_command *cmd)
c7fa9963
PO		 888{
889 u16 mode;
e89d456f 890 struct mmc_data *data = cmd->data;
c7fa9963 891
2b558c13
DA		 892 if (data == NULL) {
893 /* clear Auto CMD settings for no data CMDs */
894 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
895 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
896 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
c7fa9963 897 return;
2b558c13 898 }
c7fa9963 899
e538fbe8
PO		 900 WARN_ON(!host->data);
901
c7fa9963 902 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 903 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
904 mode |= SDHCI_TRNS_MULTI;
905 /*
906 * If we are sending CMD23, CMD12 never gets sent
907 * on successful completion (so no Auto-CMD12).
908 */
909 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
910 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 911 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
912 mode |= SDHCI_TRNS_AUTO_CMD23;
913 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
914 }
c4512f79 915 }
8edf6371 916
c7fa9963
PO		 917 if (data->flags & MMC_DATA_READ)
918 mode |= SDHCI_TRNS_READ;
c9fddbc4 919 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 920 mode |= SDHCI_TRNS_DMA;
921
4e4141a5 922 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 923}
924
925static void sdhci_finish_data(struct sdhci_host *host)
926{
927 struct mmc_data *data;
d129bceb
PO		 928
929 BUG_ON(!host->data);
930
931 data = host->data;
932 host->data = NULL;
933
c9fddbc4 934 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 935 if (host->flags & SDHCI_USE_ADMA)
936 sdhci_adma_table_post(host, data);
937 else {
938 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
939 data->sg_len, (data->flags & MMC_DATA_READ) ?
940 DMA_FROM_DEVICE : DMA_TO_DEVICE);
941 }
d129bceb
PO		 942 }
943
944 /*
c9b74c5b
PO		 945 * The specification states that the block count register must
946 * be updated, but it does not specify at what point in the
947 * data flow. That makes the register entirely useless to read
948 * back so we have to assume that nothing made it to the card
949 * in the event of an error.
d129bceb 950 */
c9b74c5b
PO		 951 if (data->error)
952 data->bytes_xfered = 0;
d129bceb 953 else
c9b74c5b 954 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 955
e89d456f
AW		 956 /*
957 * Need to send CMD12 if -
958 * a) open-ended multiblock transfer (no CMD23)
959 * b) error in multiblock transfer
960 */
961 if (data->stop &&
962 (data->error ||
963 !host->mrq->sbc)) {
964
d129bceb
PO		 965 /*
966 * The controller needs a reset of internal state machines
967 * upon error conditions.
968 */
17b0429d 969 if (data->error) {
03231f9b
RK		 970 sdhci_do_reset(host, SDHCI_RESET_CMD);
971 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 972 }
973
974 sdhci_send_command(host, data->stop);
975 } else
976 tasklet_schedule(&host->finish_tasklet);
977}
978
c0e55129 979void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 980{
981 int flags;
fd2208d7 982 u32 mask;
7cb2c76f 983 unsigned long timeout;
d129bceb
PO		 984
985 WARN_ON(host->cmd);
986
d129bceb 987 /* Wait max 10 ms */
7cb2c76f 988 timeout = 10;
fd2208d7
PO		 989
990 mask = SDHCI_CMD_INHIBIT;
991 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
992 mask |= SDHCI_DATA_INHIBIT;
993
994 /* We shouldn't wait for data inihibit for stop commands, even
995 though they might use busy signaling */
996 if (host->mrq->data && (cmd == host->mrq->data->stop))
997 mask &= ~SDHCI_DATA_INHIBIT;
998
4e4141a5 999 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1000 if (timeout == 0) {
a3c76eb9 1001 pr_err("%s: Controller never released "
acf1da45 1002 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 1003 sdhci_dumpregs(host);
17b0429d 1004 cmd->error = -EIO;
d129bceb
PO		 1005 tasklet_schedule(&host->finish_tasklet);
1006 return;
1007 }
7cb2c76f
PO		 1008 timeout--;
1009 mdelay(1);
1010 }
d129bceb 1011
3e1a6892 1012 timeout = jiffies;
1d4d7744
UH		 1013 if (!cmd->data && cmd->busy_timeout > 9000)
1014 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1015 else
1016 timeout += 10 * HZ;
1017 mod_timer(&host->timer, timeout);
d129bceb
PO		 1018
1019 host->cmd = cmd;
1020
a3c7778f 1021 sdhci_prepare_data(host, cmd);
d129bceb 1022
4e4141a5 1023 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1024
e89d456f 1025 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1026
d129bceb 1027 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1028 pr_err("%s: Unsupported response type!\n",
d129bceb 1029 mmc_hostname(host->mmc));
17b0429d 1030 cmd->error = -EINVAL;
d129bceb
PO		 1031 tasklet_schedule(&host->finish_tasklet);
1032 return;
1033 }
1034
1035 if (!(cmd->flags & MMC_RSP_PRESENT))
1036 flags = SDHCI_CMD_RESP_NONE;
1037 else if (cmd->flags & MMC_RSP_136)
1038 flags = SDHCI_CMD_RESP_LONG;
1039 else if (cmd->flags & MMC_RSP_BUSY)
1040 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1041 else
1042 flags = SDHCI_CMD_RESP_SHORT;
1043
1044 if (cmd->flags & MMC_RSP_CRC)
1045 flags |= SDHCI_CMD_CRC;
1046 if (cmd->flags & MMC_RSP_OPCODE)
1047 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1048
1049 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1050 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1051 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1052 flags |= SDHCI_CMD_DATA;
1053
4e4141a5 1054 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1055}
c0e55129 1056EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1057
1058static void sdhci_finish_command(struct sdhci_host *host)
1059{
1060 int i;
1061
1062 BUG_ON(host->cmd == NULL);
1063
1064 if (host->cmd->flags & MMC_RSP_PRESENT) {
1065 if (host->cmd->flags & MMC_RSP_136) {
1066 /* CRC is stripped so we need to do some shifting. */
1067 for (i = 0;i < 4;i++) {
4e4141a5 1068 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1069 SDHCI_RESPONSE + (3-i)*4) << 8;
1070 if (i != 3)
1071 host->cmd->resp[i] |=
4e4141a5 1072 sdhci_readb(host,
d129bceb
PO		 1073 SDHCI_RESPONSE + (3-i)*4-1);
1074 }
1075 } else {
4e4141a5 1076 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1077 }
1078 }
1079
17b0429d 1080 host->cmd->error = 0;
d129bceb 1081
e89d456f
AW		 1082 /* Finished CMD23, now send actual command. */
1083 if (host->cmd == host->mrq->sbc) {
1084 host->cmd = NULL;
1085 sdhci_send_command(host, host->mrq->cmd);
1086 } else {
e538fbe8 1087
e89d456f
AW		 1088 /* Processed actual command. */
1089 if (host->data && host->data_early)
1090 sdhci_finish_data(host);
d129bceb 1091
e89d456f
AW		 1092 if (!host->cmd->data)
1093 tasklet_schedule(&host->finish_tasklet);
1094
1095 host->cmd = NULL;
1096 }
d129bceb
PO		 1097}
1098
52983382
KL		 1099static u16 sdhci_get_preset_value(struct sdhci_host *host)
1100{
1101 u16 ctrl, preset = 0;
1102
1103 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1104
1105 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1106 case SDHCI_CTRL_UHS_SDR12:
1107 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1108 break;
1109 case SDHCI_CTRL_UHS_SDR25:
1110 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1111 break;
1112 case SDHCI_CTRL_UHS_SDR50:
1113 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1114 break;
1115 case SDHCI_CTRL_UHS_SDR104:
1116 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1117 break;
1118 case SDHCI_CTRL_UHS_DDR50:
1119 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1120 break;
1121 default:
1122 pr_warn("%s: Invalid UHS-I mode selected\n",
1123 mmc_hostname(host->mmc));
1124 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1125 break;
1126 }
1127 return preset;
1128}
1129
d129bceb
PO		 1130static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1131{
c3ed3877 1132 int div = 0; /* Initialized for compiler warning */
df16219f 1133 int real_div = div, clk_mul = 1;
c3ed3877 1134 u16 clk = 0;
7cb2c76f 1135 unsigned long timeout;
d129bceb 1136
30832ab5 1137 if (clock && clock == host->clock)
d129bceb
PO		 1138 return;
1139
df16219f
GC		 1140 host->mmc->actual_clock = 0;
1141
8114634c
AV		 1142 if (host->ops->set_clock) {
1143 host->ops->set_clock(host, clock);
1144 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1145 return;
1146 }
1147
4e4141a5 1148 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1149
1150 if (clock == 0)
1151 goto out;
1152
85105c53 1153 if (host->version >= SDHCI_SPEC_300) {
52983382
KL		 1154 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1155 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1156 u16 pre_val;
1157
1158 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1159 pre_val = sdhci_get_preset_value(host);
1160 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1161 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1162 if (host->clk_mul &&
1163 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1164 clk = SDHCI_PROG_CLOCK_MODE;
1165 real_div = div + 1;
1166 clk_mul = host->clk_mul;
1167 } else {
1168 real_div = max_t(int, 1, div << 1);
1169 }
1170 goto clock_set;
1171 }
1172
c3ed3877
AN		 1173 /*
1174 * Check if the Host Controller supports Programmable Clock
1175 * Mode.
1176 */
1177 if (host->clk_mul) {
52983382
KL		 1178 for (div = 1; div <= 1024; div++) {
1179 if ((host->max_clk * host->clk_mul / div)
1180 <= clock)
1181 break;
1182 }
c3ed3877 1183 /*
52983382
KL		 1184 * Set Programmable Clock Mode in the Clock
1185 * Control register.
c3ed3877 1186 */
52983382
KL		 1187 clk = SDHCI_PROG_CLOCK_MODE;
1188 real_div = div;
1189 clk_mul = host->clk_mul;
1190 div--;
c3ed3877
AN		 1191 } else {
1192 /* Version 3.00 divisors must be a multiple of 2. */
1193 if (host->max_clk <= clock)
1194 div = 1;
1195 else {
1196 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1197 div += 2) {
1198 if ((host->max_clk / div) <= clock)
1199 break;
1200 }
85105c53 1201 }
df16219f 1202 real_div = div;
c3ed3877 1203 div >>= 1;
85105c53
ZG		 1204 }
1205 } else {
1206 /* Version 2.00 divisors must be a power of 2. */
0397526d 1207 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1208 if ((host->max_clk / div) <= clock)
1209 break;
1210 }
df16219f 1211 real_div = div;
c3ed3877 1212 div >>= 1;
d129bceb 1213 }
d129bceb 1214
52983382 1215clock_set:
df16219f
GC		 1216 if (real_div)
1217 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1218
c3ed3877 1219 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1220 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1221 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1222 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1223 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1224
27f6cb16
CB		 1225 /* Wait max 20 ms */
1226 timeout = 20;
4e4141a5 1227 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1228 & SDHCI_CLOCK_INT_STABLE)) {
1229 if (timeout == 0) {
a3c76eb9 1230 pr_err("%s: Internal clock never "
acf1da45 1231 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1232 sdhci_dumpregs(host);
1233 return;
1234 }
7cb2c76f
PO		 1235 timeout--;
1236 mdelay(1);
1237 }
d129bceb
PO		 1238
1239 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1240 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1241
1242out:
1243 host->clock = clock;
1244}
1245
8213af3b
AS		 1246static inline void sdhci_update_clock(struct sdhci_host *host)
1247{
1248 unsigned int clock;
1249
1250 clock = host->clock;
1251 host->clock = 0;
1252 sdhci_set_clock(host, clock);
1253}
1254
ceb6143b 1255static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1256{
8364248a 1257 u8 pwr = 0;
146ad66e 1258
8364248a 1259 if (power != (unsigned short)-1) {
ae628903
PO		 1260 switch (1 << power) {
1261 case MMC_VDD_165_195:
1262 pwr = SDHCI_POWER_180;
1263 break;
1264 case MMC_VDD_29_30:
1265 case MMC_VDD_30_31:
1266 pwr = SDHCI_POWER_300;
1267 break;
1268 case MMC_VDD_32_33:
1269 case MMC_VDD_33_34:
1270 pwr = SDHCI_POWER_330;
1271 break;
1272 default:
1273 BUG();
1274 }
1275 }
1276
1277 if (host->pwr == pwr)
ceb6143b 1278 return -1;
146ad66e 1279
ae628903
PO		 1280 host->pwr = pwr;
1281
1282 if (pwr == 0) {
4e4141a5 1283 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1284 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1285 sdhci_runtime_pm_bus_off(host);
ceb6143b 1286 return 0;
9e9dc5f2
DS		 1287 }
1288
1289 /*
1290 * Spec says that we should clear the power reg before setting
1291 * a new value. Some controllers don't seem to like this though.
1292 */
b8c86fc5 1293 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1294 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1295
e08c1694 1296 /*
c71f6512 1297 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1298 * and set turn on power at the same time, so set the voltage first.
1299 */
11a2f1b7 1300 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1301 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1302
ae628903 1303 pwr |= SDHCI_POWER_ON;
146ad66e 1304
ae628903 1305 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1306
f0710a55
AH		 1307 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1308 sdhci_runtime_pm_bus_on(host);
1309
557b0697
HW		 1310 /*
1311 * Some controllers need an extra 10ms delay of 10ms before they
1312 * can apply clock after applying power
1313 */
11a2f1b7 1314 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1315 mdelay(10);
ceb6143b
AH		 1316
1317 return power;
146ad66e
PO		 1318}
1319
d129bceb
PO		 1320/*****************************************************************************\
1321 * *
1322 * MMC callbacks *
1323 * *
1324\*****************************************************************************/
1325
1326static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1327{
1328 struct sdhci_host *host;
505a8680 1329 int present;
d129bceb 1330 unsigned long flags;
473b095a 1331 u32 tuning_opcode;
d129bceb
PO		 1332
1333 host = mmc_priv(mmc);
1334
66fd8ad5
AH		 1335 sdhci_runtime_pm_get(host);
1336
d129bceb
PO		 1337 spin_lock_irqsave(&host->lock, flags);
1338
1339 WARN_ON(host->mrq != NULL);
1340
f9134319 1341#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1342 sdhci_activate_led(host);
2f730fec 1343#endif
e89d456f
AW		 1344
1345 /*
1346 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1347 * requests if Auto-CMD12 is enabled.
1348 */
1349 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1350 if (mrq->stop) {
1351 mrq->data->stop = NULL;
1352 mrq->stop = NULL;
1353 }
1354 }
d129bceb
PO		 1355
1356 host->mrq = mrq;
1357
505a8680
SG		 1358 /*
1359 * Firstly check card presence from cd-gpio. The return could
1360 * be one of the following possibilities:
1361 * negative: cd-gpio is not available
1362 * zero: cd-gpio is used, and card is removed
1363 * one: cd-gpio is used, and card is present
1364 */
1365 present = mmc_gpio_get_cd(host->mmc);
1366 if (present < 0) {
1367 /* If polling, assume that the card is always present. */
1368 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1369 present = 1;
1370 else
1371 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1372 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1373 }
1374
68d1fb7e 1375 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1376 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1377 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1378 } else {
1379 u32 present_state;
1380
1381 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1382 /*
1383 * Check if the re-tuning timer has already expired and there
1384 * is no on-going data transfer. If so, we need to execute
1385 * tuning procedure before sending command.
1386 */
1387 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1388 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1389 if (mmc->card) {
1390 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1391 tuning_opcode =
1392 mmc->card->type == MMC_TYPE_MMC ?
1393 MMC_SEND_TUNING_BLOCK_HS200 :
1394 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1395
1396 /* Here we need to set the host->mrq to NULL,
1397 * in case the pending finish_tasklet
1398 * finishes it incorrectly.
1399 */
1400 host->mrq = NULL;
1401
14efd957
CB		 1402 spin_unlock_irqrestore(&host->lock, flags);
1403 sdhci_execute_tuning(mmc, tuning_opcode);
1404 spin_lock_irqsave(&host->lock, flags);
1405
1406 /* Restore original mmc_request structure */
1407 host->mrq = mrq;
1408 }
cf2b5eea
AN		 1409 }
1410
8edf6371 1411 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1412 sdhci_send_command(host, mrq->sbc);
1413 else
1414 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1415 }
d129bceb 1416
5f25a66f 1417 mmiowb();
d129bceb
PO		 1418 spin_unlock_irqrestore(&host->lock, flags);
1419}
1420
2317f56c
RK		 1421void sdhci_set_bus_width(struct sdhci_host *host, int width)
1422{
1423 u8 ctrl;
1424
1425 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1426 if (width == MMC_BUS_WIDTH_8) {
1427 ctrl &= ~SDHCI_CTRL_4BITBUS;
1428 if (host->version >= SDHCI_SPEC_300)
1429 ctrl |= SDHCI_CTRL_8BITBUS;
1430 } else {
1431 if (host->version >= SDHCI_SPEC_300)
1432 ctrl &= ~SDHCI_CTRL_8BITBUS;
1433 if (width == MMC_BUS_WIDTH_4)
1434 ctrl |= SDHCI_CTRL_4BITBUS;
1435 else
1436 ctrl &= ~SDHCI_CTRL_4BITBUS;
1437 }
1438 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1439}
1440EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1441
66fd8ad5 1442static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1443{
d129bceb 1444 unsigned long flags;
ceb6143b 1445 int vdd_bit = -1;
d129bceb
PO		 1446 u8 ctrl;
1447
d129bceb
PO		 1448 spin_lock_irqsave(&host->lock, flags);
1449
ceb6143b
AH		 1450 if (host->flags & SDHCI_DEVICE_DEAD) {
1451 spin_unlock_irqrestore(&host->lock, flags);
1452 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1453 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1454 return;
1455 }
1e72859e 1456
d129bceb
PO		 1457 /*
1458 * Reset the chip on each power off.
1459 * Should clear out any weird states.
1460 */
1461 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1462 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1463 sdhci_reinit(host);
d129bceb
PO		 1464 }
1465
52983382 1466 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1467 (ios->power_mode == MMC_POWER_UP) &&
1468 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1469 sdhci_enable_preset_value(host, false);
1470
d129bceb
PO		 1471 sdhci_set_clock(host, ios->clock);
1472
1473 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1474 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1475 else
ceb6143b
AH		 1476 vdd_bit = sdhci_set_power(host, ios->vdd);
1477
1478 if (host->vmmc && vdd_bit != -1) {
1479 spin_unlock_irqrestore(&host->lock, flags);
1480 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1481 spin_lock_irqsave(&host->lock, flags);
1482 }
d129bceb 1483
643a81ff
PR		 1484 if (host->ops->platform_send_init_74_clocks)
1485 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1486
2317f56c 1487 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1488
15ec4461 1489 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1490
3ab9c8da
PR		 1491 if ((ios->timing == MMC_TIMING_SD_HS ||
1492 ios->timing == MMC_TIMING_MMC_HS)
1493 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1494 ctrl |= SDHCI_CTRL_HISPD;
1495 else
1496 ctrl &= ~SDHCI_CTRL_HISPD;
1497
d6d50a15 1498 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1499 u16 clk, ctrl_2;
49c468fc
AN		 1500
1501 /* In case of UHS-I modes, set High Speed Enable */
069c9f14 1502 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1503 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1504 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1505 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1506 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1507 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1508 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1509
1510 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1511 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1512 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1513 /*
1514 * We only need to set Driver Strength if the
1515 * preset value enable is not set.
1516 */
1517 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1518 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1519 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1520 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1521 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1522
1523 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1524 } else {
1525 /*
1526 * According to SDHC Spec v3.00, if the Preset Value
1527 * Enable in the Host Control 2 register is set, we
1528 * need to reset SD Clock Enable before changing High
1529 * Speed Enable to avoid generating clock gliches.
1530 */
758535c4
AN		 1531
1532 /* Reset SD Clock Enable */
1533 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1534 clk &= ~SDHCI_CLOCK_CARD_EN;
1535 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1536
1537 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1538
1539 /* Re-enable SD Clock */
8213af3b 1540 sdhci_update_clock(host);
d6d50a15 1541 }
49c468fc 1542
49c468fc
AN		 1543
1544 /* Reset SD Clock Enable */
1545 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1546 clk &= ~SDHCI_CLOCK_CARD_EN;
1547 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1548
6322cdd0
PR		 1549 if (host->ops->set_uhs_signaling)
1550 host->ops->set_uhs_signaling(host, ios->timing);
1551 else {
1552 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1553 /* Select Bus Speed Mode for host */
1554 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
59911568
GC		 1555 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1556 (ios->timing == MMC_TIMING_UHS_SDR104))
1557 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
069c9f14 1558 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1559 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1560 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1561 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1562 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1563 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
bb8175a8
SJ		 1564 else if ((ios->timing == MMC_TIMING_UHS_DDR50) ||
1565 (ios->timing == MMC_TIMING_MMC_DDR52))
6322cdd0
PR		 1566 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1567 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1568 }
49c468fc 1569
52983382
KL		 1570 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1571 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1572 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1573 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1574 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1575 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1576 u16 preset;
1577
1578 sdhci_enable_preset_value(host, true);
1579 preset = sdhci_get_preset_value(host);
1580 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1581 >> SDHCI_PRESET_DRV_SHIFT;
1582 }
1583
49c468fc 1584 /* Re-enable SD Clock */
8213af3b 1585 sdhci_update_clock(host);
758535c4
AN		 1586 } else
1587 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1588
b8352260
LD		 1589 /*
1590 * Some (ENE) controllers go apeshit on some ios operation,
1591 * signalling timeout and CRC errors even on CMD0. Resetting
1592 * it on each ios seems to solve the problem.
1593 */
b8c86fc5 1594 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1595 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1596
5f25a66f 1597 mmiowb();
d129bceb
PO		 1598 spin_unlock_irqrestore(&host->lock, flags);
1599}
1600
66fd8ad5
AH		 1601static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1602{
1603 struct sdhci_host *host = mmc_priv(mmc);
1604
1605 sdhci_runtime_pm_get(host);
1606 sdhci_do_set_ios(host, ios);
1607 sdhci_runtime_pm_put(host);
1608}
1609
94144a46
KL		 1610static int sdhci_do_get_cd(struct sdhci_host *host)
1611{
1612 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1613
1614 if (host->flags & SDHCI_DEVICE_DEAD)
1615 return 0;
1616
1617 /* If polling/nonremovable, assume that the card is always present. */
1618 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1619 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1620 return 1;
1621
1622 /* Try slot gpio detect */
1623 if (!IS_ERR_VALUE(gpio_cd))
1624 return !!gpio_cd;
1625
1626 /* Host native card detect */
1627 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1628}
1629
1630static int sdhci_get_cd(struct mmc_host *mmc)
1631{
1632 struct sdhci_host *host = mmc_priv(mmc);
1633 int ret;
1634
1635 sdhci_runtime_pm_get(host);
1636 ret = sdhci_do_get_cd(host);
1637 sdhci_runtime_pm_put(host);
1638 return ret;
1639}
1640
66fd8ad5 1641static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1642{
d129bceb 1643 unsigned long flags;
2dfb579c 1644 int is_readonly;
d129bceb 1645
d129bceb
PO		 1646 spin_lock_irqsave(&host->lock, flags);
1647
1e72859e 1648 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1649 is_readonly = 0;
1650 else if (host->ops->get_ro)
1651 is_readonly = host->ops->get_ro(host);
1e72859e 1652 else
2dfb579c
WS		 1653 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1654 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1655
1656 spin_unlock_irqrestore(&host->lock, flags);
1657
2dfb579c
WS		 1658 /* This quirk needs to be replaced by a callback-function later */
1659 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1660 !is_readonly : is_readonly;
d129bceb
PO		 1661}
1662
82b0e23a
TI		 1663#define SAMPLE_COUNT 5
1664
66fd8ad5 1665static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1666{
82b0e23a
TI		 1667 int i, ro_count;
1668
82b0e23a 1669 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1670 return sdhci_check_ro(host);
82b0e23a
TI		 1671
1672 ro_count = 0;
1673 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1674 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1675 if (++ro_count > SAMPLE_COUNT / 2)
1676 return 1;
1677 }
1678 msleep(30);
1679 }
1680 return 0;
1681}
1682
20758b66
AH		 1683static void sdhci_hw_reset(struct mmc_host *mmc)
1684{
1685 struct sdhci_host *host = mmc_priv(mmc);
1686
1687 if (host->ops && host->ops->hw_reset)
1688 host->ops->hw_reset(host);
1689}
1690
66fd8ad5 1691static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1692{
66fd8ad5
AH		 1693 struct sdhci_host *host = mmc_priv(mmc);
1694 int ret;
f75979b7 1695
66fd8ad5
AH		 1696 sdhci_runtime_pm_get(host);
1697 ret = sdhci_do_get_ro(host);
1698 sdhci_runtime_pm_put(host);
1699 return ret;
1700}
f75979b7 1701
66fd8ad5
AH		 1702static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1703{
be138554 1704 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1705 if (enable)
b537f94c 1706 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1707 else
b537f94c
RK		 1708 host->ier &= ~SDHCI_INT_CARD_INT;
1709
1710 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1711 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1712 mmiowb();
1713 }
66fd8ad5
AH		 1714}
1715
1716static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1717{
1718 struct sdhci_host *host = mmc_priv(mmc);
1719 unsigned long flags;
f75979b7 1720
ef104333
RK		 1721 sdhci_runtime_pm_get(host);
1722
66fd8ad5 1723 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1724 if (enable)
1725 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1726 else
1727 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1728
66fd8ad5 1729 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1730 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1731
1732 sdhci_runtime_pm_put(host);
f75979b7
PO		 1733}
1734
20b92a30 1735static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1736 struct mmc_ios *ios)
f2119df6 1737{
20b92a30 1738 u16 ctrl;
6231f3de 1739 int ret;
f2119df6 1740
20b92a30
KL		 1741 /*
1742 * Signal Voltage Switching is only applicable for Host Controllers
1743 * v3.00 and above.
1744 */
1745 if (host->version < SDHCI_SPEC_300)
1746 return 0;
6231f3de 1747
f2119df6 1748 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1749
21f5998f 1750 switch (ios->signal_voltage) {
20b92a30
KL		 1751 case MMC_SIGNAL_VOLTAGE_330:
1752 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1753 ctrl &= ~SDHCI_CTRL_VDD_180;
1754 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1755
20b92a30
KL		 1756 if (host->vqmmc) {
1757 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1758 if (ret) {
1759 pr_warning("%s: Switching to 3.3V signalling voltage "
1760 " failed\n", mmc_hostname(host->mmc));
1761 return -EIO;
1762 }
1763 }
1764 /* Wait for 5ms */
1765 usleep_range(5000, 5500);
f2119df6 1766
20b92a30
KL		 1767 /* 3.3V regulator output should be stable within 5 ms */
1768 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1769 if (!(ctrl & SDHCI_CTRL_VDD_180))
1770 return 0;
6231f3de 1771
20b92a30
KL		 1772 pr_warning("%s: 3.3V regulator output did not became stable\n",
1773 mmc_hostname(host->mmc));
1774
1775 return -EAGAIN;
1776 case MMC_SIGNAL_VOLTAGE_180:
1777 if (host->vqmmc) {
1778 ret = regulator_set_voltage(host->vqmmc,
1779 1700000, 1950000);
1780 if (ret) {
1781 pr_warning("%s: Switching to 1.8V signalling voltage "
1782 " failed\n", mmc_hostname(host->mmc));
1783 return -EIO;
1784 }
1785 }
6231f3de 1786
6231f3de
PR		 1787 /*
1788 * Enable 1.8V Signal Enable in the Host Control2
1789 * register
1790 */
20b92a30
KL		 1791 ctrl |= SDHCI_CTRL_VDD_180;
1792 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1793
20b92a30
KL		 1794 /* Wait for 5ms */
1795 usleep_range(5000, 5500);
f2119df6 1796
20b92a30
KL		 1797 /* 1.8V regulator output should be stable within 5 ms */
1798 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1799 if (ctrl & SDHCI_CTRL_VDD_180)
1800 return 0;
f2119df6 1801
20b92a30
KL		 1802 pr_warning("%s: 1.8V regulator output did not became stable\n",
1803 mmc_hostname(host->mmc));
f2119df6 1804
20b92a30
KL		 1805 return -EAGAIN;
1806 case MMC_SIGNAL_VOLTAGE_120:
1807 if (host->vqmmc) {
1808 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1809 if (ret) {
1810 pr_warning("%s: Switching to 1.2V signalling voltage "
1811 " failed\n", mmc_hostname(host->mmc));
1812 return -EIO;
f2119df6
AN		 1813 }
1814 }
6231f3de 1815 return 0;
20b92a30 1816 default:
f2119df6
AN		 1817 /* No signal voltage switch required */
1818 return 0;
20b92a30 1819 }
f2119df6
AN		 1820}
1821
66fd8ad5 1822static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1823 struct mmc_ios *ios)
66fd8ad5
AH		 1824{
1825 struct sdhci_host *host = mmc_priv(mmc);
1826 int err;
1827
1828 if (host->version < SDHCI_SPEC_300)
1829 return 0;
1830 sdhci_runtime_pm_get(host);
21f5998f 1831 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1832 sdhci_runtime_pm_put(host);
1833 return err;
1834}
1835
20b92a30
KL		 1836static int sdhci_card_busy(struct mmc_host *mmc)
1837{
1838 struct sdhci_host *host = mmc_priv(mmc);
1839 u32 present_state;
1840
1841 sdhci_runtime_pm_get(host);
1842 /* Check whether DAT[3:0] is 0000 */
1843 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1844 sdhci_runtime_pm_put(host);
1845
1846 return !(present_state & SDHCI_DATA_LVL_MASK);
1847}
1848
069c9f14 1849static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1850{
1851 struct sdhci_host *host;
1852 u16 ctrl;
b513ea25
AN		 1853 int tuning_loop_counter = MAX_TUNING_LOOP;
1854 unsigned long timeout;
1855 int err = 0;
069c9f14 1856 bool requires_tuning_nonuhs = false;
2b35bd83 1857 unsigned long flags;
b513ea25
AN		 1858
1859 host = mmc_priv(mmc);
1860
66fd8ad5 1861 sdhci_runtime_pm_get(host);
2b35bd83 1862 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1863
1864 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1865
1866 /*
069c9f14
G		 1867 * The Host Controller needs tuning only in case of SDR104 mode
1868 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1869 * Capabilities register.
069c9f14
G		 1870 * If the Host Controller supports the HS200 mode then the
1871 * tuning function has to be executed.
b513ea25 1872 */
069c9f14
G		 1873 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1874 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
156e14b1 1875 host->flags & SDHCI_SDR104_NEEDS_TUNING))
069c9f14
G		 1876 requires_tuning_nonuhs = true;
1877
b513ea25 1878 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1879 requires_tuning_nonuhs)
b513ea25
AN		 1880 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1881 else {
2b35bd83 1882 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 1883 sdhci_runtime_pm_put(host);
b513ea25
AN		 1884 return 0;
1885 }
1886
45251812 1887 if (host->ops->platform_execute_tuning) {
2b35bd83 1888 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1889 err = host->ops->platform_execute_tuning(host, opcode);
1890 sdhci_runtime_pm_put(host);
1891 return err;
1892 }
1893
b513ea25
AN		 1894 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1895
1896 /*
1897 * As per the Host Controller spec v3.00, tuning command
1898 * generates Buffer Read Ready interrupt, so enable that.
1899 *
1900 * Note: The spec clearly says that when tuning sequence
1901 * is being performed, the controller does not generate
1902 * interrupts other than Buffer Read Ready interrupt. But
1903 * to make sure we don't hit a controller bug, we _only_
1904 * enable Buffer Read Ready interrupt here.
1905 */
b537f94c
RK		 1906 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1907 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1908
1909 /*
1910 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1911 * of loops reaches 40 times or a timeout of 150ms occurs.
1912 */
1913 timeout = 150;
1914 do {
1915 struct mmc_command cmd = {0};
66fd8ad5 1916 struct mmc_request mrq = {NULL};
b513ea25
AN		 1917
1918 if (!tuning_loop_counter && !timeout)
1919 break;
1920
069c9f14 1921 cmd.opcode = opcode;
b513ea25
AN		 1922 cmd.arg = 0;
1923 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1924 cmd.retries = 0;
1925 cmd.data = NULL;
1926 cmd.error = 0;
1927
1928 mrq.cmd = &cmd;
1929 host->mrq = &mrq;
1930
1931 /*
1932 * In response to CMD19, the card sends 64 bytes of tuning
1933 * block to the Host Controller. So we set the block size
1934 * to 64 here.
1935 */
069c9f14
G		 1936 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1937 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1938 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1939 SDHCI_BLOCK_SIZE);
1940 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1941 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1942 SDHCI_BLOCK_SIZE);
1943 } else {
1944 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1945 SDHCI_BLOCK_SIZE);
1946 }
b513ea25
AN		 1947
1948 /*
1949 * The tuning block is sent by the card to the host controller.
1950 * So we set the TRNS_READ bit in the Transfer Mode register.
1951 * This also takes care of setting DMA Enable and Multi Block
1952 * Select in the same register to 0.
1953 */
1954 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1955
1956 sdhci_send_command(host, &cmd);
1957
1958 host->cmd = NULL;
1959 host->mrq = NULL;
1960
2b35bd83 1961 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1962 /* Wait for Buffer Read Ready interrupt */
1963 wait_event_interruptible_timeout(host->buf_ready_int,
1964 (host->tuning_done == 1),
1965 msecs_to_jiffies(50));
2b35bd83 1966 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1967
1968 if (!host->tuning_done) {
a3c76eb9 1969 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1970 "Buffer Read Ready interrupt during tuning "
1971 "procedure, falling back to fixed sampling "
1972 "clock\n");
1973 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1974 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1975 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1976 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1977
1978 err = -EIO;
1979 goto out;
1980 }
1981
1982 host->tuning_done = 0;
1983
1984 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1985 tuning_loop_counter--;
1986 timeout--;
197160d5
NS		 1987
1988 /* eMMC spec does not require a delay between tuning cycles */
1989 if (opcode == MMC_SEND_TUNING_BLOCK)
1990 mdelay(1);
b513ea25
AN		 1991 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1992
1993 /*
1994 * The Host Driver has exhausted the maximum number of loops allowed,
1995 * so use fixed sampling frequency.
1996 */
1997 if (!tuning_loop_counter || !timeout) {
1998 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1999 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
114f2bf6 2000 err = -EIO;
b513ea25
AN		 2001 } else {
2002 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 2003 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 2004 " failed, falling back to fixed sampling"
2005 " clock\n");
2006 err = -EIO;
2007 }
2008 }
2009
2010out:
cf2b5eea
AN		 2011 /*
2012 * If this is the very first time we are here, we start the retuning
2013 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2014 * flag won't be set, we check this condition before actually starting
2015 * the timer.
2016 */
2017 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2018 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 2019 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 2020 mod_timer(&host->tuning_timer, jiffies +
2021 host->tuning_count * HZ);
2022 /* Tuning mode 1 limits the maximum data length to 4MB */
2023 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2bc02485 2024 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
cf2b5eea
AN		 2025 host->flags &= ~SDHCI_NEEDS_RETUNING;
2026 /* Reload the new initial value for timer */
2bc02485
AS		 2027 mod_timer(&host->tuning_timer, jiffies +
2028 host->tuning_count * HZ);
cf2b5eea
AN		 2029 }
2030
2031 /*
2032 * In case tuning fails, host controllers which support re-tuning can
2033 * try tuning again at a later time, when the re-tuning timer expires.
2034 * So for these controllers, we return 0. Since there might be other
2035 * controllers who do not have this capability, we return error for
973905fe
AL		 2036 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2037 * a retuning timer to do the retuning for the card.
cf2b5eea 2038 */
973905fe 2039 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2040 err = 0;
2041
b537f94c
RK		 2042 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2043 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2b35bd83 2044 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2045 sdhci_runtime_pm_put(host);
b513ea25
AN		 2046
2047 return err;
2048}
2049
52983382
KL		 2050
2051static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2052{
4d55c5a1 2053 u16 ctrl;
4d55c5a1 2054
4d55c5a1
AN		 2055 /* Host Controller v3.00 defines preset value registers */
2056 if (host->version < SDHCI_SPEC_300)
2057 return;
2058
4d55c5a1
AN		 2059 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2060
2061 /*
2062 * We only enable or disable Preset Value if they are not already
2063 * enabled or disabled respectively. Otherwise, we bail out.
2064 */
2065 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2066 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2067 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2068 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 2069 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2070 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2071 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2072 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1 2073 }
66fd8ad5
AH		 2074}
2075
71e69211 2076static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2077{
71e69211 2078 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2079 unsigned long flags;
2080
722e1280
CD		 2081 /* First check if client has provided their own card event */
2082 if (host->ops->card_event)
2083 host->ops->card_event(host);
2084
d129bceb
PO		 2085 spin_lock_irqsave(&host->lock, flags);
2086
66fd8ad5 2087 /* Check host->mrq first in case we are runtime suspended */
9668d765 2088 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2089 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2090 mmc_hostname(host->mmc));
a3c76eb9 2091 pr_err("%s: Resetting controller.\n",
66fd8ad5 2092 mmc_hostname(host->mmc));
d129bceb 2093
03231f9b
RK		 2094 sdhci_do_reset(host, SDHCI_RESET_CMD);
2095 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2096
66fd8ad5
AH		 2097 host->mrq->cmd->error = -ENOMEDIUM;
2098 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2099 }
2100
2101 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2102}
2103
2104static const struct mmc_host_ops sdhci_ops = {
2105 .request = sdhci_request,
2106 .set_ios = sdhci_set_ios,
94144a46 2107 .get_cd = sdhci_get_cd,
71e69211
GL		 2108 .get_ro = sdhci_get_ro,
2109 .hw_reset = sdhci_hw_reset,
2110 .enable_sdio_irq = sdhci_enable_sdio_irq,
2111 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2112 .execute_tuning = sdhci_execute_tuning,
71e69211 2113 .card_event = sdhci_card_event,
20b92a30 2114 .card_busy = sdhci_card_busy,
71e69211
GL		 2115};
2116
2117/*****************************************************************************\
2118 * *
2119 * Tasklets *
2120 * *
2121\*****************************************************************************/
2122
d129bceb
PO		 2123static void sdhci_tasklet_finish(unsigned long param)
2124{
2125 struct sdhci_host *host;
2126 unsigned long flags;
2127 struct mmc_request *mrq;
2128
2129 host = (struct sdhci_host*)param;
2130
66fd8ad5
AH		 2131 spin_lock_irqsave(&host->lock, flags);
2132
0c9c99a7
CB		 2133 /*
2134 * If this tasklet gets rescheduled while running, it will
2135 * be run again afterwards but without any active request.
2136 */
66fd8ad5
AH		 2137 if (!host->mrq) {
2138 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2139 return;
66fd8ad5 2140 }
d129bceb
PO		 2141
2142 del_timer(&host->timer);
2143
2144 mrq = host->mrq;
2145
d129bceb
PO		 2146 /*
2147 * The controller needs a reset of internal state machines
2148 * upon error conditions.
2149 */
1e72859e 2150 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2151 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2152 (mrq->data && (mrq->data->error ||
2153 (mrq->data->stop && mrq->data->stop->error))) ||
2154 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2155
2156 /* Some controllers need this kick or reset won't work here */
8213af3b 2157 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2158 /* This is to force an update */
8213af3b 2159 sdhci_update_clock(host);
645289dc
PO		 2160
2161 /* Spec says we should do both at the same time, but Ricoh
2162 controllers do not like that. */
03231f9b
RK		 2163 sdhci_do_reset(host, SDHCI_RESET_CMD);
2164 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2165 }
2166
2167 host->mrq = NULL;
2168 host->cmd = NULL;
2169 host->data = NULL;
2170
f9134319 2171#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2172 sdhci_deactivate_led(host);
2f730fec 2173#endif
d129bceb 2174
5f25a66f 2175 mmiowb();
d129bceb
PO		 2176 spin_unlock_irqrestore(&host->lock, flags);
2177
2178 mmc_request_done(host->mmc, mrq);
66fd8ad5 2179 sdhci_runtime_pm_put(host);
d129bceb
PO		 2180}
2181
2182static void sdhci_timeout_timer(unsigned long data)
2183{
2184 struct sdhci_host *host;
2185 unsigned long flags;
2186
2187 host = (struct sdhci_host*)data;
2188
2189 spin_lock_irqsave(&host->lock, flags);
2190
2191 if (host->mrq) {
a3c76eb9 2192 pr_err("%s: Timeout waiting for hardware "
acf1da45 2193 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2194 sdhci_dumpregs(host);
2195
2196 if (host->data) {
17b0429d 2197 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2198 sdhci_finish_data(host);
2199 } else {
2200 if (host->cmd)
17b0429d 2201 host->cmd->error = -ETIMEDOUT;
d129bceb 2202 else
17b0429d 2203 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2204
2205 tasklet_schedule(&host->finish_tasklet);
2206 }
2207 }
2208
5f25a66f 2209 mmiowb();
d129bceb
PO		 2210 spin_unlock_irqrestore(&host->lock, flags);
2211}
2212
cf2b5eea
AN		 2213static void sdhci_tuning_timer(unsigned long data)
2214{
2215 struct sdhci_host *host;
2216 unsigned long flags;
2217
2218 host = (struct sdhci_host *)data;
2219
2220 spin_lock_irqsave(&host->lock, flags);
2221
2222 host->flags |= SDHCI_NEEDS_RETUNING;
2223
2224 spin_unlock_irqrestore(&host->lock, flags);
2225}
2226
d129bceb
PO		 2227/*****************************************************************************\
2228 * *
2229 * Interrupt handling *
2230 * *
2231\*****************************************************************************/
2232
2233static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2234{
2235 BUG_ON(intmask == 0);
2236
2237 if (!host->cmd) {
a3c76eb9 2238 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2239 "though no command operation was in progress.\n",
2240 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2241 sdhci_dumpregs(host);
2242 return;
2243 }
2244
43b58b36 2245 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2246 host->cmd->error = -ETIMEDOUT;
2247 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2248 SDHCI_INT_INDEX))
2249 host->cmd->error = -EILSEQ;
43b58b36 2250
e809517f 2251 if (host->cmd->error) {
d129bceb 2252 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2253 return;
2254 }
2255
2256 /*
2257 * The host can send and interrupt when the busy state has
2258 * ended, allowing us to wait without wasting CPU cycles.
2259 * Unfortunately this is overloaded on the "data complete"
2260 * interrupt, so we need to take some care when handling
2261 * it.
2262 *
2263 * Note: The 1.0 specification is a bit ambiguous about this
2264 * feature so there might be some problems with older
2265 * controllers.
2266 */
2267 if (host->cmd->flags & MMC_RSP_BUSY) {
2268 if (host->cmd->data)
2269 DBG("Cannot wait for busy signal when also "
2270 "doing a data transfer");
f945405c 2271 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2272 return;
f945405c
BD		 2273
2274 /* The controller does not support the end-of-busy IRQ,
2275 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2276 }
2277
2278 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2279 sdhci_finish_command(host);
d129bceb
PO		 2280}
2281
0957c333 2282#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2283static void sdhci_show_adma_error(struct sdhci_host *host)
2284{
2285 const char *name = mmc_hostname(host->mmc);
2286 u8 *desc = host->adma_desc;
2287 __le32 *dma;
2288 __le16 *len;
2289 u8 attr;
2290
2291 sdhci_dumpregs(host);
2292
2293 while (true) {
2294 dma = (__le32 *)(desc + 4);
2295 len = (__le16 *)(desc + 2);
2296 attr = *desc;
2297
2298 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2299 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2300
2301 desc += 8;
2302
2303 if (attr & 2)
2304 break;
2305 }
2306}
2307#else
2308static void sdhci_show_adma_error(struct sdhci_host *host) { }
2309#endif
2310
d129bceb
PO		 2311static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2312{
069c9f14 2313 u32 command;
d129bceb
PO		 2314 BUG_ON(intmask == 0);
2315
b513ea25
AN		 2316 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2317 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2318 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2319 if (command == MMC_SEND_TUNING_BLOCK ||
2320 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2321 host->tuning_done = 1;
2322 wake_up(&host->buf_ready_int);
2323 return;
2324 }
2325 }
2326
d129bceb
PO		 2327 if (!host->data) {
2328 /*
e809517f
PO		 2329 * The "data complete" interrupt is also used to
2330 * indicate that a busy state has ended. See comment
2331 * above in sdhci_cmd_irq().
d129bceb 2332 */
e809517f
PO		 2333 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2334 if (intmask & SDHCI_INT_DATA_END) {
2335 sdhci_finish_command(host);
2336 return;
2337 }
2338 }
d129bceb 2339
a3c76eb9 2340 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2341 "though no data operation was in progress.\n",
2342 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2343 sdhci_dumpregs(host);
2344
2345 return;
2346 }
2347
2348 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2349 host->data->error = -ETIMEDOUT;
22113efd
AL		 2350 else if (intmask & SDHCI_INT_DATA_END_BIT)
2351 host->data->error = -EILSEQ;
2352 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2353 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2354 != MMC_BUS_TEST_R)
17b0429d 2355 host->data->error = -EILSEQ;
6882a8c0 2356 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2357 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2358 sdhci_show_adma_error(host);
2134a922 2359 host->data->error = -EIO;
a4071fbb
HZ		 2360 if (host->ops->adma_workaround)
2361 host->ops->adma_workaround(host, intmask);
6882a8c0 2362 }
d129bceb 2363
17b0429d 2364 if (host->data->error)
d129bceb
PO		 2365 sdhci_finish_data(host);
2366 else {
a406f5a3 2367 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2368 sdhci_transfer_pio(host);
2369
6ba736a1
PO		 2370 /*
2371 * We currently don't do anything fancy with DMA
2372 * boundaries, but as we can't disable the feature
2373 * we need to at least restart the transfer.
f6a03cbf
MV		 2374 *
2375 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2376 * should return a valid address to continue from, but as
2377 * some controllers are faulty, don't trust them.
6ba736a1 2378 */
f6a03cbf
MV		 2379 if (intmask & SDHCI_INT_DMA_END) {
2380 u32 dmastart, dmanow;
2381 dmastart = sg_dma_address(host->data->sg);
2382 dmanow = dmastart + host->data->bytes_xfered;
2383 /*
2384 * Force update to the next DMA block boundary.
2385 */
2386 dmanow = (dmanow &
2387 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2388 SDHCI_DEFAULT_BOUNDARY_SIZE;
2389 host->data->bytes_xfered = dmanow - dmastart;
2390 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2391 " next 0x%08x\n",
2392 mmc_hostname(host->mmc), dmastart,
2393 host->data->bytes_xfered, dmanow);
2394 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2395 }
6ba736a1 2396
e538fbe8
PO		 2397 if (intmask & SDHCI_INT_DATA_END) {
2398 if (host->cmd) {
2399 /*
2400 * Data managed to finish before the
2401 * command completed. Make sure we do
2402 * things in the proper order.
2403 */
2404 host->data_early = 1;
2405 } else {
2406 sdhci_finish_data(host);
2407 }
2408 }
d129bceb
PO		 2409 }
2410}
2411
7d12e780 2412static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2413{
781e989c 2414 irqreturn_t result = IRQ_NONE;
66fd8ad5 2415 struct sdhci_host *host = dev_id;
41005003 2416 u32 intmask, mask, unexpected = 0;
781e989c 2417 int max_loops = 16;
d129bceb
PO		 2418
2419 spin_lock(&host->lock);
2420
be138554 2421 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2422 spin_unlock(&host->lock);
655bca76 2423 return IRQ_NONE;
66fd8ad5
AH		 2424 }
2425
4e4141a5 2426 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2427 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2428 result = IRQ_NONE;
2429 goto out;
2430 }
2431
41005003
RK		 2432 do {
2433 /* Clear selected interrupts. */
2434 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2435 SDHCI_INT_BUS_POWER);
2436 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2437
41005003
RK		 2438 DBG("*** %s got interrupt: 0x%08x\n",
2439 mmc_hostname(host->mmc), intmask);
d129bceb 2440
41005003
RK		 2441 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2442 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2443 SDHCI_CARD_PRESENT;
d129bceb 2444
41005003
RK		 2445 /*
2446 * There is a observation on i.mx esdhc. INSERT
2447 * bit will be immediately set again when it gets
2448 * cleared, if a card is inserted. We have to mask
2449 * the irq to prevent interrupt storm which will
2450 * freeze the system. And the REMOVE gets the
2451 * same situation.
2452 *
2453 * More testing are needed here to ensure it works
2454 * for other platforms though.
2455 */
b537f94c
RK		 2456 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2457 SDHCI_INT_CARD_REMOVE);
2458 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2459 SDHCI_INT_CARD_INSERT;
2460 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2461 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2462
2463 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2464 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2465
2466 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2467 SDHCI_INT_CARD_REMOVE);
2468 result = IRQ_WAKE_THREAD;
41005003 2469 }
d129bceb 2470
41005003
RK		 2471 if (intmask & SDHCI_INT_CMD_MASK)
2472 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
964f9ce2 2473
41005003
RK		 2474 if (intmask & SDHCI_INT_DATA_MASK)
2475 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2476
41005003
RK		 2477 if (intmask & SDHCI_INT_BUS_POWER)
2478 pr_err("%s: Card is consuming too much power!\n",
2479 mmc_hostname(host->mmc));
3192a28f 2480
781e989c
RK		 2481 if (intmask & SDHCI_INT_CARD_INT) {
2482 sdhci_enable_sdio_irq_nolock(host, false);
2483 host->thread_isr |= SDHCI_INT_CARD_INT;
2484 result = IRQ_WAKE_THREAD;
2485 }
f75979b7 2486
41005003
RK		 2487 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2488 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2489 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2490 SDHCI_INT_CARD_INT);
f75979b7 2491
41005003
RK		 2492 if (intmask) {
2493 unexpected |= intmask;
2494 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2495 }
d129bceb 2496
781e989c
RK		 2497 if (result == IRQ_NONE)
2498 result = IRQ_HANDLED;
d129bceb 2499
41005003 2500 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2501 } while (intmask && --max_loops);
d129bceb
PO		 2502out:
2503 spin_unlock(&host->lock);
2504
6379b237
AS		 2505 if (unexpected) {
2506 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2507 mmc_hostname(host->mmc), unexpected);
2508 sdhci_dumpregs(host);
2509 }
f75979b7 2510
d129bceb
PO		 2511 return result;
2512}
2513
781e989c
RK		 2514static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2515{
2516 struct sdhci_host *host = dev_id;
2517 unsigned long flags;
2518 u32 isr;
2519
2520 spin_lock_irqsave(&host->lock, flags);
2521 isr = host->thread_isr;
2522 host->thread_isr = 0;
2523 spin_unlock_irqrestore(&host->lock, flags);
2524
3560db8e
RK		 2525 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2526 sdhci_card_event(host->mmc);
2527 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2528 }
2529
781e989c
RK		 2530 if (isr & SDHCI_INT_CARD_INT) {
2531 sdio_run_irqs(host->mmc);
2532
2533 spin_lock_irqsave(&host->lock, flags);
2534 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2535 sdhci_enable_sdio_irq_nolock(host, true);
2536 spin_unlock_irqrestore(&host->lock, flags);
2537 }
2538
2539 return isr ? IRQ_HANDLED : IRQ_NONE;
2540}
2541
d129bceb
PO		 2542/*****************************************************************************\
2543 * *
2544 * Suspend/resume *
2545 * *
2546\*****************************************************************************/
2547
2548#ifdef CONFIG_PM
ad080d79
KL		 2549void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2550{
2551 u8 val;
2552 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2553 | SDHCI_WAKE_ON_INT;
2554
2555 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2556 val |= mask ;
2557 /* Avoid fake wake up */
2558 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2559 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2560 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2561}
2562EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2563
2564void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2565{
2566 u8 val;
2567 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2568 | SDHCI_WAKE_ON_INT;
2569
2570 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2571 val &= ~mask;
2572 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2573}
2574EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2575
29495aa0 2576int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2577{
a1b13b4e
CB		 2578 if (host->ops->platform_suspend)
2579 host->ops->platform_suspend(host);
2580
7260cf5e
AV		 2581 sdhci_disable_card_detection(host);
2582
cf2b5eea 2583 /* Disable tuning since we are suspending */
973905fe 2584 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2585 del_timer_sync(&host->tuning_timer);
cf2b5eea 2586 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2587 }
2588
ad080d79 2589 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2590 host->ier = 0;
2591 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2592 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2593 free_irq(host->irq, host);
2594 } else {
2595 sdhci_enable_irq_wakeups(host);
2596 enable_irq_wake(host->irq);
2597 }
4ee14ec6 2598 return 0;
d129bceb
PO		 2599}
2600
b8c86fc5 2601EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2602
b8c86fc5
PO		 2603int sdhci_resume_host(struct sdhci_host *host)
2604{
4ee14ec6 2605 int ret = 0;
d129bceb 2606
a13abc7b 2607 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2608 if (host->ops->enable_dma)
2609 host->ops->enable_dma(host);
2610 }
d129bceb 2611
ad080d79 2612 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2613 ret = request_threaded_irq(host->irq, sdhci_irq,
2614 sdhci_thread_irq, IRQF_SHARED,
2615 mmc_hostname(host->mmc), host);
ad080d79
KL		 2616 if (ret)
2617 return ret;
2618 } else {
2619 sdhci_disable_irq_wakeups(host);
2620 disable_irq_wake(host->irq);
2621 }
d129bceb 2622
6308d290
AH		 2623 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2624 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2625 /* Card keeps power but host controller does not */
2626 sdhci_init(host, 0);
2627 host->pwr = 0;
2628 host->clock = 0;
2629 sdhci_do_set_ios(host, &host->mmc->ios);
2630 } else {
2631 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2632 mmiowb();
2633 }
b8c86fc5 2634
7260cf5e
AV		 2635 sdhci_enable_card_detection(host);
2636
a1b13b4e
CB		 2637 if (host->ops->platform_resume)
2638 host->ops->platform_resume(host);
2639
cf2b5eea 2640 /* Set the re-tuning expiration flag */
973905fe 2641 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2642 host->flags |= SDHCI_NEEDS_RETUNING;
2643
2f4cbb3d 2644 return ret;
d129bceb
PO		 2645}
2646
b8c86fc5 2647EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2648#endif /* CONFIG_PM */
2649
66fd8ad5
AH		 2650#ifdef CONFIG_PM_RUNTIME
2651
2652static int sdhci_runtime_pm_get(struct sdhci_host *host)
2653{
2654 return pm_runtime_get_sync(host->mmc->parent);
2655}
2656
2657static int sdhci_runtime_pm_put(struct sdhci_host *host)
2658{
2659 pm_runtime_mark_last_busy(host->mmc->parent);
2660 return pm_runtime_put_autosuspend(host->mmc->parent);
2661}
2662
f0710a55
AH		 2663static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2664{
2665 if (host->runtime_suspended || host->bus_on)
2666 return;
2667 host->bus_on = true;
2668 pm_runtime_get_noresume(host->mmc->parent);
2669}
2670
2671static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2672{
2673 if (host->runtime_suspended || !host->bus_on)
2674 return;
2675 host->bus_on = false;
2676 pm_runtime_put_noidle(host->mmc->parent);
2677}
2678
66fd8ad5
AH		 2679int sdhci_runtime_suspend_host(struct sdhci_host *host)
2680{
2681 unsigned long flags;
2682 int ret = 0;
2683
2684 /* Disable tuning since we are suspending */
973905fe 2685 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2686 del_timer_sync(&host->tuning_timer);
2687 host->flags &= ~SDHCI_NEEDS_RETUNING;
2688 }
2689
2690 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2691 host->ier &= SDHCI_INT_CARD_INT;
2692 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2693 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2694 spin_unlock_irqrestore(&host->lock, flags);
2695
781e989c 2696 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2697
2698 spin_lock_irqsave(&host->lock, flags);
2699 host->runtime_suspended = true;
2700 spin_unlock_irqrestore(&host->lock, flags);
2701
2702 return ret;
2703}
2704EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2705
2706int sdhci_runtime_resume_host(struct sdhci_host *host)
2707{
2708 unsigned long flags;
2709 int ret = 0, host_flags = host->flags;
2710
2711 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2712 if (host->ops->enable_dma)
2713 host->ops->enable_dma(host);
2714 }
2715
2716 sdhci_init(host, 0);
2717
2718 /* Force clock and power re-program */
2719 host->pwr = 0;
2720 host->clock = 0;
2721 sdhci_do_set_ios(host, &host->mmc->ios);
2722
2723 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2724 if ((host_flags & SDHCI_PV_ENABLED) &&
2725 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2726 spin_lock_irqsave(&host->lock, flags);
2727 sdhci_enable_preset_value(host, true);
2728 spin_unlock_irqrestore(&host->lock, flags);
2729 }
66fd8ad5
AH		 2730
2731 /* Set the re-tuning expiration flag */
973905fe 2732 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2733 host->flags |= SDHCI_NEEDS_RETUNING;
2734
2735 spin_lock_irqsave(&host->lock, flags);
2736
2737 host->runtime_suspended = false;
2738
2739 /* Enable SDIO IRQ */
ef104333 2740 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2741 sdhci_enable_sdio_irq_nolock(host, true);
2742
2743 /* Enable Card Detection */
2744 sdhci_enable_card_detection(host);
2745
2746 spin_unlock_irqrestore(&host->lock, flags);
2747
2748 return ret;
2749}
2750EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2751
2752#endif
2753
d129bceb
PO		 2754/*****************************************************************************\
2755 * *
b8c86fc5 2756 * Device allocation/registration *
d129bceb
PO		 2757 * *
2758\*****************************************************************************/
2759
b8c86fc5
PO		 2760struct sdhci_host *sdhci_alloc_host(struct device *dev,
2761 size_t priv_size)
d129bceb 2762{
d129bceb
PO		 2763 struct mmc_host *mmc;
2764 struct sdhci_host *host;
2765
b8c86fc5 2766 WARN_ON(dev == NULL);
d129bceb 2767
b8c86fc5 2768 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2769 if (!mmc)
b8c86fc5 2770 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2771
2772 host = mmc_priv(mmc);
2773 host->mmc = mmc;
2774
b8c86fc5
PO		 2775 return host;
2776}
8a4da143 2777
b8c86fc5 2778EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2779
b8c86fc5
PO		 2780int sdhci_add_host(struct sdhci_host *host)
2781{
2782 struct mmc_host *mmc;
bd6a8c30 2783 u32 caps[2] = {0, 0};
f2119df6
AN		 2784 u32 max_current_caps;
2785 unsigned int ocr_avail;
b8c86fc5 2786 int ret;
d129bceb 2787
b8c86fc5
PO		 2788 WARN_ON(host == NULL);
2789 if (host == NULL)
2790 return -EINVAL;
d129bceb 2791
b8c86fc5 2792 mmc = host->mmc;
d129bceb 2793
b8c86fc5
PO		 2794 if (debug_quirks)
2795 host->quirks = debug_quirks;
66fd8ad5
AH		 2796 if (debug_quirks2)
2797 host->quirks2 = debug_quirks2;
d129bceb 2798
03231f9b 2799 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2800
4e4141a5 2801 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2802 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2803 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2804 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2805 pr_err("%s: Unknown controller version (%d). "
b69c9058 2806 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2807 host->version);
4a965505
PO		 2808 }
2809
f2119df6 2810 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2811 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2812
bd6a8c30
PR		 2813 if (host->version >= SDHCI_SPEC_300)
2814 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2815 host->caps1 :
2816 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2817
b8c86fc5 2818 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2819 host->flags |= SDHCI_USE_SDMA;
f2119df6 2820 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2821 DBG("Controller doesn't have SDMA capability\n");
67435274 2822 else
a13abc7b 2823 host->flags |= SDHCI_USE_SDMA;
d129bceb 2824
b8c86fc5 2825 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2826 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2827 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2828 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2829 }
2830
f2119df6
AN		 2831 if ((host->version >= SDHCI_SPEC_200) &&
2832 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2833 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2834
2835 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2836 (host->flags & SDHCI_USE_ADMA)) {
2837 DBG("Disabling ADMA as it is marked broken\n");
2838 host->flags &= ~SDHCI_USE_ADMA;
2839 }
2840
a13abc7b 2841 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2842 if (host->ops->enable_dma) {
2843 if (host->ops->enable_dma(host)) {
a3c76eb9 2844 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2845 "available. Falling back to PIO.\n",
2846 mmc_hostname(mmc));
a13abc7b
RR		 2847 host->flags &=
2848 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2849 }
d129bceb
PO		 2850 }
2851 }
2852
2134a922
PO		 2853 if (host->flags & SDHCI_USE_ADMA) {
2854 /*
2855 * We need to allocate descriptors for all sg entries
2856 * (128) and potentially one alignment transfer for
2857 * each of those entries.
2858 */
2859 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2860 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2861 if (!host->adma_desc || !host->align_buffer) {
2862 kfree(host->adma_desc);
2863 kfree(host->align_buffer);
a3c76eb9 2864 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2865 "buffers. Falling back to standard DMA.\n",
2866 mmc_hostname(mmc));
2867 host->flags &= ~SDHCI_USE_ADMA;
2868 }
2869 }
2870
7659150c
PO		 2871 /*
2872 * If we use DMA, then it's up to the caller to set the DMA
2873 * mask, but PIO does not need the hw shim so we set a new
2874 * mask here in that case.
2875 */
a13abc7b 2876 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2877 host->dma_mask = DMA_BIT_MASK(64);
2878 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2879 }
d129bceb 2880
c4687d5f 2881 if (host->version >= SDHCI_SPEC_300)
f2119df6 2882 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2883 >> SDHCI_CLOCK_BASE_SHIFT;
2884 else
f2119df6 2885 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2886 >> SDHCI_CLOCK_BASE_SHIFT;
2887
4240ff0a 2888 host->max_clk *= 1000000;
f27f47ef
AV		 2889 if (host->max_clk == 0 || host->quirks &
2890 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2891 if (!host->ops->get_max_clock) {
a3c76eb9 2892 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2893 "frequency.\n", mmc_hostname(mmc));
2894 return -ENODEV;
2895 }
2896 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2897 }
d129bceb 2898
c3ed3877
AN		 2899 /*
2900 * In case of Host Controller v3.00, find out whether clock
2901 * multiplier is supported.
2902 */
2903 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2904 SDHCI_CLOCK_MUL_SHIFT;
2905
2906 /*
2907 * In case the value in Clock Multiplier is 0, then programmable
2908 * clock mode is not supported, otherwise the actual clock
2909 * multiplier is one more than the value of Clock Multiplier
2910 * in the Capabilities Register.
2911 */
2912 if (host->clk_mul)
2913 host->clk_mul += 1;
2914
d129bceb
PO		 2915 /*
2916 * Set host parameters.
2917 */
2918 mmc->ops = &sdhci_ops;
c3ed3877 2919 mmc->f_max = host->max_clk;
ce5f036b 2920 if (host->ops->get_min_clock)
a9e58f25 2921 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2922 else if (host->version >= SDHCI_SPEC_300) {
2923 if (host->clk_mul) {
2924 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2925 mmc->f_max = host->max_clk * host->clk_mul;
2926 } else
2927 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2928 } else
0397526d 2929 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2930
272308ca
AS		 2931 host->timeout_clk =
2932 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2933 if (host->timeout_clk == 0) {
2934 if (host->ops->get_timeout_clock) {
2935 host->timeout_clk = host->ops->get_timeout_clock(host);
2936 } else if (!(host->quirks &
2937 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2938 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2939 "frequency.\n", mmc_hostname(mmc));
2940 return -ENODEV;
2941 }
2942 }
2943 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2944 host->timeout_clk *= 1000;
2945
2946 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2947 host->timeout_clk = mmc->f_max / 1000;
272308ca 2948
68eb80e0 2949 mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
58d1246d 2950
e89d456f 2951 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 2952 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 2953
2954 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2955 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2956
8edf6371 2957 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2958 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2959 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2960 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2961 host->flags |= SDHCI_AUTO_CMD23;
2962 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2963 } else {
2964 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2965 }
2966
15ec4461
PR		 2967 /*
2968 * A controller may support 8-bit width, but the board itself
2969 * might not have the pins brought out. Boards that support
2970 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2971 * their platform code before calling sdhci_add_host(), and we
2972 * won't assume 8-bit width for hosts without that CAP.
2973 */
5fe23c7f 2974 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2975 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2976
63ef5d8c
JH		 2977 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2978 mmc->caps &= ~MMC_CAP_CMD23;
2979
f2119df6 2980 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2981 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2982
176d1ed4 2983 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2984 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2985 mmc->caps |= MMC_CAP_NEEDS_POLL;
2986
6231f3de 2987 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
462849aa 2988 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2989 if (IS_ERR_OR_NULL(host->vqmmc)) {
2990 if (PTR_ERR(host->vqmmc) < 0) {
2991 pr_info("%s: no vqmmc regulator found\n",
2992 mmc_hostname(mmc));
2993 host->vqmmc = NULL;
2994 }
8363c374 2995 } else {
a3361aba 2996 ret = regulator_enable(host->vqmmc);
cec2e216
KL		 2997 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2998 1950000))
8363c374
KL		 2999 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3000 SDHCI_SUPPORT_SDR50 |
3001 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3002 if (ret) {
3003 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3004 mmc_hostname(mmc), ret);
3005 host->vqmmc = NULL;
3006 }
8363c374 3007 }
6231f3de 3008
6a66180a
DD		 3009 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3010 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3011 SDHCI_SUPPORT_DDR50);
3012
4188bba0
AC		 3013 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3014 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3015 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3016 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3017
3018 /* SDR104 supports also implies SDR50 support */
156e14b1 3019 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3020 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3021 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3022 * field can be promoted to support HS200.
3023 */
13868bf2
DC		 3024 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3025 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3026 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3027 mmc->caps |= MMC_CAP_UHS_SDR50;
3028
9107ebbf
MC		 3029 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3030 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3031 mmc->caps |= MMC_CAP_UHS_DDR50;
3032
069c9f14 3033 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3034 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3035 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3036
156e14b1 3037 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3038 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3039 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3040
d6d50a15
AN		 3041 /* Driver Type(s) (A, C, D) supported by the host */
3042 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3043 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3044 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3045 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3046 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3047 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3048
cf2b5eea
AN		 3049 /* Initial value for re-tuning timer count */
3050 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3051 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3052
3053 /*
3054 * In case Re-tuning Timer is not disabled, the actual value of
3055 * re-tuning timer will be 2 ^ (n - 1).
3056 */
3057 if (host->tuning_count)
3058 host->tuning_count = 1 << (host->tuning_count - 1);
3059
3060 /* Re-tuning mode supported by the Host Controller */
3061 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3062 SDHCI_RETUNING_MODE_SHIFT;
3063
8f230f45 3064 ocr_avail = 0;
bad37e1a 3065
462849aa 3066 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
657d5982
KL		 3067 if (IS_ERR_OR_NULL(host->vmmc)) {
3068 if (PTR_ERR(host->vmmc) < 0) {
3069 pr_info("%s: no vmmc regulator found\n",
3070 mmc_hostname(mmc));
3071 host->vmmc = NULL;
3072 }
8363c374 3073 }
bad37e1a 3074
68737043 3075#ifdef CONFIG_REGULATOR
a4f8f257
MS		 3076 /*
3077 * Voltage range check makes sense only if regulator reports
3078 * any voltage value.
3079 */
3080 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
cec2e216
KL		 3081 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3082 3600000);
68737043
PR		 3083 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3084 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 3085 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3086 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 3087 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3088 1950000);
68737043
PR		 3089 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3090 caps[0] &= ~SDHCI_CAN_VDD_180;
3091 }
3092#endif /* CONFIG_REGULATOR */
3093
f2119df6
AN		 3094 /*
3095 * According to SD Host Controller spec v3.00, if the Host System
3096 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3097 * the value is meaningful only if Voltage Support in the Capabilities
3098 * register is set. The actual current value is 4 times the register
3099 * value.
3100 */
3101 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 3102 if (!max_current_caps && host->vmmc) {
3103 u32 curr = regulator_get_current_limit(host->vmmc);
3104 if (curr > 0) {
3105
3106 /* convert to SDHCI_MAX_CURRENT format */
3107 curr = curr/1000; /* convert to mA */
3108 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3109
3110 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3111 max_current_caps =
3112 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3113 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3114 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3115 }
3116 }
f2119df6
AN		 3117
3118 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3119 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3120
55c4665e 3121 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3122 SDHCI_MAX_CURRENT_330_MASK) >>
3123 SDHCI_MAX_CURRENT_330_SHIFT) *
3124 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3125 }
3126 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3127 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3128
55c4665e 3129 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3130 SDHCI_MAX_CURRENT_300_MASK) >>
3131 SDHCI_MAX_CURRENT_300_SHIFT) *
3132 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3133 }
3134 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3135 ocr_avail |= MMC_VDD_165_195;
3136
55c4665e 3137 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3138 SDHCI_MAX_CURRENT_180_MASK) >>
3139 SDHCI_MAX_CURRENT_180_SHIFT) *
3140 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3141 }
3142
c0b887b6
HZ		 3143 if (host->ocr_mask)
3144 ocr_avail = host->ocr_mask;
3145
8f230f45
TI		 3146 mmc->ocr_avail = ocr_avail;
3147 mmc->ocr_avail_sdio = ocr_avail;
3148 if (host->ocr_avail_sdio)
3149 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3150 mmc->ocr_avail_sd = ocr_avail;
3151 if (host->ocr_avail_sd)
3152 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3153 else /* normal SD controllers don't support 1.8V */
3154 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3155 mmc->ocr_avail_mmc = ocr_avail;
3156 if (host->ocr_avail_mmc)
3157 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3158
3159 if (mmc->ocr_avail == 0) {
a3c76eb9 3160 pr_err("%s: Hardware doesn't report any "
b69c9058 3161 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3162 return -ENODEV;
146ad66e
PO		 3163 }
3164
d129bceb
PO		 3165 spin_lock_init(&host->lock);
3166
3167 /*
2134a922
PO		 3168 * Maximum number of segments. Depends on if the hardware
3169 * can do scatter/gather or not.
d129bceb 3170 */
2134a922 3171 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3172 mmc->max_segs = 128;
a13abc7b 3173 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3174 mmc->max_segs = 1;
2134a922 3175 else /* PIO */
a36274e0 3176 mmc->max_segs = 128;
d129bceb
PO		 3177
3178 /*
bab76961 3179 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3180 * size (512KiB).
d129bceb 3181 */
55db890a 3182 mmc->max_req_size = 524288;
d129bceb
PO		 3183
3184 /*
3185 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3186 * of bytes. When doing hardware scatter/gather, each entry cannot
3187 * be larger than 64 KiB though.
d129bceb 3188 */
30652aa3
OJ		 3189 if (host->flags & SDHCI_USE_ADMA) {
3190 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3191 mmc->max_seg_size = 65535;
3192 else
3193 mmc->max_seg_size = 65536;
3194 } else {
2134a922 3195 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3196 }
d129bceb 3197
fe4a3c7a
PO		 3198 /*
3199 * Maximum block size. This varies from controller to controller and
3200 * is specified in the capabilities register.
3201 */
0633f654
AV		 3202 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3203 mmc->max_blk_size = 2;
3204 } else {
f2119df6 3205 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3206 SDHCI_MAX_BLOCK_SHIFT;
3207 if (mmc->max_blk_size >= 3) {
a3c76eb9 3208 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3209 "assuming 512 bytes\n", mmc_hostname(mmc));
3210 mmc->max_blk_size = 0;
3211 }
3212 }
3213
3214 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3215
55db890a
PO		 3216 /*
3217 * Maximum block count.
3218 */
1388eefd 3219 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3220
d129bceb
PO		 3221 /*
3222 * Init tasklets.
3223 */
d129bceb
PO		 3224 tasklet_init(&host->finish_tasklet,
3225 sdhci_tasklet_finish, (unsigned long)host);
3226
e4cad1b5 3227 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3228
cf2b5eea 3229 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3230 init_waitqueue_head(&host->buf_ready_int);
3231
cf2b5eea
AN		 3232 /* Initialize re-tuning timer */
3233 init_timer(&host->tuning_timer);
3234 host->tuning_timer.data = (unsigned long)host;
3235 host->tuning_timer.function = sdhci_tuning_timer;
3236 }
3237
2af502ca
SG		 3238 sdhci_init(host, 0);
3239
781e989c
RK		 3240 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3241 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3242 if (ret) {
3243 pr_err("%s: Failed to request IRQ %d: %d\n",
3244 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3245 goto untasklet;
0fc81ee3 3246 }
d129bceb 3247
d129bceb
PO		 3248#ifdef CONFIG_MMC_DEBUG
3249 sdhci_dumpregs(host);
3250#endif
3251
f9134319 3252#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3253 snprintf(host->led_name, sizeof(host->led_name),
3254 "%s::", mmc_hostname(mmc));
3255 host->led.name = host->led_name;
2f730fec
PO		 3256 host->led.brightness = LED_OFF;
3257 host->led.default_trigger = mmc_hostname(mmc);
3258 host->led.brightness_set = sdhci_led_control;
3259
b8c86fc5 3260 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3261 if (ret) {
3262 pr_err("%s: Failed to register LED device: %d\n",
3263 mmc_hostname(mmc), ret);
2f730fec 3264 goto reset;
0fc81ee3 3265 }
2f730fec
PO		 3266#endif
3267
5f25a66f
PO		 3268 mmiowb();
3269
d129bceb
PO		 3270 mmc_add_host(mmc);
3271
a3c76eb9 3272 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3273 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3274 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3275 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3276
7260cf5e
AV		 3277 sdhci_enable_card_detection(host);
3278
d129bceb
PO		 3279 return 0;
3280
f9134319 3281#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3282reset:
03231f9b 3283 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3284 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3285 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3286 free_irq(host->irq, host);
3287#endif
8ef1a143 3288untasklet:
d129bceb 3289 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3290
3291 return ret;
3292}
3293
b8c86fc5 3294EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3295
1e72859e 3296void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3297{
1e72859e
PO		 3298 unsigned long flags;
3299
3300 if (dead) {
3301 spin_lock_irqsave(&host->lock, flags);
3302
3303 host->flags |= SDHCI_DEVICE_DEAD;
3304
3305 if (host->mrq) {
a3c76eb9 3306 pr_err("%s: Controller removed during "
1e72859e
PO		 3307 " transfer!\n", mmc_hostname(host->mmc));
3308
3309 host->mrq->cmd->error = -ENOMEDIUM;
3310 tasklet_schedule(&host->finish_tasklet);
3311 }
3312
3313 spin_unlock_irqrestore(&host->lock, flags);
3314 }
3315
7260cf5e
AV		 3316 sdhci_disable_card_detection(host);
3317
b8c86fc5 3318 mmc_remove_host(host->mmc);
d129bceb 3319
f9134319 3320#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3321 led_classdev_unregister(&host->led);
3322#endif
3323
1e72859e 3324 if (!dead)
03231f9b 3325 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3326
b537f94c
RK		 3327 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3328 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3329 free_irq(host->irq, host);
3330
3331 del_timer_sync(&host->timer);
3332
d129bceb 3333 tasklet_kill(&host->finish_tasklet);
2134a922 3334
77dcb3f4
PR		 3335 if (host->vmmc) {
3336 regulator_disable(host->vmmc);
9bea3c85 3337 regulator_put(host->vmmc);
77dcb3f4 3338 }
9bea3c85 3339
6231f3de
PR		 3340 if (host->vqmmc) {
3341 regulator_disable(host->vqmmc);
3342 regulator_put(host->vqmmc);
3343 }
3344
2134a922
PO		 3345 kfree(host->adma_desc);
3346 kfree(host->align_buffer);
3347
3348 host->adma_desc = NULL;
3349 host->align_buffer = NULL;
d129bceb
PO		 3350}
3351
b8c86fc5 3352EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3353
b8c86fc5 3354void sdhci_free_host(struct sdhci_host *host)
d129bceb 3355{
b8c86fc5 3356 mmc_free_host(host->mmc);
d129bceb
PO		 3357}
3358
b8c86fc5 3359EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3360
3361/*****************************************************************************\
3362 * *
3363 * Driver init/exit *
3364 * *
3365\*****************************************************************************/
3366
3367static int __init sdhci_drv_init(void)
3368{
a3c76eb9 3369 pr_info(DRIVER_NAME
52fbf9c9 3370 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3371 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3372
b8c86fc5 3373 return 0;
d129bceb
PO		 3374}
3375
3376static void __exit sdhci_drv_exit(void)
3377{
d129bceb
PO		 3378}
3379
3380module_init(sdhci_drv_init);
3381module_exit(sdhci_drv_exit);
3382
df673b22 3383module_param(debug_quirks, uint, 0444);
66fd8ad5 3384module_param(debug_quirks2, uint, 0444);
67435274 3385
32710e8f 3386MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3387MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3388MODULE_LICENSE("GPL");
67435274 3389
df673b22 3390MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3391MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux 6.x block layer and io_uring tree(s)