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sdhci-of: avoid writing reserved bits into host control register
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
11763609 20#include <linux/scatterlist.h>
d129bceb 21
2f730fec
PO		 22#include <linux/leds.h>
23
d129bceb 24#include <linux/mmc/host.h>
d129bceb 25
d129bceb
PO		 26#include "sdhci.h"
27
28#define DRIVER_NAME "sdhci"
d129bceb 29
d129bceb 30#define DBG(f, x...) \
c6563178 31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 32
f9134319
PO		 33#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
34 defined(CONFIG_MMC_SDHCI_MODULE))
35#define SDHCI_USE_LEDS_CLASS
36#endif
37
df673b22 38static unsigned int debug_quirks = 0;
67435274 39
d129bceb
PO		 40static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
41static void sdhci_finish_data(struct sdhci_host *);
42
43static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
44static void sdhci_finish_command(struct sdhci_host *);
45
46static void sdhci_dumpregs(struct sdhci_host *host)
47{
48 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
49
50 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 51 sdhci_readl(host, SDHCI_DMA_ADDRESS),
52 sdhci_readw(host, SDHCI_HOST_VERSION));
d129bceb 53 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 54 sdhci_readw(host, SDHCI_BLOCK_SIZE),
55 sdhci_readw(host, SDHCI_BLOCK_COUNT));
d129bceb 56 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 57 sdhci_readl(host, SDHCI_ARGUMENT),
58 sdhci_readw(host, SDHCI_TRANSFER_MODE));
d129bceb 59 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 60 sdhci_readl(host, SDHCI_PRESENT_STATE),
61 sdhci_readb(host, SDHCI_HOST_CONTROL));
d129bceb 62 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 63 sdhci_readb(host, SDHCI_POWER_CONTROL),
64 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
d129bceb 65 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 66 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
67 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
d129bceb 68 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 69 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
70 sdhci_readl(host, SDHCI_INT_STATUS));
d129bceb 71 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 72 sdhci_readl(host, SDHCI_INT_ENABLE),
73 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
d129bceb 74 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 75 sdhci_readw(host, SDHCI_ACMD12_ERR),
76 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
d129bceb 77 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
4e4141a5
AV		 78 sdhci_readl(host, SDHCI_CAPABILITIES),
79 sdhci_readl(host, SDHCI_MAX_CURRENT));
d129bceb 80
be3f4ae0
BD		 81 if (host->flags & SDHCI_USE_ADMA)
82 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
83 readl(host->ioaddr + SDHCI_ADMA_ERROR),
84 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
85
d129bceb
PO		 86 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
87}
88
89/*****************************************************************************\
90 * *
91 * Low level functions *
92 * *
93\*****************************************************************************/
94
7260cf5e
AV		 95static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
96{
97 u32 ier;
98
99 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
100 ier &= ~clear;
101 ier |= set;
102 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
103 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
104}
105
106static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
107{
108 sdhci_clear_set_irqs(host, 0, irqs);
109}
110
111static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
112{
113 sdhci_clear_set_irqs(host, irqs, 0);
114}
115
116static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
117{
118 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
119
68d1fb7e
AV		 120 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
121 return;
122
7260cf5e
AV		 123 if (enable)
124 sdhci_unmask_irqs(host, irqs);
125 else
126 sdhci_mask_irqs(host, irqs);
127}
128
129static void sdhci_enable_card_detection(struct sdhci_host *host)
130{
131 sdhci_set_card_detection(host, true);
132}
133
134static void sdhci_disable_card_detection(struct sdhci_host *host)
135{
136 sdhci_set_card_detection(host, false);
137}
138
d129bceb
PO		 139static void sdhci_reset(struct sdhci_host *host, u8 mask)
140{
e16514d8 141 unsigned long timeout;
063a9dbb 142 u32 uninitialized_var(ier);
e16514d8 143
b8c86fc5 144 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 145 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 146 SDHCI_CARD_PRESENT))
147 return;
148 }
149
063a9dbb
AV		 150 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
151 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
152
4e4141a5 153 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 154
e16514d8 155 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 156 host->clock = 0;
157
e16514d8
PO		 158 /* Wait max 100 ms */
159 timeout = 100;
160
161 /* hw clears the bit when it's done */
4e4141a5 162 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 163 if (timeout == 0) {
acf1da45 164 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 165 mmc_hostname(host->mmc), (int)mask);
166 sdhci_dumpregs(host);
167 return;
168 }
169 timeout--;
170 mdelay(1);
d129bceb 171 }
063a9dbb
AV		 172
173 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
174 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 175}
176
177static void sdhci_init(struct sdhci_host *host)
178{
d129bceb
PO		 179 sdhci_reset(host, SDHCI_RESET_ALL);
180
7260cf5e
AV		 181 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
182 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 183 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
184 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 185 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
7260cf5e 186}
d129bceb 187
7260cf5e
AV		 188static void sdhci_reinit(struct sdhci_host *host)
189{
190 sdhci_init(host);
191 sdhci_enable_card_detection(host);
d129bceb
PO		 192}
193
194static void sdhci_activate_led(struct sdhci_host *host)
195{
196 u8 ctrl;
197
4e4141a5 198 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 199 ctrl |= SDHCI_CTRL_LED;
4e4141a5 200 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 201}
202
203static void sdhci_deactivate_led(struct sdhci_host *host)
204{
205 u8 ctrl;
206
4e4141a5 207 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 208 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 209 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 210}
211
f9134319 212#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 213static void sdhci_led_control(struct led_classdev *led,
214 enum led_brightness brightness)
215{
216 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
217 unsigned long flags;
218
219 spin_lock_irqsave(&host->lock, flags);
220
221 if (brightness == LED_OFF)
222 sdhci_deactivate_led(host);
223 else
224 sdhci_activate_led(host);
225
226 spin_unlock_irqrestore(&host->lock, flags);
227}
228#endif
229
d129bceb
PO		 230/*****************************************************************************\
231 * *
232 * Core functions *
233 * *
234\*****************************************************************************/
235
a406f5a3 236static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 237{
7659150c
PO		 238 unsigned long flags;
239 size_t blksize, len, chunk;
7244b85b 240 u32 uninitialized_var(scratch);
7659150c 241 u8 *buf;
d129bceb 242
a406f5a3 243 DBG("PIO reading\n");
d129bceb 244
a406f5a3 245 blksize = host->data->blksz;
7659150c 246 chunk = 0;
d129bceb 247
7659150c 248 local_irq_save(flags);
d129bceb 249
a406f5a3 250 while (blksize) {
7659150c
PO		 251 if (!sg_miter_next(&host->sg_miter))
252 BUG();
d129bceb 253
7659150c 254 len = min(host->sg_miter.length, blksize);
d129bceb 255
7659150c
PO		 256 blksize -= len;
257 host->sg_miter.consumed = len;
14d836e7 258
7659150c 259 buf = host->sg_miter.addr;
d129bceb 260
7659150c
PO		 261 while (len) {
262 if (chunk == 0) {
4e4141a5 263 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 264 chunk = 4;
a406f5a3 265 }
7659150c
PO		 266
267 *buf = scratch & 0xFF;
268
269 buf++;
270 scratch >>= 8;
271 chunk--;
272 len--;
d129bceb 273 }
a406f5a3 274 }
7659150c
PO		 275
276 sg_miter_stop(&host->sg_miter);
277
278 local_irq_restore(flags);
a406f5a3 279}
d129bceb 280
a406f5a3
PO		 281static void sdhci_write_block_pio(struct sdhci_host *host)
282{
7659150c
PO		 283 unsigned long flags;
284 size_t blksize, len, chunk;
285 u32 scratch;
286 u8 *buf;
d129bceb 287
a406f5a3
PO		 288 DBG("PIO writing\n");
289
290 blksize = host->data->blksz;
7659150c
PO		 291 chunk = 0;
292 scratch = 0;
d129bceb 293
7659150c 294 local_irq_save(flags);
d129bceb 295
a406f5a3 296 while (blksize) {
7659150c
PO		 297 if (!sg_miter_next(&host->sg_miter))
298 BUG();
a406f5a3 299
7659150c
PO		 300 len = min(host->sg_miter.length, blksize);
301
302 blksize -= len;
303 host->sg_miter.consumed = len;
304
305 buf = host->sg_miter.addr;
d129bceb 306
7659150c
PO		 307 while (len) {
308 scratch |= (u32)*buf << (chunk * 8);
309
310 buf++;
311 chunk++;
312 len--;
313
314 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 315 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 316 chunk = 0;
317 scratch = 0;
d129bceb 318 }
d129bceb
PO		 319 }
320 }
7659150c
PO		 321
322 sg_miter_stop(&host->sg_miter);
323
324 local_irq_restore(flags);
a406f5a3
PO		 325}
326
327static void sdhci_transfer_pio(struct sdhci_host *host)
328{
329 u32 mask;
330
331 BUG_ON(!host->data);
332
7659150c 333 if (host->blocks == 0)
a406f5a3
PO		 334 return;
335
336 if (host->data->flags & MMC_DATA_READ)
337 mask = SDHCI_DATA_AVAILABLE;
338 else
339 mask = SDHCI_SPACE_AVAILABLE;
340
4a3cba32
PO		 341 /*
342 * Some controllers (JMicron JMB38x) mess up the buffer bits
343 * for transfers < 4 bytes. As long as it is just one block,
344 * we can ignore the bits.
345 */
346 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
347 (host->data->blocks == 1))
348 mask = ~0;
349
4e4141a5 350 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 351 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
352 udelay(100);
353
a406f5a3
PO		 354 if (host->data->flags & MMC_DATA_READ)
355 sdhci_read_block_pio(host);
356 else
357 sdhci_write_block_pio(host);
d129bceb 358
7659150c
PO		 359 host->blocks--;
360 if (host->blocks == 0)
a406f5a3 361 break;
a406f5a3 362 }
d129bceb 363
a406f5a3 364 DBG("PIO transfer complete.\n");
d129bceb
PO		 365}
366
2134a922
PO		 367static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
368{
369 local_irq_save(*flags);
370 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
371}
372
373static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
374{
375 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
376 local_irq_restore(*flags);
377}
378
8f1934ce 379static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 380 struct mmc_data *data)
381{
382 int direction;
383
384 u8 *desc;
385 u8 *align;
386 dma_addr_t addr;
387 dma_addr_t align_addr;
388 int len, offset;
389
390 struct scatterlist *sg;
391 int i;
392 char *buffer;
393 unsigned long flags;
394
395 /*
396 * The spec does not specify endianness of descriptor table.
397 * We currently guess that it is LE.
398 */
399
400 if (data->flags & MMC_DATA_READ)
401 direction = DMA_FROM_DEVICE;
402 else
403 direction = DMA_TO_DEVICE;
404
405 /*
406 * The ADMA descriptor table is mapped further down as we
407 * need to fill it with data first.
408 */
409
410 host->align_addr = dma_map_single(mmc_dev(host->mmc),
411 host->align_buffer, 128 * 4, direction);
8d8bb39b 412 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 413 goto fail;
2134a922
PO		 414 BUG_ON(host->align_addr & 0x3);
415
416 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
417 data->sg, data->sg_len, direction);
8f1934ce
PO		 418 if (host->sg_count == 0)
419 goto unmap_align;
2134a922
PO		 420
421 desc = host->adma_desc;
422 align = host->align_buffer;
423
424 align_addr = host->align_addr;
425
426 for_each_sg(data->sg, sg, host->sg_count, i) {
427 addr = sg_dma_address(sg);
428 len = sg_dma_len(sg);
429
430 /*
431 * The SDHCI specification states that ADMA
432 * addresses must be 32-bit aligned. If they
433 * aren't, then we use a bounce buffer for
434 * the (up to three) bytes that screw up the
435 * alignment.
436 */
437 offset = (4 - (addr & 0x3)) & 0x3;
438 if (offset) {
439 if (data->flags & MMC_DATA_WRITE) {
440 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 441 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 442 memcpy(align, buffer, offset);
443 sdhci_kunmap_atomic(buffer, &flags);
444 }
445
446 desc[7] = (align_addr >> 24) & 0xff;
447 desc[6] = (align_addr >> 16) & 0xff;
448 desc[5] = (align_addr >> 8) & 0xff;
449 desc[4] = (align_addr >> 0) & 0xff;
450
451 BUG_ON(offset > 65536);
452
453 desc[3] = (offset >> 8) & 0xff;
454 desc[2] = (offset >> 0) & 0xff;
455
456 desc[1] = 0x00;
457 desc[0] = 0x21; /* tran, valid */
458
459 align += 4;
460 align_addr += 4;
461
462 desc += 8;
463
464 addr += offset;
465 len -= offset;
466 }
467
468 desc[7] = (addr >> 24) & 0xff;
469 desc[6] = (addr >> 16) & 0xff;
470 desc[5] = (addr >> 8) & 0xff;
471 desc[4] = (addr >> 0) & 0xff;
472
473 BUG_ON(len > 65536);
474
475 desc[3] = (len >> 8) & 0xff;
476 desc[2] = (len >> 0) & 0xff;
477
478 desc[1] = 0x00;
479 desc[0] = 0x21; /* tran, valid */
480
481 desc += 8;
482
483 /*
484 * If this triggers then we have a calculation bug
485 * somewhere. :/
486 */
487 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
488 }
489
490 /*
491 * Add a terminating entry.
492 */
493 desc[7] = 0;
494 desc[6] = 0;
495 desc[5] = 0;
496 desc[4] = 0;
497
498 desc[3] = 0;
499 desc[2] = 0;
500
501 desc[1] = 0x00;
502 desc[0] = 0x03; /* nop, end, valid */
503
504 /*
505 * Resync align buffer as we might have changed it.
506 */
507 if (data->flags & MMC_DATA_WRITE) {
508 dma_sync_single_for_device(mmc_dev(host->mmc),
509 host->align_addr, 128 * 4, direction);
510 }
511
512 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
513 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 514 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 515 goto unmap_entries;
2134a922 516 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 517
518 return 0;
519
520unmap_entries:
521 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
522 data->sg_len, direction);
523unmap_align:
524 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
525 128 * 4, direction);
526fail:
527 return -EINVAL;
2134a922
PO		 528}
529
530static void sdhci_adma_table_post(struct sdhci_host *host,
531 struct mmc_data *data)
532{
533 int direction;
534
535 struct scatterlist *sg;
536 int i, size;
537 u8 *align;
538 char *buffer;
539 unsigned long flags;
540
541 if (data->flags & MMC_DATA_READ)
542 direction = DMA_FROM_DEVICE;
543 else
544 direction = DMA_TO_DEVICE;
545
546 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
547 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
548
549 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
550 128 * 4, direction);
551
552 if (data->flags & MMC_DATA_READ) {
553 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
554 data->sg_len, direction);
555
556 align = host->align_buffer;
557
558 for_each_sg(data->sg, sg, host->sg_count, i) {
559 if (sg_dma_address(sg) & 0x3) {
560 size = 4 - (sg_dma_address(sg) & 0x3);
561
562 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 563 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 564 memcpy(buffer, align, size);
565 sdhci_kunmap_atomic(buffer, &flags);
566
567 align += 4;
568 }
569 }
570 }
571
572 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
573 data->sg_len, direction);
574}
575
ee53ab5d 576static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
d129bceb 577{
1c8cde92
PO		 578 u8 count;
579 unsigned target_timeout, current_timeout;
d129bceb 580
ee53ab5d
PO		 581 /*
582 * If the host controller provides us with an incorrect timeout
583 * value, just skip the check and use 0xE. The hardware may take
584 * longer to time out, but that's much better than having a too-short
585 * timeout value.
586 */
11a2f1b7 587 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 588 return 0xE;
e538fbe8 589
1c8cde92
PO		 590 /* timeout in us */
591 target_timeout = data->timeout_ns / 1000 +
592 data->timeout_clks / host->clock;
d129bceb 593
1c8cde92
PO		 594 /*
595 * Figure out needed cycles.
596 * We do this in steps in order to fit inside a 32 bit int.
597 * The first step is the minimum timeout, which will have a
598 * minimum resolution of 6 bits:
599 * (1) 2^13*1000 > 2^22,
600 * (2) host->timeout_clk < 2^16
601 * =>
602 * (1) / (2) > 2^6
603 */
604 count = 0;
605 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
606 while (current_timeout < target_timeout) {
607 count++;
608 current_timeout <<= 1;
609 if (count >= 0xF)
610 break;
611 }
612
613 if (count >= 0xF) {
614 printk(KERN_WARNING "%s: Too large timeout requested!\n",
615 mmc_hostname(host->mmc));
616 count = 0xE;
617 }
618
ee53ab5d
PO		 619 return count;
620}
621
6aa943ab
AV		 622static void sdhci_set_transfer_irqs(struct sdhci_host *host)
623{
624 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
625 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
626
627 if (host->flags & SDHCI_REQ_USE_DMA)
628 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
629 else
630 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
631}
632
ee53ab5d
PO		 633static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
634{
635 u8 count;
2134a922 636 u8 ctrl;
8f1934ce 637 int ret;
ee53ab5d
PO		 638
639 WARN_ON(host->data);
640
641 if (data == NULL)
642 return;
643
644 /* Sanity checks */
645 BUG_ON(data->blksz * data->blocks > 524288);
646 BUG_ON(data->blksz > host->mmc->max_blk_size);
647 BUG_ON(data->blocks > 65535);
648
649 host->data = data;
650 host->data_early = 0;
651
652 count = sdhci_calc_timeout(host, data);
4e4141a5 653 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
d129bceb 654
c9fddbc4
PO		 655 if (host->flags & SDHCI_USE_DMA)
656 host->flags |= SDHCI_REQ_USE_DMA;
657
2134a922
PO		 658 /*
659 * FIXME: This doesn't account for merging when mapping the
660 * scatterlist.
661 */
662 if (host->flags & SDHCI_REQ_USE_DMA) {
663 int broken, i;
664 struct scatterlist *sg;
665
666 broken = 0;
667 if (host->flags & SDHCI_USE_ADMA) {
668 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
669 broken = 1;
670 } else {
671 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
672 broken = 1;
673 }
674
675 if (unlikely(broken)) {
676 for_each_sg(data->sg, sg, data->sg_len, i) {
677 if (sg->length & 0x3) {
678 DBG("Reverting to PIO because of "
679 "transfer size (%d)\n",
680 sg->length);
681 host->flags &= ~SDHCI_REQ_USE_DMA;
682 break;
683 }
684 }
685 }
c9fddbc4
PO		 686 }
687
688 /*
689 * The assumption here being that alignment is the same after
690 * translation to device address space.
691 */
2134a922
PO		 692 if (host->flags & SDHCI_REQ_USE_DMA) {
693 int broken, i;
694 struct scatterlist *sg;
695
696 broken = 0;
697 if (host->flags & SDHCI_USE_ADMA) {
698 /*
699 * As we use 3 byte chunks to work around
700 * alignment problems, we need to check this
701 * quirk.
702 */
703 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
704 broken = 1;
705 } else {
706 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
707 broken = 1;
708 }
709
710 if (unlikely(broken)) {
711 for_each_sg(data->sg, sg, data->sg_len, i) {
712 if (sg->offset & 0x3) {
713 DBG("Reverting to PIO because of "
714 "bad alignment\n");
715 host->flags &= ~SDHCI_REQ_USE_DMA;
716 break;
717 }
718 }
719 }
720 }
721
8f1934ce
PO		 722 if (host->flags & SDHCI_REQ_USE_DMA) {
723 if (host->flags & SDHCI_USE_ADMA) {
724 ret = sdhci_adma_table_pre(host, data);
725 if (ret) {
726 /*
727 * This only happens when someone fed
728 * us an invalid request.
729 */
730 WARN_ON(1);
ebd6d357 731 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 732 } else {
4e4141a5
AV		 733 sdhci_writel(host, host->adma_addr,
734 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 735 }
736 } else {
c8b3e02e 737 int sg_cnt;
8f1934ce 738
c8b3e02e 739 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 740 data->sg, data->sg_len,
741 (data->flags & MMC_DATA_READ) ?
742 DMA_FROM_DEVICE :
743 DMA_TO_DEVICE);
c8b3e02e 744 if (sg_cnt == 0) {
8f1934ce
PO		 745 /*
746 * This only happens when someone fed
747 * us an invalid request.
748 */
749 WARN_ON(1);
ebd6d357 750 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 751 } else {
719a61b4 752 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 753 sdhci_writel(host, sg_dma_address(data->sg),
754 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 755 }
756 }
757 }
758
2134a922
PO		 759 /*
760 * Always adjust the DMA selection as some controllers
761 * (e.g. JMicron) can't do PIO properly when the selection
762 * is ADMA.
763 */
764 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 765 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 766 ctrl &= ~SDHCI_CTRL_DMA_MASK;
767 if ((host->flags & SDHCI_REQ_USE_DMA) &&
768 (host->flags & SDHCI_USE_ADMA))
769 ctrl |= SDHCI_CTRL_ADMA32;
770 else
771 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 772 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 773 }
774
8f1934ce 775 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 776 int flags;
777
778 flags = SG_MITER_ATOMIC;
779 if (host->data->flags & MMC_DATA_READ)
780 flags |= SG_MITER_TO_SG;
781 else
782 flags |= SG_MITER_FROM_SG;
783 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 784 host->blocks = data->blocks;
d129bceb 785 }
c7fa9963 786
6aa943ab
AV		 787 sdhci_set_transfer_irqs(host);
788
bab76961 789 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
4e4141a5
AV		 790 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
791 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 792}
793
794static void sdhci_set_transfer_mode(struct sdhci_host *host,
795 struct mmc_data *data)
796{
797 u16 mode;
798
c7fa9963
PO		 799 if (data == NULL)
800 return;
801
e538fbe8
PO		 802 WARN_ON(!host->data);
803
c7fa9963
PO		 804 mode = SDHCI_TRNS_BLK_CNT_EN;
805 if (data->blocks > 1)
806 mode |= SDHCI_TRNS_MULTI;
807 if (data->flags & MMC_DATA_READ)
808 mode |= SDHCI_TRNS_READ;
c9fddbc4 809 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 810 mode |= SDHCI_TRNS_DMA;
811
4e4141a5 812 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 813}
814
815static void sdhci_finish_data(struct sdhci_host *host)
816{
817 struct mmc_data *data;
d129bceb
PO		 818
819 BUG_ON(!host->data);
820
821 data = host->data;
822 host->data = NULL;
823
c9fddbc4 824 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 825 if (host->flags & SDHCI_USE_ADMA)
826 sdhci_adma_table_post(host, data);
827 else {
828 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
829 data->sg_len, (data->flags & MMC_DATA_READ) ?
830 DMA_FROM_DEVICE : DMA_TO_DEVICE);
831 }
d129bceb
PO		 832 }
833
834 /*
c9b74c5b
PO		 835 * The specification states that the block count register must
836 * be updated, but it does not specify at what point in the
837 * data flow. That makes the register entirely useless to read
838 * back so we have to assume that nothing made it to the card
839 * in the event of an error.
d129bceb 840 */
c9b74c5b
PO		 841 if (data->error)
842 data->bytes_xfered = 0;
d129bceb 843 else
c9b74c5b 844 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 845
d129bceb
PO		 846 if (data->stop) {
847 /*
848 * The controller needs a reset of internal state machines
849 * upon error conditions.
850 */
17b0429d 851 if (data->error) {
d129bceb
PO		 852 sdhci_reset(host, SDHCI_RESET_CMD);
853 sdhci_reset(host, SDHCI_RESET_DATA);
854 }
855
856 sdhci_send_command(host, data->stop);
857 } else
858 tasklet_schedule(&host->finish_tasklet);
859}
860
861static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
862{
863 int flags;
fd2208d7 864 u32 mask;
7cb2c76f 865 unsigned long timeout;
d129bceb
PO		 866
867 WARN_ON(host->cmd);
868
d129bceb 869 /* Wait max 10 ms */
7cb2c76f 870 timeout = 10;
fd2208d7
PO		 871
872 mask = SDHCI_CMD_INHIBIT;
873 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
874 mask |= SDHCI_DATA_INHIBIT;
875
876 /* We shouldn't wait for data inihibit for stop commands, even
877 though they might use busy signaling */
878 if (host->mrq->data && (cmd == host->mrq->data->stop))
879 mask &= ~SDHCI_DATA_INHIBIT;
880
4e4141a5 881 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 882 if (timeout == 0) {
d129bceb 883 printk(KERN_ERR "%s: Controller never released "
acf1da45 884 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 885 sdhci_dumpregs(host);
17b0429d 886 cmd->error = -EIO;
d129bceb
PO		 887 tasklet_schedule(&host->finish_tasklet);
888 return;
889 }
7cb2c76f
PO		 890 timeout--;
891 mdelay(1);
892 }
d129bceb
PO		 893
894 mod_timer(&host->timer, jiffies + 10 * HZ);
895
896 host->cmd = cmd;
897
898 sdhci_prepare_data(host, cmd->data);
899
4e4141a5 900 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 901
c7fa9963
PO		 902 sdhci_set_transfer_mode(host, cmd->data);
903
d129bceb 904 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 905 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 906 mmc_hostname(host->mmc));
17b0429d 907 cmd->error = -EINVAL;
d129bceb
PO		 908 tasklet_schedule(&host->finish_tasklet);
909 return;
910 }
911
912 if (!(cmd->flags & MMC_RSP_PRESENT))
913 flags = SDHCI_CMD_RESP_NONE;
914 else if (cmd->flags & MMC_RSP_136)
915 flags = SDHCI_CMD_RESP_LONG;
916 else if (cmd->flags & MMC_RSP_BUSY)
917 flags = SDHCI_CMD_RESP_SHORT_BUSY;
918 else
919 flags = SDHCI_CMD_RESP_SHORT;
920
921 if (cmd->flags & MMC_RSP_CRC)
922 flags |= SDHCI_CMD_CRC;
923 if (cmd->flags & MMC_RSP_OPCODE)
924 flags |= SDHCI_CMD_INDEX;
925 if (cmd->data)
926 flags |= SDHCI_CMD_DATA;
927
4e4141a5 928 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 929}
930
931static void sdhci_finish_command(struct sdhci_host *host)
932{
933 int i;
934
935 BUG_ON(host->cmd == NULL);
936
937 if (host->cmd->flags & MMC_RSP_PRESENT) {
938 if (host->cmd->flags & MMC_RSP_136) {
939 /* CRC is stripped so we need to do some shifting. */
940 for (i = 0;i < 4;i++) {
4e4141a5 941 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 942 SDHCI_RESPONSE + (3-i)*4) << 8;
943 if (i != 3)
944 host->cmd->resp[i] |=
4e4141a5 945 sdhci_readb(host,
d129bceb
PO		 946 SDHCI_RESPONSE + (3-i)*4-1);
947 }
948 } else {
4e4141a5 949 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 950 }
951 }
952
17b0429d 953 host->cmd->error = 0;
d129bceb 954
e538fbe8
PO		 955 if (host->data && host->data_early)
956 sdhci_finish_data(host);
957
958 if (!host->cmd->data)
d129bceb
PO		 959 tasklet_schedule(&host->finish_tasklet);
960
961 host->cmd = NULL;
962}
963
964static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
965{
966 int div;
967 u16 clk;
7cb2c76f 968 unsigned long timeout;
d129bceb
PO		 969
970 if (clock == host->clock)
971 return;
972
8114634c
AV		 973 if (host->ops->set_clock) {
974 host->ops->set_clock(host, clock);
975 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
976 return;
977 }
978
4e4141a5 979 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 980
981 if (clock == 0)
982 goto out;
983
984 for (div = 1;div < 256;div *= 2) {
985 if ((host->max_clk / div) <= clock)
986 break;
987 }
988 div >>= 1;
989
990 clk = div << SDHCI_DIVIDER_SHIFT;
991 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 992 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 993
994 /* Wait max 10 ms */
7cb2c76f 995 timeout = 10;
4e4141a5 996 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 997 & SDHCI_CLOCK_INT_STABLE)) {
998 if (timeout == 0) {
acf1da45
PO		 999 printk(KERN_ERR "%s: Internal clock never "
1000 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1001 sdhci_dumpregs(host);
1002 return;
1003 }
7cb2c76f
PO		 1004 timeout--;
1005 mdelay(1);
1006 }
d129bceb
PO		 1007
1008 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1009 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1010
1011out:
1012 host->clock = clock;
1013}
1014
146ad66e
PO		 1015static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1016{
1017 u8 pwr;
1018
ae628903
PO		 1019 if (power == (unsigned short)-1)
1020 pwr = 0;
1021 else {
1022 switch (1 << power) {
1023 case MMC_VDD_165_195:
1024 pwr = SDHCI_POWER_180;
1025 break;
1026 case MMC_VDD_29_30:
1027 case MMC_VDD_30_31:
1028 pwr = SDHCI_POWER_300;
1029 break;
1030 case MMC_VDD_32_33:
1031 case MMC_VDD_33_34:
1032 pwr = SDHCI_POWER_330;
1033 break;
1034 default:
1035 BUG();
1036 }
1037 }
1038
1039 if (host->pwr == pwr)
146ad66e
PO		 1040 return;
1041
ae628903
PO		 1042 host->pwr = pwr;
1043
1044 if (pwr == 0) {
4e4141a5 1045 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ae628903 1046 return;
9e9dc5f2
DS		 1047 }
1048
1049 /*
1050 * Spec says that we should clear the power reg before setting
1051 * a new value. Some controllers don't seem to like this though.
1052 */
b8c86fc5 1053 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1054 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1055
e08c1694 1056 /*
c71f6512 1057 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1058 * and set turn on power at the same time, so set the voltage first.
1059 */
11a2f1b7 1060 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1061 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1062
ae628903 1063 pwr |= SDHCI_POWER_ON;
146ad66e 1064
ae628903 1065 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1066
1067 /*
1068 * Some controllers need an extra 10ms delay of 10ms before they
1069 * can apply clock after applying power
1070 */
11a2f1b7 1071 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1072 mdelay(10);
146ad66e
PO		 1073}
1074
d129bceb
PO		 1075/*****************************************************************************\
1076 * *
1077 * MMC callbacks *
1078 * *
1079\*****************************************************************************/
1080
1081static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1082{
1083 struct sdhci_host *host;
68d1fb7e 1084 bool present;
d129bceb
PO		 1085 unsigned long flags;
1086
1087 host = mmc_priv(mmc);
1088
1089 spin_lock_irqsave(&host->lock, flags);
1090
1091 WARN_ON(host->mrq != NULL);
1092
f9134319 1093#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1094 sdhci_activate_led(host);
2f730fec 1095#endif
d129bceb
PO		 1096
1097 host->mrq = mrq;
1098
68d1fb7e
AV		 1099 /* If polling, assume that the card is always present. */
1100 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1101 present = true;
1102 else
1103 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1104 SDHCI_CARD_PRESENT;
1105
1106 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1107 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1108 tasklet_schedule(&host->finish_tasklet);
1109 } else
1110 sdhci_send_command(host, mrq->cmd);
1111
5f25a66f 1112 mmiowb();
d129bceb
PO		 1113 spin_unlock_irqrestore(&host->lock, flags);
1114}
1115
1116static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1117{
1118 struct sdhci_host *host;
1119 unsigned long flags;
1120 u8 ctrl;
1121
1122 host = mmc_priv(mmc);
1123
1124 spin_lock_irqsave(&host->lock, flags);
1125
1e72859e
PO		 1126 if (host->flags & SDHCI_DEVICE_DEAD)
1127 goto out;
1128
d129bceb
PO		 1129 /*
1130 * Reset the chip on each power off.
1131 * Should clear out any weird states.
1132 */
1133 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1134 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1135 sdhci_reinit(host);
d129bceb
PO		 1136 }
1137
1138 sdhci_set_clock(host, ios->clock);
1139
1140 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1141 sdhci_set_power(host, -1);
d129bceb 1142 else
146ad66e 1143 sdhci_set_power(host, ios->vdd);
d129bceb 1144
4e4141a5 1145 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1146
d129bceb
PO		 1147 if (ios->bus_width == MMC_BUS_WIDTH_4)
1148 ctrl |= SDHCI_CTRL_4BITBUS;
1149 else
1150 ctrl &= ~SDHCI_CTRL_4BITBUS;
cd9277c0
PO		 1151
1152 if (ios->timing == MMC_TIMING_SD_HS)
1153 ctrl |= SDHCI_CTRL_HISPD;
1154 else
1155 ctrl &= ~SDHCI_CTRL_HISPD;
1156
4e4141a5 1157 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb 1158
b8352260
LD		 1159 /*
1160 * Some (ENE) controllers go apeshit on some ios operation,
1161 * signalling timeout and CRC errors even on CMD0. Resetting
1162 * it on each ios seems to solve the problem.
1163 */
b8c86fc5 1164 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1165 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1166
1e72859e 1167out:
5f25a66f 1168 mmiowb();
d129bceb
PO		 1169 spin_unlock_irqrestore(&host->lock, flags);
1170}
1171
1172static int sdhci_get_ro(struct mmc_host *mmc)
1173{
1174 struct sdhci_host *host;
1175 unsigned long flags;
1176 int present;
1177
1178 host = mmc_priv(mmc);
1179
1180 spin_lock_irqsave(&host->lock, flags);
1181
1e72859e
PO		 1182 if (host->flags & SDHCI_DEVICE_DEAD)
1183 present = 0;
1184 else
4e4141a5 1185 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
d129bceb
PO		 1186
1187 spin_unlock_irqrestore(&host->lock, flags);
1188
c5075a10
AV		 1189 if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
1190 return !!(present & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1191 return !(present & SDHCI_WRITE_PROTECT);
1192}
1193
f75979b7
PO		 1194static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1195{
1196 struct sdhci_host *host;
1197 unsigned long flags;
f75979b7
PO		 1198
1199 host = mmc_priv(mmc);
1200
1201 spin_lock_irqsave(&host->lock, flags);
1202
1e72859e
PO		 1203 if (host->flags & SDHCI_DEVICE_DEAD)
1204 goto out;
1205
f75979b7 1206 if (enable)
7260cf5e
AV		 1207 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1208 else
1209 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1210out:
f75979b7
PO		 1211 mmiowb();
1212
1213 spin_unlock_irqrestore(&host->lock, flags);
1214}
1215
ab7aefd0 1216static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1217 .request = sdhci_request,
1218 .set_ios = sdhci_set_ios,
1219 .get_ro = sdhci_get_ro,
f75979b7 1220 .enable_sdio_irq = sdhci_enable_sdio_irq,
d129bceb
PO		 1221};
1222
1223/*****************************************************************************\
1224 * *
1225 * Tasklets *
1226 * *
1227\*****************************************************************************/
1228
1229static void sdhci_tasklet_card(unsigned long param)
1230{
1231 struct sdhci_host *host;
1232 unsigned long flags;
1233
1234 host = (struct sdhci_host*)param;
1235
1236 spin_lock_irqsave(&host->lock, flags);
1237
4e4141a5 1238 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
d129bceb
PO		 1239 if (host->mrq) {
1240 printk(KERN_ERR "%s: Card removed during transfer!\n",
1241 mmc_hostname(host->mmc));
1242 printk(KERN_ERR "%s: Resetting controller.\n",
1243 mmc_hostname(host->mmc));
1244
1245 sdhci_reset(host, SDHCI_RESET_CMD);
1246 sdhci_reset(host, SDHCI_RESET_DATA);
1247
17b0429d 1248 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1249 tasklet_schedule(&host->finish_tasklet);
1250 }
1251 }
1252
1253 spin_unlock_irqrestore(&host->lock, flags);
1254
04cf585d 1255 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1256}
1257
1258static void sdhci_tasklet_finish(unsigned long param)
1259{
1260 struct sdhci_host *host;
1261 unsigned long flags;
1262 struct mmc_request *mrq;
1263
1264 host = (struct sdhci_host*)param;
1265
1266 spin_lock_irqsave(&host->lock, flags);
1267
1268 del_timer(&host->timer);
1269
1270 mrq = host->mrq;
1271
d129bceb
PO		 1272 /*
1273 * The controller needs a reset of internal state machines
1274 * upon error conditions.
1275 */
1e72859e
PO		 1276 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1277 (mrq->cmd->error ||
1278 (mrq->data && (mrq->data->error ||
1279 (mrq->data->stop && mrq->data->stop->error))) ||
1280 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1281
1282 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1283 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1284 unsigned int clock;
1285
1286 /* This is to force an update */
1287 clock = host->clock;
1288 host->clock = 0;
1289 sdhci_set_clock(host, clock);
1290 }
1291
1292 /* Spec says we should do both at the same time, but Ricoh
1293 controllers do not like that. */
d129bceb
PO		 1294 sdhci_reset(host, SDHCI_RESET_CMD);
1295 sdhci_reset(host, SDHCI_RESET_DATA);
1296 }
1297
1298 host->mrq = NULL;
1299 host->cmd = NULL;
1300 host->data = NULL;
1301
f9134319 1302#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1303 sdhci_deactivate_led(host);
2f730fec 1304#endif
d129bceb 1305
5f25a66f 1306 mmiowb();
d129bceb
PO		 1307 spin_unlock_irqrestore(&host->lock, flags);
1308
1309 mmc_request_done(host->mmc, mrq);
1310}
1311
1312static void sdhci_timeout_timer(unsigned long data)
1313{
1314 struct sdhci_host *host;
1315 unsigned long flags;
1316
1317 host = (struct sdhci_host*)data;
1318
1319 spin_lock_irqsave(&host->lock, flags);
1320
1321 if (host->mrq) {
acf1da45
PO		 1322 printk(KERN_ERR "%s: Timeout waiting for hardware "
1323 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1324 sdhci_dumpregs(host);
1325
1326 if (host->data) {
17b0429d 1327 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1328 sdhci_finish_data(host);
1329 } else {
1330 if (host->cmd)
17b0429d 1331 host->cmd->error = -ETIMEDOUT;
d129bceb 1332 else
17b0429d 1333 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1334
1335 tasklet_schedule(&host->finish_tasklet);
1336 }
1337 }
1338
5f25a66f 1339 mmiowb();
d129bceb
PO		 1340 spin_unlock_irqrestore(&host->lock, flags);
1341}
1342
1343/*****************************************************************************\
1344 * *
1345 * Interrupt handling *
1346 * *
1347\*****************************************************************************/
1348
1349static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1350{
1351 BUG_ON(intmask == 0);
1352
1353 if (!host->cmd) {
b67ac3f3
PO		 1354 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1355 "though no command operation was in progress.\n",
1356 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1357 sdhci_dumpregs(host);
1358 return;
1359 }
1360
43b58b36 1361 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1362 host->cmd->error = -ETIMEDOUT;
1363 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1364 SDHCI_INT_INDEX))
1365 host->cmd->error = -EILSEQ;
43b58b36 1366
e809517f 1367 if (host->cmd->error) {
d129bceb 1368 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 1369 return;
1370 }
1371
1372 /*
1373 * The host can send and interrupt when the busy state has
1374 * ended, allowing us to wait without wasting CPU cycles.
1375 * Unfortunately this is overloaded on the "data complete"
1376 * interrupt, so we need to take some care when handling
1377 * it.
1378 *
1379 * Note: The 1.0 specification is a bit ambiguous about this
1380 * feature so there might be some problems with older
1381 * controllers.
1382 */
1383 if (host->cmd->flags & MMC_RSP_BUSY) {
1384 if (host->cmd->data)
1385 DBG("Cannot wait for busy signal when also "
1386 "doing a data transfer");
f945405c 1387 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 1388 return;
f945405c
BD		 1389
1390 /* The controller does not support the end-of-busy IRQ,
1391 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 1392 }
1393
1394 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 1395 sdhci_finish_command(host);
d129bceb
PO		 1396}
1397
6882a8c0
BD		 1398#ifdef DEBUG
1399static void sdhci_show_adma_error(struct sdhci_host *host)
1400{
1401 const char *name = mmc_hostname(host->mmc);
1402 u8 *desc = host->adma_desc;
1403 __le32 *dma;
1404 __le16 *len;
1405 u8 attr;
1406
1407 sdhci_dumpregs(host);
1408
1409 while (true) {
1410 dma = (__le32 *)(desc + 4);
1411 len = (__le16 *)(desc + 2);
1412 attr = *desc;
1413
1414 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1415 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1416
1417 desc += 8;
1418
1419 if (attr & 2)
1420 break;
1421 }
1422}
1423#else
1424static void sdhci_show_adma_error(struct sdhci_host *host) { }
1425#endif
1426
d129bceb
PO		 1427static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1428{
1429 BUG_ON(intmask == 0);
1430
1431 if (!host->data) {
1432 /*
e809517f
PO		 1433 * The "data complete" interrupt is also used to
1434 * indicate that a busy state has ended. See comment
1435 * above in sdhci_cmd_irq().
d129bceb 1436 */
e809517f
PO		 1437 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1438 if (intmask & SDHCI_INT_DATA_END) {
1439 sdhci_finish_command(host);
1440 return;
1441 }
1442 }
d129bceb 1443
b67ac3f3
PO		 1444 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1445 "though no data operation was in progress.\n",
1446 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1447 sdhci_dumpregs(host);
1448
1449 return;
1450 }
1451
1452 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d
PO		 1453 host->data->error = -ETIMEDOUT;
1454 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1455 host->data->error = -EILSEQ;
6882a8c0
BD		 1456 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1457 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1458 sdhci_show_adma_error(host);
2134a922 1459 host->data->error = -EIO;
6882a8c0 1460 }
d129bceb 1461
17b0429d 1462 if (host->data->error)
d129bceb
PO		 1463 sdhci_finish_data(host);
1464 else {
a406f5a3 1465 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1466 sdhci_transfer_pio(host);
1467
6ba736a1
PO		 1468 /*
1469 * We currently don't do anything fancy with DMA
1470 * boundaries, but as we can't disable the feature
1471 * we need to at least restart the transfer.
1472 */
1473 if (intmask & SDHCI_INT_DMA_END)
4e4141a5
AV		 1474 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1475 SDHCI_DMA_ADDRESS);
6ba736a1 1476
e538fbe8
PO		 1477 if (intmask & SDHCI_INT_DATA_END) {
1478 if (host->cmd) {
1479 /*
1480 * Data managed to finish before the
1481 * command completed. Make sure we do
1482 * things in the proper order.
1483 */
1484 host->data_early = 1;
1485 } else {
1486 sdhci_finish_data(host);
1487 }
1488 }
d129bceb
PO		 1489 }
1490}
1491
7d12e780 1492static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1493{
1494 irqreturn_t result;
1495 struct sdhci_host* host = dev_id;
1496 u32 intmask;
f75979b7 1497 int cardint = 0;
d129bceb
PO		 1498
1499 spin_lock(&host->lock);
1500
4e4141a5 1501 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 1502
62df67a5 1503 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1504 result = IRQ_NONE;
1505 goto out;
1506 }
1507
b69c9058
PO		 1508 DBG("*** %s got interrupt: 0x%08x\n",
1509 mmc_hostname(host->mmc), intmask);
d129bceb 1510
3192a28f 1511 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
4e4141a5
AV		 1512 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1513 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
d129bceb 1514 tasklet_schedule(&host->card_tasklet);
3192a28f 1515 }
d129bceb 1516
3192a28f 1517 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1518
3192a28f 1519 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 1520 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1521 SDHCI_INT_STATUS);
3192a28f 1522 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1523 }
1524
1525 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 1526 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1527 SDHCI_INT_STATUS);
3192a28f 1528 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1529 }
1530
1531 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1532
964f9ce2
PO		 1533 intmask &= ~SDHCI_INT_ERROR;
1534
d129bceb 1535 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1536 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1537 mmc_hostname(host->mmc));
4e4141a5 1538 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 1539 }
1540
9d26a5d3 1541 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 1542
f75979b7
PO		 1543 if (intmask & SDHCI_INT_CARD_INT)
1544 cardint = 1;
1545
1546 intmask &= ~SDHCI_INT_CARD_INT;
1547
3192a28f 1548 if (intmask) {
acf1da45 1549 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1550 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1551 sdhci_dumpregs(host);
1552
4e4141a5 1553 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 1554 }
d129bceb
PO		 1555
1556 result = IRQ_HANDLED;
1557
5f25a66f 1558 mmiowb();
d129bceb
PO		 1559out:
1560 spin_unlock(&host->lock);
1561
f75979b7
PO		 1562 /*
1563 * We have to delay this as it calls back into the driver.
1564 */
1565 if (cardint)
1566 mmc_signal_sdio_irq(host->mmc);
1567
d129bceb
PO		 1568 return result;
1569}
1570
1571/*****************************************************************************\
1572 * *
1573 * Suspend/resume *
1574 * *
1575\*****************************************************************************/
1576
1577#ifdef CONFIG_PM
1578
b8c86fc5 1579int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 1580{
b8c86fc5 1581 int ret;
a715dfc7 1582
7260cf5e
AV		 1583 sdhci_disable_card_detection(host);
1584
b8c86fc5
PO		 1585 ret = mmc_suspend_host(host->mmc, state);
1586 if (ret)
1587 return ret;
a715dfc7 1588
b8c86fc5 1589 free_irq(host->irq, host);
d129bceb
PO		 1590
1591 return 0;
1592}
1593
b8c86fc5 1594EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 1595
b8c86fc5
PO		 1596int sdhci_resume_host(struct sdhci_host *host)
1597{
1598 int ret;
d129bceb 1599
b8c86fc5
PO		 1600 if (host->flags & SDHCI_USE_DMA) {
1601 if (host->ops->enable_dma)
1602 host->ops->enable_dma(host);
1603 }
d129bceb 1604
b8c86fc5
PO		 1605 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1606 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 1607 if (ret)
1608 return ret;
d129bceb 1609
b8c86fc5
PO		 1610 sdhci_init(host);
1611 mmiowb();
1612
1613 ret = mmc_resume_host(host->mmc);
1614 if (ret)
1615 return ret;
d129bceb 1616
7260cf5e
AV		 1617 sdhci_enable_card_detection(host);
1618
d129bceb
PO		 1619 return 0;
1620}
1621
b8c86fc5 1622EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 1623
1624#endif /* CONFIG_PM */
1625
1626/*****************************************************************************\
1627 * *
b8c86fc5 1628 * Device allocation/registration *
d129bceb
PO		 1629 * *
1630\*****************************************************************************/
1631
b8c86fc5
PO		 1632struct sdhci_host *sdhci_alloc_host(struct device *dev,
1633 size_t priv_size)
d129bceb 1634{
d129bceb
PO		 1635 struct mmc_host *mmc;
1636 struct sdhci_host *host;
1637
b8c86fc5 1638 WARN_ON(dev == NULL);
d129bceb 1639
b8c86fc5 1640 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 1641 if (!mmc)
b8c86fc5 1642 return ERR_PTR(-ENOMEM);
d129bceb
PO		 1643
1644 host = mmc_priv(mmc);
1645 host->mmc = mmc;
1646
b8c86fc5
PO		 1647 return host;
1648}
8a4da143 1649
b8c86fc5 1650EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 1651
b8c86fc5
PO		 1652int sdhci_add_host(struct sdhci_host *host)
1653{
1654 struct mmc_host *mmc;
1655 unsigned int caps;
b8c86fc5 1656 int ret;
d129bceb 1657
b8c86fc5
PO		 1658 WARN_ON(host == NULL);
1659 if (host == NULL)
1660 return -EINVAL;
d129bceb 1661
b8c86fc5 1662 mmc = host->mmc;
d129bceb 1663
b8c86fc5
PO		 1664 if (debug_quirks)
1665 host->quirks = debug_quirks;
d129bceb 1666
d96649ed
PO		 1667 sdhci_reset(host, SDHCI_RESET_ALL);
1668
4e4141a5 1669 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 1670 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1671 >> SDHCI_SPEC_VER_SHIFT;
1672 if (host->version > SDHCI_SPEC_200) {
4a965505 1673 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 1674 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 1675 host->version);
4a965505
PO		 1676 }
1677
4e4141a5 1678 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 1679
b8c86fc5 1680 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
98608076 1681 host->flags |= SDHCI_USE_DMA;
67435274
PO		 1682 else if (!(caps & SDHCI_CAN_DO_DMA))
1683 DBG("Controller doesn't have DMA capability\n");
1684 else
d129bceb
PO		 1685 host->flags |= SDHCI_USE_DMA;
1686
b8c86fc5 1687 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
7c168e3d 1688 (host->flags & SDHCI_USE_DMA)) {
cee687ce 1689 DBG("Disabling DMA as it is marked broken\n");
7c168e3d
FT		 1690 host->flags &= ~SDHCI_USE_DMA;
1691 }
1692
2134a922
PO		 1693 if (host->flags & SDHCI_USE_DMA) {
1694 if ((host->version >= SDHCI_SPEC_200) &&
1695 (caps & SDHCI_CAN_DO_ADMA2))
1696 host->flags |= SDHCI_USE_ADMA;
1697 }
1698
1699 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1700 (host->flags & SDHCI_USE_ADMA)) {
1701 DBG("Disabling ADMA as it is marked broken\n");
1702 host->flags &= ~SDHCI_USE_ADMA;
1703 }
1704
d129bceb 1705 if (host->flags & SDHCI_USE_DMA) {
b8c86fc5
PO		 1706 if (host->ops->enable_dma) {
1707 if (host->ops->enable_dma(host)) {
1708 printk(KERN_WARNING "%s: No suitable DMA "
1709 "available. Falling back to PIO.\n",
1710 mmc_hostname(mmc));
2134a922 1711 host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA);
b8c86fc5 1712 }
d129bceb
PO		 1713 }
1714 }
1715
2134a922
PO		 1716 if (host->flags & SDHCI_USE_ADMA) {
1717 /*
1718 * We need to allocate descriptors for all sg entries
1719 * (128) and potentially one alignment transfer for
1720 * each of those entries.
1721 */
1722 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1723 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1724 if (!host->adma_desc || !host->align_buffer) {
1725 kfree(host->adma_desc);
1726 kfree(host->align_buffer);
1727 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1728 "buffers. Falling back to standard DMA.\n",
1729 mmc_hostname(mmc));
1730 host->flags &= ~SDHCI_USE_ADMA;
1731 }
1732 }
1733
7659150c
PO		 1734 /*
1735 * If we use DMA, then it's up to the caller to set the DMA
1736 * mask, but PIO does not need the hw shim so we set a new
1737 * mask here in that case.
1738 */
1739 if (!(host->flags & SDHCI_USE_DMA)) {
1740 host->dma_mask = DMA_BIT_MASK(64);
1741 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1742 }
d129bceb 1743
8ef1a143
PO		 1744 host->max_clk =
1745 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
4240ff0a 1746 host->max_clk *= 1000000;
8ef1a143 1747 if (host->max_clk == 0) {
4240ff0a
BD		 1748 if (!host->ops->get_max_clock) {
1749 printk(KERN_ERR
1750 "%s: Hardware doesn't specify base clock "
1751 "frequency.\n", mmc_hostname(mmc));
1752 return -ENODEV;
1753 }
1754 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 1755 }
d129bceb 1756
1c8cde92
PO		 1757 host->timeout_clk =
1758 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1759 if (host->timeout_clk == 0) {
4240ff0a
BD		 1760 if (!host->ops->get_timeout_clock) {
1761 printk(KERN_ERR
1762 "%s: Hardware doesn't specify timeout clock "
1763 "frequency.\n", mmc_hostname(mmc));
1764 return -ENODEV;
1765 }
1766 host->timeout_clk = host->ops->get_timeout_clock(host);
1c8cde92
PO		 1767 }
1768 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1769 host->timeout_clk *= 1000;
d129bceb
PO		 1770
1771 /*
1772 * Set host parameters.
1773 */
1774 mmc->ops = &sdhci_ops;
e9510176
AV		 1775 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK &&
1776 host->ops->set_clock && host->ops->get_min_clock)
a9e58f25
AV		 1777 mmc->f_min = host->ops->get_min_clock(host);
1778 else
1779 mmc->f_min = host->max_clk / 256;
d129bceb 1780 mmc->f_max = host->max_clk;
5fe23c7f
AV		 1781 mmc->caps = MMC_CAP_SDIO_IRQ;
1782
1783 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1784 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 1785
86a6a874 1786 if (caps & SDHCI_CAN_DO_HISPD)
cd9277c0
PO		 1787 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1788
68d1fb7e
AV		 1789 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1790 mmc->caps |= MMC_CAP_NEEDS_POLL;
1791
146ad66e
PO		 1792 mmc->ocr_avail = 0;
1793 if (caps & SDHCI_CAN_VDD_330)
1794 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1795 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1796 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1797 if (caps & SDHCI_CAN_VDD_180)
55556da0 1798 mmc->ocr_avail |= MMC_VDD_165_195;
146ad66e
PO		 1799
1800 if (mmc->ocr_avail == 0) {
1801 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 1802 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 1803 return -ENODEV;
146ad66e
PO		 1804 }
1805
d129bceb
PO		 1806 spin_lock_init(&host->lock);
1807
1808 /*
2134a922
PO		 1809 * Maximum number of segments. Depends on if the hardware
1810 * can do scatter/gather or not.
d129bceb 1811 */
2134a922
PO		 1812 if (host->flags & SDHCI_USE_ADMA)
1813 mmc->max_hw_segs = 128;
1814 else if (host->flags & SDHCI_USE_DMA)
d129bceb 1815 mmc->max_hw_segs = 1;
2134a922
PO		 1816 else /* PIO */
1817 mmc->max_hw_segs = 128;
1818 mmc->max_phys_segs = 128;
d129bceb
PO		 1819
1820 /*
bab76961 1821 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1822 * size (512KiB).
d129bceb 1823 */
55db890a 1824 mmc->max_req_size = 524288;
d129bceb
PO		 1825
1826 /*
1827 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 1828 * of bytes. When doing hardware scatter/gather, each entry cannot
1829 * be larger than 64 KiB though.
d129bceb 1830 */
2134a922
PO		 1831 if (host->flags & SDHCI_USE_ADMA)
1832 mmc->max_seg_size = 65536;
1833 else
1834 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1835
fe4a3c7a
PO		 1836 /*
1837 * Maximum block size. This varies from controller to controller and
1838 * is specified in the capabilities register.
1839 */
0633f654
AV		 1840 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1841 mmc->max_blk_size = 2;
1842 } else {
1843 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1844 SDHCI_MAX_BLOCK_SHIFT;
1845 if (mmc->max_blk_size >= 3) {
1846 printk(KERN_WARNING "%s: Invalid maximum block size, "
1847 "assuming 512 bytes\n", mmc_hostname(mmc));
1848 mmc->max_blk_size = 0;
1849 }
1850 }
1851
1852 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 1853
55db890a
PO		 1854 /*
1855 * Maximum block count.
1856 */
1388eefd 1857 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 1858
d129bceb
PO		 1859 /*
1860 * Init tasklets.
1861 */
1862 tasklet_init(&host->card_tasklet,
1863 sdhci_tasklet_card, (unsigned long)host);
1864 tasklet_init(&host->finish_tasklet,
1865 sdhci_tasklet_finish, (unsigned long)host);
1866
e4cad1b5 1867 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1868
dace1453 1869 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 1870 mmc_hostname(mmc), host);
d129bceb 1871 if (ret)
8ef1a143 1872 goto untasklet;
d129bceb
PO		 1873
1874 sdhci_init(host);
1875
1876#ifdef CONFIG_MMC_DEBUG
1877 sdhci_dumpregs(host);
1878#endif
1879
f9134319 1880#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 1881 snprintf(host->led_name, sizeof(host->led_name),
1882 "%s::", mmc_hostname(mmc));
1883 host->led.name = host->led_name;
2f730fec
PO		 1884 host->led.brightness = LED_OFF;
1885 host->led.default_trigger = mmc_hostname(mmc);
1886 host->led.brightness_set = sdhci_led_control;
1887
b8c86fc5 1888 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 1889 if (ret)
1890 goto reset;
1891#endif
1892
5f25a66f
PO		 1893 mmiowb();
1894
d129bceb
PO		 1895 mmc_add_host(mmc);
1896
2134a922 1897 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n",
d1b26863 1898 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2134a922 1899 (host->flags & SDHCI_USE_ADMA)?"A":"",
d129bceb
PO		 1900 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1901
7260cf5e
AV		 1902 sdhci_enable_card_detection(host);
1903
d129bceb
PO		 1904 return 0;
1905
f9134319 1906#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 1907reset:
1908 sdhci_reset(host, SDHCI_RESET_ALL);
1909 free_irq(host->irq, host);
1910#endif
8ef1a143 1911untasklet:
d129bceb
PO		 1912 tasklet_kill(&host->card_tasklet);
1913 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 1914
1915 return ret;
1916}
1917
b8c86fc5 1918EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 1919
1e72859e 1920void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 1921{
1e72859e
PO		 1922 unsigned long flags;
1923
1924 if (dead) {
1925 spin_lock_irqsave(&host->lock, flags);
1926
1927 host->flags |= SDHCI_DEVICE_DEAD;
1928
1929 if (host->mrq) {
1930 printk(KERN_ERR "%s: Controller removed during "
1931 " transfer!\n", mmc_hostname(host->mmc));
1932
1933 host->mrq->cmd->error = -ENOMEDIUM;
1934 tasklet_schedule(&host->finish_tasklet);
1935 }
1936
1937 spin_unlock_irqrestore(&host->lock, flags);
1938 }
1939
7260cf5e
AV		 1940 sdhci_disable_card_detection(host);
1941
b8c86fc5 1942 mmc_remove_host(host->mmc);
d129bceb 1943
f9134319 1944#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 1945 led_classdev_unregister(&host->led);
1946#endif
1947
1e72859e
PO		 1948 if (!dead)
1949 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 1950
1951 free_irq(host->irq, host);
1952
1953 del_timer_sync(&host->timer);
1954
1955 tasklet_kill(&host->card_tasklet);
1956 tasklet_kill(&host->finish_tasklet);
2134a922
PO		 1957
1958 kfree(host->adma_desc);
1959 kfree(host->align_buffer);
1960
1961 host->adma_desc = NULL;
1962 host->align_buffer = NULL;
d129bceb
PO		 1963}
1964
b8c86fc5 1965EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 1966
b8c86fc5 1967void sdhci_free_host(struct sdhci_host *host)
d129bceb 1968{
b8c86fc5 1969 mmc_free_host(host->mmc);
d129bceb
PO		 1970}
1971
b8c86fc5 1972EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 1973
1974/*****************************************************************************\
1975 * *
1976 * Driver init/exit *
1977 * *
1978\*****************************************************************************/
1979
1980static int __init sdhci_drv_init(void)
1981{
1982 printk(KERN_INFO DRIVER_NAME
52fbf9c9 1983 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 1984 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1985
b8c86fc5 1986 return 0;
d129bceb
PO		 1987}
1988
1989static void __exit sdhci_drv_exit(void)
1990{
d129bceb
PO		 1991}
1992
1993module_init(sdhci_drv_init);
1994module_exit(sdhci_drv_exit);
1995
df673b22 1996module_param(debug_quirks, uint, 0444);
67435274 1997
32710e8f 1998MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 1999MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 2000MODULE_LICENSE("GPL");
67435274 2001
df673b22 2002MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux 6.x block layer and io_uring tree(s)