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mmc: sdhci-tegra: get rid of special PRESENT_STATE register handling
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
d1e49f77
RK		 47#define ADMA_SIZE ((128 * 2 + 1) * 4)
48
df673b22 49static unsigned int debug_quirks = 0;
66fd8ad5 50static unsigned int debug_quirks2;
67435274 51
d129bceb
PO		 52static void sdhci_finish_data(struct sdhci_host *);
53
d129bceb 54static void sdhci_finish_command(struct sdhci_host *);
069c9f14 55static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 56static void sdhci_tuning_timer(unsigned long data);
52983382 57static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 58
66fd8ad5
AH		 59#ifdef CONFIG_PM_RUNTIME
60static int sdhci_runtime_pm_get(struct sdhci_host *host);
61static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 62static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
63static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 64#else
65static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
66{
67 return 0;
68}
69static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
70{
71 return 0;
72}
f0710a55
AH		 73static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
74{
75}
76static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
77{
78}
66fd8ad5
AH		 79#endif
80
d129bceb
PO		 81static void sdhci_dumpregs(struct sdhci_host *host)
82{
a3c76eb9 83 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 84 mmc_hostname(host->mmc));
d129bceb 85
a3c76eb9 86 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 87 sdhci_readl(host, SDHCI_DMA_ADDRESS),
88 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 89 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 90 sdhci_readw(host, SDHCI_BLOCK_SIZE),
91 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 92 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 93 sdhci_readl(host, SDHCI_ARGUMENT),
94 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 95 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 96 sdhci_readl(host, SDHCI_PRESENT_STATE),
97 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 98 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 99 sdhci_readb(host, SDHCI_POWER_CONTROL),
100 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 101 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 102 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
103 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 104 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 105 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
106 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 107 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 108 sdhci_readl(host, SDHCI_INT_ENABLE),
109 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 110 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 111 sdhci_readw(host, SDHCI_ACMD12_ERR),
112 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 113 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 114 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 115 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 117 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 118 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 120 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 121
be3f4ae0 122 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
126
a3c76eb9 127 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 128}
129
130/*****************************************************************************\
131 * *
132 * Low level functions *
133 * *
134\*****************************************************************************/
135
7260cf5e
AV		 136static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
137{
5b4f1f6c 138 u32 present;
7260cf5e 139
c79396c1 140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 141 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 142 return;
143
5b4f1f6c
RK		 144 if (enable) {
145 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
146 SDHCI_CARD_PRESENT;
d25928d1 147
5b4f1f6c
RK		 148 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
149 SDHCI_INT_CARD_INSERT;
150 } else {
151 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
152 }
b537f94c
RK		 153
154 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
155 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 156}
157
158static void sdhci_enable_card_detection(struct sdhci_host *host)
159{
160 sdhci_set_card_detection(host, true);
161}
162
163static void sdhci_disable_card_detection(struct sdhci_host *host)
164{
165 sdhci_set_card_detection(host, false);
166}
167
03231f9b 168void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 169{
e16514d8 170 unsigned long timeout;
393c1a34 171
4e4141a5 172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 173
f0710a55 174 if (mask & SDHCI_RESET_ALL) {
d129bceb 175 host->clock = 0;
f0710a55
AH		 176 /* Reset-all turns off SD Bus Power */
177 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
178 sdhci_runtime_pm_bus_off(host);
179 }
d129bceb 180
e16514d8
PO		 181 /* Wait max 100 ms */
182 timeout = 100;
183
184 /* hw clears the bit when it's done */
4e4141a5 185 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 186 if (timeout == 0) {
a3c76eb9 187 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 188 mmc_hostname(host->mmc), (int)mask);
189 sdhci_dumpregs(host);
190 return;
191 }
192 timeout--;
193 mdelay(1);
d129bceb 194 }
03231f9b
RK		 195}
196EXPORT_SYMBOL_GPL(sdhci_reset);
197
198static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
199{
200 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
201 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
202 SDHCI_CARD_PRESENT))
203 return;
204 }
063a9dbb 205
03231f9b 206 host->ops->reset(host, mask);
393c1a34 207
3abc1e80
SX		 208 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
209 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
210 host->ops->enable_dma(host);
211 }
d129bceb
PO		 212}
213
2f4cbb3d
NP		 214static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
215
216static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 217{
2f4cbb3d 218 if (soft)
03231f9b 219 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 220 else
03231f9b 221 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 222
b537f94c
RK		 223 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
224 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
225 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
226 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
227 SDHCI_INT_RESPONSE;
228
229 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
230 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 231
232 if (soft) {
233 /* force clock reconfiguration */
234 host->clock = 0;
235 sdhci_set_ios(host->mmc, &host->mmc->ios);
236 }
7260cf5e 237}
d129bceb 238
7260cf5e
AV		 239static void sdhci_reinit(struct sdhci_host *host)
240{
2f4cbb3d 241 sdhci_init(host, 0);
b67c6b41
AL		 242 /*
243 * Retuning stuffs are affected by different cards inserted and only
244 * applicable to UHS-I cards. So reset these fields to their initial
245 * value when card is removed.
246 */
973905fe
AL		 247 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
248 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
249
b67c6b41
AL		 250 del_timer_sync(&host->tuning_timer);
251 host->flags &= ~SDHCI_NEEDS_RETUNING;
252 host->mmc->max_blk_count =
253 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
254 }
7260cf5e 255 sdhci_enable_card_detection(host);
d129bceb
PO		 256}
257
258static void sdhci_activate_led(struct sdhci_host *host)
259{
260 u8 ctrl;
261
4e4141a5 262 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 263 ctrl |= SDHCI_CTRL_LED;
4e4141a5 264 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 265}
266
267static void sdhci_deactivate_led(struct sdhci_host *host)
268{
269 u8 ctrl;
270
4e4141a5 271 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 272 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 273 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 274}
275
f9134319 276#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 277static void sdhci_led_control(struct led_classdev *led,
278 enum led_brightness brightness)
279{
280 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
281 unsigned long flags;
282
283 spin_lock_irqsave(&host->lock, flags);
284
66fd8ad5
AH		 285 if (host->runtime_suspended)
286 goto out;
287
2f730fec
PO		 288 if (brightness == LED_OFF)
289 sdhci_deactivate_led(host);
290 else
291 sdhci_activate_led(host);
66fd8ad5 292out:
2f730fec
PO		 293 spin_unlock_irqrestore(&host->lock, flags);
294}
295#endif
296
d129bceb
PO		 297/*****************************************************************************\
298 * *
299 * Core functions *
300 * *
301\*****************************************************************************/
302
a406f5a3 303static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 304{
7659150c
PO		 305 unsigned long flags;
306 size_t blksize, len, chunk;
7244b85b 307 u32 uninitialized_var(scratch);
7659150c 308 u8 *buf;
d129bceb 309
a406f5a3 310 DBG("PIO reading\n");
d129bceb 311
a406f5a3 312 blksize = host->data->blksz;
7659150c 313 chunk = 0;
d129bceb 314
7659150c 315 local_irq_save(flags);
d129bceb 316
a406f5a3 317 while (blksize) {
7659150c
PO		 318 if (!sg_miter_next(&host->sg_miter))
319 BUG();
d129bceb 320
7659150c 321 len = min(host->sg_miter.length, blksize);
d129bceb 322
7659150c
PO		 323 blksize -= len;
324 host->sg_miter.consumed = len;
14d836e7 325
7659150c 326 buf = host->sg_miter.addr;
d129bceb 327
7659150c
PO		 328 while (len) {
329 if (chunk == 0) {
4e4141a5 330 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 331 chunk = 4;
a406f5a3 332 }
7659150c
PO		 333
334 *buf = scratch & 0xFF;
335
336 buf++;
337 scratch >>= 8;
338 chunk--;
339 len--;
d129bceb 340 }
a406f5a3 341 }
7659150c
PO		 342
343 sg_miter_stop(&host->sg_miter);
344
345 local_irq_restore(flags);
a406f5a3 346}
d129bceb 347
a406f5a3
PO		 348static void sdhci_write_block_pio(struct sdhci_host *host)
349{
7659150c
PO		 350 unsigned long flags;
351 size_t blksize, len, chunk;
352 u32 scratch;
353 u8 *buf;
d129bceb 354
a406f5a3
PO		 355 DBG("PIO writing\n");
356
357 blksize = host->data->blksz;
7659150c
PO		 358 chunk = 0;
359 scratch = 0;
d129bceb 360
7659150c 361 local_irq_save(flags);
d129bceb 362
a406f5a3 363 while (blksize) {
7659150c
PO		 364 if (!sg_miter_next(&host->sg_miter))
365 BUG();
a406f5a3 366
7659150c
PO		 367 len = min(host->sg_miter.length, blksize);
368
369 blksize -= len;
370 host->sg_miter.consumed = len;
371
372 buf = host->sg_miter.addr;
d129bceb 373
7659150c
PO		 374 while (len) {
375 scratch |= (u32)*buf << (chunk * 8);
376
377 buf++;
378 chunk++;
379 len--;
380
381 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 382 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 383 chunk = 0;
384 scratch = 0;
d129bceb 385 }
d129bceb
PO		 386 }
387 }
7659150c
PO		 388
389 sg_miter_stop(&host->sg_miter);
390
391 local_irq_restore(flags);
a406f5a3
PO		 392}
393
394static void sdhci_transfer_pio(struct sdhci_host *host)
395{
396 u32 mask;
397
398 BUG_ON(!host->data);
399
7659150c 400 if (host->blocks == 0)
a406f5a3
PO		 401 return;
402
403 if (host->data->flags & MMC_DATA_READ)
404 mask = SDHCI_DATA_AVAILABLE;
405 else
406 mask = SDHCI_SPACE_AVAILABLE;
407
4a3cba32
PO		 408 /*
409 * Some controllers (JMicron JMB38x) mess up the buffer bits
410 * for transfers < 4 bytes. As long as it is just one block,
411 * we can ignore the bits.
412 */
413 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
414 (host->data->blocks == 1))
415 mask = ~0;
416
4e4141a5 417 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 418 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
419 udelay(100);
420
a406f5a3
PO		 421 if (host->data->flags & MMC_DATA_READ)
422 sdhci_read_block_pio(host);
423 else
424 sdhci_write_block_pio(host);
d129bceb 425
7659150c
PO		 426 host->blocks--;
427 if (host->blocks == 0)
a406f5a3 428 break;
a406f5a3 429 }
d129bceb 430
a406f5a3 431 DBG("PIO transfer complete.\n");
d129bceb
PO		 432}
433
2134a922
PO		 434static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
435{
436 local_irq_save(*flags);
482fce99 437 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 438}
439
440static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
441{
482fce99 442 kunmap_atomic(buffer);
2134a922
PO		 443 local_irq_restore(*flags);
444}
445
118cd17d
BD		 446static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
447{
9e506f35
BD		 448 __le32 *dataddr = (__le32 __force *)(desc + 4);
449 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 450
9e506f35
BD		 451 /* SDHCI specification says ADMA descriptors should be 4 byte
452 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 453
9e506f35
BD		 454 cmdlen[0] = cpu_to_le16(cmd);
455 cmdlen[1] = cpu_to_le16(len);
456
457 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 458}
459
8f1934ce 460static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 461 struct mmc_data *data)
462{
463 int direction;
464
465 u8 *desc;
466 u8 *align;
467 dma_addr_t addr;
468 dma_addr_t align_addr;
469 int len, offset;
470
471 struct scatterlist *sg;
472 int i;
473 char *buffer;
474 unsigned long flags;
475
476 /*
477 * The spec does not specify endianness of descriptor table.
478 * We currently guess that it is LE.
479 */
480
481 if (data->flags & MMC_DATA_READ)
482 direction = DMA_FROM_DEVICE;
483 else
484 direction = DMA_TO_DEVICE;
485
2134a922
PO		 486 host->align_addr = dma_map_single(mmc_dev(host->mmc),
487 host->align_buffer, 128 * 4, direction);
8d8bb39b 488 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 489 goto fail;
2134a922
PO		 490 BUG_ON(host->align_addr & 0x3);
491
492 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
493 data->sg, data->sg_len, direction);
8f1934ce
PO		 494 if (host->sg_count == 0)
495 goto unmap_align;
2134a922
PO		 496
497 desc = host->adma_desc;
498 align = host->align_buffer;
499
500 align_addr = host->align_addr;
501
502 for_each_sg(data->sg, sg, host->sg_count, i) {
503 addr = sg_dma_address(sg);
504 len = sg_dma_len(sg);
505
506 /*
507 * The SDHCI specification states that ADMA
508 * addresses must be 32-bit aligned. If they
509 * aren't, then we use a bounce buffer for
510 * the (up to three) bytes that screw up the
511 * alignment.
512 */
513 offset = (4 - (addr & 0x3)) & 0x3;
514 if (offset) {
515 if (data->flags & MMC_DATA_WRITE) {
516 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 517 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 518 memcpy(align, buffer, offset);
519 sdhci_kunmap_atomic(buffer, &flags);
520 }
521
118cd17d
BD		 522 /* tran, valid */
523 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 524
525 BUG_ON(offset > 65536);
526
2134a922
PO		 527 align += 4;
528 align_addr += 4;
529
530 desc += 8;
531
532 addr += offset;
533 len -= offset;
534 }
535
2134a922
PO		 536 BUG_ON(len > 65536);
537
118cd17d
BD		 538 /* tran, valid */
539 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 540 desc += 8;
541
542 /*
543 * If this triggers then we have a calculation bug
544 * somewhere. :/
545 */
d1e49f77 546 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
2134a922
PO		 547 }
548
70764a90
TA		 549 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
550 /*
551 * Mark the last descriptor as the terminating descriptor
552 */
553 if (desc != host->adma_desc) {
554 desc -= 8;
555 desc[0] |= 0x2; /* end */
556 }
557 } else {
558 /*
559 * Add a terminating entry.
560 */
2134a922 561
70764a90
TA		 562 /* nop, end, valid */
563 sdhci_set_adma_desc(desc, 0, 0, 0x3);
564 }
2134a922
PO		 565
566 /*
567 * Resync align buffer as we might have changed it.
568 */
569 if (data->flags & MMC_DATA_WRITE) {
570 dma_sync_single_for_device(mmc_dev(host->mmc),
571 host->align_addr, 128 * 4, direction);
572 }
573
8f1934ce
PO		 574 return 0;
575
8f1934ce
PO		 576unmap_align:
577 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
578 128 * 4, direction);
579fail:
580 return -EINVAL;
2134a922
PO		 581}
582
583static void sdhci_adma_table_post(struct sdhci_host *host,
584 struct mmc_data *data)
585{
586 int direction;
587
588 struct scatterlist *sg;
589 int i, size;
590 u8 *align;
591 char *buffer;
592 unsigned long flags;
de0b65a7 593 bool has_unaligned;
2134a922
PO		 594
595 if (data->flags & MMC_DATA_READ)
596 direction = DMA_FROM_DEVICE;
597 else
598 direction = DMA_TO_DEVICE;
599
2134a922
PO		 600 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
601 128 * 4, direction);
602
de0b65a7
RK		 603 /* Do a quick scan of the SG list for any unaligned mappings */
604 has_unaligned = false;
605 for_each_sg(data->sg, sg, host->sg_count, i)
606 if (sg_dma_address(sg) & 3) {
607 has_unaligned = true;
608 break;
609 }
610
611 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 612 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
613 data->sg_len, direction);
614
615 align = host->align_buffer;
616
617 for_each_sg(data->sg, sg, host->sg_count, i) {
618 if (sg_dma_address(sg) & 0x3) {
619 size = 4 - (sg_dma_address(sg) & 0x3);
620
621 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 622 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 623 memcpy(buffer, align, size);
624 sdhci_kunmap_atomic(buffer, &flags);
625
626 align += 4;
627 }
628 }
629 }
630
631 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
632 data->sg_len, direction);
633}
634
a3c7778f 635static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 636{
1c8cde92 637 u8 count;
a3c7778f 638 struct mmc_data *data = cmd->data;
1c8cde92 639 unsigned target_timeout, current_timeout;
d129bceb 640
ee53ab5d
PO		 641 /*
642 * If the host controller provides us with an incorrect timeout
643 * value, just skip the check and use 0xE. The hardware may take
644 * longer to time out, but that's much better than having a too-short
645 * timeout value.
646 */
11a2f1b7 647 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 648 return 0xE;
e538fbe8 649
a3c7778f 650 /* Unspecified timeout, assume max */
1d4d7744 651 if (!data && !cmd->busy_timeout)
a3c7778f 652 return 0xE;
d129bceb 653
a3c7778f
AW		 654 /* timeout in us */
655 if (!data)
1d4d7744 656 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 657 else {
658 target_timeout = data->timeout_ns / 1000;
659 if (host->clock)
660 target_timeout += data->timeout_clks / host->clock;
661 }
81b39802 662
1c8cde92
PO		 663 /*
664 * Figure out needed cycles.
665 * We do this in steps in order to fit inside a 32 bit int.
666 * The first step is the minimum timeout, which will have a
667 * minimum resolution of 6 bits:
668 * (1) 2^13*1000 > 2^22,
669 * (2) host->timeout_clk < 2^16
670 * =>
671 * (1) / (2) > 2^6
672 */
673 count = 0;
674 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
675 while (current_timeout < target_timeout) {
676 count++;
677 current_timeout <<= 1;
678 if (count >= 0xF)
679 break;
680 }
681
682 if (count >= 0xF) {
09eeff52
CB		 683 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
684 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 685 count = 0xE;
686 }
687
ee53ab5d
PO		 688 return count;
689}
690
6aa943ab
AV		 691static void sdhci_set_transfer_irqs(struct sdhci_host *host)
692{
693 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
694 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
695
696 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 697 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 698 else
b537f94c
RK		 699 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
700
701 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
702 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 703}
704
a3c7778f 705static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 706{
707 u8 count;
2134a922 708 u8 ctrl;
a3c7778f 709 struct mmc_data *data = cmd->data;
8f1934ce 710 int ret;
ee53ab5d
PO		 711
712 WARN_ON(host->data);
713
a3c7778f
AW		 714 if (data || (cmd->flags & MMC_RSP_BUSY)) {
715 count = sdhci_calc_timeout(host, cmd);
716 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
717 }
718
719 if (!data)
ee53ab5d
PO		 720 return;
721
722 /* Sanity checks */
723 BUG_ON(data->blksz * data->blocks > 524288);
724 BUG_ON(data->blksz > host->mmc->max_blk_size);
725 BUG_ON(data->blocks > 65535);
726
727 host->data = data;
728 host->data_early = 0;
f6a03cbf 729 host->data->bytes_xfered = 0;
ee53ab5d 730
a13abc7b 731 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 732 host->flags |= SDHCI_REQ_USE_DMA;
733
2134a922
PO		 734 /*
735 * FIXME: This doesn't account for merging when mapping the
736 * scatterlist.
737 */
738 if (host->flags & SDHCI_REQ_USE_DMA) {
739 int broken, i;
740 struct scatterlist *sg;
741
742 broken = 0;
743 if (host->flags & SDHCI_USE_ADMA) {
744 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
745 broken = 1;
746 } else {
747 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
748 broken = 1;
749 }
750
751 if (unlikely(broken)) {
752 for_each_sg(data->sg, sg, data->sg_len, i) {
753 if (sg->length & 0x3) {
754 DBG("Reverting to PIO because of "
755 "transfer size (%d)\n",
756 sg->length);
757 host->flags &= ~SDHCI_REQ_USE_DMA;
758 break;
759 }
760 }
761 }
c9fddbc4
PO		 762 }
763
764 /*
765 * The assumption here being that alignment is the same after
766 * translation to device address space.
767 */
2134a922
PO		 768 if (host->flags & SDHCI_REQ_USE_DMA) {
769 int broken, i;
770 struct scatterlist *sg;
771
772 broken = 0;
773 if (host->flags & SDHCI_USE_ADMA) {
774 /*
775 * As we use 3 byte chunks to work around
776 * alignment problems, we need to check this
777 * quirk.
778 */
779 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
780 broken = 1;
781 } else {
782 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
783 broken = 1;
784 }
785
786 if (unlikely(broken)) {
787 for_each_sg(data->sg, sg, data->sg_len, i) {
788 if (sg->offset & 0x3) {
789 DBG("Reverting to PIO because of "
790 "bad alignment\n");
791 host->flags &= ~SDHCI_REQ_USE_DMA;
792 break;
793 }
794 }
795 }
796 }
797
8f1934ce
PO		 798 if (host->flags & SDHCI_REQ_USE_DMA) {
799 if (host->flags & SDHCI_USE_ADMA) {
800 ret = sdhci_adma_table_pre(host, data);
801 if (ret) {
802 /*
803 * This only happens when someone fed
804 * us an invalid request.
805 */
806 WARN_ON(1);
ebd6d357 807 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 808 } else {
4e4141a5
AV		 809 sdhci_writel(host, host->adma_addr,
810 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 811 }
812 } else {
c8b3e02e 813 int sg_cnt;
8f1934ce 814
c8b3e02e 815 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 816 data->sg, data->sg_len,
817 (data->flags & MMC_DATA_READ) ?
818 DMA_FROM_DEVICE :
819 DMA_TO_DEVICE);
c8b3e02e 820 if (sg_cnt == 0) {
8f1934ce
PO		 821 /*
822 * This only happens when someone fed
823 * us an invalid request.
824 */
825 WARN_ON(1);
ebd6d357 826 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 827 } else {
719a61b4 828 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 829 sdhci_writel(host, sg_dma_address(data->sg),
830 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 831 }
832 }
833 }
834
2134a922
PO		 835 /*
836 * Always adjust the DMA selection as some controllers
837 * (e.g. JMicron) can't do PIO properly when the selection
838 * is ADMA.
839 */
840 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 841 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 842 ctrl &= ~SDHCI_CTRL_DMA_MASK;
843 if ((host->flags & SDHCI_REQ_USE_DMA) &&
844 (host->flags & SDHCI_USE_ADMA))
845 ctrl |= SDHCI_CTRL_ADMA32;
846 else
847 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 848 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 849 }
850
8f1934ce 851 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 852 int flags;
853
854 flags = SG_MITER_ATOMIC;
855 if (host->data->flags & MMC_DATA_READ)
856 flags |= SG_MITER_TO_SG;
857 else
858 flags |= SG_MITER_FROM_SG;
859 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 860 host->blocks = data->blocks;
d129bceb 861 }
c7fa9963 862
6aa943ab
AV		 863 sdhci_set_transfer_irqs(host);
864
f6a03cbf
MV		 865 /* Set the DMA boundary value and block size */
866 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
867 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 868 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 869}
870
871static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 872 struct mmc_command *cmd)
c7fa9963
PO		 873{
874 u16 mode;
e89d456f 875 struct mmc_data *data = cmd->data;
c7fa9963 876
2b558c13
DA		 877 if (data == NULL) {
878 /* clear Auto CMD settings for no data CMDs */
879 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
880 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
881 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
c7fa9963 882 return;
2b558c13 883 }
c7fa9963 884
e538fbe8
PO		 885 WARN_ON(!host->data);
886
c7fa9963 887 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 888 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
889 mode |= SDHCI_TRNS_MULTI;
890 /*
891 * If we are sending CMD23, CMD12 never gets sent
892 * on successful completion (so no Auto-CMD12).
893 */
894 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
895 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 896 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
897 mode |= SDHCI_TRNS_AUTO_CMD23;
898 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
899 }
c4512f79 900 }
8edf6371 901
c7fa9963
PO		 902 if (data->flags & MMC_DATA_READ)
903 mode |= SDHCI_TRNS_READ;
c9fddbc4 904 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 905 mode |= SDHCI_TRNS_DMA;
906
4e4141a5 907 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 908}
909
910static void sdhci_finish_data(struct sdhci_host *host)
911{
912 struct mmc_data *data;
d129bceb
PO		 913
914 BUG_ON(!host->data);
915
916 data = host->data;
917 host->data = NULL;
918
c9fddbc4 919 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 920 if (host->flags & SDHCI_USE_ADMA)
921 sdhci_adma_table_post(host, data);
922 else {
923 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
924 data->sg_len, (data->flags & MMC_DATA_READ) ?
925 DMA_FROM_DEVICE : DMA_TO_DEVICE);
926 }
d129bceb
PO		 927 }
928
929 /*
c9b74c5b
PO		 930 * The specification states that the block count register must
931 * be updated, but it does not specify at what point in the
932 * data flow. That makes the register entirely useless to read
933 * back so we have to assume that nothing made it to the card
934 * in the event of an error.
d129bceb 935 */
c9b74c5b
PO		 936 if (data->error)
937 data->bytes_xfered = 0;
d129bceb 938 else
c9b74c5b 939 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 940
e89d456f
AW		 941 /*
942 * Need to send CMD12 if -
943 * a) open-ended multiblock transfer (no CMD23)
944 * b) error in multiblock transfer
945 */
946 if (data->stop &&
947 (data->error ||
948 !host->mrq->sbc)) {
949
d129bceb
PO		 950 /*
951 * The controller needs a reset of internal state machines
952 * upon error conditions.
953 */
17b0429d 954 if (data->error) {
03231f9b
RK		 955 sdhci_do_reset(host, SDHCI_RESET_CMD);
956 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 957 }
958
959 sdhci_send_command(host, data->stop);
960 } else
961 tasklet_schedule(&host->finish_tasklet);
962}
963
c0e55129 964void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 965{
966 int flags;
fd2208d7 967 u32 mask;
7cb2c76f 968 unsigned long timeout;
d129bceb
PO		 969
970 WARN_ON(host->cmd);
971
d129bceb 972 /* Wait max 10 ms */
7cb2c76f 973 timeout = 10;
fd2208d7
PO		 974
975 mask = SDHCI_CMD_INHIBIT;
976 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
977 mask |= SDHCI_DATA_INHIBIT;
978
979 /* We shouldn't wait for data inihibit for stop commands, even
980 though they might use busy signaling */
981 if (host->mrq->data && (cmd == host->mrq->data->stop))
982 mask &= ~SDHCI_DATA_INHIBIT;
983
4e4141a5 984 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 985 if (timeout == 0) {
a3c76eb9 986 pr_err("%s: Controller never released "
acf1da45 987 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 988 sdhci_dumpregs(host);
17b0429d 989 cmd->error = -EIO;
d129bceb
PO		 990 tasklet_schedule(&host->finish_tasklet);
991 return;
992 }
7cb2c76f
PO		 993 timeout--;
994 mdelay(1);
995 }
d129bceb 996
3e1a6892 997 timeout = jiffies;
1d4d7744
UH		 998 if (!cmd->data && cmd->busy_timeout > 9000)
999 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1000 else
1001 timeout += 10 * HZ;
1002 mod_timer(&host->timer, timeout);
d129bceb
PO		 1003
1004 host->cmd = cmd;
1005
a3c7778f 1006 sdhci_prepare_data(host, cmd);
d129bceb 1007
4e4141a5 1008 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1009
e89d456f 1010 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1011
d129bceb 1012 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1013 pr_err("%s: Unsupported response type!\n",
d129bceb 1014 mmc_hostname(host->mmc));
17b0429d 1015 cmd->error = -EINVAL;
d129bceb
PO		 1016 tasklet_schedule(&host->finish_tasklet);
1017 return;
1018 }
1019
1020 if (!(cmd->flags & MMC_RSP_PRESENT))
1021 flags = SDHCI_CMD_RESP_NONE;
1022 else if (cmd->flags & MMC_RSP_136)
1023 flags = SDHCI_CMD_RESP_LONG;
1024 else if (cmd->flags & MMC_RSP_BUSY)
1025 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1026 else
1027 flags = SDHCI_CMD_RESP_SHORT;
1028
1029 if (cmd->flags & MMC_RSP_CRC)
1030 flags |= SDHCI_CMD_CRC;
1031 if (cmd->flags & MMC_RSP_OPCODE)
1032 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1033
1034 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1035 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1036 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1037 flags |= SDHCI_CMD_DATA;
1038
4e4141a5 1039 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1040}
c0e55129 1041EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1042
1043static void sdhci_finish_command(struct sdhci_host *host)
1044{
1045 int i;
1046
1047 BUG_ON(host->cmd == NULL);
1048
1049 if (host->cmd->flags & MMC_RSP_PRESENT) {
1050 if (host->cmd->flags & MMC_RSP_136) {
1051 /* CRC is stripped so we need to do some shifting. */
1052 for (i = 0;i < 4;i++) {
4e4141a5 1053 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1054 SDHCI_RESPONSE + (3-i)*4) << 8;
1055 if (i != 3)
1056 host->cmd->resp[i] |=
4e4141a5 1057 sdhci_readb(host,
d129bceb
PO		 1058 SDHCI_RESPONSE + (3-i)*4-1);
1059 }
1060 } else {
4e4141a5 1061 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1062 }
1063 }
1064
17b0429d 1065 host->cmd->error = 0;
d129bceb 1066
e89d456f
AW		 1067 /* Finished CMD23, now send actual command. */
1068 if (host->cmd == host->mrq->sbc) {
1069 host->cmd = NULL;
1070 sdhci_send_command(host, host->mrq->cmd);
1071 } else {
e538fbe8 1072
e89d456f
AW		 1073 /* Processed actual command. */
1074 if (host->data && host->data_early)
1075 sdhci_finish_data(host);
d129bceb 1076
e89d456f
AW		 1077 if (!host->cmd->data)
1078 tasklet_schedule(&host->finish_tasklet);
1079
1080 host->cmd = NULL;
1081 }
d129bceb
PO		 1082}
1083
52983382
KL		 1084static u16 sdhci_get_preset_value(struct sdhci_host *host)
1085{
d975f121 1086 u16 preset = 0;
52983382 1087
d975f121
RK		 1088 switch (host->timing) {
1089 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1090 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1091 break;
d975f121 1092 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1093 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1094 break;
d975f121 1095 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1096 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1097 break;
d975f121
RK		 1098 case MMC_TIMING_UHS_SDR104:
1099 case MMC_TIMING_MMC_HS200:
52983382
KL		 1100 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1101 break;
d975f121 1102 case MMC_TIMING_UHS_DDR50:
52983382
KL		 1103 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1104 break;
1105 default:
1106 pr_warn("%s: Invalid UHS-I mode selected\n",
1107 mmc_hostname(host->mmc));
1108 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1109 break;
1110 }
1111 return preset;
1112}
1113
1771059c 1114void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1115{
c3ed3877 1116 int div = 0; /* Initialized for compiler warning */
df16219f 1117 int real_div = div, clk_mul = 1;
c3ed3877 1118 u16 clk = 0;
7cb2c76f 1119 unsigned long timeout;
d129bceb 1120
1650d0c7
RK		 1121 host->mmc->actual_clock = 0;
1122
4e4141a5 1123 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1124
1125 if (clock == 0)
373073ef 1126 return;
d129bceb 1127
85105c53 1128 if (host->version >= SDHCI_SPEC_300) {
52983382
KL		 1129 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1130 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1131 u16 pre_val;
1132
1133 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1134 pre_val = sdhci_get_preset_value(host);
1135 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1136 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1137 if (host->clk_mul &&
1138 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1139 clk = SDHCI_PROG_CLOCK_MODE;
1140 real_div = div + 1;
1141 clk_mul = host->clk_mul;
1142 } else {
1143 real_div = max_t(int, 1, div << 1);
1144 }
1145 goto clock_set;
1146 }
1147
c3ed3877
AN		 1148 /*
1149 * Check if the Host Controller supports Programmable Clock
1150 * Mode.
1151 */
1152 if (host->clk_mul) {
52983382
KL		 1153 for (div = 1; div <= 1024; div++) {
1154 if ((host->max_clk * host->clk_mul / div)
1155 <= clock)
1156 break;
1157 }
c3ed3877 1158 /*
52983382
KL		 1159 * Set Programmable Clock Mode in the Clock
1160 * Control register.
c3ed3877 1161 */
52983382
KL		 1162 clk = SDHCI_PROG_CLOCK_MODE;
1163 real_div = div;
1164 clk_mul = host->clk_mul;
1165 div--;
c3ed3877
AN		 1166 } else {
1167 /* Version 3.00 divisors must be a multiple of 2. */
1168 if (host->max_clk <= clock)
1169 div = 1;
1170 else {
1171 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1172 div += 2) {
1173 if ((host->max_clk / div) <= clock)
1174 break;
1175 }
85105c53 1176 }
df16219f 1177 real_div = div;
c3ed3877 1178 div >>= 1;
85105c53
ZG		 1179 }
1180 } else {
1181 /* Version 2.00 divisors must be a power of 2. */
0397526d 1182 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1183 if ((host->max_clk / div) <= clock)
1184 break;
1185 }
df16219f 1186 real_div = div;
c3ed3877 1187 div >>= 1;
d129bceb 1188 }
d129bceb 1189
52983382 1190clock_set:
df16219f
GC		 1191 if (real_div)
1192 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1193
c3ed3877 1194 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1195 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1196 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1197 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1198 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1199
27f6cb16
CB		 1200 /* Wait max 20 ms */
1201 timeout = 20;
4e4141a5 1202 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1203 & SDHCI_CLOCK_INT_STABLE)) {
1204 if (timeout == 0) {
a3c76eb9 1205 pr_err("%s: Internal clock never "
acf1da45 1206 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1207 sdhci_dumpregs(host);
1208 return;
1209 }
7cb2c76f
PO		 1210 timeout--;
1211 mdelay(1);
1212 }
d129bceb
PO		 1213
1214 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1215 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1216}
1771059c 1217EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1218
ceb6143b 1219static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1220{
8364248a 1221 u8 pwr = 0;
146ad66e 1222
8364248a 1223 if (power != (unsigned short)-1) {
ae628903
PO		 1224 switch (1 << power) {
1225 case MMC_VDD_165_195:
1226 pwr = SDHCI_POWER_180;
1227 break;
1228 case MMC_VDD_29_30:
1229 case MMC_VDD_30_31:
1230 pwr = SDHCI_POWER_300;
1231 break;
1232 case MMC_VDD_32_33:
1233 case MMC_VDD_33_34:
1234 pwr = SDHCI_POWER_330;
1235 break;
1236 default:
1237 BUG();
1238 }
1239 }
1240
1241 if (host->pwr == pwr)
ceb6143b 1242 return -1;
146ad66e 1243
ae628903
PO		 1244 host->pwr = pwr;
1245
1246 if (pwr == 0) {
4e4141a5 1247 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1248 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1249 sdhci_runtime_pm_bus_off(host);
ceb6143b 1250 return 0;
9e9dc5f2
DS		 1251 }
1252
1253 /*
1254 * Spec says that we should clear the power reg before setting
1255 * a new value. Some controllers don't seem to like this though.
1256 */
b8c86fc5 1257 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1258 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1259
e08c1694 1260 /*
c71f6512 1261 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1262 * and set turn on power at the same time, so set the voltage first.
1263 */
11a2f1b7 1264 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1265 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1266
ae628903 1267 pwr |= SDHCI_POWER_ON;
146ad66e 1268
ae628903 1269 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1270
f0710a55
AH		 1271 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1272 sdhci_runtime_pm_bus_on(host);
1273
557b0697
HW		 1274 /*
1275 * Some controllers need an extra 10ms delay of 10ms before they
1276 * can apply clock after applying power
1277 */
11a2f1b7 1278 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1279 mdelay(10);
ceb6143b
AH		 1280
1281 return power;
146ad66e
PO		 1282}
1283
d129bceb
PO		 1284/*****************************************************************************\
1285 * *
1286 * MMC callbacks *
1287 * *
1288\*****************************************************************************/
1289
1290static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1291{
1292 struct sdhci_host *host;
505a8680 1293 int present;
d129bceb 1294 unsigned long flags;
473b095a 1295 u32 tuning_opcode;
d129bceb
PO		 1296
1297 host = mmc_priv(mmc);
1298
66fd8ad5
AH		 1299 sdhci_runtime_pm_get(host);
1300
d129bceb
PO		 1301 spin_lock_irqsave(&host->lock, flags);
1302
1303 WARN_ON(host->mrq != NULL);
1304
f9134319 1305#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1306 sdhci_activate_led(host);
2f730fec 1307#endif
e89d456f
AW		 1308
1309 /*
1310 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1311 * requests if Auto-CMD12 is enabled.
1312 */
1313 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1314 if (mrq->stop) {
1315 mrq->data->stop = NULL;
1316 mrq->stop = NULL;
1317 }
1318 }
d129bceb
PO		 1319
1320 host->mrq = mrq;
1321
505a8680
SG		 1322 /*
1323 * Firstly check card presence from cd-gpio. The return could
1324 * be one of the following possibilities:
1325 * negative: cd-gpio is not available
1326 * zero: cd-gpio is used, and card is removed
1327 * one: cd-gpio is used, and card is present
1328 */
1329 present = mmc_gpio_get_cd(host->mmc);
1330 if (present < 0) {
1331 /* If polling, assume that the card is always present. */
1332 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1333 present = 1;
1334 else
1335 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1336 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1337 }
1338
68d1fb7e 1339 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1340 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1341 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1342 } else {
1343 u32 present_state;
1344
1345 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1346 /*
1347 * Check if the re-tuning timer has already expired and there
1348 * is no on-going data transfer. If so, we need to execute
1349 * tuning procedure before sending command.
1350 */
1351 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1352 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1353 if (mmc->card) {
1354 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1355 tuning_opcode =
1356 mmc->card->type == MMC_TYPE_MMC ?
1357 MMC_SEND_TUNING_BLOCK_HS200 :
1358 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1359
1360 /* Here we need to set the host->mrq to NULL,
1361 * in case the pending finish_tasklet
1362 * finishes it incorrectly.
1363 */
1364 host->mrq = NULL;
1365
14efd957
CB		 1366 spin_unlock_irqrestore(&host->lock, flags);
1367 sdhci_execute_tuning(mmc, tuning_opcode);
1368 spin_lock_irqsave(&host->lock, flags);
1369
1370 /* Restore original mmc_request structure */
1371 host->mrq = mrq;
1372 }
cf2b5eea
AN		 1373 }
1374
8edf6371 1375 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1376 sdhci_send_command(host, mrq->sbc);
1377 else
1378 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1379 }
d129bceb 1380
5f25a66f 1381 mmiowb();
d129bceb
PO		 1382 spin_unlock_irqrestore(&host->lock, flags);
1383}
1384
2317f56c
RK		 1385void sdhci_set_bus_width(struct sdhci_host *host, int width)
1386{
1387 u8 ctrl;
1388
1389 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1390 if (width == MMC_BUS_WIDTH_8) {
1391 ctrl &= ~SDHCI_CTRL_4BITBUS;
1392 if (host->version >= SDHCI_SPEC_300)
1393 ctrl |= SDHCI_CTRL_8BITBUS;
1394 } else {
1395 if (host->version >= SDHCI_SPEC_300)
1396 ctrl &= ~SDHCI_CTRL_8BITBUS;
1397 if (width == MMC_BUS_WIDTH_4)
1398 ctrl |= SDHCI_CTRL_4BITBUS;
1399 else
1400 ctrl &= ~SDHCI_CTRL_4BITBUS;
1401 }
1402 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1403}
1404EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1405
96d7b78c
RK		 1406void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1407{
1408 u16 ctrl_2;
1409
1410 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1411 /* Select Bus Speed Mode for host */
1412 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1413 if ((timing == MMC_TIMING_MMC_HS200) ||
1414 (timing == MMC_TIMING_UHS_SDR104))
1415 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1416 else if (timing == MMC_TIMING_UHS_SDR12)
1417 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1418 else if (timing == MMC_TIMING_UHS_SDR25)
1419 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1420 else if (timing == MMC_TIMING_UHS_SDR50)
1421 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1422 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1423 (timing == MMC_TIMING_MMC_DDR52))
1424 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1425 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1426}
1427EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1428
66fd8ad5 1429static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1430{
d129bceb 1431 unsigned long flags;
ceb6143b 1432 int vdd_bit = -1;
d129bceb
PO		 1433 u8 ctrl;
1434
d129bceb
PO		 1435 spin_lock_irqsave(&host->lock, flags);
1436
ceb6143b
AH		 1437 if (host->flags & SDHCI_DEVICE_DEAD) {
1438 spin_unlock_irqrestore(&host->lock, flags);
1439 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1440 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1441 return;
1442 }
1e72859e 1443
d129bceb
PO		 1444 /*
1445 * Reset the chip on each power off.
1446 * Should clear out any weird states.
1447 */
1448 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1449 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1450 sdhci_reinit(host);
d129bceb
PO		 1451 }
1452
52983382 1453 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1454 (ios->power_mode == MMC_POWER_UP) &&
1455 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1456 sdhci_enable_preset_value(host, false);
1457
373073ef 1458 if (!ios->clock || ios->clock != host->clock) {
1771059c 1459 host->ops->set_clock(host, ios->clock);
373073ef
RK		 1460 host->clock = ios->clock;
1461 }
d129bceb
PO		 1462
1463 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1464 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1465 else
ceb6143b
AH		 1466 vdd_bit = sdhci_set_power(host, ios->vdd);
1467
1468 if (host->vmmc && vdd_bit != -1) {
1469 spin_unlock_irqrestore(&host->lock, flags);
1470 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1471 spin_lock_irqsave(&host->lock, flags);
1472 }
d129bceb 1473
643a81ff
PR		 1474 if (host->ops->platform_send_init_74_clocks)
1475 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1476
2317f56c 1477 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1478
15ec4461 1479 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1480
3ab9c8da
PR		 1481 if ((ios->timing == MMC_TIMING_SD_HS ||
1482 ios->timing == MMC_TIMING_MMC_HS)
1483 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1484 ctrl |= SDHCI_CTRL_HISPD;
1485 else
1486 ctrl &= ~SDHCI_CTRL_HISPD;
1487
d6d50a15 1488 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1489 u16 clk, ctrl_2;
49c468fc
AN		 1490
1491 /* In case of UHS-I modes, set High Speed Enable */
069c9f14 1492 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1493 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1494 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1495 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1496 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1497 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1498 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1499
1500 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1501 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1502 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1503 /*
1504 * We only need to set Driver Strength if the
1505 * preset value enable is not set.
1506 */
1507 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1508 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1509 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1510 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1511 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1512
1513 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1514 } else {
1515 /*
1516 * According to SDHC Spec v3.00, if the Preset Value
1517 * Enable in the Host Control 2 register is set, we
1518 * need to reset SD Clock Enable before changing High
1519 * Speed Enable to avoid generating clock gliches.
1520 */
758535c4
AN		 1521
1522 /* Reset SD Clock Enable */
1523 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1524 clk &= ~SDHCI_CLOCK_CARD_EN;
1525 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1526
1527 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1528
1529 /* Re-enable SD Clock */
1771059c 1530 host->ops->set_clock(host, host->clock);
d6d50a15 1531 }
49c468fc 1532
49c468fc
AN		 1533
1534 /* Reset SD Clock Enable */
1535 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1536 clk &= ~SDHCI_CLOCK_CARD_EN;
1537 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1538
96d7b78c 1539 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1540 host->timing = ios->timing;
49c468fc 1541
52983382
KL		 1542 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1543 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1544 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1545 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1546 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1547 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1548 u16 preset;
1549
1550 sdhci_enable_preset_value(host, true);
1551 preset = sdhci_get_preset_value(host);
1552 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1553 >> SDHCI_PRESET_DRV_SHIFT;
1554 }
1555
49c468fc 1556 /* Re-enable SD Clock */
1771059c 1557 host->ops->set_clock(host, host->clock);
758535c4
AN		 1558 } else
1559 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1560
b8352260
LD		 1561 /*
1562 * Some (ENE) controllers go apeshit on some ios operation,
1563 * signalling timeout and CRC errors even on CMD0. Resetting
1564 * it on each ios seems to solve the problem.
1565 */
b8c86fc5 1566 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1567 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1568
5f25a66f 1569 mmiowb();
d129bceb
PO		 1570 spin_unlock_irqrestore(&host->lock, flags);
1571}
1572
66fd8ad5
AH		 1573static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1574{
1575 struct sdhci_host *host = mmc_priv(mmc);
1576
1577 sdhci_runtime_pm_get(host);
1578 sdhci_do_set_ios(host, ios);
1579 sdhci_runtime_pm_put(host);
1580}
1581
94144a46
KL		 1582static int sdhci_do_get_cd(struct sdhci_host *host)
1583{
1584 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1585
1586 if (host->flags & SDHCI_DEVICE_DEAD)
1587 return 0;
1588
1589 /* If polling/nonremovable, assume that the card is always present. */
1590 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1591 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1592 return 1;
1593
1594 /* Try slot gpio detect */
1595 if (!IS_ERR_VALUE(gpio_cd))
1596 return !!gpio_cd;
1597
1598 /* Host native card detect */
1599 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1600}
1601
1602static int sdhci_get_cd(struct mmc_host *mmc)
1603{
1604 struct sdhci_host *host = mmc_priv(mmc);
1605 int ret;
1606
1607 sdhci_runtime_pm_get(host);
1608 ret = sdhci_do_get_cd(host);
1609 sdhci_runtime_pm_put(host);
1610 return ret;
1611}
1612
66fd8ad5 1613static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1614{
d129bceb 1615 unsigned long flags;
2dfb579c 1616 int is_readonly;
d129bceb 1617
d129bceb
PO		 1618 spin_lock_irqsave(&host->lock, flags);
1619
1e72859e 1620 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1621 is_readonly = 0;
1622 else if (host->ops->get_ro)
1623 is_readonly = host->ops->get_ro(host);
1e72859e 1624 else
2dfb579c
WS		 1625 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1626 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1627
1628 spin_unlock_irqrestore(&host->lock, flags);
1629
2dfb579c
WS		 1630 /* This quirk needs to be replaced by a callback-function later */
1631 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1632 !is_readonly : is_readonly;
d129bceb
PO		 1633}
1634
82b0e23a
TI		 1635#define SAMPLE_COUNT 5
1636
66fd8ad5 1637static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1638{
82b0e23a
TI		 1639 int i, ro_count;
1640
82b0e23a 1641 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1642 return sdhci_check_ro(host);
82b0e23a
TI		 1643
1644 ro_count = 0;
1645 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1646 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1647 if (++ro_count > SAMPLE_COUNT / 2)
1648 return 1;
1649 }
1650 msleep(30);
1651 }
1652 return 0;
1653}
1654
20758b66
AH		 1655static void sdhci_hw_reset(struct mmc_host *mmc)
1656{
1657 struct sdhci_host *host = mmc_priv(mmc);
1658
1659 if (host->ops && host->ops->hw_reset)
1660 host->ops->hw_reset(host);
1661}
1662
66fd8ad5 1663static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1664{
66fd8ad5
AH		 1665 struct sdhci_host *host = mmc_priv(mmc);
1666 int ret;
f75979b7 1667
66fd8ad5
AH		 1668 sdhci_runtime_pm_get(host);
1669 ret = sdhci_do_get_ro(host);
1670 sdhci_runtime_pm_put(host);
1671 return ret;
1672}
f75979b7 1673
66fd8ad5
AH		 1674static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1675{
be138554 1676 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1677 if (enable)
b537f94c 1678 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1679 else
b537f94c
RK		 1680 host->ier &= ~SDHCI_INT_CARD_INT;
1681
1682 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1683 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1684 mmiowb();
1685 }
66fd8ad5
AH		 1686}
1687
1688static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1689{
1690 struct sdhci_host *host = mmc_priv(mmc);
1691 unsigned long flags;
f75979b7 1692
ef104333
RK		 1693 sdhci_runtime_pm_get(host);
1694
66fd8ad5 1695 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1696 if (enable)
1697 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1698 else
1699 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1700
66fd8ad5 1701 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1702 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1703
1704 sdhci_runtime_pm_put(host);
f75979b7
PO		 1705}
1706
20b92a30 1707static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1708 struct mmc_ios *ios)
f2119df6 1709{
20b92a30 1710 u16 ctrl;
6231f3de 1711 int ret;
f2119df6 1712
20b92a30
KL		 1713 /*
1714 * Signal Voltage Switching is only applicable for Host Controllers
1715 * v3.00 and above.
1716 */
1717 if (host->version < SDHCI_SPEC_300)
1718 return 0;
6231f3de 1719
f2119df6 1720 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1721
21f5998f 1722 switch (ios->signal_voltage) {
20b92a30
KL		 1723 case MMC_SIGNAL_VOLTAGE_330:
1724 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1725 ctrl &= ~SDHCI_CTRL_VDD_180;
1726 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1727
20b92a30
KL		 1728 if (host->vqmmc) {
1729 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1730 if (ret) {
1731 pr_warning("%s: Switching to 3.3V signalling voltage "
1732 " failed\n", mmc_hostname(host->mmc));
1733 return -EIO;
1734 }
1735 }
1736 /* Wait for 5ms */
1737 usleep_range(5000, 5500);
f2119df6 1738
20b92a30
KL		 1739 /* 3.3V regulator output should be stable within 5 ms */
1740 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1741 if (!(ctrl & SDHCI_CTRL_VDD_180))
1742 return 0;
6231f3de 1743
20b92a30
KL		 1744 pr_warning("%s: 3.3V regulator output did not became stable\n",
1745 mmc_hostname(host->mmc));
1746
1747 return -EAGAIN;
1748 case MMC_SIGNAL_VOLTAGE_180:
1749 if (host->vqmmc) {
1750 ret = regulator_set_voltage(host->vqmmc,
1751 1700000, 1950000);
1752 if (ret) {
1753 pr_warning("%s: Switching to 1.8V signalling voltage "
1754 " failed\n", mmc_hostname(host->mmc));
1755 return -EIO;
1756 }
1757 }
6231f3de 1758
6231f3de
PR		 1759 /*
1760 * Enable 1.8V Signal Enable in the Host Control2
1761 * register
1762 */
20b92a30
KL		 1763 ctrl |= SDHCI_CTRL_VDD_180;
1764 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1765
20b92a30
KL		 1766 /* Wait for 5ms */
1767 usleep_range(5000, 5500);
f2119df6 1768
20b92a30
KL		 1769 /* 1.8V regulator output should be stable within 5 ms */
1770 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1771 if (ctrl & SDHCI_CTRL_VDD_180)
1772 return 0;
f2119df6 1773
20b92a30
KL		 1774 pr_warning("%s: 1.8V regulator output did not became stable\n",
1775 mmc_hostname(host->mmc));
f2119df6 1776
20b92a30
KL		 1777 return -EAGAIN;
1778 case MMC_SIGNAL_VOLTAGE_120:
1779 if (host->vqmmc) {
1780 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1781 if (ret) {
1782 pr_warning("%s: Switching to 1.2V signalling voltage "
1783 " failed\n", mmc_hostname(host->mmc));
1784 return -EIO;
f2119df6
AN		 1785 }
1786 }
6231f3de 1787 return 0;
20b92a30 1788 default:
f2119df6
AN		 1789 /* No signal voltage switch required */
1790 return 0;
20b92a30 1791 }
f2119df6
AN		 1792}
1793
66fd8ad5 1794static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1795 struct mmc_ios *ios)
66fd8ad5
AH		 1796{
1797 struct sdhci_host *host = mmc_priv(mmc);
1798 int err;
1799
1800 if (host->version < SDHCI_SPEC_300)
1801 return 0;
1802 sdhci_runtime_pm_get(host);
21f5998f 1803 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1804 sdhci_runtime_pm_put(host);
1805 return err;
1806}
1807
20b92a30
KL		 1808static int sdhci_card_busy(struct mmc_host *mmc)
1809{
1810 struct sdhci_host *host = mmc_priv(mmc);
1811 u32 present_state;
1812
1813 sdhci_runtime_pm_get(host);
1814 /* Check whether DAT[3:0] is 0000 */
1815 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1816 sdhci_runtime_pm_put(host);
1817
1818 return !(present_state & SDHCI_DATA_LVL_MASK);
1819}
1820
069c9f14 1821static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1822{
4b6f37d3 1823 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1824 u16 ctrl;
b513ea25
AN		 1825 int tuning_loop_counter = MAX_TUNING_LOOP;
1826 unsigned long timeout;
1827 int err = 0;
2b35bd83 1828 unsigned long flags;
b513ea25 1829
66fd8ad5 1830 sdhci_runtime_pm_get(host);
2b35bd83 1831 spin_lock_irqsave(&host->lock, flags);
b513ea25 1832
b513ea25 1833 /*
069c9f14
G		 1834 * The Host Controller needs tuning only in case of SDR104 mode
1835 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1836 * Capabilities register.
069c9f14
G		 1837 * If the Host Controller supports the HS200 mode then the
1838 * tuning function has to be executed.
b513ea25 1839 */
4b6f37d3
RK		 1840 switch (host->timing) {
1841 case MMC_TIMING_MMC_HS200:
1842 case MMC_TIMING_UHS_SDR104:
1843 break;
1844
1845 case MMC_TIMING_UHS_SDR50:
1846 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1847 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1848 break;
1849 /* FALLTHROUGH */
1850
1851 default:
2b35bd83 1852 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 1853 sdhci_runtime_pm_put(host);
b513ea25
AN		 1854 return 0;
1855 }
1856
45251812 1857 if (host->ops->platform_execute_tuning) {
2b35bd83 1858 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1859 err = host->ops->platform_execute_tuning(host, opcode);
1860 sdhci_runtime_pm_put(host);
1861 return err;
1862 }
1863
4b6f37d3
RK		 1864 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1865 ctrl |= SDHCI_CTRL_EXEC_TUNING;
b513ea25
AN		 1866 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1867
1868 /*
1869 * As per the Host Controller spec v3.00, tuning command
1870 * generates Buffer Read Ready interrupt, so enable that.
1871 *
1872 * Note: The spec clearly says that when tuning sequence
1873 * is being performed, the controller does not generate
1874 * interrupts other than Buffer Read Ready interrupt. But
1875 * to make sure we don't hit a controller bug, we _only_
1876 * enable Buffer Read Ready interrupt here.
1877 */
b537f94c
RK		 1878 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1879 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1880
1881 /*
1882 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1883 * of loops reaches 40 times or a timeout of 150ms occurs.
1884 */
1885 timeout = 150;
1886 do {
1887 struct mmc_command cmd = {0};
66fd8ad5 1888 struct mmc_request mrq = {NULL};
b513ea25
AN		 1889
1890 if (!tuning_loop_counter && !timeout)
1891 break;
1892
069c9f14 1893 cmd.opcode = opcode;
b513ea25
AN		 1894 cmd.arg = 0;
1895 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1896 cmd.retries = 0;
1897 cmd.data = NULL;
1898 cmd.error = 0;
1899
1900 mrq.cmd = &cmd;
1901 host->mrq = &mrq;
1902
1903 /*
1904 * In response to CMD19, the card sends 64 bytes of tuning
1905 * block to the Host Controller. So we set the block size
1906 * to 64 here.
1907 */
069c9f14
G		 1908 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1909 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1910 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1911 SDHCI_BLOCK_SIZE);
1912 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1913 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1914 SDHCI_BLOCK_SIZE);
1915 } else {
1916 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1917 SDHCI_BLOCK_SIZE);
1918 }
b513ea25
AN		 1919
1920 /*
1921 * The tuning block is sent by the card to the host controller.
1922 * So we set the TRNS_READ bit in the Transfer Mode register.
1923 * This also takes care of setting DMA Enable and Multi Block
1924 * Select in the same register to 0.
1925 */
1926 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1927
1928 sdhci_send_command(host, &cmd);
1929
1930 host->cmd = NULL;
1931 host->mrq = NULL;
1932
2b35bd83 1933 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1934 /* Wait for Buffer Read Ready interrupt */
1935 wait_event_interruptible_timeout(host->buf_ready_int,
1936 (host->tuning_done == 1),
1937 msecs_to_jiffies(50));
2b35bd83 1938 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1939
1940 if (!host->tuning_done) {
a3c76eb9 1941 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1942 "Buffer Read Ready interrupt during tuning "
1943 "procedure, falling back to fixed sampling "
1944 "clock\n");
1945 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1946 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1947 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1948 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1949
1950 err = -EIO;
1951 goto out;
1952 }
1953
1954 host->tuning_done = 0;
1955
1956 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1957 tuning_loop_counter--;
1958 timeout--;
197160d5
NS		 1959
1960 /* eMMC spec does not require a delay between tuning cycles */
1961 if (opcode == MMC_SEND_TUNING_BLOCK)
1962 mdelay(1);
b513ea25
AN		 1963 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1964
1965 /*
1966 * The Host Driver has exhausted the maximum number of loops allowed,
1967 * so use fixed sampling frequency.
1968 */
1969 if (!tuning_loop_counter || !timeout) {
1970 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1971 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
114f2bf6 1972 err = -EIO;
b513ea25
AN		 1973 } else {
1974 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1975 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1976 " failed, falling back to fixed sampling"
1977 " clock\n");
1978 err = -EIO;
1979 }
1980 }
1981
1982out:
cf2b5eea
AN		 1983 /*
1984 * If this is the very first time we are here, we start the retuning
1985 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1986 * flag won't be set, we check this condition before actually starting
1987 * the timer.
1988 */
1989 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1990 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 1991 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 1992 mod_timer(&host->tuning_timer, jiffies +
1993 host->tuning_count * HZ);
1994 /* Tuning mode 1 limits the maximum data length to 4MB */
1995 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2bc02485 1996 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
cf2b5eea
AN		 1997 host->flags &= ~SDHCI_NEEDS_RETUNING;
1998 /* Reload the new initial value for timer */
2bc02485
AS		 1999 mod_timer(&host->tuning_timer, jiffies +
2000 host->tuning_count * HZ);
cf2b5eea
AN		 2001 }
2002
2003 /*
2004 * In case tuning fails, host controllers which support re-tuning can
2005 * try tuning again at a later time, when the re-tuning timer expires.
2006 * So for these controllers, we return 0. Since there might be other
2007 * controllers who do not have this capability, we return error for
973905fe
AL		 2008 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2009 * a retuning timer to do the retuning for the card.
cf2b5eea 2010 */
973905fe 2011 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2012 err = 0;
2013
b537f94c
RK		 2014 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2015 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2b35bd83 2016 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2017 sdhci_runtime_pm_put(host);
b513ea25
AN		 2018
2019 return err;
2020}
2021
52983382
KL		 2022
2023static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2024{
4d55c5a1 2025 u16 ctrl;
4d55c5a1 2026
4d55c5a1
AN		 2027 /* Host Controller v3.00 defines preset value registers */
2028 if (host->version < SDHCI_SPEC_300)
2029 return;
2030
4d55c5a1
AN		 2031 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2032
2033 /*
2034 * We only enable or disable Preset Value if they are not already
2035 * enabled or disabled respectively. Otherwise, we bail out.
2036 */
2037 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2038 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2039 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2040 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 2041 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2042 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2043 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2044 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1 2045 }
66fd8ad5
AH		 2046}
2047
71e69211 2048static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2049{
71e69211 2050 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2051 unsigned long flags;
2052
722e1280
CD		 2053 /* First check if client has provided their own card event */
2054 if (host->ops->card_event)
2055 host->ops->card_event(host);
2056
d129bceb
PO		 2057 spin_lock_irqsave(&host->lock, flags);
2058
66fd8ad5 2059 /* Check host->mrq first in case we are runtime suspended */
9668d765 2060 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2061 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2062 mmc_hostname(host->mmc));
a3c76eb9 2063 pr_err("%s: Resetting controller.\n",
66fd8ad5 2064 mmc_hostname(host->mmc));
d129bceb 2065
03231f9b
RK		 2066 sdhci_do_reset(host, SDHCI_RESET_CMD);
2067 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2068
66fd8ad5
AH		 2069 host->mrq->cmd->error = -ENOMEDIUM;
2070 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2071 }
2072
2073 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2074}
2075
2076static const struct mmc_host_ops sdhci_ops = {
2077 .request = sdhci_request,
2078 .set_ios = sdhci_set_ios,
94144a46 2079 .get_cd = sdhci_get_cd,
71e69211
GL		 2080 .get_ro = sdhci_get_ro,
2081 .hw_reset = sdhci_hw_reset,
2082 .enable_sdio_irq = sdhci_enable_sdio_irq,
2083 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2084 .execute_tuning = sdhci_execute_tuning,
71e69211 2085 .card_event = sdhci_card_event,
20b92a30 2086 .card_busy = sdhci_card_busy,
71e69211
GL		 2087};
2088
2089/*****************************************************************************\
2090 * *
2091 * Tasklets *
2092 * *
2093\*****************************************************************************/
2094
d129bceb
PO		 2095static void sdhci_tasklet_finish(unsigned long param)
2096{
2097 struct sdhci_host *host;
2098 unsigned long flags;
2099 struct mmc_request *mrq;
2100
2101 host = (struct sdhci_host*)param;
2102
66fd8ad5
AH		 2103 spin_lock_irqsave(&host->lock, flags);
2104
0c9c99a7
CB		 2105 /*
2106 * If this tasklet gets rescheduled while running, it will
2107 * be run again afterwards but without any active request.
2108 */
66fd8ad5
AH		 2109 if (!host->mrq) {
2110 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2111 return;
66fd8ad5 2112 }
d129bceb
PO		 2113
2114 del_timer(&host->timer);
2115
2116 mrq = host->mrq;
2117
d129bceb
PO		 2118 /*
2119 * The controller needs a reset of internal state machines
2120 * upon error conditions.
2121 */
1e72859e 2122 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2123 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2124 (mrq->data && (mrq->data->error ||
2125 (mrq->data->stop && mrq->data->stop->error))) ||
2126 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2127
2128 /* Some controllers need this kick or reset won't work here */
8213af3b 2129 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2130 /* This is to force an update */
1771059c 2131 host->ops->set_clock(host, host->clock);
645289dc
PO		 2132
2133 /* Spec says we should do both at the same time, but Ricoh
2134 controllers do not like that. */
03231f9b
RK		 2135 sdhci_do_reset(host, SDHCI_RESET_CMD);
2136 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2137 }
2138
2139 host->mrq = NULL;
2140 host->cmd = NULL;
2141 host->data = NULL;
2142
f9134319 2143#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2144 sdhci_deactivate_led(host);
2f730fec 2145#endif
d129bceb 2146
5f25a66f 2147 mmiowb();
d129bceb
PO		 2148 spin_unlock_irqrestore(&host->lock, flags);
2149
2150 mmc_request_done(host->mmc, mrq);
66fd8ad5 2151 sdhci_runtime_pm_put(host);
d129bceb
PO		 2152}
2153
2154static void sdhci_timeout_timer(unsigned long data)
2155{
2156 struct sdhci_host *host;
2157 unsigned long flags;
2158
2159 host = (struct sdhci_host*)data;
2160
2161 spin_lock_irqsave(&host->lock, flags);
2162
2163 if (host->mrq) {
a3c76eb9 2164 pr_err("%s: Timeout waiting for hardware "
acf1da45 2165 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2166 sdhci_dumpregs(host);
2167
2168 if (host->data) {
17b0429d 2169 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2170 sdhci_finish_data(host);
2171 } else {
2172 if (host->cmd)
17b0429d 2173 host->cmd->error = -ETIMEDOUT;
d129bceb 2174 else
17b0429d 2175 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2176
2177 tasklet_schedule(&host->finish_tasklet);
2178 }
2179 }
2180
5f25a66f 2181 mmiowb();
d129bceb
PO		 2182 spin_unlock_irqrestore(&host->lock, flags);
2183}
2184
cf2b5eea
AN		 2185static void sdhci_tuning_timer(unsigned long data)
2186{
2187 struct sdhci_host *host;
2188 unsigned long flags;
2189
2190 host = (struct sdhci_host *)data;
2191
2192 spin_lock_irqsave(&host->lock, flags);
2193
2194 host->flags |= SDHCI_NEEDS_RETUNING;
2195
2196 spin_unlock_irqrestore(&host->lock, flags);
2197}
2198
d129bceb
PO		 2199/*****************************************************************************\
2200 * *
2201 * Interrupt handling *
2202 * *
2203\*****************************************************************************/
2204
2205static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2206{
2207 BUG_ON(intmask == 0);
2208
2209 if (!host->cmd) {
a3c76eb9 2210 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2211 "though no command operation was in progress.\n",
2212 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2213 sdhci_dumpregs(host);
2214 return;
2215 }
2216
43b58b36 2217 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2218 host->cmd->error = -ETIMEDOUT;
2219 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2220 SDHCI_INT_INDEX))
2221 host->cmd->error = -EILSEQ;
43b58b36 2222
e809517f 2223 if (host->cmd->error) {
d129bceb 2224 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2225 return;
2226 }
2227
2228 /*
2229 * The host can send and interrupt when the busy state has
2230 * ended, allowing us to wait without wasting CPU cycles.
2231 * Unfortunately this is overloaded on the "data complete"
2232 * interrupt, so we need to take some care when handling
2233 * it.
2234 *
2235 * Note: The 1.0 specification is a bit ambiguous about this
2236 * feature so there might be some problems with older
2237 * controllers.
2238 */
2239 if (host->cmd->flags & MMC_RSP_BUSY) {
2240 if (host->cmd->data)
2241 DBG("Cannot wait for busy signal when also "
2242 "doing a data transfer");
f945405c 2243 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2244 return;
f945405c
BD		 2245
2246 /* The controller does not support the end-of-busy IRQ,
2247 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2248 }
2249
2250 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2251 sdhci_finish_command(host);
d129bceb
PO		 2252}
2253
0957c333 2254#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2255static void sdhci_show_adma_error(struct sdhci_host *host)
2256{
2257 const char *name = mmc_hostname(host->mmc);
2258 u8 *desc = host->adma_desc;
2259 __le32 *dma;
2260 __le16 *len;
2261 u8 attr;
2262
2263 sdhci_dumpregs(host);
2264
2265 while (true) {
2266 dma = (__le32 *)(desc + 4);
2267 len = (__le16 *)(desc + 2);
2268 attr = *desc;
2269
2270 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2271 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2272
2273 desc += 8;
2274
2275 if (attr & 2)
2276 break;
2277 }
2278}
2279#else
2280static void sdhci_show_adma_error(struct sdhci_host *host) { }
2281#endif
2282
d129bceb
PO		 2283static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2284{
069c9f14 2285 u32 command;
d129bceb
PO		 2286 BUG_ON(intmask == 0);
2287
b513ea25
AN		 2288 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2289 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2290 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2291 if (command == MMC_SEND_TUNING_BLOCK ||
2292 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2293 host->tuning_done = 1;
2294 wake_up(&host->buf_ready_int);
2295 return;
2296 }
2297 }
2298
d129bceb
PO		 2299 if (!host->data) {
2300 /*
e809517f
PO		 2301 * The "data complete" interrupt is also used to
2302 * indicate that a busy state has ended. See comment
2303 * above in sdhci_cmd_irq().
d129bceb 2304 */
e809517f
PO		 2305 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2306 if (intmask & SDHCI_INT_DATA_END) {
2307 sdhci_finish_command(host);
2308 return;
2309 }
2310 }
d129bceb 2311
a3c76eb9 2312 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2313 "though no data operation was in progress.\n",
2314 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2315 sdhci_dumpregs(host);
2316
2317 return;
2318 }
2319
2320 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2321 host->data->error = -ETIMEDOUT;
22113efd
AL		 2322 else if (intmask & SDHCI_INT_DATA_END_BIT)
2323 host->data->error = -EILSEQ;
2324 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2325 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2326 != MMC_BUS_TEST_R)
17b0429d 2327 host->data->error = -EILSEQ;
6882a8c0 2328 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2329 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2330 sdhci_show_adma_error(host);
2134a922 2331 host->data->error = -EIO;
a4071fbb
HZ		 2332 if (host->ops->adma_workaround)
2333 host->ops->adma_workaround(host, intmask);
6882a8c0 2334 }
d129bceb 2335
17b0429d 2336 if (host->data->error)
d129bceb
PO		 2337 sdhci_finish_data(host);
2338 else {
a406f5a3 2339 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2340 sdhci_transfer_pio(host);
2341
6ba736a1
PO		 2342 /*
2343 * We currently don't do anything fancy with DMA
2344 * boundaries, but as we can't disable the feature
2345 * we need to at least restart the transfer.
f6a03cbf
MV		 2346 *
2347 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2348 * should return a valid address to continue from, but as
2349 * some controllers are faulty, don't trust them.
6ba736a1 2350 */
f6a03cbf
MV		 2351 if (intmask & SDHCI_INT_DMA_END) {
2352 u32 dmastart, dmanow;
2353 dmastart = sg_dma_address(host->data->sg);
2354 dmanow = dmastart + host->data->bytes_xfered;
2355 /*
2356 * Force update to the next DMA block boundary.
2357 */
2358 dmanow = (dmanow &
2359 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2360 SDHCI_DEFAULT_BOUNDARY_SIZE;
2361 host->data->bytes_xfered = dmanow - dmastart;
2362 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2363 " next 0x%08x\n",
2364 mmc_hostname(host->mmc), dmastart,
2365 host->data->bytes_xfered, dmanow);
2366 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2367 }
6ba736a1 2368
e538fbe8
PO		 2369 if (intmask & SDHCI_INT_DATA_END) {
2370 if (host->cmd) {
2371 /*
2372 * Data managed to finish before the
2373 * command completed. Make sure we do
2374 * things in the proper order.
2375 */
2376 host->data_early = 1;
2377 } else {
2378 sdhci_finish_data(host);
2379 }
2380 }
d129bceb
PO		 2381 }
2382}
2383
7d12e780 2384static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2385{
781e989c 2386 irqreturn_t result = IRQ_NONE;
66fd8ad5 2387 struct sdhci_host *host = dev_id;
41005003 2388 u32 intmask, mask, unexpected = 0;
781e989c 2389 int max_loops = 16;
d129bceb
PO		 2390
2391 spin_lock(&host->lock);
2392
be138554 2393 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2394 spin_unlock(&host->lock);
655bca76 2395 return IRQ_NONE;
66fd8ad5
AH		 2396 }
2397
4e4141a5 2398 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2399 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2400 result = IRQ_NONE;
2401 goto out;
2402 }
2403
41005003
RK		 2404 do {
2405 /* Clear selected interrupts. */
2406 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2407 SDHCI_INT_BUS_POWER);
2408 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2409
41005003
RK		 2410 DBG("*** %s got interrupt: 0x%08x\n",
2411 mmc_hostname(host->mmc), intmask);
d129bceb 2412
41005003
RK		 2413 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2414 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2415 SDHCI_CARD_PRESENT;
d129bceb 2416
41005003
RK		 2417 /*
2418 * There is a observation on i.mx esdhc. INSERT
2419 * bit will be immediately set again when it gets
2420 * cleared, if a card is inserted. We have to mask
2421 * the irq to prevent interrupt storm which will
2422 * freeze the system. And the REMOVE gets the
2423 * same situation.
2424 *
2425 * More testing are needed here to ensure it works
2426 * for other platforms though.
2427 */
b537f94c
RK		 2428 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2429 SDHCI_INT_CARD_REMOVE);
2430 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2431 SDHCI_INT_CARD_INSERT;
2432 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2433 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2434
2435 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2436 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2437
2438 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2439 SDHCI_INT_CARD_REMOVE);
2440 result = IRQ_WAKE_THREAD;
41005003 2441 }
d129bceb 2442
41005003
RK		 2443 if (intmask & SDHCI_INT_CMD_MASK)
2444 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
964f9ce2 2445
41005003
RK		 2446 if (intmask & SDHCI_INT_DATA_MASK)
2447 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2448
41005003
RK		 2449 if (intmask & SDHCI_INT_BUS_POWER)
2450 pr_err("%s: Card is consuming too much power!\n",
2451 mmc_hostname(host->mmc));
3192a28f 2452
781e989c
RK		 2453 if (intmask & SDHCI_INT_CARD_INT) {
2454 sdhci_enable_sdio_irq_nolock(host, false);
2455 host->thread_isr |= SDHCI_INT_CARD_INT;
2456 result = IRQ_WAKE_THREAD;
2457 }
f75979b7 2458
41005003
RK		 2459 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2460 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2461 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2462 SDHCI_INT_CARD_INT);
f75979b7 2463
41005003
RK		 2464 if (intmask) {
2465 unexpected |= intmask;
2466 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2467 }
d129bceb 2468
781e989c
RK		 2469 if (result == IRQ_NONE)
2470 result = IRQ_HANDLED;
d129bceb 2471
41005003 2472 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2473 } while (intmask && --max_loops);
d129bceb
PO		 2474out:
2475 spin_unlock(&host->lock);
2476
6379b237
AS		 2477 if (unexpected) {
2478 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2479 mmc_hostname(host->mmc), unexpected);
2480 sdhci_dumpregs(host);
2481 }
f75979b7 2482
d129bceb
PO		 2483 return result;
2484}
2485
781e989c
RK		 2486static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2487{
2488 struct sdhci_host *host = dev_id;
2489 unsigned long flags;
2490 u32 isr;
2491
2492 spin_lock_irqsave(&host->lock, flags);
2493 isr = host->thread_isr;
2494 host->thread_isr = 0;
2495 spin_unlock_irqrestore(&host->lock, flags);
2496
3560db8e
RK		 2497 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2498 sdhci_card_event(host->mmc);
2499 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2500 }
2501
781e989c
RK		 2502 if (isr & SDHCI_INT_CARD_INT) {
2503 sdio_run_irqs(host->mmc);
2504
2505 spin_lock_irqsave(&host->lock, flags);
2506 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2507 sdhci_enable_sdio_irq_nolock(host, true);
2508 spin_unlock_irqrestore(&host->lock, flags);
2509 }
2510
2511 return isr ? IRQ_HANDLED : IRQ_NONE;
2512}
2513
d129bceb
PO		 2514/*****************************************************************************\
2515 * *
2516 * Suspend/resume *
2517 * *
2518\*****************************************************************************/
2519
2520#ifdef CONFIG_PM
ad080d79
KL		 2521void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2522{
2523 u8 val;
2524 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2525 | SDHCI_WAKE_ON_INT;
2526
2527 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2528 val |= mask ;
2529 /* Avoid fake wake up */
2530 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2531 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2532 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2533}
2534EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2535
2536void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2537{
2538 u8 val;
2539 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2540 | SDHCI_WAKE_ON_INT;
2541
2542 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2543 val &= ~mask;
2544 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2545}
2546EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2547
29495aa0 2548int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2549{
7260cf5e
AV		 2550 sdhci_disable_card_detection(host);
2551
cf2b5eea 2552 /* Disable tuning since we are suspending */
973905fe 2553 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2554 del_timer_sync(&host->tuning_timer);
cf2b5eea 2555 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2556 }
2557
ad080d79 2558 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2559 host->ier = 0;
2560 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2561 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2562 free_irq(host->irq, host);
2563 } else {
2564 sdhci_enable_irq_wakeups(host);
2565 enable_irq_wake(host->irq);
2566 }
4ee14ec6 2567 return 0;
d129bceb
PO		 2568}
2569
b8c86fc5 2570EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2571
b8c86fc5
PO		 2572int sdhci_resume_host(struct sdhci_host *host)
2573{
4ee14ec6 2574 int ret = 0;
d129bceb 2575
a13abc7b 2576 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2577 if (host->ops->enable_dma)
2578 host->ops->enable_dma(host);
2579 }
d129bceb 2580
ad080d79 2581 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2582 ret = request_threaded_irq(host->irq, sdhci_irq,
2583 sdhci_thread_irq, IRQF_SHARED,
2584 mmc_hostname(host->mmc), host);
ad080d79
KL		 2585 if (ret)
2586 return ret;
2587 } else {
2588 sdhci_disable_irq_wakeups(host);
2589 disable_irq_wake(host->irq);
2590 }
d129bceb 2591
6308d290
AH		 2592 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2593 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2594 /* Card keeps power but host controller does not */
2595 sdhci_init(host, 0);
2596 host->pwr = 0;
2597 host->clock = 0;
2598 sdhci_do_set_ios(host, &host->mmc->ios);
2599 } else {
2600 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2601 mmiowb();
2602 }
b8c86fc5 2603
7260cf5e
AV		 2604 sdhci_enable_card_detection(host);
2605
cf2b5eea 2606 /* Set the re-tuning expiration flag */
973905fe 2607 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2608 host->flags |= SDHCI_NEEDS_RETUNING;
2609
2f4cbb3d 2610 return ret;
d129bceb
PO		 2611}
2612
b8c86fc5 2613EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2614#endif /* CONFIG_PM */
2615
66fd8ad5
AH		 2616#ifdef CONFIG_PM_RUNTIME
2617
2618static int sdhci_runtime_pm_get(struct sdhci_host *host)
2619{
2620 return pm_runtime_get_sync(host->mmc->parent);
2621}
2622
2623static int sdhci_runtime_pm_put(struct sdhci_host *host)
2624{
2625 pm_runtime_mark_last_busy(host->mmc->parent);
2626 return pm_runtime_put_autosuspend(host->mmc->parent);
2627}
2628
f0710a55
AH		 2629static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2630{
2631 if (host->runtime_suspended || host->bus_on)
2632 return;
2633 host->bus_on = true;
2634 pm_runtime_get_noresume(host->mmc->parent);
2635}
2636
2637static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2638{
2639 if (host->runtime_suspended || !host->bus_on)
2640 return;
2641 host->bus_on = false;
2642 pm_runtime_put_noidle(host->mmc->parent);
2643}
2644
66fd8ad5
AH		 2645int sdhci_runtime_suspend_host(struct sdhci_host *host)
2646{
2647 unsigned long flags;
2648 int ret = 0;
2649
2650 /* Disable tuning since we are suspending */
973905fe 2651 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2652 del_timer_sync(&host->tuning_timer);
2653 host->flags &= ~SDHCI_NEEDS_RETUNING;
2654 }
2655
2656 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2657 host->ier &= SDHCI_INT_CARD_INT;
2658 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2659 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2660 spin_unlock_irqrestore(&host->lock, flags);
2661
781e989c 2662 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2663
2664 spin_lock_irqsave(&host->lock, flags);
2665 host->runtime_suspended = true;
2666 spin_unlock_irqrestore(&host->lock, flags);
2667
2668 return ret;
2669}
2670EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2671
2672int sdhci_runtime_resume_host(struct sdhci_host *host)
2673{
2674 unsigned long flags;
2675 int ret = 0, host_flags = host->flags;
2676
2677 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2678 if (host->ops->enable_dma)
2679 host->ops->enable_dma(host);
2680 }
2681
2682 sdhci_init(host, 0);
2683
2684 /* Force clock and power re-program */
2685 host->pwr = 0;
2686 host->clock = 0;
2687 sdhci_do_set_ios(host, &host->mmc->ios);
2688
2689 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2690 if ((host_flags & SDHCI_PV_ENABLED) &&
2691 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2692 spin_lock_irqsave(&host->lock, flags);
2693 sdhci_enable_preset_value(host, true);
2694 spin_unlock_irqrestore(&host->lock, flags);
2695 }
66fd8ad5
AH		 2696
2697 /* Set the re-tuning expiration flag */
973905fe 2698 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2699 host->flags |= SDHCI_NEEDS_RETUNING;
2700
2701 spin_lock_irqsave(&host->lock, flags);
2702
2703 host->runtime_suspended = false;
2704
2705 /* Enable SDIO IRQ */
ef104333 2706 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2707 sdhci_enable_sdio_irq_nolock(host, true);
2708
2709 /* Enable Card Detection */
2710 sdhci_enable_card_detection(host);
2711
2712 spin_unlock_irqrestore(&host->lock, flags);
2713
2714 return ret;
2715}
2716EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2717
2718#endif
2719
d129bceb
PO		 2720/*****************************************************************************\
2721 * *
b8c86fc5 2722 * Device allocation/registration *
d129bceb
PO		 2723 * *
2724\*****************************************************************************/
2725
b8c86fc5
PO		 2726struct sdhci_host *sdhci_alloc_host(struct device *dev,
2727 size_t priv_size)
d129bceb 2728{
d129bceb
PO		 2729 struct mmc_host *mmc;
2730 struct sdhci_host *host;
2731
b8c86fc5 2732 WARN_ON(dev == NULL);
d129bceb 2733
b8c86fc5 2734 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2735 if (!mmc)
b8c86fc5 2736 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2737
2738 host = mmc_priv(mmc);
2739 host->mmc = mmc;
2740
b8c86fc5
PO		 2741 return host;
2742}
8a4da143 2743
b8c86fc5 2744EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2745
b8c86fc5
PO		 2746int sdhci_add_host(struct sdhci_host *host)
2747{
2748 struct mmc_host *mmc;
bd6a8c30 2749 u32 caps[2] = {0, 0};
f2119df6
AN		 2750 u32 max_current_caps;
2751 unsigned int ocr_avail;
b8c86fc5 2752 int ret;
d129bceb 2753
b8c86fc5
PO		 2754 WARN_ON(host == NULL);
2755 if (host == NULL)
2756 return -EINVAL;
d129bceb 2757
b8c86fc5 2758 mmc = host->mmc;
d129bceb 2759
b8c86fc5
PO		 2760 if (debug_quirks)
2761 host->quirks = debug_quirks;
66fd8ad5
AH		 2762 if (debug_quirks2)
2763 host->quirks2 = debug_quirks2;
d129bceb 2764
03231f9b 2765 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2766
4e4141a5 2767 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2768 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2769 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2770 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2771 pr_err("%s: Unknown controller version (%d). "
b69c9058 2772 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2773 host->version);
4a965505
PO		 2774 }
2775
f2119df6 2776 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2777 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2778
bd6a8c30
PR		 2779 if (host->version >= SDHCI_SPEC_300)
2780 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2781 host->caps1 :
2782 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2783
b8c86fc5 2784 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2785 host->flags |= SDHCI_USE_SDMA;
f2119df6 2786 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2787 DBG("Controller doesn't have SDMA capability\n");
67435274 2788 else
a13abc7b 2789 host->flags |= SDHCI_USE_SDMA;
d129bceb 2790
b8c86fc5 2791 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2792 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2793 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2794 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2795 }
2796
f2119df6
AN		 2797 if ((host->version >= SDHCI_SPEC_200) &&
2798 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2799 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2800
2801 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2802 (host->flags & SDHCI_USE_ADMA)) {
2803 DBG("Disabling ADMA as it is marked broken\n");
2804 host->flags &= ~SDHCI_USE_ADMA;
2805 }
2806
a13abc7b 2807 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2808 if (host->ops->enable_dma) {
2809 if (host->ops->enable_dma(host)) {
a3c76eb9 2810 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2811 "available. Falling back to PIO.\n",
2812 mmc_hostname(mmc));
a13abc7b
RR		 2813 host->flags &=
2814 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2815 }
d129bceb
PO		 2816 }
2817 }
2818
2134a922
PO		 2819 if (host->flags & SDHCI_USE_ADMA) {
2820 /*
2821 * We need to allocate descriptors for all sg entries
2822 * (128) and potentially one alignment transfer for
2823 * each of those entries.
2824 */
d1e49f77
RK		 2825 host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc),
2826 ADMA_SIZE, &host->adma_addr,
2827 GFP_KERNEL);
2134a922
PO		 2828 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2829 if (!host->adma_desc || !host->align_buffer) {
d1e49f77
RK		 2830 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2831 host->adma_desc, host->adma_addr);
2134a922 2832 kfree(host->align_buffer);
a3c76eb9 2833 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2834 "buffers. Falling back to standard DMA.\n",
2835 mmc_hostname(mmc));
2836 host->flags &= ~SDHCI_USE_ADMA;
d1e49f77
RK		 2837 host->adma_desc = NULL;
2838 host->align_buffer = NULL;
2839 } else if (host->adma_addr & 3) {
2840 pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2841 mmc_hostname(mmc));
2842 host->flags &= ~SDHCI_USE_ADMA;
2843 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2844 host->adma_desc, host->adma_addr);
2845 kfree(host->align_buffer);
2846 host->adma_desc = NULL;
2847 host->align_buffer = NULL;
2134a922
PO		 2848 }
2849 }
2850
7659150c
PO		 2851 /*
2852 * If we use DMA, then it's up to the caller to set the DMA
2853 * mask, but PIO does not need the hw shim so we set a new
2854 * mask here in that case.
2855 */
a13abc7b 2856 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2857 host->dma_mask = DMA_BIT_MASK(64);
2858 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2859 }
d129bceb 2860
c4687d5f 2861 if (host->version >= SDHCI_SPEC_300)
f2119df6 2862 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2863 >> SDHCI_CLOCK_BASE_SHIFT;
2864 else
f2119df6 2865 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2866 >> SDHCI_CLOCK_BASE_SHIFT;
2867
4240ff0a 2868 host->max_clk *= 1000000;
f27f47ef
AV		 2869 if (host->max_clk == 0 || host->quirks &
2870 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2871 if (!host->ops->get_max_clock) {
a3c76eb9 2872 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2873 "frequency.\n", mmc_hostname(mmc));
2874 return -ENODEV;
2875 }
2876 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2877 }
d129bceb 2878
c3ed3877
AN		 2879 /*
2880 * In case of Host Controller v3.00, find out whether clock
2881 * multiplier is supported.
2882 */
2883 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2884 SDHCI_CLOCK_MUL_SHIFT;
2885
2886 /*
2887 * In case the value in Clock Multiplier is 0, then programmable
2888 * clock mode is not supported, otherwise the actual clock
2889 * multiplier is one more than the value of Clock Multiplier
2890 * in the Capabilities Register.
2891 */
2892 if (host->clk_mul)
2893 host->clk_mul += 1;
2894
d129bceb
PO		 2895 /*
2896 * Set host parameters.
2897 */
2898 mmc->ops = &sdhci_ops;
c3ed3877 2899 mmc->f_max = host->max_clk;
ce5f036b 2900 if (host->ops->get_min_clock)
a9e58f25 2901 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2902 else if (host->version >= SDHCI_SPEC_300) {
2903 if (host->clk_mul) {
2904 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2905 mmc->f_max = host->max_clk * host->clk_mul;
2906 } else
2907 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2908 } else
0397526d 2909 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2910
272308ca
AS		 2911 host->timeout_clk =
2912 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2913 if (host->timeout_clk == 0) {
2914 if (host->ops->get_timeout_clock) {
2915 host->timeout_clk = host->ops->get_timeout_clock(host);
2916 } else if (!(host->quirks &
2917 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2918 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2919 "frequency.\n", mmc_hostname(mmc));
2920 return -ENODEV;
2921 }
2922 }
2923 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2924 host->timeout_clk *= 1000;
2925
2926 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2927 host->timeout_clk = mmc->f_max / 1000;
272308ca 2928
68eb80e0 2929 mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
58d1246d 2930
e89d456f 2931 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 2932 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 2933
2934 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2935 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2936
8edf6371 2937 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2938 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2939 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2940 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2941 host->flags |= SDHCI_AUTO_CMD23;
2942 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2943 } else {
2944 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2945 }
2946
15ec4461
PR		 2947 /*
2948 * A controller may support 8-bit width, but the board itself
2949 * might not have the pins brought out. Boards that support
2950 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2951 * their platform code before calling sdhci_add_host(), and we
2952 * won't assume 8-bit width for hosts without that CAP.
2953 */
5fe23c7f 2954 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2955 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2956
63ef5d8c
JH		 2957 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2958 mmc->caps &= ~MMC_CAP_CMD23;
2959
f2119df6 2960 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2961 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2962
176d1ed4 2963 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2964 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2965 mmc->caps |= MMC_CAP_NEEDS_POLL;
2966
6231f3de 2967 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
462849aa 2968 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2969 if (IS_ERR_OR_NULL(host->vqmmc)) {
2970 if (PTR_ERR(host->vqmmc) < 0) {
2971 pr_info("%s: no vqmmc regulator found\n",
2972 mmc_hostname(mmc));
2973 host->vqmmc = NULL;
2974 }
8363c374 2975 } else {
a3361aba 2976 ret = regulator_enable(host->vqmmc);
cec2e216
KL		 2977 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2978 1950000))
8363c374
KL		 2979 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2980 SDHCI_SUPPORT_SDR50 |
2981 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 2982 if (ret) {
2983 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2984 mmc_hostname(mmc), ret);
2985 host->vqmmc = NULL;
2986 }
8363c374 2987 }
6231f3de 2988
6a66180a
DD		 2989 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2990 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2991 SDHCI_SUPPORT_DDR50);
2992
4188bba0
AC		 2993 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2994 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2995 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 2996 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2997
2998 /* SDR104 supports also implies SDR50 support */
156e14b1 2999 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3000 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3001 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3002 * field can be promoted to support HS200.
3003 */
13868bf2
DC		 3004 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3005 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3006 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3007 mmc->caps |= MMC_CAP_UHS_SDR50;
3008
9107ebbf
MC		 3009 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3010 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3011 mmc->caps |= MMC_CAP_UHS_DDR50;
3012
069c9f14 3013 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3014 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3015 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3016
156e14b1 3017 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3018 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3019 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3020
d6d50a15
AN		 3021 /* Driver Type(s) (A, C, D) supported by the host */
3022 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3023 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3024 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3025 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3026 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3027 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3028
cf2b5eea
AN		 3029 /* Initial value for re-tuning timer count */
3030 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3031 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3032
3033 /*
3034 * In case Re-tuning Timer is not disabled, the actual value of
3035 * re-tuning timer will be 2 ^ (n - 1).
3036 */
3037 if (host->tuning_count)
3038 host->tuning_count = 1 << (host->tuning_count - 1);
3039
3040 /* Re-tuning mode supported by the Host Controller */
3041 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3042 SDHCI_RETUNING_MODE_SHIFT;
3043
8f230f45 3044 ocr_avail = 0;
bad37e1a 3045
462849aa 3046 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
657d5982
KL		 3047 if (IS_ERR_OR_NULL(host->vmmc)) {
3048 if (PTR_ERR(host->vmmc) < 0) {
3049 pr_info("%s: no vmmc regulator found\n",
3050 mmc_hostname(mmc));
3051 host->vmmc = NULL;
3052 }
8363c374 3053 }
bad37e1a 3054
68737043 3055#ifdef CONFIG_REGULATOR
a4f8f257
MS		 3056 /*
3057 * Voltage range check makes sense only if regulator reports
3058 * any voltage value.
3059 */
3060 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
cec2e216
KL		 3061 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3062 3600000);
68737043
PR		 3063 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3064 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 3065 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3066 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 3067 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3068 1950000);
68737043
PR		 3069 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3070 caps[0] &= ~SDHCI_CAN_VDD_180;
3071 }
3072#endif /* CONFIG_REGULATOR */
3073
f2119df6
AN		 3074 /*
3075 * According to SD Host Controller spec v3.00, if the Host System
3076 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3077 * the value is meaningful only if Voltage Support in the Capabilities
3078 * register is set. The actual current value is 4 times the register
3079 * value.
3080 */
3081 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 3082 if (!max_current_caps && host->vmmc) {
3083 u32 curr = regulator_get_current_limit(host->vmmc);
3084 if (curr > 0) {
3085
3086 /* convert to SDHCI_MAX_CURRENT format */
3087 curr = curr/1000; /* convert to mA */
3088 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3089
3090 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3091 max_current_caps =
3092 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3093 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3094 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3095 }
3096 }
f2119df6
AN		 3097
3098 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3099 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3100
55c4665e 3101 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3102 SDHCI_MAX_CURRENT_330_MASK) >>
3103 SDHCI_MAX_CURRENT_330_SHIFT) *
3104 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3105 }
3106 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3107 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3108
55c4665e 3109 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3110 SDHCI_MAX_CURRENT_300_MASK) >>
3111 SDHCI_MAX_CURRENT_300_SHIFT) *
3112 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3113 }
3114 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3115 ocr_avail |= MMC_VDD_165_195;
3116
55c4665e 3117 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3118 SDHCI_MAX_CURRENT_180_MASK) >>
3119 SDHCI_MAX_CURRENT_180_SHIFT) *
3120 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3121 }
3122
c0b887b6
HZ		 3123 if (host->ocr_mask)
3124 ocr_avail = host->ocr_mask;
3125
8f230f45
TI		 3126 mmc->ocr_avail = ocr_avail;
3127 mmc->ocr_avail_sdio = ocr_avail;
3128 if (host->ocr_avail_sdio)
3129 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3130 mmc->ocr_avail_sd = ocr_avail;
3131 if (host->ocr_avail_sd)
3132 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3133 else /* normal SD controllers don't support 1.8V */
3134 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3135 mmc->ocr_avail_mmc = ocr_avail;
3136 if (host->ocr_avail_mmc)
3137 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3138
3139 if (mmc->ocr_avail == 0) {
a3c76eb9 3140 pr_err("%s: Hardware doesn't report any "
b69c9058 3141 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3142 return -ENODEV;
146ad66e
PO		 3143 }
3144
d129bceb
PO		 3145 spin_lock_init(&host->lock);
3146
3147 /*
2134a922
PO		 3148 * Maximum number of segments. Depends on if the hardware
3149 * can do scatter/gather or not.
d129bceb 3150 */
2134a922 3151 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3152 mmc->max_segs = 128;
a13abc7b 3153 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3154 mmc->max_segs = 1;
2134a922 3155 else /* PIO */
a36274e0 3156 mmc->max_segs = 128;
d129bceb
PO		 3157
3158 /*
bab76961 3159 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3160 * size (512KiB).
d129bceb 3161 */
55db890a 3162 mmc->max_req_size = 524288;
d129bceb
PO		 3163
3164 /*
3165 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3166 * of bytes. When doing hardware scatter/gather, each entry cannot
3167 * be larger than 64 KiB though.
d129bceb 3168 */
30652aa3
OJ		 3169 if (host->flags & SDHCI_USE_ADMA) {
3170 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3171 mmc->max_seg_size = 65535;
3172 else
3173 mmc->max_seg_size = 65536;
3174 } else {
2134a922 3175 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3176 }
d129bceb 3177
fe4a3c7a
PO		 3178 /*
3179 * Maximum block size. This varies from controller to controller and
3180 * is specified in the capabilities register.
3181 */
0633f654
AV		 3182 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3183 mmc->max_blk_size = 2;
3184 } else {
f2119df6 3185 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3186 SDHCI_MAX_BLOCK_SHIFT;
3187 if (mmc->max_blk_size >= 3) {
a3c76eb9 3188 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3189 "assuming 512 bytes\n", mmc_hostname(mmc));
3190 mmc->max_blk_size = 0;
3191 }
3192 }
3193
3194 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3195
55db890a
PO		 3196 /*
3197 * Maximum block count.
3198 */
1388eefd 3199 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3200
d129bceb
PO		 3201 /*
3202 * Init tasklets.
3203 */
d129bceb
PO		 3204 tasklet_init(&host->finish_tasklet,
3205 sdhci_tasklet_finish, (unsigned long)host);
3206
e4cad1b5 3207 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3208
cf2b5eea 3209 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3210 init_waitqueue_head(&host->buf_ready_int);
3211
cf2b5eea
AN		 3212 /* Initialize re-tuning timer */
3213 init_timer(&host->tuning_timer);
3214 host->tuning_timer.data = (unsigned long)host;
3215 host->tuning_timer.function = sdhci_tuning_timer;
3216 }
3217
2af502ca
SG		 3218 sdhci_init(host, 0);
3219
781e989c
RK		 3220 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3221 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3222 if (ret) {
3223 pr_err("%s: Failed to request IRQ %d: %d\n",
3224 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3225 goto untasklet;
0fc81ee3 3226 }
d129bceb 3227
d129bceb
PO		 3228#ifdef CONFIG_MMC_DEBUG
3229 sdhci_dumpregs(host);
3230#endif
3231
f9134319 3232#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3233 snprintf(host->led_name, sizeof(host->led_name),
3234 "%s::", mmc_hostname(mmc));
3235 host->led.name = host->led_name;
2f730fec
PO		 3236 host->led.brightness = LED_OFF;
3237 host->led.default_trigger = mmc_hostname(mmc);
3238 host->led.brightness_set = sdhci_led_control;
3239
b8c86fc5 3240 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3241 if (ret) {
3242 pr_err("%s: Failed to register LED device: %d\n",
3243 mmc_hostname(mmc), ret);
2f730fec 3244 goto reset;
0fc81ee3 3245 }
2f730fec
PO		 3246#endif
3247
5f25a66f
PO		 3248 mmiowb();
3249
d129bceb
PO		 3250 mmc_add_host(mmc);
3251
a3c76eb9 3252 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3253 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3254 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3255 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3256
7260cf5e
AV		 3257 sdhci_enable_card_detection(host);
3258
d129bceb
PO		 3259 return 0;
3260
f9134319 3261#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3262reset:
03231f9b 3263 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3264 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3265 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3266 free_irq(host->irq, host);
3267#endif
8ef1a143 3268untasklet:
d129bceb 3269 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3270
3271 return ret;
3272}
3273
b8c86fc5 3274EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3275
1e72859e 3276void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3277{
1e72859e
PO		 3278 unsigned long flags;
3279
3280 if (dead) {
3281 spin_lock_irqsave(&host->lock, flags);
3282
3283 host->flags |= SDHCI_DEVICE_DEAD;
3284
3285 if (host->mrq) {
a3c76eb9 3286 pr_err("%s: Controller removed during "
1e72859e
PO		 3287 " transfer!\n", mmc_hostname(host->mmc));
3288
3289 host->mrq->cmd->error = -ENOMEDIUM;
3290 tasklet_schedule(&host->finish_tasklet);
3291 }
3292
3293 spin_unlock_irqrestore(&host->lock, flags);
3294 }
3295
7260cf5e
AV		 3296 sdhci_disable_card_detection(host);
3297
b8c86fc5 3298 mmc_remove_host(host->mmc);
d129bceb 3299
f9134319 3300#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3301 led_classdev_unregister(&host->led);
3302#endif
3303
1e72859e 3304 if (!dead)
03231f9b 3305 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3306
b537f94c
RK		 3307 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3308 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3309 free_irq(host->irq, host);
3310
3311 del_timer_sync(&host->timer);
3312
d129bceb 3313 tasklet_kill(&host->finish_tasklet);
2134a922 3314
77dcb3f4
PR		 3315 if (host->vmmc) {
3316 regulator_disable(host->vmmc);
9bea3c85 3317 regulator_put(host->vmmc);
77dcb3f4 3318 }
9bea3c85 3319
6231f3de
PR		 3320 if (host->vqmmc) {
3321 regulator_disable(host->vqmmc);
3322 regulator_put(host->vqmmc);
3323 }
3324
d1e49f77
RK		 3325 if (host->adma_desc)
3326 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
3327 host->adma_desc, host->adma_addr);
2134a922
PO		 3328 kfree(host->align_buffer);
3329
3330 host->adma_desc = NULL;
3331 host->align_buffer = NULL;
d129bceb
PO		 3332}
3333
b8c86fc5 3334EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3335
b8c86fc5 3336void sdhci_free_host(struct sdhci_host *host)
d129bceb 3337{
b8c86fc5 3338 mmc_free_host(host->mmc);
d129bceb
PO		 3339}
3340
b8c86fc5 3341EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3342
3343/*****************************************************************************\
3344 * *
3345 * Driver init/exit *
3346 * *
3347\*****************************************************************************/
3348
3349static int __init sdhci_drv_init(void)
3350{
a3c76eb9 3351 pr_info(DRIVER_NAME
52fbf9c9 3352 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3353 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3354
b8c86fc5 3355 return 0;
d129bceb
PO		 3356}
3357
3358static void __exit sdhci_drv_exit(void)
3359{
d129bceb
PO		 3360}
3361
3362module_init(sdhci_drv_init);
3363module_exit(sdhci_drv_exit);
3364
df673b22 3365module_param(debug_quirks, uint, 0444);
66fd8ad5 3366module_param(debug_quirks2, uint, 0444);
67435274 3367
32710e8f 3368MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3369MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3370MODULE_LICENSE("GPL");
67435274 3371
df673b22 3372MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3373MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux 6.x block layer and io_uring tree(s)