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mmc: sdhci: clean up sdhci_update_clock()/sdhci_set_clock()
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
d1e49f77
RK		 47#define ADMA_SIZE ((128 * 2 + 1) * 4)
48
df673b22 49static unsigned int debug_quirks = 0;
66fd8ad5 50static unsigned int debug_quirks2;
67435274 51
d129bceb
PO		 52static void sdhci_finish_data(struct sdhci_host *);
53
d129bceb 54static void sdhci_finish_command(struct sdhci_host *);
069c9f14 55static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 56static void sdhci_tuning_timer(unsigned long data);
52983382 57static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 58
66fd8ad5
AH		 59#ifdef CONFIG_PM_RUNTIME
60static int sdhci_runtime_pm_get(struct sdhci_host *host);
61static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 62static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
63static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 64#else
65static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
66{
67 return 0;
68}
69static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
70{
71 return 0;
72}
f0710a55
AH		 73static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
74{
75}
76static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
77{
78}
66fd8ad5
AH		 79#endif
80
d129bceb
PO		 81static void sdhci_dumpregs(struct sdhci_host *host)
82{
a3c76eb9 83 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 84 mmc_hostname(host->mmc));
d129bceb 85
a3c76eb9 86 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 87 sdhci_readl(host, SDHCI_DMA_ADDRESS),
88 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 89 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 90 sdhci_readw(host, SDHCI_BLOCK_SIZE),
91 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 92 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 93 sdhci_readl(host, SDHCI_ARGUMENT),
94 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 95 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 96 sdhci_readl(host, SDHCI_PRESENT_STATE),
97 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 98 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 99 sdhci_readb(host, SDHCI_POWER_CONTROL),
100 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 101 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 102 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
103 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 104 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 105 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
106 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 107 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 108 sdhci_readl(host, SDHCI_INT_ENABLE),
109 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 110 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 111 sdhci_readw(host, SDHCI_ACMD12_ERR),
112 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 113 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 114 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 115 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 117 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 118 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 120 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 121
be3f4ae0 122 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
126
a3c76eb9 127 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 128}
129
130/*****************************************************************************\
131 * *
132 * Low level functions *
133 * *
134\*****************************************************************************/
135
7260cf5e
AV		 136static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
137{
5b4f1f6c 138 u32 present;
7260cf5e 139
c79396c1 140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 141 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 142 return;
143
5b4f1f6c
RK		 144 if (enable) {
145 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
146 SDHCI_CARD_PRESENT;
d25928d1 147
5b4f1f6c
RK		 148 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
149 SDHCI_INT_CARD_INSERT;
150 } else {
151 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
152 }
b537f94c
RK		 153
154 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
155 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 156}
157
158static void sdhci_enable_card_detection(struct sdhci_host *host)
159{
160 sdhci_set_card_detection(host, true);
161}
162
163static void sdhci_disable_card_detection(struct sdhci_host *host)
164{
165 sdhci_set_card_detection(host, false);
166}
167
03231f9b 168void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 169{
e16514d8 170 unsigned long timeout;
393c1a34 171
4e4141a5 172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 173
f0710a55 174 if (mask & SDHCI_RESET_ALL) {
d129bceb 175 host->clock = 0;
f0710a55
AH		 176 /* Reset-all turns off SD Bus Power */
177 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
178 sdhci_runtime_pm_bus_off(host);
179 }
d129bceb 180
e16514d8
PO		 181 /* Wait max 100 ms */
182 timeout = 100;
183
184 /* hw clears the bit when it's done */
4e4141a5 185 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 186 if (timeout == 0) {
a3c76eb9 187 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 188 mmc_hostname(host->mmc), (int)mask);
189 sdhci_dumpregs(host);
190 return;
191 }
192 timeout--;
193 mdelay(1);
d129bceb 194 }
03231f9b
RK		 195}
196EXPORT_SYMBOL_GPL(sdhci_reset);
197
198static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
199{
200 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
201 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
202 SDHCI_CARD_PRESENT))
203 return;
204 }
063a9dbb 205
03231f9b 206 host->ops->reset(host, mask);
393c1a34 207
3abc1e80
SX		 208 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
209 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
210 host->ops->enable_dma(host);
211 }
d129bceb
PO		 212}
213
2f4cbb3d
NP		 214static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
215
216static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 217{
2f4cbb3d 218 if (soft)
03231f9b 219 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 220 else
03231f9b 221 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 222
b537f94c
RK		 223 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
224 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
225 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
226 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
227 SDHCI_INT_RESPONSE;
228
229 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
230 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 231
232 if (soft) {
233 /* force clock reconfiguration */
234 host->clock = 0;
235 sdhci_set_ios(host->mmc, &host->mmc->ios);
236 }
7260cf5e 237}
d129bceb 238
7260cf5e
AV		 239static void sdhci_reinit(struct sdhci_host *host)
240{
2f4cbb3d 241 sdhci_init(host, 0);
b67c6b41
AL		 242 /*
243 * Retuning stuffs are affected by different cards inserted and only
244 * applicable to UHS-I cards. So reset these fields to their initial
245 * value when card is removed.
246 */
973905fe
AL		 247 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
248 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
249
b67c6b41
AL		 250 del_timer_sync(&host->tuning_timer);
251 host->flags &= ~SDHCI_NEEDS_RETUNING;
252 host->mmc->max_blk_count =
253 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
254 }
7260cf5e 255 sdhci_enable_card_detection(host);
d129bceb
PO		 256}
257
258static void sdhci_activate_led(struct sdhci_host *host)
259{
260 u8 ctrl;
261
4e4141a5 262 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 263 ctrl |= SDHCI_CTRL_LED;
4e4141a5 264 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 265}
266
267static void sdhci_deactivate_led(struct sdhci_host *host)
268{
269 u8 ctrl;
270
4e4141a5 271 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 272 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 273 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 274}
275
f9134319 276#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 277static void sdhci_led_control(struct led_classdev *led,
278 enum led_brightness brightness)
279{
280 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
281 unsigned long flags;
282
283 spin_lock_irqsave(&host->lock, flags);
284
66fd8ad5
AH		 285 if (host->runtime_suspended)
286 goto out;
287
2f730fec
PO		 288 if (brightness == LED_OFF)
289 sdhci_deactivate_led(host);
290 else
291 sdhci_activate_led(host);
66fd8ad5 292out:
2f730fec
PO		 293 spin_unlock_irqrestore(&host->lock, flags);
294}
295#endif
296
d129bceb
PO		 297/*****************************************************************************\
298 * *
299 * Core functions *
300 * *
301\*****************************************************************************/
302
a406f5a3 303static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 304{
7659150c
PO		 305 unsigned long flags;
306 size_t blksize, len, chunk;
7244b85b 307 u32 uninitialized_var(scratch);
7659150c 308 u8 *buf;
d129bceb 309
a406f5a3 310 DBG("PIO reading\n");
d129bceb 311
a406f5a3 312 blksize = host->data->blksz;
7659150c 313 chunk = 0;
d129bceb 314
7659150c 315 local_irq_save(flags);
d129bceb 316
a406f5a3 317 while (blksize) {
7659150c
PO		 318 if (!sg_miter_next(&host->sg_miter))
319 BUG();
d129bceb 320
7659150c 321 len = min(host->sg_miter.length, blksize);
d129bceb 322
7659150c
PO		 323 blksize -= len;
324 host->sg_miter.consumed = len;
14d836e7 325
7659150c 326 buf = host->sg_miter.addr;
d129bceb 327
7659150c
PO		 328 while (len) {
329 if (chunk == 0) {
4e4141a5 330 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 331 chunk = 4;
a406f5a3 332 }
7659150c
PO		 333
334 *buf = scratch & 0xFF;
335
336 buf++;
337 scratch >>= 8;
338 chunk--;
339 len--;
d129bceb 340 }
a406f5a3 341 }
7659150c
PO		 342
343 sg_miter_stop(&host->sg_miter);
344
345 local_irq_restore(flags);
a406f5a3 346}
d129bceb 347
a406f5a3
PO		 348static void sdhci_write_block_pio(struct sdhci_host *host)
349{
7659150c
PO		 350 unsigned long flags;
351 size_t blksize, len, chunk;
352 u32 scratch;
353 u8 *buf;
d129bceb 354
a406f5a3
PO		 355 DBG("PIO writing\n");
356
357 blksize = host->data->blksz;
7659150c
PO		 358 chunk = 0;
359 scratch = 0;
d129bceb 360
7659150c 361 local_irq_save(flags);
d129bceb 362
a406f5a3 363 while (blksize) {
7659150c
PO		 364 if (!sg_miter_next(&host->sg_miter))
365 BUG();
a406f5a3 366
7659150c
PO		 367 len = min(host->sg_miter.length, blksize);
368
369 blksize -= len;
370 host->sg_miter.consumed = len;
371
372 buf = host->sg_miter.addr;
d129bceb 373
7659150c
PO		 374 while (len) {
375 scratch |= (u32)*buf << (chunk * 8);
376
377 buf++;
378 chunk++;
379 len--;
380
381 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 382 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 383 chunk = 0;
384 scratch = 0;
d129bceb 385 }
d129bceb
PO		 386 }
387 }
7659150c
PO		 388
389 sg_miter_stop(&host->sg_miter);
390
391 local_irq_restore(flags);
a406f5a3
PO		 392}
393
394static void sdhci_transfer_pio(struct sdhci_host *host)
395{
396 u32 mask;
397
398 BUG_ON(!host->data);
399
7659150c 400 if (host->blocks == 0)
a406f5a3
PO		 401 return;
402
403 if (host->data->flags & MMC_DATA_READ)
404 mask = SDHCI_DATA_AVAILABLE;
405 else
406 mask = SDHCI_SPACE_AVAILABLE;
407
4a3cba32
PO		 408 /*
409 * Some controllers (JMicron JMB38x) mess up the buffer bits
410 * for transfers < 4 bytes. As long as it is just one block,
411 * we can ignore the bits.
412 */
413 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
414 (host->data->blocks == 1))
415 mask = ~0;
416
4e4141a5 417 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 418 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
419 udelay(100);
420
a406f5a3
PO		 421 if (host->data->flags & MMC_DATA_READ)
422 sdhci_read_block_pio(host);
423 else
424 sdhci_write_block_pio(host);
d129bceb 425
7659150c
PO		 426 host->blocks--;
427 if (host->blocks == 0)
a406f5a3 428 break;
a406f5a3 429 }
d129bceb 430
a406f5a3 431 DBG("PIO transfer complete.\n");
d129bceb
PO		 432}
433
2134a922
PO		 434static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
435{
436 local_irq_save(*flags);
482fce99 437 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 438}
439
440static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
441{
482fce99 442 kunmap_atomic(buffer);
2134a922
PO		 443 local_irq_restore(*flags);
444}
445
118cd17d
BD		 446static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
447{
9e506f35
BD		 448 __le32 *dataddr = (__le32 __force *)(desc + 4);
449 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 450
9e506f35
BD		 451 /* SDHCI specification says ADMA descriptors should be 4 byte
452 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 453
9e506f35
BD		 454 cmdlen[0] = cpu_to_le16(cmd);
455 cmdlen[1] = cpu_to_le16(len);
456
457 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 458}
459
8f1934ce 460static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 461 struct mmc_data *data)
462{
463 int direction;
464
465 u8 *desc;
466 u8 *align;
467 dma_addr_t addr;
468 dma_addr_t align_addr;
469 int len, offset;
470
471 struct scatterlist *sg;
472 int i;
473 char *buffer;
474 unsigned long flags;
475
476 /*
477 * The spec does not specify endianness of descriptor table.
478 * We currently guess that it is LE.
479 */
480
481 if (data->flags & MMC_DATA_READ)
482 direction = DMA_FROM_DEVICE;
483 else
484 direction = DMA_TO_DEVICE;
485
2134a922
PO		 486 host->align_addr = dma_map_single(mmc_dev(host->mmc),
487 host->align_buffer, 128 * 4, direction);
8d8bb39b 488 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 489 goto fail;
2134a922
PO		 490 BUG_ON(host->align_addr & 0x3);
491
492 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
493 data->sg, data->sg_len, direction);
8f1934ce
PO		 494 if (host->sg_count == 0)
495 goto unmap_align;
2134a922
PO		 496
497 desc = host->adma_desc;
498 align = host->align_buffer;
499
500 align_addr = host->align_addr;
501
502 for_each_sg(data->sg, sg, host->sg_count, i) {
503 addr = sg_dma_address(sg);
504 len = sg_dma_len(sg);
505
506 /*
507 * The SDHCI specification states that ADMA
508 * addresses must be 32-bit aligned. If they
509 * aren't, then we use a bounce buffer for
510 * the (up to three) bytes that screw up the
511 * alignment.
512 */
513 offset = (4 - (addr & 0x3)) & 0x3;
514 if (offset) {
515 if (data->flags & MMC_DATA_WRITE) {
516 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 517 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 518 memcpy(align, buffer, offset);
519 sdhci_kunmap_atomic(buffer, &flags);
520 }
521
118cd17d
BD		 522 /* tran, valid */
523 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 524
525 BUG_ON(offset > 65536);
526
2134a922
PO		 527 align += 4;
528 align_addr += 4;
529
530 desc += 8;
531
532 addr += offset;
533 len -= offset;
534 }
535
2134a922
PO		 536 BUG_ON(len > 65536);
537
118cd17d
BD		 538 /* tran, valid */
539 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 540 desc += 8;
541
542 /*
543 * If this triggers then we have a calculation bug
544 * somewhere. :/
545 */
d1e49f77 546 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
2134a922
PO		 547 }
548
70764a90
TA		 549 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
550 /*
551 * Mark the last descriptor as the terminating descriptor
552 */
553 if (desc != host->adma_desc) {
554 desc -= 8;
555 desc[0] |= 0x2; /* end */
556 }
557 } else {
558 /*
559 * Add a terminating entry.
560 */
2134a922 561
70764a90
TA		 562 /* nop, end, valid */
563 sdhci_set_adma_desc(desc, 0, 0, 0x3);
564 }
2134a922
PO		 565
566 /*
567 * Resync align buffer as we might have changed it.
568 */
569 if (data->flags & MMC_DATA_WRITE) {
570 dma_sync_single_for_device(mmc_dev(host->mmc),
571 host->align_addr, 128 * 4, direction);
572 }
573
8f1934ce
PO		 574 return 0;
575
8f1934ce
PO		 576unmap_align:
577 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
578 128 * 4, direction);
579fail:
580 return -EINVAL;
2134a922
PO		 581}
582
583static void sdhci_adma_table_post(struct sdhci_host *host,
584 struct mmc_data *data)
585{
586 int direction;
587
588 struct scatterlist *sg;
589 int i, size;
590 u8 *align;
591 char *buffer;
592 unsigned long flags;
de0b65a7 593 bool has_unaligned;
2134a922
PO		 594
595 if (data->flags & MMC_DATA_READ)
596 direction = DMA_FROM_DEVICE;
597 else
598 direction = DMA_TO_DEVICE;
599
2134a922
PO		 600 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
601 128 * 4, direction);
602
de0b65a7
RK		 603 /* Do a quick scan of the SG list for any unaligned mappings */
604 has_unaligned = false;
605 for_each_sg(data->sg, sg, host->sg_count, i)
606 if (sg_dma_address(sg) & 3) {
607 has_unaligned = true;
608 break;
609 }
610
611 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 612 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
613 data->sg_len, direction);
614
615 align = host->align_buffer;
616
617 for_each_sg(data->sg, sg, host->sg_count, i) {
618 if (sg_dma_address(sg) & 0x3) {
619 size = 4 - (sg_dma_address(sg) & 0x3);
620
621 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 622 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 623 memcpy(buffer, align, size);
624 sdhci_kunmap_atomic(buffer, &flags);
625
626 align += 4;
627 }
628 }
629 }
630
631 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
632 data->sg_len, direction);
633}
634
a3c7778f 635static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 636{
1c8cde92 637 u8 count;
a3c7778f 638 struct mmc_data *data = cmd->data;
1c8cde92 639 unsigned target_timeout, current_timeout;
d129bceb 640
ee53ab5d
PO		 641 /*
642 * If the host controller provides us with an incorrect timeout
643 * value, just skip the check and use 0xE. The hardware may take
644 * longer to time out, but that's much better than having a too-short
645 * timeout value.
646 */
11a2f1b7 647 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 648 return 0xE;
e538fbe8 649
a3c7778f 650 /* Unspecified timeout, assume max */
1d4d7744 651 if (!data && !cmd->busy_timeout)
a3c7778f 652 return 0xE;
d129bceb 653
a3c7778f
AW		 654 /* timeout in us */
655 if (!data)
1d4d7744 656 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 657 else {
658 target_timeout = data->timeout_ns / 1000;
659 if (host->clock)
660 target_timeout += data->timeout_clks / host->clock;
661 }
81b39802 662
1c8cde92
PO		 663 /*
664 * Figure out needed cycles.
665 * We do this in steps in order to fit inside a 32 bit int.
666 * The first step is the minimum timeout, which will have a
667 * minimum resolution of 6 bits:
668 * (1) 2^13*1000 > 2^22,
669 * (2) host->timeout_clk < 2^16
670 * =>
671 * (1) / (2) > 2^6
672 */
673 count = 0;
674 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
675 while (current_timeout < target_timeout) {
676 count++;
677 current_timeout <<= 1;
678 if (count >= 0xF)
679 break;
680 }
681
682 if (count >= 0xF) {
09eeff52
CB		 683 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
684 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 685 count = 0xE;
686 }
687
ee53ab5d
PO		 688 return count;
689}
690
6aa943ab
AV		 691static void sdhci_set_transfer_irqs(struct sdhci_host *host)
692{
693 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
694 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
695
696 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 697 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 698 else
b537f94c
RK		 699 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
700
701 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
702 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 703}
704
a3c7778f 705static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 706{
707 u8 count;
2134a922 708 u8 ctrl;
a3c7778f 709 struct mmc_data *data = cmd->data;
8f1934ce 710 int ret;
ee53ab5d
PO		 711
712 WARN_ON(host->data);
713
a3c7778f
AW		 714 if (data || (cmd->flags & MMC_RSP_BUSY)) {
715 count = sdhci_calc_timeout(host, cmd);
716 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
717 }
718
719 if (!data)
ee53ab5d
PO		 720 return;
721
722 /* Sanity checks */
723 BUG_ON(data->blksz * data->blocks > 524288);
724 BUG_ON(data->blksz > host->mmc->max_blk_size);
725 BUG_ON(data->blocks > 65535);
726
727 host->data = data;
728 host->data_early = 0;
f6a03cbf 729 host->data->bytes_xfered = 0;
ee53ab5d 730
a13abc7b 731 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 732 host->flags |= SDHCI_REQ_USE_DMA;
733
2134a922
PO		 734 /*
735 * FIXME: This doesn't account for merging when mapping the
736 * scatterlist.
737 */
738 if (host->flags & SDHCI_REQ_USE_DMA) {
739 int broken, i;
740 struct scatterlist *sg;
741
742 broken = 0;
743 if (host->flags & SDHCI_USE_ADMA) {
744 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
745 broken = 1;
746 } else {
747 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
748 broken = 1;
749 }
750
751 if (unlikely(broken)) {
752 for_each_sg(data->sg, sg, data->sg_len, i) {
753 if (sg->length & 0x3) {
754 DBG("Reverting to PIO because of "
755 "transfer size (%d)\n",
756 sg->length);
757 host->flags &= ~SDHCI_REQ_USE_DMA;
758 break;
759 }
760 }
761 }
c9fddbc4
PO		 762 }
763
764 /*
765 * The assumption here being that alignment is the same after
766 * translation to device address space.
767 */
2134a922
PO		 768 if (host->flags & SDHCI_REQ_USE_DMA) {
769 int broken, i;
770 struct scatterlist *sg;
771
772 broken = 0;
773 if (host->flags & SDHCI_USE_ADMA) {
774 /*
775 * As we use 3 byte chunks to work around
776 * alignment problems, we need to check this
777 * quirk.
778 */
779 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
780 broken = 1;
781 } else {
782 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
783 broken = 1;
784 }
785
786 if (unlikely(broken)) {
787 for_each_sg(data->sg, sg, data->sg_len, i) {
788 if (sg->offset & 0x3) {
789 DBG("Reverting to PIO because of "
790 "bad alignment\n");
791 host->flags &= ~SDHCI_REQ_USE_DMA;
792 break;
793 }
794 }
795 }
796 }
797
8f1934ce
PO		 798 if (host->flags & SDHCI_REQ_USE_DMA) {
799 if (host->flags & SDHCI_USE_ADMA) {
800 ret = sdhci_adma_table_pre(host, data);
801 if (ret) {
802 /*
803 * This only happens when someone fed
804 * us an invalid request.
805 */
806 WARN_ON(1);
ebd6d357 807 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 808 } else {
4e4141a5
AV		 809 sdhci_writel(host, host->adma_addr,
810 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 811 }
812 } else {
c8b3e02e 813 int sg_cnt;
8f1934ce 814
c8b3e02e 815 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 816 data->sg, data->sg_len,
817 (data->flags & MMC_DATA_READ) ?
818 DMA_FROM_DEVICE :
819 DMA_TO_DEVICE);
c8b3e02e 820 if (sg_cnt == 0) {
8f1934ce
PO		 821 /*
822 * This only happens when someone fed
823 * us an invalid request.
824 */
825 WARN_ON(1);
ebd6d357 826 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 827 } else {
719a61b4 828 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 829 sdhci_writel(host, sg_dma_address(data->sg),
830 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 831 }
832 }
833 }
834
2134a922
PO		 835 /*
836 * Always adjust the DMA selection as some controllers
837 * (e.g. JMicron) can't do PIO properly when the selection
838 * is ADMA.
839 */
840 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 841 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 842 ctrl &= ~SDHCI_CTRL_DMA_MASK;
843 if ((host->flags & SDHCI_REQ_USE_DMA) &&
844 (host->flags & SDHCI_USE_ADMA))
845 ctrl |= SDHCI_CTRL_ADMA32;
846 else
847 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 848 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 849 }
850
8f1934ce 851 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 852 int flags;
853
854 flags = SG_MITER_ATOMIC;
855 if (host->data->flags & MMC_DATA_READ)
856 flags |= SG_MITER_TO_SG;
857 else
858 flags |= SG_MITER_FROM_SG;
859 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 860 host->blocks = data->blocks;
d129bceb 861 }
c7fa9963 862
6aa943ab
AV		 863 sdhci_set_transfer_irqs(host);
864
f6a03cbf
MV		 865 /* Set the DMA boundary value and block size */
866 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
867 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 868 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 869}
870
871static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 872 struct mmc_command *cmd)
c7fa9963
PO		 873{
874 u16 mode;
e89d456f 875 struct mmc_data *data = cmd->data;
c7fa9963 876
2b558c13
DA		 877 if (data == NULL) {
878 /* clear Auto CMD settings for no data CMDs */
879 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
880 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
881 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
c7fa9963 882 return;
2b558c13 883 }
c7fa9963 884
e538fbe8
PO		 885 WARN_ON(!host->data);
886
c7fa9963 887 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 888 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
889 mode |= SDHCI_TRNS_MULTI;
890 /*
891 * If we are sending CMD23, CMD12 never gets sent
892 * on successful completion (so no Auto-CMD12).
893 */
894 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
895 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 896 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
897 mode |= SDHCI_TRNS_AUTO_CMD23;
898 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
899 }
c4512f79 900 }
8edf6371 901
c7fa9963
PO		 902 if (data->flags & MMC_DATA_READ)
903 mode |= SDHCI_TRNS_READ;
c9fddbc4 904 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 905 mode |= SDHCI_TRNS_DMA;
906
4e4141a5 907 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 908}
909
910static void sdhci_finish_data(struct sdhci_host *host)
911{
912 struct mmc_data *data;
d129bceb
PO		 913
914 BUG_ON(!host->data);
915
916 data = host->data;
917 host->data = NULL;
918
c9fddbc4 919 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 920 if (host->flags & SDHCI_USE_ADMA)
921 sdhci_adma_table_post(host, data);
922 else {
923 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
924 data->sg_len, (data->flags & MMC_DATA_READ) ?
925 DMA_FROM_DEVICE : DMA_TO_DEVICE);
926 }
d129bceb
PO		 927 }
928
929 /*
c9b74c5b
PO		 930 * The specification states that the block count register must
931 * be updated, but it does not specify at what point in the
932 * data flow. That makes the register entirely useless to read
933 * back so we have to assume that nothing made it to the card
934 * in the event of an error.
d129bceb 935 */
c9b74c5b
PO		 936 if (data->error)
937 data->bytes_xfered = 0;
d129bceb 938 else
c9b74c5b 939 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 940
e89d456f
AW		 941 /*
942 * Need to send CMD12 if -
943 * a) open-ended multiblock transfer (no CMD23)
944 * b) error in multiblock transfer
945 */
946 if (data->stop &&
947 (data->error ||
948 !host->mrq->sbc)) {
949
d129bceb
PO		 950 /*
951 * The controller needs a reset of internal state machines
952 * upon error conditions.
953 */
17b0429d 954 if (data->error) {
03231f9b
RK		 955 sdhci_do_reset(host, SDHCI_RESET_CMD);
956 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 957 }
958
959 sdhci_send_command(host, data->stop);
960 } else
961 tasklet_schedule(&host->finish_tasklet);
962}
963
c0e55129 964void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 965{
966 int flags;
fd2208d7 967 u32 mask;
7cb2c76f 968 unsigned long timeout;
d129bceb
PO		 969
970 WARN_ON(host->cmd);
971
d129bceb 972 /* Wait max 10 ms */
7cb2c76f 973 timeout = 10;
fd2208d7
PO		 974
975 mask = SDHCI_CMD_INHIBIT;
976 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
977 mask |= SDHCI_DATA_INHIBIT;
978
979 /* We shouldn't wait for data inihibit for stop commands, even
980 though they might use busy signaling */
981 if (host->mrq->data && (cmd == host->mrq->data->stop))
982 mask &= ~SDHCI_DATA_INHIBIT;
983
4e4141a5 984 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 985 if (timeout == 0) {
a3c76eb9 986 pr_err("%s: Controller never released "
acf1da45 987 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 988 sdhci_dumpregs(host);
17b0429d 989 cmd->error = -EIO;
d129bceb
PO		 990 tasklet_schedule(&host->finish_tasklet);
991 return;
992 }
7cb2c76f
PO		 993 timeout--;
994 mdelay(1);
995 }
d129bceb 996
3e1a6892 997 timeout = jiffies;
1d4d7744
UH		 998 if (!cmd->data && cmd->busy_timeout > 9000)
999 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1000 else
1001 timeout += 10 * HZ;
1002 mod_timer(&host->timer, timeout);
d129bceb
PO		 1003
1004 host->cmd = cmd;
1005
a3c7778f 1006 sdhci_prepare_data(host, cmd);
d129bceb 1007
4e4141a5 1008 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1009
e89d456f 1010 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1011
d129bceb 1012 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1013 pr_err("%s: Unsupported response type!\n",
d129bceb 1014 mmc_hostname(host->mmc));
17b0429d 1015 cmd->error = -EINVAL;
d129bceb
PO		 1016 tasklet_schedule(&host->finish_tasklet);
1017 return;
1018 }
1019
1020 if (!(cmd->flags & MMC_RSP_PRESENT))
1021 flags = SDHCI_CMD_RESP_NONE;
1022 else if (cmd->flags & MMC_RSP_136)
1023 flags = SDHCI_CMD_RESP_LONG;
1024 else if (cmd->flags & MMC_RSP_BUSY)
1025 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1026 else
1027 flags = SDHCI_CMD_RESP_SHORT;
1028
1029 if (cmd->flags & MMC_RSP_CRC)
1030 flags |= SDHCI_CMD_CRC;
1031 if (cmd->flags & MMC_RSP_OPCODE)
1032 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1033
1034 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1035 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1036 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1037 flags |= SDHCI_CMD_DATA;
1038
4e4141a5 1039 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1040}
c0e55129 1041EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1042
1043static void sdhci_finish_command(struct sdhci_host *host)
1044{
1045 int i;
1046
1047 BUG_ON(host->cmd == NULL);
1048
1049 if (host->cmd->flags & MMC_RSP_PRESENT) {
1050 if (host->cmd->flags & MMC_RSP_136) {
1051 /* CRC is stripped so we need to do some shifting. */
1052 for (i = 0;i < 4;i++) {
4e4141a5 1053 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1054 SDHCI_RESPONSE + (3-i)*4) << 8;
1055 if (i != 3)
1056 host->cmd->resp[i] |=
4e4141a5 1057 sdhci_readb(host,
d129bceb
PO		 1058 SDHCI_RESPONSE + (3-i)*4-1);
1059 }
1060 } else {
4e4141a5 1061 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1062 }
1063 }
1064
17b0429d 1065 host->cmd->error = 0;
d129bceb 1066
e89d456f
AW		 1067 /* Finished CMD23, now send actual command. */
1068 if (host->cmd == host->mrq->sbc) {
1069 host->cmd = NULL;
1070 sdhci_send_command(host, host->mrq->cmd);
1071 } else {
e538fbe8 1072
e89d456f
AW		 1073 /* Processed actual command. */
1074 if (host->data && host->data_early)
1075 sdhci_finish_data(host);
d129bceb 1076
e89d456f
AW		 1077 if (!host->cmd->data)
1078 tasklet_schedule(&host->finish_tasklet);
1079
1080 host->cmd = NULL;
1081 }
d129bceb
PO		 1082}
1083
52983382
KL		 1084static u16 sdhci_get_preset_value(struct sdhci_host *host)
1085{
1086 u16 ctrl, preset = 0;
1087
1088 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1089
1090 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1091 case SDHCI_CTRL_UHS_SDR12:
1092 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1093 break;
1094 case SDHCI_CTRL_UHS_SDR25:
1095 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1096 break;
1097 case SDHCI_CTRL_UHS_SDR50:
1098 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1099 break;
1100 case SDHCI_CTRL_UHS_SDR104:
1101 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1102 break;
1103 case SDHCI_CTRL_UHS_DDR50:
1104 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1105 break;
1106 default:
1107 pr_warn("%s: Invalid UHS-I mode selected\n",
1108 mmc_hostname(host->mmc));
1109 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1110 break;
1111 }
1112 return preset;
1113}
1114
d129bceb
PO		 1115static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1116{
c3ed3877 1117 int div = 0; /* Initialized for compiler warning */
df16219f 1118 int real_div = div, clk_mul = 1;
c3ed3877 1119 u16 clk = 0;
7cb2c76f 1120 unsigned long timeout;
d129bceb 1121
df16219f
GC		 1122 host->mmc->actual_clock = 0;
1123
8114634c
AV		 1124 if (host->ops->set_clock) {
1125 host->ops->set_clock(host, clock);
1126 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1127 return;
1128 }
1129
4e4141a5 1130 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1131
1132 if (clock == 0)
1133 goto out;
1134
85105c53 1135 if (host->version >= SDHCI_SPEC_300) {
52983382
KL		 1136 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1137 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1138 u16 pre_val;
1139
1140 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1141 pre_val = sdhci_get_preset_value(host);
1142 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1143 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1144 if (host->clk_mul &&
1145 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1146 clk = SDHCI_PROG_CLOCK_MODE;
1147 real_div = div + 1;
1148 clk_mul = host->clk_mul;
1149 } else {
1150 real_div = max_t(int, 1, div << 1);
1151 }
1152 goto clock_set;
1153 }
1154
c3ed3877
AN		 1155 /*
1156 * Check if the Host Controller supports Programmable Clock
1157 * Mode.
1158 */
1159 if (host->clk_mul) {
52983382
KL		 1160 for (div = 1; div <= 1024; div++) {
1161 if ((host->max_clk * host->clk_mul / div)
1162 <= clock)
1163 break;
1164 }
c3ed3877 1165 /*
52983382
KL		 1166 * Set Programmable Clock Mode in the Clock
1167 * Control register.
c3ed3877 1168 */
52983382
KL		 1169 clk = SDHCI_PROG_CLOCK_MODE;
1170 real_div = div;
1171 clk_mul = host->clk_mul;
1172 div--;
c3ed3877
AN		 1173 } else {
1174 /* Version 3.00 divisors must be a multiple of 2. */
1175 if (host->max_clk <= clock)
1176 div = 1;
1177 else {
1178 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1179 div += 2) {
1180 if ((host->max_clk / div) <= clock)
1181 break;
1182 }
85105c53 1183 }
df16219f 1184 real_div = div;
c3ed3877 1185 div >>= 1;
85105c53
ZG		 1186 }
1187 } else {
1188 /* Version 2.00 divisors must be a power of 2. */
0397526d 1189 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1190 if ((host->max_clk / div) <= clock)
1191 break;
1192 }
df16219f 1193 real_div = div;
c3ed3877 1194 div >>= 1;
d129bceb 1195 }
d129bceb 1196
52983382 1197clock_set:
df16219f
GC		 1198 if (real_div)
1199 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1200
c3ed3877 1201 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1202 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1203 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1204 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1205 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1206
27f6cb16
CB		 1207 /* Wait max 20 ms */
1208 timeout = 20;
4e4141a5 1209 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1210 & SDHCI_CLOCK_INT_STABLE)) {
1211 if (timeout == 0) {
a3c76eb9 1212 pr_err("%s: Internal clock never "
acf1da45 1213 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1214 sdhci_dumpregs(host);
1215 return;
1216 }
7cb2c76f
PO		 1217 timeout--;
1218 mdelay(1);
1219 }
d129bceb
PO		 1220
1221 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1222 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1223
1224out:
1225 host->clock = clock;
1226}
1227
ceb6143b 1228static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1229{
8364248a 1230 u8 pwr = 0;
146ad66e 1231
8364248a 1232 if (power != (unsigned short)-1) {
ae628903
PO		 1233 switch (1 << power) {
1234 case MMC_VDD_165_195:
1235 pwr = SDHCI_POWER_180;
1236 break;
1237 case MMC_VDD_29_30:
1238 case MMC_VDD_30_31:
1239 pwr = SDHCI_POWER_300;
1240 break;
1241 case MMC_VDD_32_33:
1242 case MMC_VDD_33_34:
1243 pwr = SDHCI_POWER_330;
1244 break;
1245 default:
1246 BUG();
1247 }
1248 }
1249
1250 if (host->pwr == pwr)
ceb6143b 1251 return -1;
146ad66e 1252
ae628903
PO		 1253 host->pwr = pwr;
1254
1255 if (pwr == 0) {
4e4141a5 1256 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1257 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1258 sdhci_runtime_pm_bus_off(host);
ceb6143b 1259 return 0;
9e9dc5f2
DS		 1260 }
1261
1262 /*
1263 * Spec says that we should clear the power reg before setting
1264 * a new value. Some controllers don't seem to like this though.
1265 */
b8c86fc5 1266 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1267 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1268
e08c1694 1269 /*
c71f6512 1270 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1271 * and set turn on power at the same time, so set the voltage first.
1272 */
11a2f1b7 1273 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1274 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1275
ae628903 1276 pwr |= SDHCI_POWER_ON;
146ad66e 1277
ae628903 1278 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1279
f0710a55
AH		 1280 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1281 sdhci_runtime_pm_bus_on(host);
1282
557b0697
HW		 1283 /*
1284 * Some controllers need an extra 10ms delay of 10ms before they
1285 * can apply clock after applying power
1286 */
11a2f1b7 1287 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1288 mdelay(10);
ceb6143b
AH		 1289
1290 return power;
146ad66e
PO		 1291}
1292
d129bceb
PO		 1293/*****************************************************************************\
1294 * *
1295 * MMC callbacks *
1296 * *
1297\*****************************************************************************/
1298
1299static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1300{
1301 struct sdhci_host *host;
505a8680 1302 int present;
d129bceb 1303 unsigned long flags;
473b095a 1304 u32 tuning_opcode;
d129bceb
PO		 1305
1306 host = mmc_priv(mmc);
1307
66fd8ad5
AH		 1308 sdhci_runtime_pm_get(host);
1309
d129bceb
PO		 1310 spin_lock_irqsave(&host->lock, flags);
1311
1312 WARN_ON(host->mrq != NULL);
1313
f9134319 1314#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1315 sdhci_activate_led(host);
2f730fec 1316#endif
e89d456f
AW		 1317
1318 /*
1319 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1320 * requests if Auto-CMD12 is enabled.
1321 */
1322 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1323 if (mrq->stop) {
1324 mrq->data->stop = NULL;
1325 mrq->stop = NULL;
1326 }
1327 }
d129bceb
PO		 1328
1329 host->mrq = mrq;
1330
505a8680
SG		 1331 /*
1332 * Firstly check card presence from cd-gpio. The return could
1333 * be one of the following possibilities:
1334 * negative: cd-gpio is not available
1335 * zero: cd-gpio is used, and card is removed
1336 * one: cd-gpio is used, and card is present
1337 */
1338 present = mmc_gpio_get_cd(host->mmc);
1339 if (present < 0) {
1340 /* If polling, assume that the card is always present. */
1341 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1342 present = 1;
1343 else
1344 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1345 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1346 }
1347
68d1fb7e 1348 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1349 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1350 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1351 } else {
1352 u32 present_state;
1353
1354 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1355 /*
1356 * Check if the re-tuning timer has already expired and there
1357 * is no on-going data transfer. If so, we need to execute
1358 * tuning procedure before sending command.
1359 */
1360 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1361 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1362 if (mmc->card) {
1363 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1364 tuning_opcode =
1365 mmc->card->type == MMC_TYPE_MMC ?
1366 MMC_SEND_TUNING_BLOCK_HS200 :
1367 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1368
1369 /* Here we need to set the host->mrq to NULL,
1370 * in case the pending finish_tasklet
1371 * finishes it incorrectly.
1372 */
1373 host->mrq = NULL;
1374
14efd957
CB		 1375 spin_unlock_irqrestore(&host->lock, flags);
1376 sdhci_execute_tuning(mmc, tuning_opcode);
1377 spin_lock_irqsave(&host->lock, flags);
1378
1379 /* Restore original mmc_request structure */
1380 host->mrq = mrq;
1381 }
cf2b5eea
AN		 1382 }
1383
8edf6371 1384 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1385 sdhci_send_command(host, mrq->sbc);
1386 else
1387 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1388 }
d129bceb 1389
5f25a66f 1390 mmiowb();
d129bceb
PO		 1391 spin_unlock_irqrestore(&host->lock, flags);
1392}
1393
2317f56c
RK		 1394void sdhci_set_bus_width(struct sdhci_host *host, int width)
1395{
1396 u8 ctrl;
1397
1398 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1399 if (width == MMC_BUS_WIDTH_8) {
1400 ctrl &= ~SDHCI_CTRL_4BITBUS;
1401 if (host->version >= SDHCI_SPEC_300)
1402 ctrl |= SDHCI_CTRL_8BITBUS;
1403 } else {
1404 if (host->version >= SDHCI_SPEC_300)
1405 ctrl &= ~SDHCI_CTRL_8BITBUS;
1406 if (width == MMC_BUS_WIDTH_4)
1407 ctrl |= SDHCI_CTRL_4BITBUS;
1408 else
1409 ctrl &= ~SDHCI_CTRL_4BITBUS;
1410 }
1411 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1412}
1413EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1414
66fd8ad5 1415static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1416{
d129bceb 1417 unsigned long flags;
ceb6143b 1418 int vdd_bit = -1;
d129bceb
PO		 1419 u8 ctrl;
1420
d129bceb
PO		 1421 spin_lock_irqsave(&host->lock, flags);
1422
ceb6143b
AH		 1423 if (host->flags & SDHCI_DEVICE_DEAD) {
1424 spin_unlock_irqrestore(&host->lock, flags);
1425 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1426 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1427 return;
1428 }
1e72859e 1429
d129bceb
PO		 1430 /*
1431 * Reset the chip on each power off.
1432 * Should clear out any weird states.
1433 */
1434 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1435 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1436 sdhci_reinit(host);
d129bceb
PO		 1437 }
1438
52983382 1439 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1440 (ios->power_mode == MMC_POWER_UP) &&
1441 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1442 sdhci_enable_preset_value(host, false);
1443
91138ca5
RK		 1444 if (!ios->clock || ios->clock != host->clock)
1445 sdhci_set_clock(host, ios->clock);
d129bceb
PO		 1446
1447 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1448 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1449 else
ceb6143b
AH		 1450 vdd_bit = sdhci_set_power(host, ios->vdd);
1451
1452 if (host->vmmc && vdd_bit != -1) {
1453 spin_unlock_irqrestore(&host->lock, flags);
1454 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1455 spin_lock_irqsave(&host->lock, flags);
1456 }
d129bceb 1457
643a81ff
PR		 1458 if (host->ops->platform_send_init_74_clocks)
1459 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1460
2317f56c 1461 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1462
15ec4461 1463 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1464
3ab9c8da
PR		 1465 if ((ios->timing == MMC_TIMING_SD_HS ||
1466 ios->timing == MMC_TIMING_MMC_HS)
1467 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1468 ctrl |= SDHCI_CTRL_HISPD;
1469 else
1470 ctrl &= ~SDHCI_CTRL_HISPD;
1471
d6d50a15 1472 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1473 u16 clk, ctrl_2;
49c468fc
AN		 1474
1475 /* In case of UHS-I modes, set High Speed Enable */
069c9f14 1476 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1477 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1478 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1479 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1480 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1481 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1482 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1483
1484 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1485 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1486 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1487 /*
1488 * We only need to set Driver Strength if the
1489 * preset value enable is not set.
1490 */
1491 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1492 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1493 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1494 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1495 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1496
1497 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1498 } else {
1499 /*
1500 * According to SDHC Spec v3.00, if the Preset Value
1501 * Enable in the Host Control 2 register is set, we
1502 * need to reset SD Clock Enable before changing High
1503 * Speed Enable to avoid generating clock gliches.
1504 */
758535c4
AN		 1505
1506 /* Reset SD Clock Enable */
1507 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1508 clk &= ~SDHCI_CLOCK_CARD_EN;
1509 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1510
1511 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1512
1513 /* Re-enable SD Clock */
91138ca5 1514 sdhci_set_clock(host, host->clock);
d6d50a15 1515 }
49c468fc 1516
49c468fc
AN		 1517
1518 /* Reset SD Clock Enable */
1519 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1520 clk &= ~SDHCI_CLOCK_CARD_EN;
1521 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1522
6322cdd0
PR		 1523 if (host->ops->set_uhs_signaling)
1524 host->ops->set_uhs_signaling(host, ios->timing);
1525 else {
1526 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1527 /* Select Bus Speed Mode for host */
1528 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
59911568
GC		 1529 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1530 (ios->timing == MMC_TIMING_UHS_SDR104))
1531 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
069c9f14 1532 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1533 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1534 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1535 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1536 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1537 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
bb8175a8
SJ		 1538 else if ((ios->timing == MMC_TIMING_UHS_DDR50) ||
1539 (ios->timing == MMC_TIMING_MMC_DDR52))
6322cdd0
PR		 1540 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1541 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1542 }
49c468fc 1543
52983382
KL		 1544 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1545 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1546 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1547 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1548 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1549 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1550 u16 preset;
1551
1552 sdhci_enable_preset_value(host, true);
1553 preset = sdhci_get_preset_value(host);
1554 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1555 >> SDHCI_PRESET_DRV_SHIFT;
1556 }
1557
49c468fc 1558 /* Re-enable SD Clock */
91138ca5 1559 sdhci_set_clock(host, host->clock);
758535c4
AN		 1560 } else
1561 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1562
b8352260
LD		 1563 /*
1564 * Some (ENE) controllers go apeshit on some ios operation,
1565 * signalling timeout and CRC errors even on CMD0. Resetting
1566 * it on each ios seems to solve the problem.
1567 */
b8c86fc5 1568 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1569 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1570
5f25a66f 1571 mmiowb();
d129bceb
PO		 1572 spin_unlock_irqrestore(&host->lock, flags);
1573}
1574
66fd8ad5
AH		 1575static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1576{
1577 struct sdhci_host *host = mmc_priv(mmc);
1578
1579 sdhci_runtime_pm_get(host);
1580 sdhci_do_set_ios(host, ios);
1581 sdhci_runtime_pm_put(host);
1582}
1583
94144a46
KL		 1584static int sdhci_do_get_cd(struct sdhci_host *host)
1585{
1586 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1587
1588 if (host->flags & SDHCI_DEVICE_DEAD)
1589 return 0;
1590
1591 /* If polling/nonremovable, assume that the card is always present. */
1592 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1593 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1594 return 1;
1595
1596 /* Try slot gpio detect */
1597 if (!IS_ERR_VALUE(gpio_cd))
1598 return !!gpio_cd;
1599
1600 /* Host native card detect */
1601 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1602}
1603
1604static int sdhci_get_cd(struct mmc_host *mmc)
1605{
1606 struct sdhci_host *host = mmc_priv(mmc);
1607 int ret;
1608
1609 sdhci_runtime_pm_get(host);
1610 ret = sdhci_do_get_cd(host);
1611 sdhci_runtime_pm_put(host);
1612 return ret;
1613}
1614
66fd8ad5 1615static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1616{
d129bceb 1617 unsigned long flags;
2dfb579c 1618 int is_readonly;
d129bceb 1619
d129bceb
PO		 1620 spin_lock_irqsave(&host->lock, flags);
1621
1e72859e 1622 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1623 is_readonly = 0;
1624 else if (host->ops->get_ro)
1625 is_readonly = host->ops->get_ro(host);
1e72859e 1626 else
2dfb579c
WS		 1627 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1628 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1629
1630 spin_unlock_irqrestore(&host->lock, flags);
1631
2dfb579c
WS		 1632 /* This quirk needs to be replaced by a callback-function later */
1633 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1634 !is_readonly : is_readonly;
d129bceb
PO		 1635}
1636
82b0e23a
TI		 1637#define SAMPLE_COUNT 5
1638
66fd8ad5 1639static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1640{
82b0e23a
TI		 1641 int i, ro_count;
1642
82b0e23a 1643 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1644 return sdhci_check_ro(host);
82b0e23a
TI		 1645
1646 ro_count = 0;
1647 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1648 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1649 if (++ro_count > SAMPLE_COUNT / 2)
1650 return 1;
1651 }
1652 msleep(30);
1653 }
1654 return 0;
1655}
1656
20758b66
AH		 1657static void sdhci_hw_reset(struct mmc_host *mmc)
1658{
1659 struct sdhci_host *host = mmc_priv(mmc);
1660
1661 if (host->ops && host->ops->hw_reset)
1662 host->ops->hw_reset(host);
1663}
1664
66fd8ad5 1665static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1666{
66fd8ad5
AH		 1667 struct sdhci_host *host = mmc_priv(mmc);
1668 int ret;
f75979b7 1669
66fd8ad5
AH		 1670 sdhci_runtime_pm_get(host);
1671 ret = sdhci_do_get_ro(host);
1672 sdhci_runtime_pm_put(host);
1673 return ret;
1674}
f75979b7 1675
66fd8ad5
AH		 1676static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1677{
be138554 1678 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1679 if (enable)
b537f94c 1680 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1681 else
b537f94c
RK		 1682 host->ier &= ~SDHCI_INT_CARD_INT;
1683
1684 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1685 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1686 mmiowb();
1687 }
66fd8ad5
AH		 1688}
1689
1690static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1691{
1692 struct sdhci_host *host = mmc_priv(mmc);
1693 unsigned long flags;
f75979b7 1694
ef104333
RK		 1695 sdhci_runtime_pm_get(host);
1696
66fd8ad5 1697 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1698 if (enable)
1699 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1700 else
1701 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1702
66fd8ad5 1703 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1704 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1705
1706 sdhci_runtime_pm_put(host);
f75979b7
PO		 1707}
1708
20b92a30 1709static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1710 struct mmc_ios *ios)
f2119df6 1711{
20b92a30 1712 u16 ctrl;
6231f3de 1713 int ret;
f2119df6 1714
20b92a30
KL		 1715 /*
1716 * Signal Voltage Switching is only applicable for Host Controllers
1717 * v3.00 and above.
1718 */
1719 if (host->version < SDHCI_SPEC_300)
1720 return 0;
6231f3de 1721
f2119df6 1722 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1723
21f5998f 1724 switch (ios->signal_voltage) {
20b92a30
KL		 1725 case MMC_SIGNAL_VOLTAGE_330:
1726 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1727 ctrl &= ~SDHCI_CTRL_VDD_180;
1728 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1729
20b92a30
KL		 1730 if (host->vqmmc) {
1731 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1732 if (ret) {
1733 pr_warning("%s: Switching to 3.3V signalling voltage "
1734 " failed\n", mmc_hostname(host->mmc));
1735 return -EIO;
1736 }
1737 }
1738 /* Wait for 5ms */
1739 usleep_range(5000, 5500);
f2119df6 1740
20b92a30
KL		 1741 /* 3.3V regulator output should be stable within 5 ms */
1742 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1743 if (!(ctrl & SDHCI_CTRL_VDD_180))
1744 return 0;
6231f3de 1745
20b92a30
KL		 1746 pr_warning("%s: 3.3V regulator output did not became stable\n",
1747 mmc_hostname(host->mmc));
1748
1749 return -EAGAIN;
1750 case MMC_SIGNAL_VOLTAGE_180:
1751 if (host->vqmmc) {
1752 ret = regulator_set_voltage(host->vqmmc,
1753 1700000, 1950000);
1754 if (ret) {
1755 pr_warning("%s: Switching to 1.8V signalling voltage "
1756 " failed\n", mmc_hostname(host->mmc));
1757 return -EIO;
1758 }
1759 }
6231f3de 1760
6231f3de
PR		 1761 /*
1762 * Enable 1.8V Signal Enable in the Host Control2
1763 * register
1764 */
20b92a30
KL		 1765 ctrl |= SDHCI_CTRL_VDD_180;
1766 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1767
20b92a30
KL		 1768 /* Wait for 5ms */
1769 usleep_range(5000, 5500);
f2119df6 1770
20b92a30
KL		 1771 /* 1.8V regulator output should be stable within 5 ms */
1772 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1773 if (ctrl & SDHCI_CTRL_VDD_180)
1774 return 0;
f2119df6 1775
20b92a30
KL		 1776 pr_warning("%s: 1.8V regulator output did not became stable\n",
1777 mmc_hostname(host->mmc));
f2119df6 1778
20b92a30
KL		 1779 return -EAGAIN;
1780 case MMC_SIGNAL_VOLTAGE_120:
1781 if (host->vqmmc) {
1782 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1783 if (ret) {
1784 pr_warning("%s: Switching to 1.2V signalling voltage "
1785 " failed\n", mmc_hostname(host->mmc));
1786 return -EIO;
f2119df6
AN		 1787 }
1788 }
6231f3de 1789 return 0;
20b92a30 1790 default:
f2119df6
AN		 1791 /* No signal voltage switch required */
1792 return 0;
20b92a30 1793 }
f2119df6
AN		 1794}
1795
66fd8ad5 1796static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1797 struct mmc_ios *ios)
66fd8ad5
AH		 1798{
1799 struct sdhci_host *host = mmc_priv(mmc);
1800 int err;
1801
1802 if (host->version < SDHCI_SPEC_300)
1803 return 0;
1804 sdhci_runtime_pm_get(host);
21f5998f 1805 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1806 sdhci_runtime_pm_put(host);
1807 return err;
1808}
1809
20b92a30
KL		 1810static int sdhci_card_busy(struct mmc_host *mmc)
1811{
1812 struct sdhci_host *host = mmc_priv(mmc);
1813 u32 present_state;
1814
1815 sdhci_runtime_pm_get(host);
1816 /* Check whether DAT[3:0] is 0000 */
1817 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1818 sdhci_runtime_pm_put(host);
1819
1820 return !(present_state & SDHCI_DATA_LVL_MASK);
1821}
1822
069c9f14 1823static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1824{
1825 struct sdhci_host *host;
1826 u16 ctrl;
b513ea25
AN		 1827 int tuning_loop_counter = MAX_TUNING_LOOP;
1828 unsigned long timeout;
1829 int err = 0;
069c9f14 1830 bool requires_tuning_nonuhs = false;
2b35bd83 1831 unsigned long flags;
b513ea25
AN		 1832
1833 host = mmc_priv(mmc);
1834
66fd8ad5 1835 sdhci_runtime_pm_get(host);
2b35bd83 1836 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1837
1838 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1839
1840 /*
069c9f14
G		 1841 * The Host Controller needs tuning only in case of SDR104 mode
1842 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1843 * Capabilities register.
069c9f14
G		 1844 * If the Host Controller supports the HS200 mode then the
1845 * tuning function has to be executed.
b513ea25 1846 */
069c9f14
G		 1847 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1848 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
156e14b1 1849 host->flags & SDHCI_SDR104_NEEDS_TUNING))
069c9f14
G		 1850 requires_tuning_nonuhs = true;
1851
b513ea25 1852 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1853 requires_tuning_nonuhs)
b513ea25
AN		 1854 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1855 else {
2b35bd83 1856 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 1857 sdhci_runtime_pm_put(host);
b513ea25
AN		 1858 return 0;
1859 }
1860
45251812 1861 if (host->ops->platform_execute_tuning) {
2b35bd83 1862 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1863 err = host->ops->platform_execute_tuning(host, opcode);
1864 sdhci_runtime_pm_put(host);
1865 return err;
1866 }
1867
b513ea25
AN		 1868 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1869
1870 /*
1871 * As per the Host Controller spec v3.00, tuning command
1872 * generates Buffer Read Ready interrupt, so enable that.
1873 *
1874 * Note: The spec clearly says that when tuning sequence
1875 * is being performed, the controller does not generate
1876 * interrupts other than Buffer Read Ready interrupt. But
1877 * to make sure we don't hit a controller bug, we _only_
1878 * enable Buffer Read Ready interrupt here.
1879 */
b537f94c
RK		 1880 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1881 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1882
1883 /*
1884 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1885 * of loops reaches 40 times or a timeout of 150ms occurs.
1886 */
1887 timeout = 150;
1888 do {
1889 struct mmc_command cmd = {0};
66fd8ad5 1890 struct mmc_request mrq = {NULL};
b513ea25
AN		 1891
1892 if (!tuning_loop_counter && !timeout)
1893 break;
1894
069c9f14 1895 cmd.opcode = opcode;
b513ea25
AN		 1896 cmd.arg = 0;
1897 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1898 cmd.retries = 0;
1899 cmd.data = NULL;
1900 cmd.error = 0;
1901
1902 mrq.cmd = &cmd;
1903 host->mrq = &mrq;
1904
1905 /*
1906 * In response to CMD19, the card sends 64 bytes of tuning
1907 * block to the Host Controller. So we set the block size
1908 * to 64 here.
1909 */
069c9f14
G		 1910 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1911 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1912 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1913 SDHCI_BLOCK_SIZE);
1914 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1915 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1916 SDHCI_BLOCK_SIZE);
1917 } else {
1918 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1919 SDHCI_BLOCK_SIZE);
1920 }
b513ea25
AN		 1921
1922 /*
1923 * The tuning block is sent by the card to the host controller.
1924 * So we set the TRNS_READ bit in the Transfer Mode register.
1925 * This also takes care of setting DMA Enable and Multi Block
1926 * Select in the same register to 0.
1927 */
1928 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1929
1930 sdhci_send_command(host, &cmd);
1931
1932 host->cmd = NULL;
1933 host->mrq = NULL;
1934
2b35bd83 1935 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1936 /* Wait for Buffer Read Ready interrupt */
1937 wait_event_interruptible_timeout(host->buf_ready_int,
1938 (host->tuning_done == 1),
1939 msecs_to_jiffies(50));
2b35bd83 1940 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1941
1942 if (!host->tuning_done) {
a3c76eb9 1943 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1944 "Buffer Read Ready interrupt during tuning "
1945 "procedure, falling back to fixed sampling "
1946 "clock\n");
1947 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1948 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1949 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1950 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1951
1952 err = -EIO;
1953 goto out;
1954 }
1955
1956 host->tuning_done = 0;
1957
1958 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1959 tuning_loop_counter--;
1960 timeout--;
197160d5
NS		 1961
1962 /* eMMC spec does not require a delay between tuning cycles */
1963 if (opcode == MMC_SEND_TUNING_BLOCK)
1964 mdelay(1);
b513ea25
AN		 1965 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1966
1967 /*
1968 * The Host Driver has exhausted the maximum number of loops allowed,
1969 * so use fixed sampling frequency.
1970 */
1971 if (!tuning_loop_counter || !timeout) {
1972 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1973 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
114f2bf6 1974 err = -EIO;
b513ea25
AN		 1975 } else {
1976 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1977 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1978 " failed, falling back to fixed sampling"
1979 " clock\n");
1980 err = -EIO;
1981 }
1982 }
1983
1984out:
cf2b5eea
AN		 1985 /*
1986 * If this is the very first time we are here, we start the retuning
1987 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1988 * flag won't be set, we check this condition before actually starting
1989 * the timer.
1990 */
1991 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1992 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 1993 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 1994 mod_timer(&host->tuning_timer, jiffies +
1995 host->tuning_count * HZ);
1996 /* Tuning mode 1 limits the maximum data length to 4MB */
1997 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2bc02485 1998 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
cf2b5eea
AN		 1999 host->flags &= ~SDHCI_NEEDS_RETUNING;
2000 /* Reload the new initial value for timer */
2bc02485
AS		 2001 mod_timer(&host->tuning_timer, jiffies +
2002 host->tuning_count * HZ);
cf2b5eea
AN		 2003 }
2004
2005 /*
2006 * In case tuning fails, host controllers which support re-tuning can
2007 * try tuning again at a later time, when the re-tuning timer expires.
2008 * So for these controllers, we return 0. Since there might be other
2009 * controllers who do not have this capability, we return error for
973905fe
AL		 2010 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2011 * a retuning timer to do the retuning for the card.
cf2b5eea 2012 */
973905fe 2013 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2014 err = 0;
2015
b537f94c
RK		 2016 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2017 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2b35bd83 2018 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2019 sdhci_runtime_pm_put(host);
b513ea25
AN		 2020
2021 return err;
2022}
2023
52983382
KL		 2024
2025static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2026{
4d55c5a1 2027 u16 ctrl;
4d55c5a1 2028
4d55c5a1
AN		 2029 /* Host Controller v3.00 defines preset value registers */
2030 if (host->version < SDHCI_SPEC_300)
2031 return;
2032
4d55c5a1
AN		 2033 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2034
2035 /*
2036 * We only enable or disable Preset Value if they are not already
2037 * enabled or disabled respectively. Otherwise, we bail out.
2038 */
2039 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2040 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2041 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2042 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 2043 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2044 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2045 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2046 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1 2047 }
66fd8ad5
AH		 2048}
2049
71e69211 2050static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2051{
71e69211 2052 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2053 unsigned long flags;
2054
722e1280
CD		 2055 /* First check if client has provided their own card event */
2056 if (host->ops->card_event)
2057 host->ops->card_event(host);
2058
d129bceb
PO		 2059 spin_lock_irqsave(&host->lock, flags);
2060
66fd8ad5 2061 /* Check host->mrq first in case we are runtime suspended */
9668d765 2062 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2063 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2064 mmc_hostname(host->mmc));
a3c76eb9 2065 pr_err("%s: Resetting controller.\n",
66fd8ad5 2066 mmc_hostname(host->mmc));
d129bceb 2067
03231f9b
RK		 2068 sdhci_do_reset(host, SDHCI_RESET_CMD);
2069 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2070
66fd8ad5
AH		 2071 host->mrq->cmd->error = -ENOMEDIUM;
2072 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2073 }
2074
2075 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2076}
2077
2078static const struct mmc_host_ops sdhci_ops = {
2079 .request = sdhci_request,
2080 .set_ios = sdhci_set_ios,
94144a46 2081 .get_cd = sdhci_get_cd,
71e69211
GL		 2082 .get_ro = sdhci_get_ro,
2083 .hw_reset = sdhci_hw_reset,
2084 .enable_sdio_irq = sdhci_enable_sdio_irq,
2085 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2086 .execute_tuning = sdhci_execute_tuning,
71e69211 2087 .card_event = sdhci_card_event,
20b92a30 2088 .card_busy = sdhci_card_busy,
71e69211
GL		 2089};
2090
2091/*****************************************************************************\
2092 * *
2093 * Tasklets *
2094 * *
2095\*****************************************************************************/
2096
d129bceb
PO		 2097static void sdhci_tasklet_finish(unsigned long param)
2098{
2099 struct sdhci_host *host;
2100 unsigned long flags;
2101 struct mmc_request *mrq;
2102
2103 host = (struct sdhci_host*)param;
2104
66fd8ad5
AH		 2105 spin_lock_irqsave(&host->lock, flags);
2106
0c9c99a7
CB		 2107 /*
2108 * If this tasklet gets rescheduled while running, it will
2109 * be run again afterwards but without any active request.
2110 */
66fd8ad5
AH		 2111 if (!host->mrq) {
2112 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2113 return;
66fd8ad5 2114 }
d129bceb
PO		 2115
2116 del_timer(&host->timer);
2117
2118 mrq = host->mrq;
2119
d129bceb
PO		 2120 /*
2121 * The controller needs a reset of internal state machines
2122 * upon error conditions.
2123 */
1e72859e 2124 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2125 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2126 (mrq->data && (mrq->data->error ||
2127 (mrq->data->stop && mrq->data->stop->error))) ||
2128 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2129
2130 /* Some controllers need this kick or reset won't work here */
8213af3b 2131 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2132 /* This is to force an update */
91138ca5 2133 sdhci_set_clock(host, host->clock);
645289dc
PO		 2134
2135 /* Spec says we should do both at the same time, but Ricoh
2136 controllers do not like that. */
03231f9b
RK		 2137 sdhci_do_reset(host, SDHCI_RESET_CMD);
2138 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2139 }
2140
2141 host->mrq = NULL;
2142 host->cmd = NULL;
2143 host->data = NULL;
2144
f9134319 2145#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2146 sdhci_deactivate_led(host);
2f730fec 2147#endif
d129bceb 2148
5f25a66f 2149 mmiowb();
d129bceb
PO		 2150 spin_unlock_irqrestore(&host->lock, flags);
2151
2152 mmc_request_done(host->mmc, mrq);
66fd8ad5 2153 sdhci_runtime_pm_put(host);
d129bceb
PO		 2154}
2155
2156static void sdhci_timeout_timer(unsigned long data)
2157{
2158 struct sdhci_host *host;
2159 unsigned long flags;
2160
2161 host = (struct sdhci_host*)data;
2162
2163 spin_lock_irqsave(&host->lock, flags);
2164
2165 if (host->mrq) {
a3c76eb9 2166 pr_err("%s: Timeout waiting for hardware "
acf1da45 2167 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2168 sdhci_dumpregs(host);
2169
2170 if (host->data) {
17b0429d 2171 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2172 sdhci_finish_data(host);
2173 } else {
2174 if (host->cmd)
17b0429d 2175 host->cmd->error = -ETIMEDOUT;
d129bceb 2176 else
17b0429d 2177 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2178
2179 tasklet_schedule(&host->finish_tasklet);
2180 }
2181 }
2182
5f25a66f 2183 mmiowb();
d129bceb
PO		 2184 spin_unlock_irqrestore(&host->lock, flags);
2185}
2186
cf2b5eea
AN		 2187static void sdhci_tuning_timer(unsigned long data)
2188{
2189 struct sdhci_host *host;
2190 unsigned long flags;
2191
2192 host = (struct sdhci_host *)data;
2193
2194 spin_lock_irqsave(&host->lock, flags);
2195
2196 host->flags |= SDHCI_NEEDS_RETUNING;
2197
2198 spin_unlock_irqrestore(&host->lock, flags);
2199}
2200
d129bceb
PO		 2201/*****************************************************************************\
2202 * *
2203 * Interrupt handling *
2204 * *
2205\*****************************************************************************/
2206
2207static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2208{
2209 BUG_ON(intmask == 0);
2210
2211 if (!host->cmd) {
a3c76eb9 2212 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2213 "though no command operation was in progress.\n",
2214 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2215 sdhci_dumpregs(host);
2216 return;
2217 }
2218
43b58b36 2219 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2220 host->cmd->error = -ETIMEDOUT;
2221 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2222 SDHCI_INT_INDEX))
2223 host->cmd->error = -EILSEQ;
43b58b36 2224
e809517f 2225 if (host->cmd->error) {
d129bceb 2226 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2227 return;
2228 }
2229
2230 /*
2231 * The host can send and interrupt when the busy state has
2232 * ended, allowing us to wait without wasting CPU cycles.
2233 * Unfortunately this is overloaded on the "data complete"
2234 * interrupt, so we need to take some care when handling
2235 * it.
2236 *
2237 * Note: The 1.0 specification is a bit ambiguous about this
2238 * feature so there might be some problems with older
2239 * controllers.
2240 */
2241 if (host->cmd->flags & MMC_RSP_BUSY) {
2242 if (host->cmd->data)
2243 DBG("Cannot wait for busy signal when also "
2244 "doing a data transfer");
f945405c 2245 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2246 return;
f945405c
BD		 2247
2248 /* The controller does not support the end-of-busy IRQ,
2249 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2250 }
2251
2252 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2253 sdhci_finish_command(host);
d129bceb
PO		 2254}
2255
0957c333 2256#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2257static void sdhci_show_adma_error(struct sdhci_host *host)
2258{
2259 const char *name = mmc_hostname(host->mmc);
2260 u8 *desc = host->adma_desc;
2261 __le32 *dma;
2262 __le16 *len;
2263 u8 attr;
2264
2265 sdhci_dumpregs(host);
2266
2267 while (true) {
2268 dma = (__le32 *)(desc + 4);
2269 len = (__le16 *)(desc + 2);
2270 attr = *desc;
2271
2272 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2273 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2274
2275 desc += 8;
2276
2277 if (attr & 2)
2278 break;
2279 }
2280}
2281#else
2282static void sdhci_show_adma_error(struct sdhci_host *host) { }
2283#endif
2284
d129bceb
PO		 2285static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2286{
069c9f14 2287 u32 command;
d129bceb
PO		 2288 BUG_ON(intmask == 0);
2289
b513ea25
AN		 2290 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2291 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2292 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2293 if (command == MMC_SEND_TUNING_BLOCK ||
2294 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2295 host->tuning_done = 1;
2296 wake_up(&host->buf_ready_int);
2297 return;
2298 }
2299 }
2300
d129bceb
PO		 2301 if (!host->data) {
2302 /*
e809517f
PO		 2303 * The "data complete" interrupt is also used to
2304 * indicate that a busy state has ended. See comment
2305 * above in sdhci_cmd_irq().
d129bceb 2306 */
e809517f
PO		 2307 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2308 if (intmask & SDHCI_INT_DATA_END) {
2309 sdhci_finish_command(host);
2310 return;
2311 }
2312 }
d129bceb 2313
a3c76eb9 2314 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2315 "though no data operation was in progress.\n",
2316 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2317 sdhci_dumpregs(host);
2318
2319 return;
2320 }
2321
2322 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2323 host->data->error = -ETIMEDOUT;
22113efd
AL		 2324 else if (intmask & SDHCI_INT_DATA_END_BIT)
2325 host->data->error = -EILSEQ;
2326 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2327 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2328 != MMC_BUS_TEST_R)
17b0429d 2329 host->data->error = -EILSEQ;
6882a8c0 2330 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2331 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2332 sdhci_show_adma_error(host);
2134a922 2333 host->data->error = -EIO;
a4071fbb
HZ		 2334 if (host->ops->adma_workaround)
2335 host->ops->adma_workaround(host, intmask);
6882a8c0 2336 }
d129bceb 2337
17b0429d 2338 if (host->data->error)
d129bceb
PO		 2339 sdhci_finish_data(host);
2340 else {
a406f5a3 2341 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2342 sdhci_transfer_pio(host);
2343
6ba736a1
PO		 2344 /*
2345 * We currently don't do anything fancy with DMA
2346 * boundaries, but as we can't disable the feature
2347 * we need to at least restart the transfer.
f6a03cbf
MV		 2348 *
2349 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2350 * should return a valid address to continue from, but as
2351 * some controllers are faulty, don't trust them.
6ba736a1 2352 */
f6a03cbf
MV		 2353 if (intmask & SDHCI_INT_DMA_END) {
2354 u32 dmastart, dmanow;
2355 dmastart = sg_dma_address(host->data->sg);
2356 dmanow = dmastart + host->data->bytes_xfered;
2357 /*
2358 * Force update to the next DMA block boundary.
2359 */
2360 dmanow = (dmanow &
2361 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2362 SDHCI_DEFAULT_BOUNDARY_SIZE;
2363 host->data->bytes_xfered = dmanow - dmastart;
2364 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2365 " next 0x%08x\n",
2366 mmc_hostname(host->mmc), dmastart,
2367 host->data->bytes_xfered, dmanow);
2368 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2369 }
6ba736a1 2370
e538fbe8
PO		 2371 if (intmask & SDHCI_INT_DATA_END) {
2372 if (host->cmd) {
2373 /*
2374 * Data managed to finish before the
2375 * command completed. Make sure we do
2376 * things in the proper order.
2377 */
2378 host->data_early = 1;
2379 } else {
2380 sdhci_finish_data(host);
2381 }
2382 }
d129bceb
PO		 2383 }
2384}
2385
7d12e780 2386static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2387{
781e989c 2388 irqreturn_t result = IRQ_NONE;
66fd8ad5 2389 struct sdhci_host *host = dev_id;
41005003 2390 u32 intmask, mask, unexpected = 0;
781e989c 2391 int max_loops = 16;
d129bceb
PO		 2392
2393 spin_lock(&host->lock);
2394
be138554 2395 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2396 spin_unlock(&host->lock);
655bca76 2397 return IRQ_NONE;
66fd8ad5
AH		 2398 }
2399
4e4141a5 2400 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2401 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2402 result = IRQ_NONE;
2403 goto out;
2404 }
2405
41005003
RK		 2406 do {
2407 /* Clear selected interrupts. */
2408 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2409 SDHCI_INT_BUS_POWER);
2410 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2411
41005003
RK		 2412 DBG("*** %s got interrupt: 0x%08x\n",
2413 mmc_hostname(host->mmc), intmask);
d129bceb 2414
41005003
RK		 2415 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2416 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2417 SDHCI_CARD_PRESENT;
d129bceb 2418
41005003
RK		 2419 /*
2420 * There is a observation on i.mx esdhc. INSERT
2421 * bit will be immediately set again when it gets
2422 * cleared, if a card is inserted. We have to mask
2423 * the irq to prevent interrupt storm which will
2424 * freeze the system. And the REMOVE gets the
2425 * same situation.
2426 *
2427 * More testing are needed here to ensure it works
2428 * for other platforms though.
2429 */
b537f94c
RK		 2430 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2431 SDHCI_INT_CARD_REMOVE);
2432 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2433 SDHCI_INT_CARD_INSERT;
2434 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2435 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2436
2437 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2438 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2439
2440 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2441 SDHCI_INT_CARD_REMOVE);
2442 result = IRQ_WAKE_THREAD;
41005003 2443 }
d129bceb 2444
41005003
RK		 2445 if (intmask & SDHCI_INT_CMD_MASK)
2446 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
964f9ce2 2447
41005003
RK		 2448 if (intmask & SDHCI_INT_DATA_MASK)
2449 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2450
41005003
RK		 2451 if (intmask & SDHCI_INT_BUS_POWER)
2452 pr_err("%s: Card is consuming too much power!\n",
2453 mmc_hostname(host->mmc));
3192a28f 2454
781e989c
RK		 2455 if (intmask & SDHCI_INT_CARD_INT) {
2456 sdhci_enable_sdio_irq_nolock(host, false);
2457 host->thread_isr |= SDHCI_INT_CARD_INT;
2458 result = IRQ_WAKE_THREAD;
2459 }
f75979b7 2460
41005003
RK		 2461 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2462 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2463 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2464 SDHCI_INT_CARD_INT);
f75979b7 2465
41005003
RK		 2466 if (intmask) {
2467 unexpected |= intmask;
2468 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2469 }
d129bceb 2470
781e989c
RK		 2471 if (result == IRQ_NONE)
2472 result = IRQ_HANDLED;
d129bceb 2473
41005003 2474 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2475 } while (intmask && --max_loops);
d129bceb
PO		 2476out:
2477 spin_unlock(&host->lock);
2478
6379b237
AS		 2479 if (unexpected) {
2480 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2481 mmc_hostname(host->mmc), unexpected);
2482 sdhci_dumpregs(host);
2483 }
f75979b7 2484
d129bceb
PO		 2485 return result;
2486}
2487
781e989c
RK		 2488static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2489{
2490 struct sdhci_host *host = dev_id;
2491 unsigned long flags;
2492 u32 isr;
2493
2494 spin_lock_irqsave(&host->lock, flags);
2495 isr = host->thread_isr;
2496 host->thread_isr = 0;
2497 spin_unlock_irqrestore(&host->lock, flags);
2498
3560db8e
RK		 2499 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2500 sdhci_card_event(host->mmc);
2501 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2502 }
2503
781e989c
RK		 2504 if (isr & SDHCI_INT_CARD_INT) {
2505 sdio_run_irqs(host->mmc);
2506
2507 spin_lock_irqsave(&host->lock, flags);
2508 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2509 sdhci_enable_sdio_irq_nolock(host, true);
2510 spin_unlock_irqrestore(&host->lock, flags);
2511 }
2512
2513 return isr ? IRQ_HANDLED : IRQ_NONE;
2514}
2515
d129bceb
PO		 2516/*****************************************************************************\
2517 * *
2518 * Suspend/resume *
2519 * *
2520\*****************************************************************************/
2521
2522#ifdef CONFIG_PM
ad080d79
KL		 2523void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2524{
2525 u8 val;
2526 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2527 | SDHCI_WAKE_ON_INT;
2528
2529 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2530 val |= mask ;
2531 /* Avoid fake wake up */
2532 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2533 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2534 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2535}
2536EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2537
2538void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2539{
2540 u8 val;
2541 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2542 | SDHCI_WAKE_ON_INT;
2543
2544 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2545 val &= ~mask;
2546 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2547}
2548EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2549
29495aa0 2550int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2551{
a1b13b4e
CB		 2552 if (host->ops->platform_suspend)
2553 host->ops->platform_suspend(host);
2554
7260cf5e
AV		 2555 sdhci_disable_card_detection(host);
2556
cf2b5eea 2557 /* Disable tuning since we are suspending */
973905fe 2558 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2559 del_timer_sync(&host->tuning_timer);
cf2b5eea 2560 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2561 }
2562
ad080d79 2563 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2564 host->ier = 0;
2565 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2566 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2567 free_irq(host->irq, host);
2568 } else {
2569 sdhci_enable_irq_wakeups(host);
2570 enable_irq_wake(host->irq);
2571 }
4ee14ec6 2572 return 0;
d129bceb
PO		 2573}
2574
b8c86fc5 2575EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2576
b8c86fc5
PO		 2577int sdhci_resume_host(struct sdhci_host *host)
2578{
4ee14ec6 2579 int ret = 0;
d129bceb 2580
a13abc7b 2581 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2582 if (host->ops->enable_dma)
2583 host->ops->enable_dma(host);
2584 }
d129bceb 2585
ad080d79 2586 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2587 ret = request_threaded_irq(host->irq, sdhci_irq,
2588 sdhci_thread_irq, IRQF_SHARED,
2589 mmc_hostname(host->mmc), host);
ad080d79
KL		 2590 if (ret)
2591 return ret;
2592 } else {
2593 sdhci_disable_irq_wakeups(host);
2594 disable_irq_wake(host->irq);
2595 }
d129bceb 2596
6308d290
AH		 2597 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2598 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2599 /* Card keeps power but host controller does not */
2600 sdhci_init(host, 0);
2601 host->pwr = 0;
2602 host->clock = 0;
2603 sdhci_do_set_ios(host, &host->mmc->ios);
2604 } else {
2605 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2606 mmiowb();
2607 }
b8c86fc5 2608
7260cf5e
AV		 2609 sdhci_enable_card_detection(host);
2610
a1b13b4e
CB		 2611 if (host->ops->platform_resume)
2612 host->ops->platform_resume(host);
2613
cf2b5eea 2614 /* Set the re-tuning expiration flag */
973905fe 2615 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2616 host->flags |= SDHCI_NEEDS_RETUNING;
2617
2f4cbb3d 2618 return ret;
d129bceb
PO		 2619}
2620
b8c86fc5 2621EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2622#endif /* CONFIG_PM */
2623
66fd8ad5
AH		 2624#ifdef CONFIG_PM_RUNTIME
2625
2626static int sdhci_runtime_pm_get(struct sdhci_host *host)
2627{
2628 return pm_runtime_get_sync(host->mmc->parent);
2629}
2630
2631static int sdhci_runtime_pm_put(struct sdhci_host *host)
2632{
2633 pm_runtime_mark_last_busy(host->mmc->parent);
2634 return pm_runtime_put_autosuspend(host->mmc->parent);
2635}
2636
f0710a55
AH		 2637static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2638{
2639 if (host->runtime_suspended || host->bus_on)
2640 return;
2641 host->bus_on = true;
2642 pm_runtime_get_noresume(host->mmc->parent);
2643}
2644
2645static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2646{
2647 if (host->runtime_suspended || !host->bus_on)
2648 return;
2649 host->bus_on = false;
2650 pm_runtime_put_noidle(host->mmc->parent);
2651}
2652
66fd8ad5
AH		 2653int sdhci_runtime_suspend_host(struct sdhci_host *host)
2654{
2655 unsigned long flags;
2656 int ret = 0;
2657
2658 /* Disable tuning since we are suspending */
973905fe 2659 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2660 del_timer_sync(&host->tuning_timer);
2661 host->flags &= ~SDHCI_NEEDS_RETUNING;
2662 }
2663
2664 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2665 host->ier &= SDHCI_INT_CARD_INT;
2666 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2667 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2668 spin_unlock_irqrestore(&host->lock, flags);
2669
781e989c 2670 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2671
2672 spin_lock_irqsave(&host->lock, flags);
2673 host->runtime_suspended = true;
2674 spin_unlock_irqrestore(&host->lock, flags);
2675
2676 return ret;
2677}
2678EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2679
2680int sdhci_runtime_resume_host(struct sdhci_host *host)
2681{
2682 unsigned long flags;
2683 int ret = 0, host_flags = host->flags;
2684
2685 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2686 if (host->ops->enable_dma)
2687 host->ops->enable_dma(host);
2688 }
2689
2690 sdhci_init(host, 0);
2691
2692 /* Force clock and power re-program */
2693 host->pwr = 0;
2694 host->clock = 0;
2695 sdhci_do_set_ios(host, &host->mmc->ios);
2696
2697 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2698 if ((host_flags & SDHCI_PV_ENABLED) &&
2699 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2700 spin_lock_irqsave(&host->lock, flags);
2701 sdhci_enable_preset_value(host, true);
2702 spin_unlock_irqrestore(&host->lock, flags);
2703 }
66fd8ad5
AH		 2704
2705 /* Set the re-tuning expiration flag */
973905fe 2706 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2707 host->flags |= SDHCI_NEEDS_RETUNING;
2708
2709 spin_lock_irqsave(&host->lock, flags);
2710
2711 host->runtime_suspended = false;
2712
2713 /* Enable SDIO IRQ */
ef104333 2714 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2715 sdhci_enable_sdio_irq_nolock(host, true);
2716
2717 /* Enable Card Detection */
2718 sdhci_enable_card_detection(host);
2719
2720 spin_unlock_irqrestore(&host->lock, flags);
2721
2722 return ret;
2723}
2724EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2725
2726#endif
2727
d129bceb
PO		 2728/*****************************************************************************\
2729 * *
b8c86fc5 2730 * Device allocation/registration *
d129bceb
PO		 2731 * *
2732\*****************************************************************************/
2733
b8c86fc5
PO		 2734struct sdhci_host *sdhci_alloc_host(struct device *dev,
2735 size_t priv_size)
d129bceb 2736{
d129bceb
PO		 2737 struct mmc_host *mmc;
2738 struct sdhci_host *host;
2739
b8c86fc5 2740 WARN_ON(dev == NULL);
d129bceb 2741
b8c86fc5 2742 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2743 if (!mmc)
b8c86fc5 2744 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2745
2746 host = mmc_priv(mmc);
2747 host->mmc = mmc;
2748
b8c86fc5
PO		 2749 return host;
2750}
8a4da143 2751
b8c86fc5 2752EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2753
b8c86fc5
PO		 2754int sdhci_add_host(struct sdhci_host *host)
2755{
2756 struct mmc_host *mmc;
bd6a8c30 2757 u32 caps[2] = {0, 0};
f2119df6
AN		 2758 u32 max_current_caps;
2759 unsigned int ocr_avail;
b8c86fc5 2760 int ret;
d129bceb 2761
b8c86fc5
PO		 2762 WARN_ON(host == NULL);
2763 if (host == NULL)
2764 return -EINVAL;
d129bceb 2765
b8c86fc5 2766 mmc = host->mmc;
d129bceb 2767
b8c86fc5
PO		 2768 if (debug_quirks)
2769 host->quirks = debug_quirks;
66fd8ad5
AH		 2770 if (debug_quirks2)
2771 host->quirks2 = debug_quirks2;
d129bceb 2772
03231f9b 2773 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2774
4e4141a5 2775 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2776 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2777 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2778 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2779 pr_err("%s: Unknown controller version (%d). "
b69c9058 2780 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2781 host->version);
4a965505
PO		 2782 }
2783
f2119df6 2784 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2785 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2786
bd6a8c30
PR		 2787 if (host->version >= SDHCI_SPEC_300)
2788 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2789 host->caps1 :
2790 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2791
b8c86fc5 2792 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2793 host->flags |= SDHCI_USE_SDMA;
f2119df6 2794 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2795 DBG("Controller doesn't have SDMA capability\n");
67435274 2796 else
a13abc7b 2797 host->flags |= SDHCI_USE_SDMA;
d129bceb 2798
b8c86fc5 2799 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2800 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2801 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2802 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2803 }
2804
f2119df6
AN		 2805 if ((host->version >= SDHCI_SPEC_200) &&
2806 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2807 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2808
2809 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2810 (host->flags & SDHCI_USE_ADMA)) {
2811 DBG("Disabling ADMA as it is marked broken\n");
2812 host->flags &= ~SDHCI_USE_ADMA;
2813 }
2814
a13abc7b 2815 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2816 if (host->ops->enable_dma) {
2817 if (host->ops->enable_dma(host)) {
a3c76eb9 2818 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2819 "available. Falling back to PIO.\n",
2820 mmc_hostname(mmc));
a13abc7b
RR		 2821 host->flags &=
2822 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2823 }
d129bceb
PO		 2824 }
2825 }
2826
2134a922
PO		 2827 if (host->flags & SDHCI_USE_ADMA) {
2828 /*
2829 * We need to allocate descriptors for all sg entries
2830 * (128) and potentially one alignment transfer for
2831 * each of those entries.
2832 */
d1e49f77
RK		 2833 host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc),
2834 ADMA_SIZE, &host->adma_addr,
2835 GFP_KERNEL);
2134a922
PO		 2836 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2837 if (!host->adma_desc || !host->align_buffer) {
d1e49f77
RK		 2838 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2839 host->adma_desc, host->adma_addr);
2134a922 2840 kfree(host->align_buffer);
a3c76eb9 2841 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2842 "buffers. Falling back to standard DMA.\n",
2843 mmc_hostname(mmc));
2844 host->flags &= ~SDHCI_USE_ADMA;
d1e49f77
RK		 2845 host->adma_desc = NULL;
2846 host->align_buffer = NULL;
2847 } else if (host->adma_addr & 3) {
2848 pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2849 mmc_hostname(mmc));
2850 host->flags &= ~SDHCI_USE_ADMA;
2851 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2852 host->adma_desc, host->adma_addr);
2853 kfree(host->align_buffer);
2854 host->adma_desc = NULL;
2855 host->align_buffer = NULL;
2134a922
PO		 2856 }
2857 }
2858
7659150c
PO		 2859 /*
2860 * If we use DMA, then it's up to the caller to set the DMA
2861 * mask, but PIO does not need the hw shim so we set a new
2862 * mask here in that case.
2863 */
a13abc7b 2864 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2865 host->dma_mask = DMA_BIT_MASK(64);
2866 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2867 }
d129bceb 2868
c4687d5f 2869 if (host->version >= SDHCI_SPEC_300)
f2119df6 2870 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2871 >> SDHCI_CLOCK_BASE_SHIFT;
2872 else
f2119df6 2873 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2874 >> SDHCI_CLOCK_BASE_SHIFT;
2875
4240ff0a 2876 host->max_clk *= 1000000;
f27f47ef
AV		 2877 if (host->max_clk == 0 || host->quirks &
2878 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2879 if (!host->ops->get_max_clock) {
a3c76eb9 2880 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2881 "frequency.\n", mmc_hostname(mmc));
2882 return -ENODEV;
2883 }
2884 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2885 }
d129bceb 2886
c3ed3877
AN		 2887 /*
2888 * In case of Host Controller v3.00, find out whether clock
2889 * multiplier is supported.
2890 */
2891 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2892 SDHCI_CLOCK_MUL_SHIFT;
2893
2894 /*
2895 * In case the value in Clock Multiplier is 0, then programmable
2896 * clock mode is not supported, otherwise the actual clock
2897 * multiplier is one more than the value of Clock Multiplier
2898 * in the Capabilities Register.
2899 */
2900 if (host->clk_mul)
2901 host->clk_mul += 1;
2902
d129bceb
PO		 2903 /*
2904 * Set host parameters.
2905 */
2906 mmc->ops = &sdhci_ops;
c3ed3877 2907 mmc->f_max = host->max_clk;
ce5f036b 2908 if (host->ops->get_min_clock)
a9e58f25 2909 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2910 else if (host->version >= SDHCI_SPEC_300) {
2911 if (host->clk_mul) {
2912 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2913 mmc->f_max = host->max_clk * host->clk_mul;
2914 } else
2915 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2916 } else
0397526d 2917 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2918
272308ca
AS		 2919 host->timeout_clk =
2920 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2921 if (host->timeout_clk == 0) {
2922 if (host->ops->get_timeout_clock) {
2923 host->timeout_clk = host->ops->get_timeout_clock(host);
2924 } else if (!(host->quirks &
2925 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2926 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2927 "frequency.\n", mmc_hostname(mmc));
2928 return -ENODEV;
2929 }
2930 }
2931 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2932 host->timeout_clk *= 1000;
2933
2934 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2935 host->timeout_clk = mmc->f_max / 1000;
272308ca 2936
68eb80e0 2937 mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
58d1246d 2938
e89d456f 2939 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 2940 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 2941
2942 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2943 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2944
8edf6371 2945 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2946 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2947 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2948 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2949 host->flags |= SDHCI_AUTO_CMD23;
2950 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2951 } else {
2952 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2953 }
2954
15ec4461
PR		 2955 /*
2956 * A controller may support 8-bit width, but the board itself
2957 * might not have the pins brought out. Boards that support
2958 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2959 * their platform code before calling sdhci_add_host(), and we
2960 * won't assume 8-bit width for hosts without that CAP.
2961 */
5fe23c7f 2962 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2963 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2964
63ef5d8c
JH		 2965 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2966 mmc->caps &= ~MMC_CAP_CMD23;
2967
f2119df6 2968 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2969 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2970
176d1ed4 2971 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2972 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2973 mmc->caps |= MMC_CAP_NEEDS_POLL;
2974
6231f3de 2975 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
462849aa 2976 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2977 if (IS_ERR_OR_NULL(host->vqmmc)) {
2978 if (PTR_ERR(host->vqmmc) < 0) {
2979 pr_info("%s: no vqmmc regulator found\n",
2980 mmc_hostname(mmc));
2981 host->vqmmc = NULL;
2982 }
8363c374 2983 } else {
a3361aba 2984 ret = regulator_enable(host->vqmmc);
cec2e216
KL		 2985 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2986 1950000))
8363c374
KL		 2987 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2988 SDHCI_SUPPORT_SDR50 |
2989 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 2990 if (ret) {
2991 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2992 mmc_hostname(mmc), ret);
2993 host->vqmmc = NULL;
2994 }
8363c374 2995 }
6231f3de 2996
6a66180a
DD		 2997 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2998 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2999 SDHCI_SUPPORT_DDR50);
3000
4188bba0
AC		 3001 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3002 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3003 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3004 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3005
3006 /* SDR104 supports also implies SDR50 support */
156e14b1 3007 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3008 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3009 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3010 * field can be promoted to support HS200.
3011 */
13868bf2
DC		 3012 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3013 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3014 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3015 mmc->caps |= MMC_CAP_UHS_SDR50;
3016
9107ebbf
MC		 3017 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3018 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3019 mmc->caps |= MMC_CAP_UHS_DDR50;
3020
069c9f14 3021 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3022 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3023 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3024
156e14b1 3025 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3026 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3027 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3028
d6d50a15
AN		 3029 /* Driver Type(s) (A, C, D) supported by the host */
3030 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3031 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3032 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3033 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3034 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3035 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3036
cf2b5eea
AN		 3037 /* Initial value for re-tuning timer count */
3038 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3039 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3040
3041 /*
3042 * In case Re-tuning Timer is not disabled, the actual value of
3043 * re-tuning timer will be 2 ^ (n - 1).
3044 */
3045 if (host->tuning_count)
3046 host->tuning_count = 1 << (host->tuning_count - 1);
3047
3048 /* Re-tuning mode supported by the Host Controller */
3049 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3050 SDHCI_RETUNING_MODE_SHIFT;
3051
8f230f45 3052 ocr_avail = 0;
bad37e1a 3053
462849aa 3054 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
657d5982
KL		 3055 if (IS_ERR_OR_NULL(host->vmmc)) {
3056 if (PTR_ERR(host->vmmc) < 0) {
3057 pr_info("%s: no vmmc regulator found\n",
3058 mmc_hostname(mmc));
3059 host->vmmc = NULL;
3060 }
8363c374 3061 }
bad37e1a 3062
68737043 3063#ifdef CONFIG_REGULATOR
a4f8f257
MS		 3064 /*
3065 * Voltage range check makes sense only if regulator reports
3066 * any voltage value.
3067 */
3068 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
cec2e216
KL		 3069 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3070 3600000);
68737043
PR		 3071 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3072 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 3073 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3074 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 3075 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3076 1950000);
68737043
PR		 3077 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3078 caps[0] &= ~SDHCI_CAN_VDD_180;
3079 }
3080#endif /* CONFIG_REGULATOR */
3081
f2119df6
AN		 3082 /*
3083 * According to SD Host Controller spec v3.00, if the Host System
3084 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3085 * the value is meaningful only if Voltage Support in the Capabilities
3086 * register is set. The actual current value is 4 times the register
3087 * value.
3088 */
3089 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 3090 if (!max_current_caps && host->vmmc) {
3091 u32 curr = regulator_get_current_limit(host->vmmc);
3092 if (curr > 0) {
3093
3094 /* convert to SDHCI_MAX_CURRENT format */
3095 curr = curr/1000; /* convert to mA */
3096 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3097
3098 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3099 max_current_caps =
3100 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3101 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3102 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3103 }
3104 }
f2119df6
AN		 3105
3106 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3107 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3108
55c4665e 3109 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3110 SDHCI_MAX_CURRENT_330_MASK) >>
3111 SDHCI_MAX_CURRENT_330_SHIFT) *
3112 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3113 }
3114 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3115 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3116
55c4665e 3117 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3118 SDHCI_MAX_CURRENT_300_MASK) >>
3119 SDHCI_MAX_CURRENT_300_SHIFT) *
3120 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3121 }
3122 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3123 ocr_avail |= MMC_VDD_165_195;
3124
55c4665e 3125 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3126 SDHCI_MAX_CURRENT_180_MASK) >>
3127 SDHCI_MAX_CURRENT_180_SHIFT) *
3128 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3129 }
3130
c0b887b6
HZ		 3131 if (host->ocr_mask)
3132 ocr_avail = host->ocr_mask;
3133
8f230f45
TI		 3134 mmc->ocr_avail = ocr_avail;
3135 mmc->ocr_avail_sdio = ocr_avail;
3136 if (host->ocr_avail_sdio)
3137 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3138 mmc->ocr_avail_sd = ocr_avail;
3139 if (host->ocr_avail_sd)
3140 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3141 else /* normal SD controllers don't support 1.8V */
3142 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3143 mmc->ocr_avail_mmc = ocr_avail;
3144 if (host->ocr_avail_mmc)
3145 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3146
3147 if (mmc->ocr_avail == 0) {
a3c76eb9 3148 pr_err("%s: Hardware doesn't report any "
b69c9058 3149 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3150 return -ENODEV;
146ad66e
PO		 3151 }
3152
d129bceb
PO		 3153 spin_lock_init(&host->lock);
3154
3155 /*
2134a922
PO		 3156 * Maximum number of segments. Depends on if the hardware
3157 * can do scatter/gather or not.
d129bceb 3158 */
2134a922 3159 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3160 mmc->max_segs = 128;
a13abc7b 3161 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3162 mmc->max_segs = 1;
2134a922 3163 else /* PIO */
a36274e0 3164 mmc->max_segs = 128;
d129bceb
PO		 3165
3166 /*
bab76961 3167 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3168 * size (512KiB).
d129bceb 3169 */
55db890a 3170 mmc->max_req_size = 524288;
d129bceb
PO		 3171
3172 /*
3173 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3174 * of bytes. When doing hardware scatter/gather, each entry cannot
3175 * be larger than 64 KiB though.
d129bceb 3176 */
30652aa3
OJ		 3177 if (host->flags & SDHCI_USE_ADMA) {
3178 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3179 mmc->max_seg_size = 65535;
3180 else
3181 mmc->max_seg_size = 65536;
3182 } else {
2134a922 3183 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3184 }
d129bceb 3185
fe4a3c7a
PO		 3186 /*
3187 * Maximum block size. This varies from controller to controller and
3188 * is specified in the capabilities register.
3189 */
0633f654
AV		 3190 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3191 mmc->max_blk_size = 2;
3192 } else {
f2119df6 3193 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3194 SDHCI_MAX_BLOCK_SHIFT;
3195 if (mmc->max_blk_size >= 3) {
a3c76eb9 3196 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3197 "assuming 512 bytes\n", mmc_hostname(mmc));
3198 mmc->max_blk_size = 0;
3199 }
3200 }
3201
3202 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3203
55db890a
PO		 3204 /*
3205 * Maximum block count.
3206 */
1388eefd 3207 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3208
d129bceb
PO		 3209 /*
3210 * Init tasklets.
3211 */
d129bceb
PO		 3212 tasklet_init(&host->finish_tasklet,
3213 sdhci_tasklet_finish, (unsigned long)host);
3214
e4cad1b5 3215 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3216
cf2b5eea 3217 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3218 init_waitqueue_head(&host->buf_ready_int);
3219
cf2b5eea
AN		 3220 /* Initialize re-tuning timer */
3221 init_timer(&host->tuning_timer);
3222 host->tuning_timer.data = (unsigned long)host;
3223 host->tuning_timer.function = sdhci_tuning_timer;
3224 }
3225
2af502ca
SG		 3226 sdhci_init(host, 0);
3227
781e989c
RK		 3228 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3229 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3230 if (ret) {
3231 pr_err("%s: Failed to request IRQ %d: %d\n",
3232 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3233 goto untasklet;
0fc81ee3 3234 }
d129bceb 3235
d129bceb
PO		 3236#ifdef CONFIG_MMC_DEBUG
3237 sdhci_dumpregs(host);
3238#endif
3239
f9134319 3240#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3241 snprintf(host->led_name, sizeof(host->led_name),
3242 "%s::", mmc_hostname(mmc));
3243 host->led.name = host->led_name;
2f730fec
PO		 3244 host->led.brightness = LED_OFF;
3245 host->led.default_trigger = mmc_hostname(mmc);
3246 host->led.brightness_set = sdhci_led_control;
3247
b8c86fc5 3248 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3249 if (ret) {
3250 pr_err("%s: Failed to register LED device: %d\n",
3251 mmc_hostname(mmc), ret);
2f730fec 3252 goto reset;
0fc81ee3 3253 }
2f730fec
PO		 3254#endif
3255
5f25a66f
PO		 3256 mmiowb();
3257
d129bceb
PO		 3258 mmc_add_host(mmc);
3259
a3c76eb9 3260 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3261 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3262 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3263 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3264
7260cf5e
AV		 3265 sdhci_enable_card_detection(host);
3266
d129bceb
PO		 3267 return 0;
3268
f9134319 3269#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3270reset:
03231f9b 3271 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3272 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3273 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3274 free_irq(host->irq, host);
3275#endif
8ef1a143 3276untasklet:
d129bceb 3277 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3278
3279 return ret;
3280}
3281
b8c86fc5 3282EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3283
1e72859e 3284void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3285{
1e72859e
PO		 3286 unsigned long flags;
3287
3288 if (dead) {
3289 spin_lock_irqsave(&host->lock, flags);
3290
3291 host->flags |= SDHCI_DEVICE_DEAD;
3292
3293 if (host->mrq) {
a3c76eb9 3294 pr_err("%s: Controller removed during "
1e72859e
PO		 3295 " transfer!\n", mmc_hostname(host->mmc));
3296
3297 host->mrq->cmd->error = -ENOMEDIUM;
3298 tasklet_schedule(&host->finish_tasklet);
3299 }
3300
3301 spin_unlock_irqrestore(&host->lock, flags);
3302 }
3303
7260cf5e
AV		 3304 sdhci_disable_card_detection(host);
3305
b8c86fc5 3306 mmc_remove_host(host->mmc);
d129bceb 3307
f9134319 3308#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3309 led_classdev_unregister(&host->led);
3310#endif
3311
1e72859e 3312 if (!dead)
03231f9b 3313 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3314
b537f94c
RK		 3315 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3316 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3317 free_irq(host->irq, host);
3318
3319 del_timer_sync(&host->timer);
3320
d129bceb 3321 tasklet_kill(&host->finish_tasklet);
2134a922 3322
77dcb3f4
PR		 3323 if (host->vmmc) {
3324 regulator_disable(host->vmmc);
9bea3c85 3325 regulator_put(host->vmmc);
77dcb3f4 3326 }
9bea3c85 3327
6231f3de
PR		 3328 if (host->vqmmc) {
3329 regulator_disable(host->vqmmc);
3330 regulator_put(host->vqmmc);
3331 }
3332
d1e49f77
RK		 3333 if (host->adma_desc)
3334 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
3335 host->adma_desc, host->adma_addr);
2134a922
PO		 3336 kfree(host->align_buffer);
3337
3338 host->adma_desc = NULL;
3339 host->align_buffer = NULL;
d129bceb
PO		 3340}
3341
b8c86fc5 3342EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3343
b8c86fc5 3344void sdhci_free_host(struct sdhci_host *host)
d129bceb 3345{
b8c86fc5 3346 mmc_free_host(host->mmc);
d129bceb
PO		 3347}
3348
b8c86fc5 3349EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3350
3351/*****************************************************************************\
3352 * *
3353 * Driver init/exit *
3354 * *
3355\*****************************************************************************/
3356
3357static int __init sdhci_drv_init(void)
3358{
a3c76eb9 3359 pr_info(DRIVER_NAME
52fbf9c9 3360 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3361 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3362
b8c86fc5 3363 return 0;
d129bceb
PO		 3364}
3365
3366static void __exit sdhci_drv_exit(void)
3367{
d129bceb
PO		 3368}
3369
3370module_init(sdhci_drv_init);
3371module_exit(sdhci_drv_exit);
3372
df673b22 3373module_param(debug_quirks, uint, 0444);
66fd8ad5 3374module_param(debug_quirks2, uint, 0444);
67435274 3375
32710e8f 3376MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3377MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3378MODULE_LICENSE("GPL");
67435274 3379
df673b22 3380MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3381MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux 6.x block layer and io_uring tree(s)