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mmc: dw_mmc: miscaculated the fifo-depth with wrong bit operation
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
d129bceb 30
d129bceb
PO		 31#include "sdhci.h"
32
33#define DRIVER_NAME "sdhci"
d129bceb 34
d129bceb 35#define DBG(f, x...) \
c6563178 36 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 37
f9134319
PO		 38#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
39 defined(CONFIG_MMC_SDHCI_MODULE))
40#define SDHCI_USE_LEDS_CLASS
41#endif
42
b513ea25
AN		 43#define MAX_TUNING_LOOP 40
44
df673b22 45static unsigned int debug_quirks = 0;
66fd8ad5 46static unsigned int debug_quirks2;
67435274 47
d129bceb
PO		 48static void sdhci_finish_data(struct sdhci_host *);
49
50static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
51static void sdhci_finish_command(struct sdhci_host *);
069c9f14 52static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 53static void sdhci_tuning_timer(unsigned long data);
d129bceb 54
66fd8ad5
AH		 55#ifdef CONFIG_PM_RUNTIME
56static int sdhci_runtime_pm_get(struct sdhci_host *host);
57static int sdhci_runtime_pm_put(struct sdhci_host *host);
58#else
59static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
60{
61 return 0;
62}
63static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
64{
65 return 0;
66}
67#endif
68
d129bceb
PO		 69static void sdhci_dumpregs(struct sdhci_host *host)
70{
a3c76eb9 71 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 72 mmc_hostname(host->mmc));
d129bceb 73
a3c76eb9 74 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 75 sdhci_readl(host, SDHCI_DMA_ADDRESS),
76 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 77 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 78 sdhci_readw(host, SDHCI_BLOCK_SIZE),
79 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 80 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 81 sdhci_readl(host, SDHCI_ARGUMENT),
82 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 83 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 84 sdhci_readl(host, SDHCI_PRESENT_STATE),
85 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 86 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 87 sdhci_readb(host, SDHCI_POWER_CONTROL),
88 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 89 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 90 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
91 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 92 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 93 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
94 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 95 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 96 sdhci_readl(host, SDHCI_INT_ENABLE),
97 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 98 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 99 sdhci_readw(host, SDHCI_ACMD12_ERR),
100 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 101 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 102 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 103 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 104 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 105 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 106 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 107 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 108 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 109
be3f4ae0 110 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 111 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 112 readl(host->ioaddr + SDHCI_ADMA_ERROR),
113 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
114
a3c76eb9 115 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 116}
117
118/*****************************************************************************\
119 * *
120 * Low level functions *
121 * *
122\*****************************************************************************/
123
7260cf5e
AV		 124static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
125{
126 u32 ier;
127
128 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
129 ier &= ~clear;
130 ier |= set;
131 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
132 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
133}
134
135static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
136{
137 sdhci_clear_set_irqs(host, 0, irqs);
138}
139
140static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
141{
142 sdhci_clear_set_irqs(host, irqs, 0);
143}
144
145static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
146{
d25928d1 147 u32 present, irqs;
7260cf5e 148
c79396c1 149 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
c79396c1 150 !mmc_card_is_removable(host->mmc))
66fd8ad5
AH		 151 return;
152
d25928d1
SG		 153 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
154 SDHCI_CARD_PRESENT;
155 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
156
7260cf5e
AV		 157 if (enable)
158 sdhci_unmask_irqs(host, irqs);
159 else
160 sdhci_mask_irqs(host, irqs);
161}
162
163static void sdhci_enable_card_detection(struct sdhci_host *host)
164{
165 sdhci_set_card_detection(host, true);
166}
167
168static void sdhci_disable_card_detection(struct sdhci_host *host)
169{
170 sdhci_set_card_detection(host, false);
171}
172
d129bceb
PO		 173static void sdhci_reset(struct sdhci_host *host, u8 mask)
174{
e16514d8 175 unsigned long timeout;
063a9dbb 176 u32 uninitialized_var(ier);
e16514d8 177
b8c86fc5 178 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 179 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 180 SDHCI_CARD_PRESENT))
181 return;
182 }
183
063a9dbb
AV		 184 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
185 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
186
393c1a34
PR		 187 if (host->ops->platform_reset_enter)
188 host->ops->platform_reset_enter(host, mask);
189
4e4141a5 190 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 191
e16514d8 192 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 193 host->clock = 0;
194
e16514d8
PO		 195 /* Wait max 100 ms */
196 timeout = 100;
197
198 /* hw clears the bit when it's done */
4e4141a5 199 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 200 if (timeout == 0) {
a3c76eb9 201 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 202 mmc_hostname(host->mmc), (int)mask);
203 sdhci_dumpregs(host);
204 return;
205 }
206 timeout--;
207 mdelay(1);
d129bceb 208 }
063a9dbb 209
393c1a34
PR		 210 if (host->ops->platform_reset_exit)
211 host->ops->platform_reset_exit(host, mask);
212
063a9dbb
AV		 213 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
214 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 215}
216
2f4cbb3d
NP		 217static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
218
219static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 220{
2f4cbb3d
NP		 221 if (soft)
222 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
223 else
224 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 225
7260cf5e
AV		 226 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
227 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 228 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
229 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 230 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 231
232 if (soft) {
233 /* force clock reconfiguration */
234 host->clock = 0;
235 sdhci_set_ios(host->mmc, &host->mmc->ios);
236 }
7260cf5e 237}
d129bceb 238
7260cf5e
AV		 239static void sdhci_reinit(struct sdhci_host *host)
240{
2f4cbb3d 241 sdhci_init(host, 0);
7260cf5e 242 sdhci_enable_card_detection(host);
d129bceb
PO		 243}
244
245static void sdhci_activate_led(struct sdhci_host *host)
246{
247 u8 ctrl;
248
4e4141a5 249 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 250 ctrl |= SDHCI_CTRL_LED;
4e4141a5 251 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 252}
253
254static void sdhci_deactivate_led(struct sdhci_host *host)
255{
256 u8 ctrl;
257
4e4141a5 258 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 259 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 260 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 261}
262
f9134319 263#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 264static void sdhci_led_control(struct led_classdev *led,
265 enum led_brightness brightness)
266{
267 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
268 unsigned long flags;
269
270 spin_lock_irqsave(&host->lock, flags);
271
66fd8ad5
AH		 272 if (host->runtime_suspended)
273 goto out;
274
2f730fec
PO		 275 if (brightness == LED_OFF)
276 sdhci_deactivate_led(host);
277 else
278 sdhci_activate_led(host);
66fd8ad5 279out:
2f730fec
PO		 280 spin_unlock_irqrestore(&host->lock, flags);
281}
282#endif
283
d129bceb
PO		 284/*****************************************************************************\
285 * *
286 * Core functions *
287 * *
288\*****************************************************************************/
289
a406f5a3 290static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 291{
7659150c
PO		 292 unsigned long flags;
293 size_t blksize, len, chunk;
7244b85b 294 u32 uninitialized_var(scratch);
7659150c 295 u8 *buf;
d129bceb 296
a406f5a3 297 DBG("PIO reading\n");
d129bceb 298
a406f5a3 299 blksize = host->data->blksz;
7659150c 300 chunk = 0;
d129bceb 301
7659150c 302 local_irq_save(flags);
d129bceb 303
a406f5a3 304 while (blksize) {
7659150c
PO		 305 if (!sg_miter_next(&host->sg_miter))
306 BUG();
d129bceb 307
7659150c 308 len = min(host->sg_miter.length, blksize);
d129bceb 309
7659150c
PO		 310 blksize -= len;
311 host->sg_miter.consumed = len;
14d836e7 312
7659150c 313 buf = host->sg_miter.addr;
d129bceb 314
7659150c
PO		 315 while (len) {
316 if (chunk == 0) {
4e4141a5 317 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 318 chunk = 4;
a406f5a3 319 }
7659150c
PO		 320
321 *buf = scratch & 0xFF;
322
323 buf++;
324 scratch >>= 8;
325 chunk--;
326 len--;
d129bceb 327 }
a406f5a3 328 }
7659150c
PO		 329
330 sg_miter_stop(&host->sg_miter);
331
332 local_irq_restore(flags);
a406f5a3 333}
d129bceb 334
a406f5a3
PO		 335static void sdhci_write_block_pio(struct sdhci_host *host)
336{
7659150c
PO		 337 unsigned long flags;
338 size_t blksize, len, chunk;
339 u32 scratch;
340 u8 *buf;
d129bceb 341
a406f5a3
PO		 342 DBG("PIO writing\n");
343
344 blksize = host->data->blksz;
7659150c
PO		 345 chunk = 0;
346 scratch = 0;
d129bceb 347
7659150c 348 local_irq_save(flags);
d129bceb 349
a406f5a3 350 while (blksize) {
7659150c
PO		 351 if (!sg_miter_next(&host->sg_miter))
352 BUG();
a406f5a3 353
7659150c
PO		 354 len = min(host->sg_miter.length, blksize);
355
356 blksize -= len;
357 host->sg_miter.consumed = len;
358
359 buf = host->sg_miter.addr;
d129bceb 360
7659150c
PO		 361 while (len) {
362 scratch |= (u32)*buf << (chunk * 8);
363
364 buf++;
365 chunk++;
366 len--;
367
368 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 369 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 370 chunk = 0;
371 scratch = 0;
d129bceb 372 }
d129bceb
PO		 373 }
374 }
7659150c
PO		 375
376 sg_miter_stop(&host->sg_miter);
377
378 local_irq_restore(flags);
a406f5a3
PO		 379}
380
381static void sdhci_transfer_pio(struct sdhci_host *host)
382{
383 u32 mask;
384
385 BUG_ON(!host->data);
386
7659150c 387 if (host->blocks == 0)
a406f5a3
PO		 388 return;
389
390 if (host->data->flags & MMC_DATA_READ)
391 mask = SDHCI_DATA_AVAILABLE;
392 else
393 mask = SDHCI_SPACE_AVAILABLE;
394
4a3cba32
PO		 395 /*
396 * Some controllers (JMicron JMB38x) mess up the buffer bits
397 * for transfers < 4 bytes. As long as it is just one block,
398 * we can ignore the bits.
399 */
400 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
401 (host->data->blocks == 1))
402 mask = ~0;
403
4e4141a5 404 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 405 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
406 udelay(100);
407
a406f5a3
PO		 408 if (host->data->flags & MMC_DATA_READ)
409 sdhci_read_block_pio(host);
410 else
411 sdhci_write_block_pio(host);
d129bceb 412
7659150c
PO		 413 host->blocks--;
414 if (host->blocks == 0)
a406f5a3 415 break;
a406f5a3 416 }
d129bceb 417
a406f5a3 418 DBG("PIO transfer complete.\n");
d129bceb
PO		 419}
420
2134a922
PO		 421static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
422{
423 local_irq_save(*flags);
482fce99 424 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 425}
426
427static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
428{
482fce99 429 kunmap_atomic(buffer);
2134a922
PO		 430 local_irq_restore(*flags);
431}
432
118cd17d
BD		 433static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
434{
9e506f35
BD		 435 __le32 *dataddr = (__le32 __force *)(desc + 4);
436 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 437
9e506f35
BD		 438 /* SDHCI specification says ADMA descriptors should be 4 byte
439 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 440
9e506f35
BD		 441 cmdlen[0] = cpu_to_le16(cmd);
442 cmdlen[1] = cpu_to_le16(len);
443
444 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 445}
446
8f1934ce 447static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 448 struct mmc_data *data)
449{
450 int direction;
451
452 u8 *desc;
453 u8 *align;
454 dma_addr_t addr;
455 dma_addr_t align_addr;
456 int len, offset;
457
458 struct scatterlist *sg;
459 int i;
460 char *buffer;
461 unsigned long flags;
462
463 /*
464 * The spec does not specify endianness of descriptor table.
465 * We currently guess that it is LE.
466 */
467
468 if (data->flags & MMC_DATA_READ)
469 direction = DMA_FROM_DEVICE;
470 else
471 direction = DMA_TO_DEVICE;
472
473 /*
474 * The ADMA descriptor table is mapped further down as we
475 * need to fill it with data first.
476 */
477
478 host->align_addr = dma_map_single(mmc_dev(host->mmc),
479 host->align_buffer, 128 * 4, direction);
8d8bb39b 480 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 481 goto fail;
2134a922
PO		 482 BUG_ON(host->align_addr & 0x3);
483
484 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
485 data->sg, data->sg_len, direction);
8f1934ce
PO		 486 if (host->sg_count == 0)
487 goto unmap_align;
2134a922
PO		 488
489 desc = host->adma_desc;
490 align = host->align_buffer;
491
492 align_addr = host->align_addr;
493
494 for_each_sg(data->sg, sg, host->sg_count, i) {
495 addr = sg_dma_address(sg);
496 len = sg_dma_len(sg);
497
498 /*
499 * The SDHCI specification states that ADMA
500 * addresses must be 32-bit aligned. If they
501 * aren't, then we use a bounce buffer for
502 * the (up to three) bytes that screw up the
503 * alignment.
504 */
505 offset = (4 - (addr & 0x3)) & 0x3;
506 if (offset) {
507 if (data->flags & MMC_DATA_WRITE) {
508 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 509 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 510 memcpy(align, buffer, offset);
511 sdhci_kunmap_atomic(buffer, &flags);
512 }
513
118cd17d
BD		 514 /* tran, valid */
515 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 516
517 BUG_ON(offset > 65536);
518
2134a922
PO		 519 align += 4;
520 align_addr += 4;
521
522 desc += 8;
523
524 addr += offset;
525 len -= offset;
526 }
527
2134a922
PO		 528 BUG_ON(len > 65536);
529
118cd17d
BD		 530 /* tran, valid */
531 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 532 desc += 8;
533
534 /*
535 * If this triggers then we have a calculation bug
536 * somewhere. :/
537 */
538 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
539 }
540
70764a90
TA		 541 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
542 /*
543 * Mark the last descriptor as the terminating descriptor
544 */
545 if (desc != host->adma_desc) {
546 desc -= 8;
547 desc[0] |= 0x2; /* end */
548 }
549 } else {
550 /*
551 * Add a terminating entry.
552 */
2134a922 553
70764a90
TA		 554 /* nop, end, valid */
555 sdhci_set_adma_desc(desc, 0, 0, 0x3);
556 }
2134a922
PO		 557
558 /*
559 * Resync align buffer as we might have changed it.
560 */
561 if (data->flags & MMC_DATA_WRITE) {
562 dma_sync_single_for_device(mmc_dev(host->mmc),
563 host->align_addr, 128 * 4, direction);
564 }
565
566 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
567 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 568 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 569 goto unmap_entries;
2134a922 570 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 571
572 return 0;
573
574unmap_entries:
575 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
576 data->sg_len, direction);
577unmap_align:
578 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
579 128 * 4, direction);
580fail:
581 return -EINVAL;
2134a922
PO		 582}
583
584static void sdhci_adma_table_post(struct sdhci_host *host,
585 struct mmc_data *data)
586{
587 int direction;
588
589 struct scatterlist *sg;
590 int i, size;
591 u8 *align;
592 char *buffer;
593 unsigned long flags;
594
595 if (data->flags & MMC_DATA_READ)
596 direction = DMA_FROM_DEVICE;
597 else
598 direction = DMA_TO_DEVICE;
599
600 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
601 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
602
603 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
604 128 * 4, direction);
605
606 if (data->flags & MMC_DATA_READ) {
607 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
608 data->sg_len, direction);
609
610 align = host->align_buffer;
611
612 for_each_sg(data->sg, sg, host->sg_count, i) {
613 if (sg_dma_address(sg) & 0x3) {
614 size = 4 - (sg_dma_address(sg) & 0x3);
615
616 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 617 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 618 memcpy(buffer, align, size);
619 sdhci_kunmap_atomic(buffer, &flags);
620
621 align += 4;
622 }
623 }
624 }
625
626 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
627 data->sg_len, direction);
628}
629
a3c7778f 630static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 631{
1c8cde92 632 u8 count;
a3c7778f 633 struct mmc_data *data = cmd->data;
1c8cde92 634 unsigned target_timeout, current_timeout;
d129bceb 635
ee53ab5d
PO		 636 /*
637 * If the host controller provides us with an incorrect timeout
638 * value, just skip the check and use 0xE. The hardware may take
639 * longer to time out, but that's much better than having a too-short
640 * timeout value.
641 */
11a2f1b7 642 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 643 return 0xE;
e538fbe8 644
a3c7778f
AW		 645 /* Unspecified timeout, assume max */
646 if (!data && !cmd->cmd_timeout_ms)
647 return 0xE;
d129bceb 648
a3c7778f
AW		 649 /* timeout in us */
650 if (!data)
651 target_timeout = cmd->cmd_timeout_ms * 1000;
78a2ca27
AS		 652 else {
653 target_timeout = data->timeout_ns / 1000;
654 if (host->clock)
655 target_timeout += data->timeout_clks / host->clock;
656 }
81b39802 657
1c8cde92
PO		 658 /*
659 * Figure out needed cycles.
660 * We do this in steps in order to fit inside a 32 bit int.
661 * The first step is the minimum timeout, which will have a
662 * minimum resolution of 6 bits:
663 * (1) 2^13*1000 > 2^22,
664 * (2) host->timeout_clk < 2^16
665 * =>
666 * (1) / (2) > 2^6
667 */
668 count = 0;
669 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
670 while (current_timeout < target_timeout) {
671 count++;
672 current_timeout <<= 1;
673 if (count >= 0xF)
674 break;
675 }
676
677 if (count >= 0xF) {
a3c76eb9 678 pr_warning("%s: Too large timeout requested for CMD%d!\n",
a3c7778f 679 mmc_hostname(host->mmc), cmd->opcode);
1c8cde92
PO		 680 count = 0xE;
681 }
682
ee53ab5d
PO		 683 return count;
684}
685
6aa943ab
AV		 686static void sdhci_set_transfer_irqs(struct sdhci_host *host)
687{
688 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
689 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
690
691 if (host->flags & SDHCI_REQ_USE_DMA)
692 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
693 else
694 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
695}
696
a3c7778f 697static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 698{
699 u8 count;
2134a922 700 u8 ctrl;
a3c7778f 701 struct mmc_data *data = cmd->data;
8f1934ce 702 int ret;
ee53ab5d
PO		 703
704 WARN_ON(host->data);
705
a3c7778f
AW		 706 if (data || (cmd->flags & MMC_RSP_BUSY)) {
707 count = sdhci_calc_timeout(host, cmd);
708 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
709 }
710
711 if (!data)
ee53ab5d
PO		 712 return;
713
714 /* Sanity checks */
715 BUG_ON(data->blksz * data->blocks > 524288);
716 BUG_ON(data->blksz > host->mmc->max_blk_size);
717 BUG_ON(data->blocks > 65535);
718
719 host->data = data;
720 host->data_early = 0;
f6a03cbf 721 host->data->bytes_xfered = 0;
ee53ab5d 722
a13abc7b 723 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 724 host->flags |= SDHCI_REQ_USE_DMA;
725
2134a922
PO		 726 /*
727 * FIXME: This doesn't account for merging when mapping the
728 * scatterlist.
729 */
730 if (host->flags & SDHCI_REQ_USE_DMA) {
731 int broken, i;
732 struct scatterlist *sg;
733
734 broken = 0;
735 if (host->flags & SDHCI_USE_ADMA) {
736 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
737 broken = 1;
738 } else {
739 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
740 broken = 1;
741 }
742
743 if (unlikely(broken)) {
744 for_each_sg(data->sg, sg, data->sg_len, i) {
745 if (sg->length & 0x3) {
746 DBG("Reverting to PIO because of "
747 "transfer size (%d)\n",
748 sg->length);
749 host->flags &= ~SDHCI_REQ_USE_DMA;
750 break;
751 }
752 }
753 }
c9fddbc4
PO		 754 }
755
756 /*
757 * The assumption here being that alignment is the same after
758 * translation to device address space.
759 */
2134a922
PO		 760 if (host->flags & SDHCI_REQ_USE_DMA) {
761 int broken, i;
762 struct scatterlist *sg;
763
764 broken = 0;
765 if (host->flags & SDHCI_USE_ADMA) {
766 /*
767 * As we use 3 byte chunks to work around
768 * alignment problems, we need to check this
769 * quirk.
770 */
771 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
772 broken = 1;
773 } else {
774 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
775 broken = 1;
776 }
777
778 if (unlikely(broken)) {
779 for_each_sg(data->sg, sg, data->sg_len, i) {
780 if (sg->offset & 0x3) {
781 DBG("Reverting to PIO because of "
782 "bad alignment\n");
783 host->flags &= ~SDHCI_REQ_USE_DMA;
784 break;
785 }
786 }
787 }
788 }
789
8f1934ce
PO		 790 if (host->flags & SDHCI_REQ_USE_DMA) {
791 if (host->flags & SDHCI_USE_ADMA) {
792 ret = sdhci_adma_table_pre(host, data);
793 if (ret) {
794 /*
795 * This only happens when someone fed
796 * us an invalid request.
797 */
798 WARN_ON(1);
ebd6d357 799 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 800 } else {
4e4141a5
AV		 801 sdhci_writel(host, host->adma_addr,
802 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 803 }
804 } else {
c8b3e02e 805 int sg_cnt;
8f1934ce 806
c8b3e02e 807 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 808 data->sg, data->sg_len,
809 (data->flags & MMC_DATA_READ) ?
810 DMA_FROM_DEVICE :
811 DMA_TO_DEVICE);
c8b3e02e 812 if (sg_cnt == 0) {
8f1934ce
PO		 813 /*
814 * This only happens when someone fed
815 * us an invalid request.
816 */
817 WARN_ON(1);
ebd6d357 818 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 819 } else {
719a61b4 820 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 821 sdhci_writel(host, sg_dma_address(data->sg),
822 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 823 }
824 }
825 }
826
2134a922
PO		 827 /*
828 * Always adjust the DMA selection as some controllers
829 * (e.g. JMicron) can't do PIO properly when the selection
830 * is ADMA.
831 */
832 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 833 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 834 ctrl &= ~SDHCI_CTRL_DMA_MASK;
835 if ((host->flags & SDHCI_REQ_USE_DMA) &&
836 (host->flags & SDHCI_USE_ADMA))
837 ctrl |= SDHCI_CTRL_ADMA32;
838 else
839 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 840 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 841 }
842
8f1934ce 843 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 844 int flags;
845
846 flags = SG_MITER_ATOMIC;
847 if (host->data->flags & MMC_DATA_READ)
848 flags |= SG_MITER_TO_SG;
849 else
850 flags |= SG_MITER_FROM_SG;
851 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 852 host->blocks = data->blocks;
d129bceb 853 }
c7fa9963 854
6aa943ab
AV		 855 sdhci_set_transfer_irqs(host);
856
f6a03cbf
MV		 857 /* Set the DMA boundary value and block size */
858 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
859 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 860 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 861}
862
863static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 864 struct mmc_command *cmd)
c7fa9963
PO		 865{
866 u16 mode;
e89d456f 867 struct mmc_data *data = cmd->data;
c7fa9963 868
c7fa9963
PO		 869 if (data == NULL)
870 return;
871
e538fbe8
PO		 872 WARN_ON(!host->data);
873
c7fa9963 874 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 875 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
876 mode |= SDHCI_TRNS_MULTI;
877 /*
878 * If we are sending CMD23, CMD12 never gets sent
879 * on successful completion (so no Auto-CMD12).
880 */
881 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
882 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 883 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
884 mode |= SDHCI_TRNS_AUTO_CMD23;
885 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
886 }
c4512f79 887 }
8edf6371 888
c7fa9963
PO		 889 if (data->flags & MMC_DATA_READ)
890 mode |= SDHCI_TRNS_READ;
c9fddbc4 891 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 892 mode |= SDHCI_TRNS_DMA;
893
4e4141a5 894 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 895}
896
897static void sdhci_finish_data(struct sdhci_host *host)
898{
899 struct mmc_data *data;
d129bceb
PO		 900
901 BUG_ON(!host->data);
902
903 data = host->data;
904 host->data = NULL;
905
c9fddbc4 906 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 907 if (host->flags & SDHCI_USE_ADMA)
908 sdhci_adma_table_post(host, data);
909 else {
910 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
911 data->sg_len, (data->flags & MMC_DATA_READ) ?
912 DMA_FROM_DEVICE : DMA_TO_DEVICE);
913 }
d129bceb
PO		 914 }
915
916 /*
c9b74c5b
PO		 917 * The specification states that the block count register must
918 * be updated, but it does not specify at what point in the
919 * data flow. That makes the register entirely useless to read
920 * back so we have to assume that nothing made it to the card
921 * in the event of an error.
d129bceb 922 */
c9b74c5b
PO		 923 if (data->error)
924 data->bytes_xfered = 0;
d129bceb 925 else
c9b74c5b 926 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 927
e89d456f
AW		 928 /*
929 * Need to send CMD12 if -
930 * a) open-ended multiblock transfer (no CMD23)
931 * b) error in multiblock transfer
932 */
933 if (data->stop &&
934 (data->error ||
935 !host->mrq->sbc)) {
936
d129bceb
PO		 937 /*
938 * The controller needs a reset of internal state machines
939 * upon error conditions.
940 */
17b0429d 941 if (data->error) {
d129bceb
PO		 942 sdhci_reset(host, SDHCI_RESET_CMD);
943 sdhci_reset(host, SDHCI_RESET_DATA);
944 }
945
946 sdhci_send_command(host, data->stop);
947 } else
948 tasklet_schedule(&host->finish_tasklet);
949}
950
951static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
952{
953 int flags;
fd2208d7 954 u32 mask;
7cb2c76f 955 unsigned long timeout;
d129bceb
PO		 956
957 WARN_ON(host->cmd);
958
d129bceb 959 /* Wait max 10 ms */
7cb2c76f 960 timeout = 10;
fd2208d7
PO		 961
962 mask = SDHCI_CMD_INHIBIT;
963 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
964 mask |= SDHCI_DATA_INHIBIT;
965
966 /* We shouldn't wait for data inihibit for stop commands, even
967 though they might use busy signaling */
968 if (host->mrq->data && (cmd == host->mrq->data->stop))
969 mask &= ~SDHCI_DATA_INHIBIT;
970
4e4141a5 971 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 972 if (timeout == 0) {
a3c76eb9 973 pr_err("%s: Controller never released "
acf1da45 974 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 975 sdhci_dumpregs(host);
17b0429d 976 cmd->error = -EIO;
d129bceb
PO		 977 tasklet_schedule(&host->finish_tasklet);
978 return;
979 }
7cb2c76f
PO		 980 timeout--;
981 mdelay(1);
982 }
d129bceb
PO		 983
984 mod_timer(&host->timer, jiffies + 10 * HZ);
985
986 host->cmd = cmd;
987
a3c7778f 988 sdhci_prepare_data(host, cmd);
d129bceb 989
4e4141a5 990 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 991
e89d456f 992 sdhci_set_transfer_mode(host, cmd);
c7fa9963 993
d129bceb 994 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 995 pr_err("%s: Unsupported response type!\n",
d129bceb 996 mmc_hostname(host->mmc));
17b0429d 997 cmd->error = -EINVAL;
d129bceb
PO		 998 tasklet_schedule(&host->finish_tasklet);
999 return;
1000 }
1001
1002 if (!(cmd->flags & MMC_RSP_PRESENT))
1003 flags = SDHCI_CMD_RESP_NONE;
1004 else if (cmd->flags & MMC_RSP_136)
1005 flags = SDHCI_CMD_RESP_LONG;
1006 else if (cmd->flags & MMC_RSP_BUSY)
1007 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1008 else
1009 flags = SDHCI_CMD_RESP_SHORT;
1010
1011 if (cmd->flags & MMC_RSP_CRC)
1012 flags |= SDHCI_CMD_CRC;
1013 if (cmd->flags & MMC_RSP_OPCODE)
1014 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1015
1016 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1017 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1018 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1019 flags |= SDHCI_CMD_DATA;
1020
4e4141a5 1021 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 1022}
1023
1024static void sdhci_finish_command(struct sdhci_host *host)
1025{
1026 int i;
1027
1028 BUG_ON(host->cmd == NULL);
1029
1030 if (host->cmd->flags & MMC_RSP_PRESENT) {
1031 if (host->cmd->flags & MMC_RSP_136) {
1032 /* CRC is stripped so we need to do some shifting. */
1033 for (i = 0;i < 4;i++) {
4e4141a5 1034 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1035 SDHCI_RESPONSE + (3-i)*4) << 8;
1036 if (i != 3)
1037 host->cmd->resp[i] |=
4e4141a5 1038 sdhci_readb(host,
d129bceb
PO		 1039 SDHCI_RESPONSE + (3-i)*4-1);
1040 }
1041 } else {
4e4141a5 1042 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1043 }
1044 }
1045
17b0429d 1046 host->cmd->error = 0;
d129bceb 1047
e89d456f
AW		 1048 /* Finished CMD23, now send actual command. */
1049 if (host->cmd == host->mrq->sbc) {
1050 host->cmd = NULL;
1051 sdhci_send_command(host, host->mrq->cmd);
1052 } else {
e538fbe8 1053
e89d456f
AW		 1054 /* Processed actual command. */
1055 if (host->data && host->data_early)
1056 sdhci_finish_data(host);
d129bceb 1057
e89d456f
AW		 1058 if (!host->cmd->data)
1059 tasklet_schedule(&host->finish_tasklet);
1060
1061 host->cmd = NULL;
1062 }
d129bceb
PO		 1063}
1064
1065static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1066{
c3ed3877 1067 int div = 0; /* Initialized for compiler warning */
df16219f 1068 int real_div = div, clk_mul = 1;
c3ed3877 1069 u16 clk = 0;
7cb2c76f 1070 unsigned long timeout;
d129bceb 1071
30832ab5 1072 if (clock && clock == host->clock)
d129bceb
PO		 1073 return;
1074
df16219f
GC		 1075 host->mmc->actual_clock = 0;
1076
8114634c
AV		 1077 if (host->ops->set_clock) {
1078 host->ops->set_clock(host, clock);
1079 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1080 return;
1081 }
1082
4e4141a5 1083 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1084
1085 if (clock == 0)
1086 goto out;
1087
85105c53 1088 if (host->version >= SDHCI_SPEC_300) {
c3ed3877
AN		 1089 /*
1090 * Check if the Host Controller supports Programmable Clock
1091 * Mode.
1092 */
1093 if (host->clk_mul) {
1094 u16 ctrl;
1095
1096 /*
1097 * We need to figure out whether the Host Driver needs
1098 * to select Programmable Clock Mode, or the value can
1099 * be set automatically by the Host Controller based on
1100 * the Preset Value registers.
1101 */
1102 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1103 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1104 for (div = 1; div <= 1024; div++) {
1105 if (((host->max_clk * host->clk_mul) /
1106 div) <= clock)
1107 break;
1108 }
1109 /*
1110 * Set Programmable Clock Mode in the Clock
1111 * Control register.
1112 */
1113 clk = SDHCI_PROG_CLOCK_MODE;
df16219f
GC		 1114 real_div = div;
1115 clk_mul = host->clk_mul;
c3ed3877
AN		 1116 div--;
1117 }
1118 } else {
1119 /* Version 3.00 divisors must be a multiple of 2. */
1120 if (host->max_clk <= clock)
1121 div = 1;
1122 else {
1123 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1124 div += 2) {
1125 if ((host->max_clk / div) <= clock)
1126 break;
1127 }
85105c53 1128 }
df16219f 1129 real_div = div;
c3ed3877 1130 div >>= 1;
85105c53
ZG		 1131 }
1132 } else {
1133 /* Version 2.00 divisors must be a power of 2. */
0397526d 1134 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1135 if ((host->max_clk / div) <= clock)
1136 break;
1137 }
df16219f 1138 real_div = div;
c3ed3877 1139 div >>= 1;
d129bceb 1140 }
d129bceb 1141
df16219f
GC		 1142 if (real_div)
1143 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1144
c3ed3877 1145 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1146 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1147 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1148 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1149 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1150
27f6cb16
CB		 1151 /* Wait max 20 ms */
1152 timeout = 20;
4e4141a5 1153 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1154 & SDHCI_CLOCK_INT_STABLE)) {
1155 if (timeout == 0) {
a3c76eb9 1156 pr_err("%s: Internal clock never "
acf1da45 1157 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1158 sdhci_dumpregs(host);
1159 return;
1160 }
7cb2c76f
PO		 1161 timeout--;
1162 mdelay(1);
1163 }
d129bceb
PO		 1164
1165 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1166 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1167
1168out:
1169 host->clock = clock;
1170}
1171
ceb6143b 1172static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1173{
8364248a 1174 u8 pwr = 0;
146ad66e 1175
8364248a 1176 if (power != (unsigned short)-1) {
ae628903
PO		 1177 switch (1 << power) {
1178 case MMC_VDD_165_195:
1179 pwr = SDHCI_POWER_180;
1180 break;
1181 case MMC_VDD_29_30:
1182 case MMC_VDD_30_31:
1183 pwr = SDHCI_POWER_300;
1184 break;
1185 case MMC_VDD_32_33:
1186 case MMC_VDD_33_34:
1187 pwr = SDHCI_POWER_330;
1188 break;
1189 default:
1190 BUG();
1191 }
1192 }
1193
1194 if (host->pwr == pwr)
ceb6143b 1195 return -1;
146ad66e 1196
ae628903
PO		 1197 host->pwr = pwr;
1198
1199 if (pwr == 0) {
4e4141a5 1200 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ceb6143b 1201 return 0;
9e9dc5f2
DS		 1202 }
1203
1204 /*
1205 * Spec says that we should clear the power reg before setting
1206 * a new value. Some controllers don't seem to like this though.
1207 */
b8c86fc5 1208 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1209 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1210
e08c1694 1211 /*
c71f6512 1212 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1213 * and set turn on power at the same time, so set the voltage first.
1214 */
11a2f1b7 1215 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1216 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1217
ae628903 1218 pwr |= SDHCI_POWER_ON;
146ad66e 1219
ae628903 1220 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1221
1222 /*
1223 * Some controllers need an extra 10ms delay of 10ms before they
1224 * can apply clock after applying power
1225 */
11a2f1b7 1226 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1227 mdelay(10);
ceb6143b
AH		 1228
1229 return power;
146ad66e
PO		 1230}
1231
d129bceb
PO		 1232/*****************************************************************************\
1233 * *
1234 * MMC callbacks *
1235 * *
1236\*****************************************************************************/
1237
1238static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1239{
1240 struct sdhci_host *host;
68d1fb7e 1241 bool present;
d129bceb
PO		 1242 unsigned long flags;
1243
1244 host = mmc_priv(mmc);
1245
66fd8ad5
AH		 1246 sdhci_runtime_pm_get(host);
1247
d129bceb
PO		 1248 spin_lock_irqsave(&host->lock, flags);
1249
1250 WARN_ON(host->mrq != NULL);
1251
f9134319 1252#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1253 sdhci_activate_led(host);
2f730fec 1254#endif
e89d456f
AW		 1255
1256 /*
1257 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1258 * requests if Auto-CMD12 is enabled.
1259 */
1260 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1261 if (mrq->stop) {
1262 mrq->data->stop = NULL;
1263 mrq->stop = NULL;
1264 }
1265 }
d129bceb
PO		 1266
1267 host->mrq = mrq;
1268
68d1fb7e
AV		 1269 /* If polling, assume that the card is always present. */
1270 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1271 present = true;
1272 else
1273 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1274 SDHCI_CARD_PRESENT;
1275
1276 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1277 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1278 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1279 } else {
1280 u32 present_state;
1281
1282 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1283 /*
1284 * Check if the re-tuning timer has already expired and there
1285 * is no on-going data transfer. If so, we need to execute
1286 * tuning procedure before sending command.
1287 */
1288 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1289 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1290 spin_unlock_irqrestore(&host->lock, flags);
069c9f14 1291 sdhci_execute_tuning(mmc, mrq->cmd->opcode);
cf2b5eea
AN		 1292 spin_lock_irqsave(&host->lock, flags);
1293
1294 /* Restore original mmc_request structure */
1295 host->mrq = mrq;
1296 }
1297
8edf6371 1298 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1299 sdhci_send_command(host, mrq->sbc);
1300 else
1301 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1302 }
d129bceb 1303
5f25a66f 1304 mmiowb();
d129bceb
PO		 1305 spin_unlock_irqrestore(&host->lock, flags);
1306}
1307
66fd8ad5 1308static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1309{
d129bceb 1310 unsigned long flags;
ceb6143b 1311 int vdd_bit = -1;
d129bceb
PO		 1312 u8 ctrl;
1313
d129bceb
PO		 1314 spin_lock_irqsave(&host->lock, flags);
1315
ceb6143b
AH		 1316 if (host->flags & SDHCI_DEVICE_DEAD) {
1317 spin_unlock_irqrestore(&host->lock, flags);
1318 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1319 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1320 return;
1321 }
1e72859e 1322
d129bceb
PO		 1323 /*
1324 * Reset the chip on each power off.
1325 * Should clear out any weird states.
1326 */
1327 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1328 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1329 sdhci_reinit(host);
d129bceb
PO		 1330 }
1331
1332 sdhci_set_clock(host, ios->clock);
1333
1334 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1335 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1336 else
ceb6143b
AH		 1337 vdd_bit = sdhci_set_power(host, ios->vdd);
1338
1339 if (host->vmmc && vdd_bit != -1) {
1340 spin_unlock_irqrestore(&host->lock, flags);
1341 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1342 spin_lock_irqsave(&host->lock, flags);
1343 }
d129bceb 1344
643a81ff
PR		 1345 if (host->ops->platform_send_init_74_clocks)
1346 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1347
15ec4461
PR		 1348 /*
1349 * If your platform has 8-bit width support but is not a v3 controller,
1350 * or if it requires special setup code, you should implement that in
1351 * platform_8bit_width().
1352 */
1353 if (host->ops->platform_8bit_width)
1354 host->ops->platform_8bit_width(host, ios->bus_width);
1355 else {
1356 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1357 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1358 ctrl &= ~SDHCI_CTRL_4BITBUS;
1359 if (host->version >= SDHCI_SPEC_300)
1360 ctrl |= SDHCI_CTRL_8BITBUS;
1361 } else {
1362 if (host->version >= SDHCI_SPEC_300)
1363 ctrl &= ~SDHCI_CTRL_8BITBUS;
1364 if (ios->bus_width == MMC_BUS_WIDTH_4)
1365 ctrl |= SDHCI_CTRL_4BITBUS;
1366 else
1367 ctrl &= ~SDHCI_CTRL_4BITBUS;
1368 }
1369 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1370 }
ae6d6c92 1371
15ec4461 1372 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1373
3ab9c8da
PR		 1374 if ((ios->timing == MMC_TIMING_SD_HS ||
1375 ios->timing == MMC_TIMING_MMC_HS)
1376 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1377 ctrl |= SDHCI_CTRL_HISPD;
1378 else
1379 ctrl &= ~SDHCI_CTRL_HISPD;
1380
d6d50a15 1381 if (host->version >= SDHCI_SPEC_300) {
49c468fc
AN		 1382 u16 clk, ctrl_2;
1383 unsigned int clock;
1384
1385 /* In case of UHS-I modes, set High Speed Enable */
069c9f14
G		 1386 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1387 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1388 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1389 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1390 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1391 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1392
1393 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1394 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1395 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1396 /*
1397 * We only need to set Driver Strength if the
1398 * preset value enable is not set.
1399 */
1400 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1401 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1402 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1403 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1404 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1405
1406 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1407 } else {
1408 /*
1409 * According to SDHC Spec v3.00, if the Preset Value
1410 * Enable in the Host Control 2 register is set, we
1411 * need to reset SD Clock Enable before changing High
1412 * Speed Enable to avoid generating clock gliches.
1413 */
758535c4
AN		 1414
1415 /* Reset SD Clock Enable */
1416 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1417 clk &= ~SDHCI_CLOCK_CARD_EN;
1418 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1419
1420 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1421
1422 /* Re-enable SD Clock */
1423 clock = host->clock;
1424 host->clock = 0;
1425 sdhci_set_clock(host, clock);
d6d50a15 1426 }
49c468fc 1427
49c468fc
AN		 1428
1429 /* Reset SD Clock Enable */
1430 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1431 clk &= ~SDHCI_CLOCK_CARD_EN;
1432 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1433
6322cdd0
PR		 1434 if (host->ops->set_uhs_signaling)
1435 host->ops->set_uhs_signaling(host, ios->timing);
1436 else {
1437 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1438 /* Select Bus Speed Mode for host */
1439 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
069c9f14
G		 1440 if (ios->timing == MMC_TIMING_MMC_HS200)
1441 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1442 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1443 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1444 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1445 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1446 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1447 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1448 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1449 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1450 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1451 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1452 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1453 }
49c468fc
AN		 1454
1455 /* Re-enable SD Clock */
1456 clock = host->clock;
1457 host->clock = 0;
1458 sdhci_set_clock(host, clock);
758535c4
AN		 1459 } else
1460 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1461
b8352260
LD		 1462 /*
1463 * Some (ENE) controllers go apeshit on some ios operation,
1464 * signalling timeout and CRC errors even on CMD0. Resetting
1465 * it on each ios seems to solve the problem.
1466 */
b8c86fc5 1467 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1468 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1469
5f25a66f 1470 mmiowb();
d129bceb
PO		 1471 spin_unlock_irqrestore(&host->lock, flags);
1472}
1473
66fd8ad5
AH		 1474static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1475{
1476 struct sdhci_host *host = mmc_priv(mmc);
1477
1478 sdhci_runtime_pm_get(host);
1479 sdhci_do_set_ios(host, ios);
1480 sdhci_runtime_pm_put(host);
1481}
1482
1483static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1484{
d129bceb 1485 unsigned long flags;
2dfb579c 1486 int is_readonly;
d129bceb 1487
d129bceb
PO		 1488 spin_lock_irqsave(&host->lock, flags);
1489
1e72859e 1490 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1491 is_readonly = 0;
1492 else if (host->ops->get_ro)
1493 is_readonly = host->ops->get_ro(host);
1e72859e 1494 else
2dfb579c
WS		 1495 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1496 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1497
1498 spin_unlock_irqrestore(&host->lock, flags);
1499
2dfb579c
WS		 1500 /* This quirk needs to be replaced by a callback-function later */
1501 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1502 !is_readonly : is_readonly;
d129bceb
PO		 1503}
1504
82b0e23a
TI		 1505#define SAMPLE_COUNT 5
1506
66fd8ad5 1507static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1508{
82b0e23a
TI		 1509 int i, ro_count;
1510
82b0e23a 1511 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1512 return sdhci_check_ro(host);
82b0e23a
TI		 1513
1514 ro_count = 0;
1515 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1516 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1517 if (++ro_count > SAMPLE_COUNT / 2)
1518 return 1;
1519 }
1520 msleep(30);
1521 }
1522 return 0;
1523}
1524
20758b66
AH		 1525static void sdhci_hw_reset(struct mmc_host *mmc)
1526{
1527 struct sdhci_host *host = mmc_priv(mmc);
1528
1529 if (host->ops && host->ops->hw_reset)
1530 host->ops->hw_reset(host);
1531}
1532
66fd8ad5 1533static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1534{
66fd8ad5
AH		 1535 struct sdhci_host *host = mmc_priv(mmc);
1536 int ret;
f75979b7 1537
66fd8ad5
AH		 1538 sdhci_runtime_pm_get(host);
1539 ret = sdhci_do_get_ro(host);
1540 sdhci_runtime_pm_put(host);
1541 return ret;
1542}
f75979b7 1543
66fd8ad5
AH		 1544static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1545{
1e72859e
PO		 1546 if (host->flags & SDHCI_DEVICE_DEAD)
1547 goto out;
1548
66fd8ad5
AH		 1549 if (enable)
1550 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1551 else
1552 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1553
1554 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1555 if (host->runtime_suspended)
1556 goto out;
1557
f75979b7 1558 if (enable)
7260cf5e
AV		 1559 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1560 else
1561 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1562out:
f75979b7 1563 mmiowb();
66fd8ad5
AH		 1564}
1565
1566static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1567{
1568 struct sdhci_host *host = mmc_priv(mmc);
1569 unsigned long flags;
f75979b7 1570
66fd8ad5
AH		 1571 spin_lock_irqsave(&host->lock, flags);
1572 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1573 spin_unlock_irqrestore(&host->lock, flags);
1574}
1575
66fd8ad5
AH		 1576static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1577 struct mmc_ios *ios)
f2119df6 1578{
f2119df6
AN		 1579 u8 pwr;
1580 u16 clk, ctrl;
1581 u32 present_state;
1582
f2119df6
AN		 1583 /*
1584 * Signal Voltage Switching is only applicable for Host Controllers
1585 * v3.00 and above.
1586 */
1587 if (host->version < SDHCI_SPEC_300)
1588 return 0;
1589
1590 /*
1591 * We first check whether the request is to set signalling voltage
1592 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1593 */
1594 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1595 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1596 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1597 ctrl &= ~SDHCI_CTRL_VDD_180;
1598 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1599
1600 /* Wait for 5ms */
1601 usleep_range(5000, 5500);
1602
1603 /* 3.3V regulator output should be stable within 5 ms */
1604 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1605 if (!(ctrl & SDHCI_CTRL_VDD_180))
1606 return 0;
1607 else {
a3c76eb9 1608 pr_info(DRIVER_NAME ": Switching to 3.3V "
f2119df6
AN		 1609 "signalling voltage failed\n");
1610 return -EIO;
1611 }
1612 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1613 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1614 /* Stop SDCLK */
1615 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1616 clk &= ~SDHCI_CLOCK_CARD_EN;
1617 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1618
1619 /* Check whether DAT[3:0] is 0000 */
1620 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1621 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1622 SDHCI_DATA_LVL_SHIFT)) {
1623 /*
1624 * Enable 1.8V Signal Enable in the Host Control2
1625 * register
1626 */
1627 ctrl |= SDHCI_CTRL_VDD_180;
1628 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1629
1630 /* Wait for 5ms */
1631 usleep_range(5000, 5500);
1632
1633 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1634 if (ctrl & SDHCI_CTRL_VDD_180) {
1635 /* Provide SDCLK again and wait for 1ms*/
1636 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1637 clk |= SDHCI_CLOCK_CARD_EN;
1638 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1639 usleep_range(1000, 1500);
1640
1641 /*
1642 * If DAT[3:0] level is 1111b, then the card
1643 * was successfully switched to 1.8V signaling.
1644 */
1645 present_state = sdhci_readl(host,
1646 SDHCI_PRESENT_STATE);
1647 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1648 SDHCI_DATA_LVL_MASK)
1649 return 0;
1650 }
1651 }
1652
1653 /*
1654 * If we are here, that means the switch to 1.8V signaling
1655 * failed. We power cycle the card, and retry initialization
1656 * sequence by setting S18R to 0.
1657 */
1658 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1659 pwr &= ~SDHCI_POWER_ON;
1660 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1661
1662 /* Wait for 1ms as per the spec */
1663 usleep_range(1000, 1500);
1664 pwr |= SDHCI_POWER_ON;
1665 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1666
a3c76eb9 1667 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
f2119df6
AN		 1668 "voltage failed, retrying with S18R set to 0\n");
1669 return -EAGAIN;
1670 } else
1671 /* No signal voltage switch required */
1672 return 0;
1673}
1674
66fd8ad5
AH		 1675static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1676 struct mmc_ios *ios)
1677{
1678 struct sdhci_host *host = mmc_priv(mmc);
1679 int err;
1680
1681 if (host->version < SDHCI_SPEC_300)
1682 return 0;
1683 sdhci_runtime_pm_get(host);
1684 err = sdhci_do_start_signal_voltage_switch(host, ios);
1685 sdhci_runtime_pm_put(host);
1686 return err;
1687}
1688
069c9f14 1689static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1690{
1691 struct sdhci_host *host;
1692 u16 ctrl;
1693 u32 ier;
1694 int tuning_loop_counter = MAX_TUNING_LOOP;
1695 unsigned long timeout;
1696 int err = 0;
069c9f14 1697 bool requires_tuning_nonuhs = false;
b513ea25
AN		 1698
1699 host = mmc_priv(mmc);
1700
66fd8ad5 1701 sdhci_runtime_pm_get(host);
b513ea25
AN		 1702 disable_irq(host->irq);
1703 spin_lock(&host->lock);
1704
1705 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1706
1707 /*
069c9f14
G		 1708 * The Host Controller needs tuning only in case of SDR104 mode
1709 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1710 * Capabilities register.
069c9f14
G		 1711 * If the Host Controller supports the HS200 mode then the
1712 * tuning function has to be executed.
b513ea25 1713 */
069c9f14
G		 1714 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1715 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1716 host->flags & SDHCI_HS200_NEEDS_TUNING))
1717 requires_tuning_nonuhs = true;
1718
b513ea25 1719 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1720 requires_tuning_nonuhs)
b513ea25
AN		 1721 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1722 else {
1723 spin_unlock(&host->lock);
1724 enable_irq(host->irq);
66fd8ad5 1725 sdhci_runtime_pm_put(host);
b513ea25
AN		 1726 return 0;
1727 }
1728
1729 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1730
1731 /*
1732 * As per the Host Controller spec v3.00, tuning command
1733 * generates Buffer Read Ready interrupt, so enable that.
1734 *
1735 * Note: The spec clearly says that when tuning sequence
1736 * is being performed, the controller does not generate
1737 * interrupts other than Buffer Read Ready interrupt. But
1738 * to make sure we don't hit a controller bug, we _only_
1739 * enable Buffer Read Ready interrupt here.
1740 */
1741 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1742 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1743
1744 /*
1745 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1746 * of loops reaches 40 times or a timeout of 150ms occurs.
1747 */
1748 timeout = 150;
1749 do {
1750 struct mmc_command cmd = {0};
66fd8ad5 1751 struct mmc_request mrq = {NULL};
b513ea25
AN		 1752
1753 if (!tuning_loop_counter && !timeout)
1754 break;
1755
069c9f14 1756 cmd.opcode = opcode;
b513ea25
AN		 1757 cmd.arg = 0;
1758 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1759 cmd.retries = 0;
1760 cmd.data = NULL;
1761 cmd.error = 0;
1762
1763 mrq.cmd = &cmd;
1764 host->mrq = &mrq;
1765
1766 /*
1767 * In response to CMD19, the card sends 64 bytes of tuning
1768 * block to the Host Controller. So we set the block size
1769 * to 64 here.
1770 */
069c9f14
G		 1771 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1772 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1773 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1774 SDHCI_BLOCK_SIZE);
1775 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1776 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1777 SDHCI_BLOCK_SIZE);
1778 } else {
1779 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1780 SDHCI_BLOCK_SIZE);
1781 }
b513ea25
AN		 1782
1783 /*
1784 * The tuning block is sent by the card to the host controller.
1785 * So we set the TRNS_READ bit in the Transfer Mode register.
1786 * This also takes care of setting DMA Enable and Multi Block
1787 * Select in the same register to 0.
1788 */
1789 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1790
1791 sdhci_send_command(host, &cmd);
1792
1793 host->cmd = NULL;
1794 host->mrq = NULL;
1795
1796 spin_unlock(&host->lock);
1797 enable_irq(host->irq);
1798
1799 /* Wait for Buffer Read Ready interrupt */
1800 wait_event_interruptible_timeout(host->buf_ready_int,
1801 (host->tuning_done == 1),
1802 msecs_to_jiffies(50));
1803 disable_irq(host->irq);
1804 spin_lock(&host->lock);
1805
1806 if (!host->tuning_done) {
a3c76eb9 1807 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1808 "Buffer Read Ready interrupt during tuning "
1809 "procedure, falling back to fixed sampling "
1810 "clock\n");
1811 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1812 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1813 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1814 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1815
1816 err = -EIO;
1817 goto out;
1818 }
1819
1820 host->tuning_done = 0;
1821
1822 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1823 tuning_loop_counter--;
1824 timeout--;
1825 mdelay(1);
1826 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1827
1828 /*
1829 * The Host Driver has exhausted the maximum number of loops allowed,
1830 * so use fixed sampling frequency.
1831 */
1832 if (!tuning_loop_counter || !timeout) {
1833 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1834 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1835 } else {
1836 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1837 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1838 " failed, falling back to fixed sampling"
1839 " clock\n");
1840 err = -EIO;
1841 }
1842 }
1843
1844out:
cf2b5eea
AN		 1845 /*
1846 * If this is the very first time we are here, we start the retuning
1847 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1848 * flag won't be set, we check this condition before actually starting
1849 * the timer.
1850 */
1851 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1852 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1853 mod_timer(&host->tuning_timer, jiffies +
1854 host->tuning_count * HZ);
1855 /* Tuning mode 1 limits the maximum data length to 4MB */
1856 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1857 } else {
1858 host->flags &= ~SDHCI_NEEDS_RETUNING;
1859 /* Reload the new initial value for timer */
1860 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1861 mod_timer(&host->tuning_timer, jiffies +
1862 host->tuning_count * HZ);
1863 }
1864
1865 /*
1866 * In case tuning fails, host controllers which support re-tuning can
1867 * try tuning again at a later time, when the re-tuning timer expires.
1868 * So for these controllers, we return 0. Since there might be other
1869 * controllers who do not have this capability, we return error for
1870 * them.
1871 */
1872 if (err && host->tuning_count &&
1873 host->tuning_mode == SDHCI_TUNING_MODE_1)
1874 err = 0;
1875
b513ea25
AN		 1876 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1877 spin_unlock(&host->lock);
1878 enable_irq(host->irq);
66fd8ad5 1879 sdhci_runtime_pm_put(host);
b513ea25
AN		 1880
1881 return err;
1882}
1883
66fd8ad5 1884static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 1885{
4d55c5a1
AN		 1886 u16 ctrl;
1887 unsigned long flags;
1888
4d55c5a1
AN		 1889 /* Host Controller v3.00 defines preset value registers */
1890 if (host->version < SDHCI_SPEC_300)
1891 return;
1892
1893 spin_lock_irqsave(&host->lock, flags);
1894
1895 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1896
1897 /*
1898 * We only enable or disable Preset Value if they are not already
1899 * enabled or disabled respectively. Otherwise, we bail out.
1900 */
1901 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1902 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1903 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1904 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 1905 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1906 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1907 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1908 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1
AN		 1909 }
1910
1911 spin_unlock_irqrestore(&host->lock, flags);
1912}
1913
66fd8ad5
AH		 1914static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1915{
1916 struct sdhci_host *host = mmc_priv(mmc);
1917
1918 sdhci_runtime_pm_get(host);
1919 sdhci_do_enable_preset_value(host, enable);
1920 sdhci_runtime_pm_put(host);
1921}
1922
ab7aefd0 1923static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1924 .request = sdhci_request,
1925 .set_ios = sdhci_set_ios,
1926 .get_ro = sdhci_get_ro,
20758b66 1927 .hw_reset = sdhci_hw_reset,
f75979b7 1928 .enable_sdio_irq = sdhci_enable_sdio_irq,
f2119df6 1929 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b513ea25 1930 .execute_tuning = sdhci_execute_tuning,
4d55c5a1 1931 .enable_preset_value = sdhci_enable_preset_value,
d129bceb
PO		 1932};
1933
1934/*****************************************************************************\
1935 * *
1936 * Tasklets *
1937 * *
1938\*****************************************************************************/
1939
1940static void sdhci_tasklet_card(unsigned long param)
1941{
1942 struct sdhci_host *host;
1943 unsigned long flags;
1944
1945 host = (struct sdhci_host*)param;
1946
1947 spin_lock_irqsave(&host->lock, flags);
1948
66fd8ad5
AH		 1949 /* Check host->mrq first in case we are runtime suspended */
1950 if (host->mrq &&
1951 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
a3c76eb9 1952 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 1953 mmc_hostname(host->mmc));
a3c76eb9 1954 pr_err("%s: Resetting controller.\n",
66fd8ad5 1955 mmc_hostname(host->mmc));
d129bceb 1956
66fd8ad5
AH		 1957 sdhci_reset(host, SDHCI_RESET_CMD);
1958 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 1959
66fd8ad5
AH		 1960 host->mrq->cmd->error = -ENOMEDIUM;
1961 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 1962 }
1963
1964 spin_unlock_irqrestore(&host->lock, flags);
1965
04cf585d 1966 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1967}
1968
1969static void sdhci_tasklet_finish(unsigned long param)
1970{
1971 struct sdhci_host *host;
1972 unsigned long flags;
1973 struct mmc_request *mrq;
1974
1975 host = (struct sdhci_host*)param;
1976
66fd8ad5
AH		 1977 spin_lock_irqsave(&host->lock, flags);
1978
0c9c99a7
CB		 1979 /*
1980 * If this tasklet gets rescheduled while running, it will
1981 * be run again afterwards but without any active request.
1982 */
66fd8ad5
AH		 1983 if (!host->mrq) {
1984 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 1985 return;
66fd8ad5 1986 }
d129bceb
PO		 1987
1988 del_timer(&host->timer);
1989
1990 mrq = host->mrq;
1991
d129bceb
PO		 1992 /*
1993 * The controller needs a reset of internal state machines
1994 * upon error conditions.
1995 */
1e72859e 1996 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 1997 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 1998 (mrq->data && (mrq->data->error ||
1999 (mrq->data->stop && mrq->data->stop->error))) ||
2000 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2001
2002 /* Some controllers need this kick or reset won't work here */
b8c86fc5 2003 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 2004 unsigned int clock;
2005
2006 /* This is to force an update */
2007 clock = host->clock;
2008 host->clock = 0;
2009 sdhci_set_clock(host, clock);
2010 }
2011
2012 /* Spec says we should do both at the same time, but Ricoh
2013 controllers do not like that. */
d129bceb
PO		 2014 sdhci_reset(host, SDHCI_RESET_CMD);
2015 sdhci_reset(host, SDHCI_RESET_DATA);
2016 }
2017
2018 host->mrq = NULL;
2019 host->cmd = NULL;
2020 host->data = NULL;
2021
f9134319 2022#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2023 sdhci_deactivate_led(host);
2f730fec 2024#endif
d129bceb 2025
5f25a66f 2026 mmiowb();
d129bceb
PO		 2027 spin_unlock_irqrestore(&host->lock, flags);
2028
2029 mmc_request_done(host->mmc, mrq);
66fd8ad5 2030 sdhci_runtime_pm_put(host);
d129bceb
PO		 2031}
2032
2033static void sdhci_timeout_timer(unsigned long data)
2034{
2035 struct sdhci_host *host;
2036 unsigned long flags;
2037
2038 host = (struct sdhci_host*)data;
2039
2040 spin_lock_irqsave(&host->lock, flags);
2041
2042 if (host->mrq) {
a3c76eb9 2043 pr_err("%s: Timeout waiting for hardware "
acf1da45 2044 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2045 sdhci_dumpregs(host);
2046
2047 if (host->data) {
17b0429d 2048 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2049 sdhci_finish_data(host);
2050 } else {
2051 if (host->cmd)
17b0429d 2052 host->cmd->error = -ETIMEDOUT;
d129bceb 2053 else
17b0429d 2054 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2055
2056 tasklet_schedule(&host->finish_tasklet);
2057 }
2058 }
2059
5f25a66f 2060 mmiowb();
d129bceb
PO		 2061 spin_unlock_irqrestore(&host->lock, flags);
2062}
2063
cf2b5eea
AN		 2064static void sdhci_tuning_timer(unsigned long data)
2065{
2066 struct sdhci_host *host;
2067 unsigned long flags;
2068
2069 host = (struct sdhci_host *)data;
2070
2071 spin_lock_irqsave(&host->lock, flags);
2072
2073 host->flags |= SDHCI_NEEDS_RETUNING;
2074
2075 spin_unlock_irqrestore(&host->lock, flags);
2076}
2077
d129bceb
PO		 2078/*****************************************************************************\
2079 * *
2080 * Interrupt handling *
2081 * *
2082\*****************************************************************************/
2083
2084static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2085{
2086 BUG_ON(intmask == 0);
2087
2088 if (!host->cmd) {
a3c76eb9 2089 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2090 "though no command operation was in progress.\n",
2091 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2092 sdhci_dumpregs(host);
2093 return;
2094 }
2095
43b58b36 2096 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2097 host->cmd->error = -ETIMEDOUT;
2098 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2099 SDHCI_INT_INDEX))
2100 host->cmd->error = -EILSEQ;
43b58b36 2101
e809517f 2102 if (host->cmd->error) {
d129bceb 2103 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2104 return;
2105 }
2106
2107 /*
2108 * The host can send and interrupt when the busy state has
2109 * ended, allowing us to wait without wasting CPU cycles.
2110 * Unfortunately this is overloaded on the "data complete"
2111 * interrupt, so we need to take some care when handling
2112 * it.
2113 *
2114 * Note: The 1.0 specification is a bit ambiguous about this
2115 * feature so there might be some problems with older
2116 * controllers.
2117 */
2118 if (host->cmd->flags & MMC_RSP_BUSY) {
2119 if (host->cmd->data)
2120 DBG("Cannot wait for busy signal when also "
2121 "doing a data transfer");
f945405c 2122 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2123 return;
f945405c
BD		 2124
2125 /* The controller does not support the end-of-busy IRQ,
2126 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2127 }
2128
2129 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2130 sdhci_finish_command(host);
d129bceb
PO		 2131}
2132
0957c333 2133#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2134static void sdhci_show_adma_error(struct sdhci_host *host)
2135{
2136 const char *name = mmc_hostname(host->mmc);
2137 u8 *desc = host->adma_desc;
2138 __le32 *dma;
2139 __le16 *len;
2140 u8 attr;
2141
2142 sdhci_dumpregs(host);
2143
2144 while (true) {
2145 dma = (__le32 *)(desc + 4);
2146 len = (__le16 *)(desc + 2);
2147 attr = *desc;
2148
2149 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2150 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2151
2152 desc += 8;
2153
2154 if (attr & 2)
2155 break;
2156 }
2157}
2158#else
2159static void sdhci_show_adma_error(struct sdhci_host *host) { }
2160#endif
2161
d129bceb
PO		 2162static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2163{
069c9f14 2164 u32 command;
d129bceb
PO		 2165 BUG_ON(intmask == 0);
2166
b513ea25
AN		 2167 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2168 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2169 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2170 if (command == MMC_SEND_TUNING_BLOCK ||
2171 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2172 host->tuning_done = 1;
2173 wake_up(&host->buf_ready_int);
2174 return;
2175 }
2176 }
2177
d129bceb
PO		 2178 if (!host->data) {
2179 /*
e809517f
PO		 2180 * The "data complete" interrupt is also used to
2181 * indicate that a busy state has ended. See comment
2182 * above in sdhci_cmd_irq().
d129bceb 2183 */
e809517f
PO		 2184 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2185 if (intmask & SDHCI_INT_DATA_END) {
2186 sdhci_finish_command(host);
2187 return;
2188 }
2189 }
d129bceb 2190
a3c76eb9 2191 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2192 "though no data operation was in progress.\n",
2193 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2194 sdhci_dumpregs(host);
2195
2196 return;
2197 }
2198
2199 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2200 host->data->error = -ETIMEDOUT;
22113efd
AL		 2201 else if (intmask & SDHCI_INT_DATA_END_BIT)
2202 host->data->error = -EILSEQ;
2203 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2204 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2205 != MMC_BUS_TEST_R)
17b0429d 2206 host->data->error = -EILSEQ;
6882a8c0 2207 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2208 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2209 sdhci_show_adma_error(host);
2134a922 2210 host->data->error = -EIO;
6882a8c0 2211 }
d129bceb 2212
17b0429d 2213 if (host->data->error)
d129bceb
PO		 2214 sdhci_finish_data(host);
2215 else {
a406f5a3 2216 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2217 sdhci_transfer_pio(host);
2218
6ba736a1
PO		 2219 /*
2220 * We currently don't do anything fancy with DMA
2221 * boundaries, but as we can't disable the feature
2222 * we need to at least restart the transfer.
f6a03cbf
MV		 2223 *
2224 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2225 * should return a valid address to continue from, but as
2226 * some controllers are faulty, don't trust them.
6ba736a1 2227 */
f6a03cbf
MV		 2228 if (intmask & SDHCI_INT_DMA_END) {
2229 u32 dmastart, dmanow;
2230 dmastart = sg_dma_address(host->data->sg);
2231 dmanow = dmastart + host->data->bytes_xfered;
2232 /*
2233 * Force update to the next DMA block boundary.
2234 */
2235 dmanow = (dmanow &
2236 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2237 SDHCI_DEFAULT_BOUNDARY_SIZE;
2238 host->data->bytes_xfered = dmanow - dmastart;
2239 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2240 " next 0x%08x\n",
2241 mmc_hostname(host->mmc), dmastart,
2242 host->data->bytes_xfered, dmanow);
2243 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2244 }
6ba736a1 2245
e538fbe8
PO		 2246 if (intmask & SDHCI_INT_DATA_END) {
2247 if (host->cmd) {
2248 /*
2249 * Data managed to finish before the
2250 * command completed. Make sure we do
2251 * things in the proper order.
2252 */
2253 host->data_early = 1;
2254 } else {
2255 sdhci_finish_data(host);
2256 }
2257 }
d129bceb
PO		 2258 }
2259}
2260
7d12e780 2261static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2262{
2263 irqreturn_t result;
66fd8ad5 2264 struct sdhci_host *host = dev_id;
d129bceb 2265 u32 intmask;
f75979b7 2266 int cardint = 0;
d129bceb
PO		 2267
2268 spin_lock(&host->lock);
2269
66fd8ad5
AH		 2270 if (host->runtime_suspended) {
2271 spin_unlock(&host->lock);
a3c76eb9 2272 pr_warning("%s: got irq while runtime suspended\n",
66fd8ad5
AH		 2273 mmc_hostname(host->mmc));
2274 return IRQ_HANDLED;
2275 }
2276
4e4141a5 2277 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2278
62df67a5 2279 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2280 result = IRQ_NONE;
2281 goto out;
2282 }
2283
b69c9058
PO		 2284 DBG("*** %s got interrupt: 0x%08x\n",
2285 mmc_hostname(host->mmc), intmask);
d129bceb 2286
3192a28f 2287 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2288 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2289 SDHCI_CARD_PRESENT;
2290
2291 /*
2292 * There is a observation on i.mx esdhc. INSERT bit will be
2293 * immediately set again when it gets cleared, if a card is
2294 * inserted. We have to mask the irq to prevent interrupt
2295 * storm which will freeze the system. And the REMOVE gets
2296 * the same situation.
2297 *
2298 * More testing are needed here to ensure it works for other
2299 * platforms though.
2300 */
2301 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2302 SDHCI_INT_CARD_REMOVE);
2303 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2304 SDHCI_INT_CARD_INSERT);
2305
4e4141a5 2306 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2307 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2308 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2309 tasklet_schedule(&host->card_tasklet);
3192a28f 2310 }
d129bceb 2311
3192a28f 2312 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2313 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2314 SDHCI_INT_STATUS);
3192a28f 2315 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2316 }
2317
2318 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2319 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2320 SDHCI_INT_STATUS);
3192a28f 2321 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2322 }
2323
2324 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2325
964f9ce2
PO		 2326 intmask &= ~SDHCI_INT_ERROR;
2327
d129bceb 2328 if (intmask & SDHCI_INT_BUS_POWER) {
a3c76eb9 2329 pr_err("%s: Card is consuming too much power!\n",
d129bceb 2330 mmc_hostname(host->mmc));
4e4141a5 2331 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2332 }
2333
9d26a5d3 2334 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2335
f75979b7
PO		 2336 if (intmask & SDHCI_INT_CARD_INT)
2337 cardint = 1;
2338
2339 intmask &= ~SDHCI_INT_CARD_INT;
2340
3192a28f 2341 if (intmask) {
a3c76eb9 2342 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3192a28f 2343 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 2344 sdhci_dumpregs(host);
2345
4e4141a5 2346 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2347 }
d129bceb
PO		 2348
2349 result = IRQ_HANDLED;
2350
5f25a66f 2351 mmiowb();
d129bceb
PO		 2352out:
2353 spin_unlock(&host->lock);
2354
f75979b7
PO		 2355 /*
2356 * We have to delay this as it calls back into the driver.
2357 */
2358 if (cardint)
2359 mmc_signal_sdio_irq(host->mmc);
2360
d129bceb
PO		 2361 return result;
2362}
2363
2364/*****************************************************************************\
2365 * *
2366 * Suspend/resume *
2367 * *
2368\*****************************************************************************/
2369
2370#ifdef CONFIG_PM
2371
29495aa0 2372int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2373{
b8c86fc5 2374 int ret;
38a60ea2 2375 bool has_tuning_timer;
a715dfc7 2376
7260cf5e
AV		 2377 sdhci_disable_card_detection(host);
2378
cf2b5eea 2379 /* Disable tuning since we are suspending */
38a60ea2
AL		 2380 has_tuning_timer = host->version >= SDHCI_SPEC_300 &&
2381 host->tuning_count && host->tuning_mode == SDHCI_TUNING_MODE_1;
2382 if (has_tuning_timer) {
c6ced0db 2383 del_timer_sync(&host->tuning_timer);
cf2b5eea 2384 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2385 }
2386
1a13f8fa 2387 ret = mmc_suspend_host(host->mmc);
38a60ea2
AL		 2388 if (ret) {
2389 if (has_tuning_timer) {
2390 host->flags |= SDHCI_NEEDS_RETUNING;
2391 mod_timer(&host->tuning_timer, jiffies +
2392 host->tuning_count * HZ);
2393 }
2394
2395 sdhci_enable_card_detection(host);
2396
b8c86fc5 2397 return ret;
38a60ea2 2398 }
a715dfc7 2399
b8c86fc5 2400 free_irq(host->irq, host);
d129bceb 2401
9bea3c85 2402 return ret;
d129bceb
PO		 2403}
2404
b8c86fc5 2405EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2406
b8c86fc5
PO		 2407int sdhci_resume_host(struct sdhci_host *host)
2408{
2409 int ret;
d129bceb 2410
a13abc7b 2411 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2412 if (host->ops->enable_dma)
2413 host->ops->enable_dma(host);
2414 }
d129bceb 2415
b8c86fc5
PO		 2416 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2417 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 2418 if (ret)
2419 return ret;
d129bceb 2420
2f4cbb3d 2421 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 2422 mmiowb();
2423
2424 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2425 sdhci_enable_card_detection(host);
2426
cf2b5eea
AN		 2427 /* Set the re-tuning expiration flag */
2428 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2429 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2430 host->flags |= SDHCI_NEEDS_RETUNING;
2431
2f4cbb3d 2432 return ret;
d129bceb
PO		 2433}
2434
b8c86fc5 2435EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 2436
5f619704
DD		 2437void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2438{
2439 u8 val;
2440 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2441 val |= SDHCI_WAKE_ON_INT;
2442 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2443}
2444
2445EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2446
d129bceb
PO		 2447#endif /* CONFIG_PM */
2448
66fd8ad5
AH		 2449#ifdef CONFIG_PM_RUNTIME
2450
2451static int sdhci_runtime_pm_get(struct sdhci_host *host)
2452{
2453 return pm_runtime_get_sync(host->mmc->parent);
2454}
2455
2456static int sdhci_runtime_pm_put(struct sdhci_host *host)
2457{
2458 pm_runtime_mark_last_busy(host->mmc->parent);
2459 return pm_runtime_put_autosuspend(host->mmc->parent);
2460}
2461
2462int sdhci_runtime_suspend_host(struct sdhci_host *host)
2463{
2464 unsigned long flags;
2465 int ret = 0;
2466
2467 /* Disable tuning since we are suspending */
2468 if (host->version >= SDHCI_SPEC_300 &&
2469 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2470 del_timer_sync(&host->tuning_timer);
2471 host->flags &= ~SDHCI_NEEDS_RETUNING;
2472 }
2473
2474 spin_lock_irqsave(&host->lock, flags);
2475 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2476 spin_unlock_irqrestore(&host->lock, flags);
2477
2478 synchronize_irq(host->irq);
2479
2480 spin_lock_irqsave(&host->lock, flags);
2481 host->runtime_suspended = true;
2482 spin_unlock_irqrestore(&host->lock, flags);
2483
2484 return ret;
2485}
2486EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2487
2488int sdhci_runtime_resume_host(struct sdhci_host *host)
2489{
2490 unsigned long flags;
2491 int ret = 0, host_flags = host->flags;
2492
2493 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2494 if (host->ops->enable_dma)
2495 host->ops->enable_dma(host);
2496 }
2497
2498 sdhci_init(host, 0);
2499
2500 /* Force clock and power re-program */
2501 host->pwr = 0;
2502 host->clock = 0;
2503 sdhci_do_set_ios(host, &host->mmc->ios);
2504
2505 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2506 if (host_flags & SDHCI_PV_ENABLED)
2507 sdhci_do_enable_preset_value(host, true);
2508
2509 /* Set the re-tuning expiration flag */
2510 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2511 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2512 host->flags |= SDHCI_NEEDS_RETUNING;
2513
2514 spin_lock_irqsave(&host->lock, flags);
2515
2516 host->runtime_suspended = false;
2517
2518 /* Enable SDIO IRQ */
2519 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2520 sdhci_enable_sdio_irq_nolock(host, true);
2521
2522 /* Enable Card Detection */
2523 sdhci_enable_card_detection(host);
2524
2525 spin_unlock_irqrestore(&host->lock, flags);
2526
2527 return ret;
2528}
2529EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2530
2531#endif
2532
d129bceb
PO		 2533/*****************************************************************************\
2534 * *
b8c86fc5 2535 * Device allocation/registration *
d129bceb
PO		 2536 * *
2537\*****************************************************************************/
2538
b8c86fc5
PO		 2539struct sdhci_host *sdhci_alloc_host(struct device *dev,
2540 size_t priv_size)
d129bceb 2541{
d129bceb
PO		 2542 struct mmc_host *mmc;
2543 struct sdhci_host *host;
2544
b8c86fc5 2545 WARN_ON(dev == NULL);
d129bceb 2546
b8c86fc5 2547 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2548 if (!mmc)
b8c86fc5 2549 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2550
2551 host = mmc_priv(mmc);
2552 host->mmc = mmc;
2553
b8c86fc5
PO		 2554 return host;
2555}
8a4da143 2556
b8c86fc5 2557EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2558
b8c86fc5
PO		 2559int sdhci_add_host(struct sdhci_host *host)
2560{
2561 struct mmc_host *mmc;
f2119df6
AN		 2562 u32 caps[2];
2563 u32 max_current_caps;
2564 unsigned int ocr_avail;
b8c86fc5 2565 int ret;
d129bceb 2566
b8c86fc5
PO		 2567 WARN_ON(host == NULL);
2568 if (host == NULL)
2569 return -EINVAL;
d129bceb 2570
b8c86fc5 2571 mmc = host->mmc;
d129bceb 2572
b8c86fc5
PO		 2573 if (debug_quirks)
2574 host->quirks = debug_quirks;
66fd8ad5
AH		 2575 if (debug_quirks2)
2576 host->quirks2 = debug_quirks2;
d129bceb 2577
d96649ed
PO		 2578 sdhci_reset(host, SDHCI_RESET_ALL);
2579
4e4141a5 2580 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2581 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2582 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2583 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2584 pr_err("%s: Unknown controller version (%d). "
b69c9058 2585 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2586 host->version);
4a965505
PO		 2587 }
2588
f2119df6 2589 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2590 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2591
f2119df6
AN		 2592 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2593 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2594
b8c86fc5 2595 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2596 host->flags |= SDHCI_USE_SDMA;
f2119df6 2597 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2598 DBG("Controller doesn't have SDMA capability\n");
67435274 2599 else
a13abc7b 2600 host->flags |= SDHCI_USE_SDMA;
d129bceb 2601
b8c86fc5 2602 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2603 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2604 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2605 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2606 }
2607
f2119df6
AN		 2608 if ((host->version >= SDHCI_SPEC_200) &&
2609 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2610 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2611
2612 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2613 (host->flags & SDHCI_USE_ADMA)) {
2614 DBG("Disabling ADMA as it is marked broken\n");
2615 host->flags &= ~SDHCI_USE_ADMA;
2616 }
2617
a13abc7b 2618 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2619 if (host->ops->enable_dma) {
2620 if (host->ops->enable_dma(host)) {
a3c76eb9 2621 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2622 "available. Falling back to PIO.\n",
2623 mmc_hostname(mmc));
a13abc7b
RR		 2624 host->flags &=
2625 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2626 }
d129bceb
PO		 2627 }
2628 }
2629
2134a922
PO		 2630 if (host->flags & SDHCI_USE_ADMA) {
2631 /*
2632 * We need to allocate descriptors for all sg entries
2633 * (128) and potentially one alignment transfer for
2634 * each of those entries.
2635 */
2636 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2637 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2638 if (!host->adma_desc || !host->align_buffer) {
2639 kfree(host->adma_desc);
2640 kfree(host->align_buffer);
a3c76eb9 2641 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2642 "buffers. Falling back to standard DMA.\n",
2643 mmc_hostname(mmc));
2644 host->flags &= ~SDHCI_USE_ADMA;
2645 }
2646 }
2647
7659150c
PO		 2648 /*
2649 * If we use DMA, then it's up to the caller to set the DMA
2650 * mask, but PIO does not need the hw shim so we set a new
2651 * mask here in that case.
2652 */
a13abc7b 2653 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2654 host->dma_mask = DMA_BIT_MASK(64);
2655 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2656 }
d129bceb 2657
c4687d5f 2658 if (host->version >= SDHCI_SPEC_300)
f2119df6 2659 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2660 >> SDHCI_CLOCK_BASE_SHIFT;
2661 else
f2119df6 2662 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2663 >> SDHCI_CLOCK_BASE_SHIFT;
2664
4240ff0a 2665 host->max_clk *= 1000000;
f27f47ef
AV		 2666 if (host->max_clk == 0 || host->quirks &
2667 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2668 if (!host->ops->get_max_clock) {
a3c76eb9 2669 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2670 "frequency.\n", mmc_hostname(mmc));
2671 return -ENODEV;
2672 }
2673 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2674 }
d129bceb 2675
c3ed3877
AN		 2676 /*
2677 * In case of Host Controller v3.00, find out whether clock
2678 * multiplier is supported.
2679 */
2680 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2681 SDHCI_CLOCK_MUL_SHIFT;
2682
2683 /*
2684 * In case the value in Clock Multiplier is 0, then programmable
2685 * clock mode is not supported, otherwise the actual clock
2686 * multiplier is one more than the value of Clock Multiplier
2687 * in the Capabilities Register.
2688 */
2689 if (host->clk_mul)
2690 host->clk_mul += 1;
2691
d129bceb
PO		 2692 /*
2693 * Set host parameters.
2694 */
2695 mmc->ops = &sdhci_ops;
c3ed3877 2696 mmc->f_max = host->max_clk;
ce5f036b 2697 if (host->ops->get_min_clock)
a9e58f25 2698 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2699 else if (host->version >= SDHCI_SPEC_300) {
2700 if (host->clk_mul) {
2701 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2702 mmc->f_max = host->max_clk * host->clk_mul;
2703 } else
2704 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2705 } else
0397526d 2706 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2707
272308ca
AS		 2708 host->timeout_clk =
2709 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2710 if (host->timeout_clk == 0) {
2711 if (host->ops->get_timeout_clock) {
2712 host->timeout_clk = host->ops->get_timeout_clock(host);
2713 } else if (!(host->quirks &
2714 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2715 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2716 "frequency.\n", mmc_hostname(mmc));
2717 return -ENODEV;
2718 }
2719 }
2720 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2721 host->timeout_clk *= 1000;
2722
2723 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2724 host->timeout_clk = mmc->f_max / 1000;
272308ca 2725
65be3fef 2726 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
58d1246d 2727
e89d456f
AW		 2728 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2729
2730 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2731 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2732
8edf6371 2733 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2734 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2735 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2736 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2737 host->flags |= SDHCI_AUTO_CMD23;
2738 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2739 } else {
2740 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2741 }
2742
15ec4461
PR		 2743 /*
2744 * A controller may support 8-bit width, but the board itself
2745 * might not have the pins brought out. Boards that support
2746 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2747 * their platform code before calling sdhci_add_host(), and we
2748 * won't assume 8-bit width for hosts without that CAP.
2749 */
5fe23c7f 2750 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2751 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2752
f2119df6 2753 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2754 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2755
176d1ed4
JC		 2756 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2757 mmc_card_is_removable(mmc))
68d1fb7e
AV		 2758 mmc->caps |= MMC_CAP_NEEDS_POLL;
2759
f2119df6
AN		 2760 /* UHS-I mode(s) supported by the host controller. */
2761 if (host->version >= SDHCI_SPEC_300)
2762 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2763
2764 /* SDR104 supports also implies SDR50 support */
2765 if (caps[1] & SDHCI_SUPPORT_SDR104)
2766 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2767 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2768 mmc->caps |= MMC_CAP_UHS_SDR50;
2769
2770 if (caps[1] & SDHCI_SUPPORT_DDR50)
2771 mmc->caps |= MMC_CAP_UHS_DDR50;
2772
069c9f14 2773 /* Does the host need tuning for SDR50? */
b513ea25
AN		 2774 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2775 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2776
069c9f14
G		 2777 /* Does the host need tuning for HS200? */
2778 if (mmc->caps2 & MMC_CAP2_HS200)
2779 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2780
d6d50a15
AN		 2781 /* Driver Type(s) (A, C, D) supported by the host */
2782 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2783 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2784 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2785 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2786 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2787 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2788
bec8726a
G		 2789 /*
2790 * If Power Off Notify capability is enabled by the host,
2791 * set notify to short power off notify timeout value.
2792 */
2793 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2794 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2795 else
2796 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2797
cf2b5eea
AN		 2798 /* Initial value for re-tuning timer count */
2799 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2800 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2801
2802 /*
2803 * In case Re-tuning Timer is not disabled, the actual value of
2804 * re-tuning timer will be 2 ^ (n - 1).
2805 */
2806 if (host->tuning_count)
2807 host->tuning_count = 1 << (host->tuning_count - 1);
2808
2809 /* Re-tuning mode supported by the Host Controller */
2810 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2811 SDHCI_RETUNING_MODE_SHIFT;
2812
8f230f45 2813 ocr_avail = 0;
f2119df6
AN		 2814 /*
2815 * According to SD Host Controller spec v3.00, if the Host System
2816 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2817 * the value is meaningful only if Voltage Support in the Capabilities
2818 * register is set. The actual current value is 4 times the register
2819 * value.
2820 */
2821 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2822
2823 if (caps[0] & SDHCI_CAN_VDD_330) {
2824 int max_current_330;
2825
8f230f45 2826 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6
AN		 2827
2828 max_current_330 = ((max_current_caps &
2829 SDHCI_MAX_CURRENT_330_MASK) >>
2830 SDHCI_MAX_CURRENT_330_SHIFT) *
2831 SDHCI_MAX_CURRENT_MULTIPLIER;
2832
2833 if (max_current_330 > 150)
2834 mmc->caps |= MMC_CAP_SET_XPC_330;
2835 }
2836 if (caps[0] & SDHCI_CAN_VDD_300) {
2837 int max_current_300;
2838
8f230f45 2839 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6
AN		 2840
2841 max_current_300 = ((max_current_caps &
2842 SDHCI_MAX_CURRENT_300_MASK) >>
2843 SDHCI_MAX_CURRENT_300_SHIFT) *
2844 SDHCI_MAX_CURRENT_MULTIPLIER;
2845
2846 if (max_current_300 > 150)
2847 mmc->caps |= MMC_CAP_SET_XPC_300;
2848 }
2849 if (caps[0] & SDHCI_CAN_VDD_180) {
2850 int max_current_180;
2851
8f230f45
TI		 2852 ocr_avail |= MMC_VDD_165_195;
2853
f2119df6
AN		 2854 max_current_180 = ((max_current_caps &
2855 SDHCI_MAX_CURRENT_180_MASK) >>
2856 SDHCI_MAX_CURRENT_180_SHIFT) *
2857 SDHCI_MAX_CURRENT_MULTIPLIER;
2858
2859 if (max_current_180 > 150)
2860 mmc->caps |= MMC_CAP_SET_XPC_180;
5371c927
AN		 2861
2862 /* Maximum current capabilities of the host at 1.8V */
2863 if (max_current_180 >= 800)
2864 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2865 else if (max_current_180 >= 600)
2866 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2867 else if (max_current_180 >= 400)
2868 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2869 else
2870 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
f2119df6
AN		 2871 }
2872
8f230f45
TI		 2873 mmc->ocr_avail = ocr_avail;
2874 mmc->ocr_avail_sdio = ocr_avail;
2875 if (host->ocr_avail_sdio)
2876 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2877 mmc->ocr_avail_sd = ocr_avail;
2878 if (host->ocr_avail_sd)
2879 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2880 else /* normal SD controllers don't support 1.8V */
2881 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2882 mmc->ocr_avail_mmc = ocr_avail;
2883 if (host->ocr_avail_mmc)
2884 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 2885
2886 if (mmc->ocr_avail == 0) {
a3c76eb9 2887 pr_err("%s: Hardware doesn't report any "
b69c9058 2888 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 2889 return -ENODEV;
146ad66e
PO		 2890 }
2891
d129bceb
PO		 2892 spin_lock_init(&host->lock);
2893
2894 /*
2134a922
PO		 2895 * Maximum number of segments. Depends on if the hardware
2896 * can do scatter/gather or not.
d129bceb 2897 */
2134a922 2898 if (host->flags & SDHCI_USE_ADMA)
a36274e0 2899 mmc->max_segs = 128;
a13abc7b 2900 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 2901 mmc->max_segs = 1;
2134a922 2902 else /* PIO */
a36274e0 2903 mmc->max_segs = 128;
d129bceb
PO		 2904
2905 /*
bab76961 2906 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 2907 * size (512KiB).
d129bceb 2908 */
55db890a 2909 mmc->max_req_size = 524288;
d129bceb
PO		 2910
2911 /*
2912 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 2913 * of bytes. When doing hardware scatter/gather, each entry cannot
2914 * be larger than 64 KiB though.
d129bceb 2915 */
30652aa3
OJ		 2916 if (host->flags & SDHCI_USE_ADMA) {
2917 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2918 mmc->max_seg_size = 65535;
2919 else
2920 mmc->max_seg_size = 65536;
2921 } else {
2134a922 2922 mmc->max_seg_size = mmc->max_req_size;
30652aa3 2923 }
d129bceb 2924
fe4a3c7a
PO		 2925 /*
2926 * Maximum block size. This varies from controller to controller and
2927 * is specified in the capabilities register.
2928 */
0633f654
AV		 2929 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2930 mmc->max_blk_size = 2;
2931 } else {
f2119df6 2932 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 2933 SDHCI_MAX_BLOCK_SHIFT;
2934 if (mmc->max_blk_size >= 3) {
a3c76eb9 2935 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 2936 "assuming 512 bytes\n", mmc_hostname(mmc));
2937 mmc->max_blk_size = 0;
2938 }
2939 }
2940
2941 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 2942
55db890a
PO		 2943 /*
2944 * Maximum block count.
2945 */
1388eefd 2946 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 2947
d129bceb
PO		 2948 /*
2949 * Init tasklets.
2950 */
2951 tasklet_init(&host->card_tasklet,
2952 sdhci_tasklet_card, (unsigned long)host);
2953 tasklet_init(&host->finish_tasklet,
2954 sdhci_tasklet_finish, (unsigned long)host);
2955
e4cad1b5 2956 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 2957
cf2b5eea 2958 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 2959 init_waitqueue_head(&host->buf_ready_int);
2960
cf2b5eea
AN		 2961 /* Initialize re-tuning timer */
2962 init_timer(&host->tuning_timer);
2963 host->tuning_timer.data = (unsigned long)host;
2964 host->tuning_timer.function = sdhci_tuning_timer;
2965 }
2966
dace1453 2967 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 2968 mmc_hostname(mmc), host);
d129bceb 2969 if (ret)
8ef1a143 2970 goto untasklet;
d129bceb 2971
9bea3c85
MS		 2972 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2973 if (IS_ERR(host->vmmc)) {
a3c76eb9 2974 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
9bea3c85 2975 host->vmmc = NULL;
9bea3c85
MS		 2976 }
2977
2f4cbb3d 2978 sdhci_init(host, 0);
d129bceb
PO		 2979
2980#ifdef CONFIG_MMC_DEBUG
2981 sdhci_dumpregs(host);
2982#endif
2983
f9134319 2984#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 2985 snprintf(host->led_name, sizeof(host->led_name),
2986 "%s::", mmc_hostname(mmc));
2987 host->led.name = host->led_name;
2f730fec
PO		 2988 host->led.brightness = LED_OFF;
2989 host->led.default_trigger = mmc_hostname(mmc);
2990 host->led.brightness_set = sdhci_led_control;
2991
b8c86fc5 2992 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 2993 if (ret)
2994 goto reset;
2995#endif
2996
5f25a66f
PO		 2997 mmiowb();
2998
d129bceb
PO		 2999 mmc_add_host(mmc);
3000
a3c76eb9 3001 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3002 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3003 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3004 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3005
7260cf5e
AV		 3006 sdhci_enable_card_detection(host);
3007
d129bceb
PO		 3008 return 0;
3009
f9134319 3010#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3011reset:
3012 sdhci_reset(host, SDHCI_RESET_ALL);
3013 free_irq(host->irq, host);
3014#endif
8ef1a143 3015untasklet:
d129bceb
PO		 3016 tasklet_kill(&host->card_tasklet);
3017 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3018
3019 return ret;
3020}
3021
b8c86fc5 3022EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3023
1e72859e 3024void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3025{
1e72859e
PO		 3026 unsigned long flags;
3027
3028 if (dead) {
3029 spin_lock_irqsave(&host->lock, flags);
3030
3031 host->flags |= SDHCI_DEVICE_DEAD;
3032
3033 if (host->mrq) {
a3c76eb9 3034 pr_err("%s: Controller removed during "
1e72859e
PO		 3035 " transfer!\n", mmc_hostname(host->mmc));
3036
3037 host->mrq->cmd->error = -ENOMEDIUM;
3038 tasklet_schedule(&host->finish_tasklet);
3039 }
3040
3041 spin_unlock_irqrestore(&host->lock, flags);
3042 }
3043
7260cf5e
AV		 3044 sdhci_disable_card_detection(host);
3045
b8c86fc5 3046 mmc_remove_host(host->mmc);
d129bceb 3047
f9134319 3048#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3049 led_classdev_unregister(&host->led);
3050#endif
3051
1e72859e
PO		 3052 if (!dead)
3053 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 3054
3055 free_irq(host->irq, host);
3056
3057 del_timer_sync(&host->timer);
cf2b5eea
AN		 3058 if (host->version >= SDHCI_SPEC_300)
3059 del_timer_sync(&host->tuning_timer);
d129bceb
PO		 3060
3061 tasklet_kill(&host->card_tasklet);
3062 tasklet_kill(&host->finish_tasklet);
2134a922 3063
ceb6143b 3064 if (host->vmmc)
9bea3c85 3065 regulator_put(host->vmmc);
9bea3c85 3066
2134a922
PO		 3067 kfree(host->adma_desc);
3068 kfree(host->align_buffer);
3069
3070 host->adma_desc = NULL;
3071 host->align_buffer = NULL;
d129bceb
PO		 3072}
3073
b8c86fc5 3074EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3075
b8c86fc5 3076void sdhci_free_host(struct sdhci_host *host)
d129bceb 3077{
b8c86fc5 3078 mmc_free_host(host->mmc);
d129bceb
PO		 3079}
3080
b8c86fc5 3081EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3082
3083/*****************************************************************************\
3084 * *
3085 * Driver init/exit *
3086 * *
3087\*****************************************************************************/
3088
3089static int __init sdhci_drv_init(void)
3090{
a3c76eb9 3091 pr_info(DRIVER_NAME
52fbf9c9 3092 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3093 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3094
b8c86fc5 3095 return 0;
d129bceb
PO		 3096}
3097
3098static void __exit sdhci_drv_exit(void)
3099{
d129bceb
PO		 3100}
3101
3102module_init(sdhci_drv_init);
3103module_exit(sdhci_drv_exit);
3104
df673b22 3105module_param(debug_quirks, uint, 0444);
66fd8ad5 3106module_param(debug_quirks2, uint, 0444);
67435274 3107
32710e8f 3108MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3109MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3110MODULE_LICENSE("GPL");
67435274 3111
df673b22 3112MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3113MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux 6.x block layer and io_uring tree(s)