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mmc: sdhci: convert to new SDIO IRQ handling
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
d129bceb 52static void sdhci_finish_command(struct sdhci_host *);
069c9f14 53static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 54static void sdhci_tuning_timer(unsigned long data);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 56
66fd8ad5
AH		 57#ifdef CONFIG_PM_RUNTIME
58static int sdhci_runtime_pm_get(struct sdhci_host *host);
59static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 60static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
61static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 62#else
63static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
64{
65 return 0;
66}
67static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
68{
69 return 0;
70}
f0710a55
AH		 71static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
72{
73}
74static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
75{
76}
66fd8ad5
AH		 77#endif
78
d129bceb
PO		 79static void sdhci_dumpregs(struct sdhci_host *host)
80{
a3c76eb9 81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 82 mmc_hostname(host->mmc));
d129bceb 83
a3c76eb9 84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 85 sdhci_readl(host, SDHCI_DMA_ADDRESS),
86 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readw(host, SDHCI_BLOCK_SIZE),
89 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readl(host, SDHCI_ARGUMENT),
92 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readl(host, SDHCI_PRESENT_STATE),
95 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readb(host, SDHCI_POWER_CONTROL),
98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
101 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
104 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 106 sdhci_readl(host, SDHCI_INT_ENABLE),
107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 109 sdhci_readw(host, SDHCI_ACMD12_ERR),
110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 112 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 113 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 115 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 116 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 118 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 119
be3f4ae0 120 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 121 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 122 readl(host->ioaddr + SDHCI_ADMA_ERROR),
123 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
124
a3c76eb9 125 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 126}
127
128/*****************************************************************************\
129 * *
130 * Low level functions *
131 * *
132\*****************************************************************************/
133
7260cf5e
AV		 134static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
135{
136 u32 ier;
137
138 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
139 ier &= ~clear;
140 ier |= set;
141 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
142 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
143}
144
145static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
146{
147 sdhci_clear_set_irqs(host, 0, irqs);
148}
149
150static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
151{
152 sdhci_clear_set_irqs(host, irqs, 0);
153}
154
155static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
156{
d25928d1 157 u32 present, irqs;
7260cf5e 158
c79396c1 159 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 160 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 161 return;
162
d25928d1
SG		 163 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
164 SDHCI_CARD_PRESENT;
165 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
166
7260cf5e
AV		 167 if (enable)
168 sdhci_unmask_irqs(host, irqs);
169 else
170 sdhci_mask_irqs(host, irqs);
171}
172
173static void sdhci_enable_card_detection(struct sdhci_host *host)
174{
175 sdhci_set_card_detection(host, true);
176}
177
178static void sdhci_disable_card_detection(struct sdhci_host *host)
179{
180 sdhci_set_card_detection(host, false);
181}
182
d129bceb
PO		 183static void sdhci_reset(struct sdhci_host *host, u8 mask)
184{
e16514d8 185 unsigned long timeout;
063a9dbb 186 u32 uninitialized_var(ier);
e16514d8 187
b8c86fc5 188 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 189 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 190 SDHCI_CARD_PRESENT))
191 return;
192 }
193
063a9dbb
AV		 194 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
195 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
196
393c1a34
PR		 197 if (host->ops->platform_reset_enter)
198 host->ops->platform_reset_enter(host, mask);
199
4e4141a5 200 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 201
f0710a55 202 if (mask & SDHCI_RESET_ALL) {
d129bceb 203 host->clock = 0;
f0710a55
AH		 204 /* Reset-all turns off SD Bus Power */
205 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
206 sdhci_runtime_pm_bus_off(host);
207 }
d129bceb 208
e16514d8
PO		 209 /* Wait max 100 ms */
210 timeout = 100;
211
212 /* hw clears the bit when it's done */
4e4141a5 213 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 214 if (timeout == 0) {
a3c76eb9 215 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 216 mmc_hostname(host->mmc), (int)mask);
217 sdhci_dumpregs(host);
218 return;
219 }
220 timeout--;
221 mdelay(1);
d129bceb 222 }
063a9dbb 223
393c1a34
PR		 224 if (host->ops->platform_reset_exit)
225 host->ops->platform_reset_exit(host, mask);
226
063a9dbb
AV		 227 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
228 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
3abc1e80
SX		 229
230 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
231 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
232 host->ops->enable_dma(host);
233 }
d129bceb
PO		 234}
235
2f4cbb3d
NP		 236static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
237
238static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 239{
2f4cbb3d
NP		 240 if (soft)
241 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
242 else
243 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 244
7260cf5e
AV		 245 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
246 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 247 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
248 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 249 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 250
251 if (soft) {
252 /* force clock reconfiguration */
253 host->clock = 0;
254 sdhci_set_ios(host->mmc, &host->mmc->ios);
255 }
7260cf5e 256}
d129bceb 257
7260cf5e
AV		 258static void sdhci_reinit(struct sdhci_host *host)
259{
2f4cbb3d 260 sdhci_init(host, 0);
b67c6b41
AL		 261 /*
262 * Retuning stuffs are affected by different cards inserted and only
263 * applicable to UHS-I cards. So reset these fields to their initial
264 * value when card is removed.
265 */
973905fe
AL		 266 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
267 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
268
b67c6b41
AL		 269 del_timer_sync(&host->tuning_timer);
270 host->flags &= ~SDHCI_NEEDS_RETUNING;
271 host->mmc->max_blk_count =
272 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
273 }
7260cf5e 274 sdhci_enable_card_detection(host);
d129bceb
PO		 275}
276
277static void sdhci_activate_led(struct sdhci_host *host)
278{
279 u8 ctrl;
280
4e4141a5 281 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 282 ctrl |= SDHCI_CTRL_LED;
4e4141a5 283 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 284}
285
286static void sdhci_deactivate_led(struct sdhci_host *host)
287{
288 u8 ctrl;
289
4e4141a5 290 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 291 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 292 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 293}
294
f9134319 295#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 296static void sdhci_led_control(struct led_classdev *led,
297 enum led_brightness brightness)
298{
299 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
300 unsigned long flags;
301
302 spin_lock_irqsave(&host->lock, flags);
303
66fd8ad5
AH		 304 if (host->runtime_suspended)
305 goto out;
306
2f730fec
PO		 307 if (brightness == LED_OFF)
308 sdhci_deactivate_led(host);
309 else
310 sdhci_activate_led(host);
66fd8ad5 311out:
2f730fec
PO		 312 spin_unlock_irqrestore(&host->lock, flags);
313}
314#endif
315
d129bceb
PO		 316/*****************************************************************************\
317 * *
318 * Core functions *
319 * *
320\*****************************************************************************/
321
a406f5a3 322static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 323{
7659150c
PO		 324 unsigned long flags;
325 size_t blksize, len, chunk;
7244b85b 326 u32 uninitialized_var(scratch);
7659150c 327 u8 *buf;
d129bceb 328
a406f5a3 329 DBG("PIO reading\n");
d129bceb 330
a406f5a3 331 blksize = host->data->blksz;
7659150c 332 chunk = 0;
d129bceb 333
7659150c 334 local_irq_save(flags);
d129bceb 335
a406f5a3 336 while (blksize) {
7659150c
PO		 337 if (!sg_miter_next(&host->sg_miter))
338 BUG();
d129bceb 339
7659150c 340 len = min(host->sg_miter.length, blksize);
d129bceb 341
7659150c
PO		 342 blksize -= len;
343 host->sg_miter.consumed = len;
14d836e7 344
7659150c 345 buf = host->sg_miter.addr;
d129bceb 346
7659150c
PO		 347 while (len) {
348 if (chunk == 0) {
4e4141a5 349 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 350 chunk = 4;
a406f5a3 351 }
7659150c
PO		 352
353 *buf = scratch & 0xFF;
354
355 buf++;
356 scratch >>= 8;
357 chunk--;
358 len--;
d129bceb 359 }
a406f5a3 360 }
7659150c
PO		 361
362 sg_miter_stop(&host->sg_miter);
363
364 local_irq_restore(flags);
a406f5a3 365}
d129bceb 366
a406f5a3
PO		 367static void sdhci_write_block_pio(struct sdhci_host *host)
368{
7659150c
PO		 369 unsigned long flags;
370 size_t blksize, len, chunk;
371 u32 scratch;
372 u8 *buf;
d129bceb 373
a406f5a3
PO		 374 DBG("PIO writing\n");
375
376 blksize = host->data->blksz;
7659150c
PO		 377 chunk = 0;
378 scratch = 0;
d129bceb 379
7659150c 380 local_irq_save(flags);
d129bceb 381
a406f5a3 382 while (blksize) {
7659150c
PO		 383 if (!sg_miter_next(&host->sg_miter))
384 BUG();
a406f5a3 385
7659150c
PO		 386 len = min(host->sg_miter.length, blksize);
387
388 blksize -= len;
389 host->sg_miter.consumed = len;
390
391 buf = host->sg_miter.addr;
d129bceb 392
7659150c
PO		 393 while (len) {
394 scratch |= (u32)*buf << (chunk * 8);
395
396 buf++;
397 chunk++;
398 len--;
399
400 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 401 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 402 chunk = 0;
403 scratch = 0;
d129bceb 404 }
d129bceb
PO		 405 }
406 }
7659150c
PO		 407
408 sg_miter_stop(&host->sg_miter);
409
410 local_irq_restore(flags);
a406f5a3
PO		 411}
412
413static void sdhci_transfer_pio(struct sdhci_host *host)
414{
415 u32 mask;
416
417 BUG_ON(!host->data);
418
7659150c 419 if (host->blocks == 0)
a406f5a3
PO		 420 return;
421
422 if (host->data->flags & MMC_DATA_READ)
423 mask = SDHCI_DATA_AVAILABLE;
424 else
425 mask = SDHCI_SPACE_AVAILABLE;
426
4a3cba32
PO		 427 /*
428 * Some controllers (JMicron JMB38x) mess up the buffer bits
429 * for transfers < 4 bytes. As long as it is just one block,
430 * we can ignore the bits.
431 */
432 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
433 (host->data->blocks == 1))
434 mask = ~0;
435
4e4141a5 436 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 437 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
438 udelay(100);
439
a406f5a3
PO		 440 if (host->data->flags & MMC_DATA_READ)
441 sdhci_read_block_pio(host);
442 else
443 sdhci_write_block_pio(host);
d129bceb 444
7659150c
PO		 445 host->blocks--;
446 if (host->blocks == 0)
a406f5a3 447 break;
a406f5a3 448 }
d129bceb 449
a406f5a3 450 DBG("PIO transfer complete.\n");
d129bceb
PO		 451}
452
2134a922
PO		 453static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
454{
455 local_irq_save(*flags);
482fce99 456 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 457}
458
459static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
460{
482fce99 461 kunmap_atomic(buffer);
2134a922
PO		 462 local_irq_restore(*flags);
463}
464
118cd17d
BD		 465static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
466{
9e506f35
BD		 467 __le32 *dataddr = (__le32 __force *)(desc + 4);
468 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 469
9e506f35
BD		 470 /* SDHCI specification says ADMA descriptors should be 4 byte
471 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 472
9e506f35
BD		 473 cmdlen[0] = cpu_to_le16(cmd);
474 cmdlen[1] = cpu_to_le16(len);
475
476 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 477}
478
8f1934ce 479static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 480 struct mmc_data *data)
481{
482 int direction;
483
484 u8 *desc;
485 u8 *align;
486 dma_addr_t addr;
487 dma_addr_t align_addr;
488 int len, offset;
489
490 struct scatterlist *sg;
491 int i;
492 char *buffer;
493 unsigned long flags;
494
495 /*
496 * The spec does not specify endianness of descriptor table.
497 * We currently guess that it is LE.
498 */
499
500 if (data->flags & MMC_DATA_READ)
501 direction = DMA_FROM_DEVICE;
502 else
503 direction = DMA_TO_DEVICE;
504
505 /*
506 * The ADMA descriptor table is mapped further down as we
507 * need to fill it with data first.
508 */
509
510 host->align_addr = dma_map_single(mmc_dev(host->mmc),
511 host->align_buffer, 128 * 4, direction);
8d8bb39b 512 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 513 goto fail;
2134a922
PO		 514 BUG_ON(host->align_addr & 0x3);
515
516 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
517 data->sg, data->sg_len, direction);
8f1934ce
PO		 518 if (host->sg_count == 0)
519 goto unmap_align;
2134a922
PO		 520
521 desc = host->adma_desc;
522 align = host->align_buffer;
523
524 align_addr = host->align_addr;
525
526 for_each_sg(data->sg, sg, host->sg_count, i) {
527 addr = sg_dma_address(sg);
528 len = sg_dma_len(sg);
529
530 /*
531 * The SDHCI specification states that ADMA
532 * addresses must be 32-bit aligned. If they
533 * aren't, then we use a bounce buffer for
534 * the (up to three) bytes that screw up the
535 * alignment.
536 */
537 offset = (4 - (addr & 0x3)) & 0x3;
538 if (offset) {
539 if (data->flags & MMC_DATA_WRITE) {
540 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 541 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 542 memcpy(align, buffer, offset);
543 sdhci_kunmap_atomic(buffer, &flags);
544 }
545
118cd17d
BD		 546 /* tran, valid */
547 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 548
549 BUG_ON(offset > 65536);
550
2134a922
PO		 551 align += 4;
552 align_addr += 4;
553
554 desc += 8;
555
556 addr += offset;
557 len -= offset;
558 }
559
2134a922
PO		 560 BUG_ON(len > 65536);
561
118cd17d
BD		 562 /* tran, valid */
563 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 564 desc += 8;
565
566 /*
567 * If this triggers then we have a calculation bug
568 * somewhere. :/
569 */
570 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
571 }
572
70764a90
TA		 573 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
574 /*
575 * Mark the last descriptor as the terminating descriptor
576 */
577 if (desc != host->adma_desc) {
578 desc -= 8;
579 desc[0] |= 0x2; /* end */
580 }
581 } else {
582 /*
583 * Add a terminating entry.
584 */
2134a922 585
70764a90
TA		 586 /* nop, end, valid */
587 sdhci_set_adma_desc(desc, 0, 0, 0x3);
588 }
2134a922
PO		 589
590 /*
591 * Resync align buffer as we might have changed it.
592 */
593 if (data->flags & MMC_DATA_WRITE) {
594 dma_sync_single_for_device(mmc_dev(host->mmc),
595 host->align_addr, 128 * 4, direction);
596 }
597
598 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
599 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 600 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 601 goto unmap_entries;
2134a922 602 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 603
604 return 0;
605
606unmap_entries:
607 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
608 data->sg_len, direction);
609unmap_align:
610 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
611 128 * 4, direction);
612fail:
613 return -EINVAL;
2134a922
PO		 614}
615
616static void sdhci_adma_table_post(struct sdhci_host *host,
617 struct mmc_data *data)
618{
619 int direction;
620
621 struct scatterlist *sg;
622 int i, size;
623 u8 *align;
624 char *buffer;
625 unsigned long flags;
626
627 if (data->flags & MMC_DATA_READ)
628 direction = DMA_FROM_DEVICE;
629 else
630 direction = DMA_TO_DEVICE;
631
632 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
633 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
634
635 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
636 128 * 4, direction);
637
638 if (data->flags & MMC_DATA_READ) {
639 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
640 data->sg_len, direction);
641
642 align = host->align_buffer;
643
644 for_each_sg(data->sg, sg, host->sg_count, i) {
645 if (sg_dma_address(sg) & 0x3) {
646 size = 4 - (sg_dma_address(sg) & 0x3);
647
648 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 649 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 650 memcpy(buffer, align, size);
651 sdhci_kunmap_atomic(buffer, &flags);
652
653 align += 4;
654 }
655 }
656 }
657
658 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
659 data->sg_len, direction);
660}
661
a3c7778f 662static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 663{
1c8cde92 664 u8 count;
a3c7778f 665 struct mmc_data *data = cmd->data;
1c8cde92 666 unsigned target_timeout, current_timeout;
d129bceb 667
ee53ab5d
PO		 668 /*
669 * If the host controller provides us with an incorrect timeout
670 * value, just skip the check and use 0xE. The hardware may take
671 * longer to time out, but that's much better than having a too-short
672 * timeout value.
673 */
11a2f1b7 674 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 675 return 0xE;
e538fbe8 676
a3c7778f 677 /* Unspecified timeout, assume max */
1d4d7744 678 if (!data && !cmd->busy_timeout)
a3c7778f 679 return 0xE;
d129bceb 680
a3c7778f
AW		 681 /* timeout in us */
682 if (!data)
1d4d7744 683 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 684 else {
685 target_timeout = data->timeout_ns / 1000;
686 if (host->clock)
687 target_timeout += data->timeout_clks / host->clock;
688 }
81b39802 689
1c8cde92
PO		 690 /*
691 * Figure out needed cycles.
692 * We do this in steps in order to fit inside a 32 bit int.
693 * The first step is the minimum timeout, which will have a
694 * minimum resolution of 6 bits:
695 * (1) 2^13*1000 > 2^22,
696 * (2) host->timeout_clk < 2^16
697 * =>
698 * (1) / (2) > 2^6
699 */
700 count = 0;
701 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
702 while (current_timeout < target_timeout) {
703 count++;
704 current_timeout <<= 1;
705 if (count >= 0xF)
706 break;
707 }
708
709 if (count >= 0xF) {
09eeff52
CB		 710 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
711 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 712 count = 0xE;
713 }
714
ee53ab5d
PO		 715 return count;
716}
717
6aa943ab
AV		 718static void sdhci_set_transfer_irqs(struct sdhci_host *host)
719{
720 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
721 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
722
723 if (host->flags & SDHCI_REQ_USE_DMA)
724 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
725 else
726 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
727}
728
a3c7778f 729static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 730{
731 u8 count;
2134a922 732 u8 ctrl;
a3c7778f 733 struct mmc_data *data = cmd->data;
8f1934ce 734 int ret;
ee53ab5d
PO		 735
736 WARN_ON(host->data);
737
a3c7778f
AW		 738 if (data || (cmd->flags & MMC_RSP_BUSY)) {
739 count = sdhci_calc_timeout(host, cmd);
740 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
741 }
742
743 if (!data)
ee53ab5d
PO		 744 return;
745
746 /* Sanity checks */
747 BUG_ON(data->blksz * data->blocks > 524288);
748 BUG_ON(data->blksz > host->mmc->max_blk_size);
749 BUG_ON(data->blocks > 65535);
750
751 host->data = data;
752 host->data_early = 0;
f6a03cbf 753 host->data->bytes_xfered = 0;
ee53ab5d 754
a13abc7b 755 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 756 host->flags |= SDHCI_REQ_USE_DMA;
757
2134a922
PO		 758 /*
759 * FIXME: This doesn't account for merging when mapping the
760 * scatterlist.
761 */
762 if (host->flags & SDHCI_REQ_USE_DMA) {
763 int broken, i;
764 struct scatterlist *sg;
765
766 broken = 0;
767 if (host->flags & SDHCI_USE_ADMA) {
768 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
769 broken = 1;
770 } else {
771 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
772 broken = 1;
773 }
774
775 if (unlikely(broken)) {
776 for_each_sg(data->sg, sg, data->sg_len, i) {
777 if (sg->length & 0x3) {
778 DBG("Reverting to PIO because of "
779 "transfer size (%d)\n",
780 sg->length);
781 host->flags &= ~SDHCI_REQ_USE_DMA;
782 break;
783 }
784 }
785 }
c9fddbc4
PO		 786 }
787
788 /*
789 * The assumption here being that alignment is the same after
790 * translation to device address space.
791 */
2134a922
PO		 792 if (host->flags & SDHCI_REQ_USE_DMA) {
793 int broken, i;
794 struct scatterlist *sg;
795
796 broken = 0;
797 if (host->flags & SDHCI_USE_ADMA) {
798 /*
799 * As we use 3 byte chunks to work around
800 * alignment problems, we need to check this
801 * quirk.
802 */
803 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
804 broken = 1;
805 } else {
806 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
807 broken = 1;
808 }
809
810 if (unlikely(broken)) {
811 for_each_sg(data->sg, sg, data->sg_len, i) {
812 if (sg->offset & 0x3) {
813 DBG("Reverting to PIO because of "
814 "bad alignment\n");
815 host->flags &= ~SDHCI_REQ_USE_DMA;
816 break;
817 }
818 }
819 }
820 }
821
8f1934ce
PO		 822 if (host->flags & SDHCI_REQ_USE_DMA) {
823 if (host->flags & SDHCI_USE_ADMA) {
824 ret = sdhci_adma_table_pre(host, data);
825 if (ret) {
826 /*
827 * This only happens when someone fed
828 * us an invalid request.
829 */
830 WARN_ON(1);
ebd6d357 831 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 832 } else {
4e4141a5
AV		 833 sdhci_writel(host, host->adma_addr,
834 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 835 }
836 } else {
c8b3e02e 837 int sg_cnt;
8f1934ce 838
c8b3e02e 839 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 840 data->sg, data->sg_len,
841 (data->flags & MMC_DATA_READ) ?
842 DMA_FROM_DEVICE :
843 DMA_TO_DEVICE);
c8b3e02e 844 if (sg_cnt == 0) {
8f1934ce
PO		 845 /*
846 * This only happens when someone fed
847 * us an invalid request.
848 */
849 WARN_ON(1);
ebd6d357 850 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 851 } else {
719a61b4 852 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 853 sdhci_writel(host, sg_dma_address(data->sg),
854 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 855 }
856 }
857 }
858
2134a922
PO		 859 /*
860 * Always adjust the DMA selection as some controllers
861 * (e.g. JMicron) can't do PIO properly when the selection
862 * is ADMA.
863 */
864 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 865 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 866 ctrl &= ~SDHCI_CTRL_DMA_MASK;
867 if ((host->flags & SDHCI_REQ_USE_DMA) &&
868 (host->flags & SDHCI_USE_ADMA))
869 ctrl |= SDHCI_CTRL_ADMA32;
870 else
871 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 872 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 873 }
874
8f1934ce 875 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 876 int flags;
877
878 flags = SG_MITER_ATOMIC;
879 if (host->data->flags & MMC_DATA_READ)
880 flags |= SG_MITER_TO_SG;
881 else
882 flags |= SG_MITER_FROM_SG;
883 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 884 host->blocks = data->blocks;
d129bceb 885 }
c7fa9963 886
6aa943ab
AV		 887 sdhci_set_transfer_irqs(host);
888
f6a03cbf
MV		 889 /* Set the DMA boundary value and block size */
890 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
891 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 892 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 893}
894
895static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 896 struct mmc_command *cmd)
c7fa9963
PO		 897{
898 u16 mode;
e89d456f 899 struct mmc_data *data = cmd->data;
c7fa9963 900
2b558c13
DA		 901 if (data == NULL) {
902 /* clear Auto CMD settings for no data CMDs */
903 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
904 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
905 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
c7fa9963 906 return;
2b558c13 907 }
c7fa9963 908
e538fbe8
PO		 909 WARN_ON(!host->data);
910
c7fa9963 911 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 912 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
913 mode |= SDHCI_TRNS_MULTI;
914 /*
915 * If we are sending CMD23, CMD12 never gets sent
916 * on successful completion (so no Auto-CMD12).
917 */
918 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
919 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 920 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
921 mode |= SDHCI_TRNS_AUTO_CMD23;
922 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
923 }
c4512f79 924 }
8edf6371 925
c7fa9963
PO		 926 if (data->flags & MMC_DATA_READ)
927 mode |= SDHCI_TRNS_READ;
c9fddbc4 928 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 929 mode |= SDHCI_TRNS_DMA;
930
4e4141a5 931 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 932}
933
934static void sdhci_finish_data(struct sdhci_host *host)
935{
936 struct mmc_data *data;
d129bceb
PO		 937
938 BUG_ON(!host->data);
939
940 data = host->data;
941 host->data = NULL;
942
c9fddbc4 943 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 944 if (host->flags & SDHCI_USE_ADMA)
945 sdhci_adma_table_post(host, data);
946 else {
947 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
948 data->sg_len, (data->flags & MMC_DATA_READ) ?
949 DMA_FROM_DEVICE : DMA_TO_DEVICE);
950 }
d129bceb
PO		 951 }
952
953 /*
c9b74c5b
PO		 954 * The specification states that the block count register must
955 * be updated, but it does not specify at what point in the
956 * data flow. That makes the register entirely useless to read
957 * back so we have to assume that nothing made it to the card
958 * in the event of an error.
d129bceb 959 */
c9b74c5b
PO		 960 if (data->error)
961 data->bytes_xfered = 0;
d129bceb 962 else
c9b74c5b 963 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 964
e89d456f
AW		 965 /*
966 * Need to send CMD12 if -
967 * a) open-ended multiblock transfer (no CMD23)
968 * b) error in multiblock transfer
969 */
970 if (data->stop &&
971 (data->error ||
972 !host->mrq->sbc)) {
973
d129bceb
PO		 974 /*
975 * The controller needs a reset of internal state machines
976 * upon error conditions.
977 */
17b0429d 978 if (data->error) {
d129bceb
PO		 979 sdhci_reset(host, SDHCI_RESET_CMD);
980 sdhci_reset(host, SDHCI_RESET_DATA);
981 }
982
983 sdhci_send_command(host, data->stop);
984 } else
985 tasklet_schedule(&host->finish_tasklet);
986}
987
c0e55129 988void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 989{
990 int flags;
fd2208d7 991 u32 mask;
7cb2c76f 992 unsigned long timeout;
d129bceb
PO		 993
994 WARN_ON(host->cmd);
995
d129bceb 996 /* Wait max 10 ms */
7cb2c76f 997 timeout = 10;
fd2208d7
PO		 998
999 mask = SDHCI_CMD_INHIBIT;
1000 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1001 mask |= SDHCI_DATA_INHIBIT;
1002
1003 /* We shouldn't wait for data inihibit for stop commands, even
1004 though they might use busy signaling */
1005 if (host->mrq->data && (cmd == host->mrq->data->stop))
1006 mask &= ~SDHCI_DATA_INHIBIT;
1007
4e4141a5 1008 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1009 if (timeout == 0) {
a3c76eb9 1010 pr_err("%s: Controller never released "
acf1da45 1011 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 1012 sdhci_dumpregs(host);
17b0429d 1013 cmd->error = -EIO;
d129bceb
PO		 1014 tasklet_schedule(&host->finish_tasklet);
1015 return;
1016 }
7cb2c76f
PO		 1017 timeout--;
1018 mdelay(1);
1019 }
d129bceb 1020
3e1a6892 1021 timeout = jiffies;
1d4d7744
UH		 1022 if (!cmd->data && cmd->busy_timeout > 9000)
1023 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1024 else
1025 timeout += 10 * HZ;
1026 mod_timer(&host->timer, timeout);
d129bceb
PO		 1027
1028 host->cmd = cmd;
1029
a3c7778f 1030 sdhci_prepare_data(host, cmd);
d129bceb 1031
4e4141a5 1032 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1033
e89d456f 1034 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1035
d129bceb 1036 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1037 pr_err("%s: Unsupported response type!\n",
d129bceb 1038 mmc_hostname(host->mmc));
17b0429d 1039 cmd->error = -EINVAL;
d129bceb
PO		 1040 tasklet_schedule(&host->finish_tasklet);
1041 return;
1042 }
1043
1044 if (!(cmd->flags & MMC_RSP_PRESENT))
1045 flags = SDHCI_CMD_RESP_NONE;
1046 else if (cmd->flags & MMC_RSP_136)
1047 flags = SDHCI_CMD_RESP_LONG;
1048 else if (cmd->flags & MMC_RSP_BUSY)
1049 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1050 else
1051 flags = SDHCI_CMD_RESP_SHORT;
1052
1053 if (cmd->flags & MMC_RSP_CRC)
1054 flags |= SDHCI_CMD_CRC;
1055 if (cmd->flags & MMC_RSP_OPCODE)
1056 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1057
1058 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1059 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1060 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1061 flags |= SDHCI_CMD_DATA;
1062
4e4141a5 1063 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1064}
c0e55129 1065EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1066
1067static void sdhci_finish_command(struct sdhci_host *host)
1068{
1069 int i;
1070
1071 BUG_ON(host->cmd == NULL);
1072
1073 if (host->cmd->flags & MMC_RSP_PRESENT) {
1074 if (host->cmd->flags & MMC_RSP_136) {
1075 /* CRC is stripped so we need to do some shifting. */
1076 for (i = 0;i < 4;i++) {
4e4141a5 1077 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1078 SDHCI_RESPONSE + (3-i)*4) << 8;
1079 if (i != 3)
1080 host->cmd->resp[i] |=
4e4141a5 1081 sdhci_readb(host,
d129bceb
PO		 1082 SDHCI_RESPONSE + (3-i)*4-1);
1083 }
1084 } else {
4e4141a5 1085 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1086 }
1087 }
1088
17b0429d 1089 host->cmd->error = 0;
d129bceb 1090
e89d456f
AW		 1091 /* Finished CMD23, now send actual command. */
1092 if (host->cmd == host->mrq->sbc) {
1093 host->cmd = NULL;
1094 sdhci_send_command(host, host->mrq->cmd);
1095 } else {
e538fbe8 1096
e89d456f
AW		 1097 /* Processed actual command. */
1098 if (host->data && host->data_early)
1099 sdhci_finish_data(host);
d129bceb 1100
e89d456f
AW		 1101 if (!host->cmd->data)
1102 tasklet_schedule(&host->finish_tasklet);
1103
1104 host->cmd = NULL;
1105 }
d129bceb
PO		 1106}
1107
52983382
KL		 1108static u16 sdhci_get_preset_value(struct sdhci_host *host)
1109{
1110 u16 ctrl, preset = 0;
1111
1112 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1113
1114 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1115 case SDHCI_CTRL_UHS_SDR12:
1116 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1117 break;
1118 case SDHCI_CTRL_UHS_SDR25:
1119 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1120 break;
1121 case SDHCI_CTRL_UHS_SDR50:
1122 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1123 break;
1124 case SDHCI_CTRL_UHS_SDR104:
1125 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1126 break;
1127 case SDHCI_CTRL_UHS_DDR50:
1128 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1129 break;
1130 default:
1131 pr_warn("%s: Invalid UHS-I mode selected\n",
1132 mmc_hostname(host->mmc));
1133 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1134 break;
1135 }
1136 return preset;
1137}
1138
d129bceb
PO		 1139static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1140{
c3ed3877 1141 int div = 0; /* Initialized for compiler warning */
df16219f 1142 int real_div = div, clk_mul = 1;
c3ed3877 1143 u16 clk = 0;
7cb2c76f 1144 unsigned long timeout;
d129bceb 1145
30832ab5 1146 if (clock && clock == host->clock)
d129bceb
PO		 1147 return;
1148
df16219f
GC		 1149 host->mmc->actual_clock = 0;
1150
8114634c
AV		 1151 if (host->ops->set_clock) {
1152 host->ops->set_clock(host, clock);
1153 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1154 return;
1155 }
1156
4e4141a5 1157 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1158
1159 if (clock == 0)
1160 goto out;
1161
85105c53 1162 if (host->version >= SDHCI_SPEC_300) {
52983382
KL		 1163 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1164 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1165 u16 pre_val;
1166
1167 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1168 pre_val = sdhci_get_preset_value(host);
1169 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1170 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1171 if (host->clk_mul &&
1172 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1173 clk = SDHCI_PROG_CLOCK_MODE;
1174 real_div = div + 1;
1175 clk_mul = host->clk_mul;
1176 } else {
1177 real_div = max_t(int, 1, div << 1);
1178 }
1179 goto clock_set;
1180 }
1181
c3ed3877
AN		 1182 /*
1183 * Check if the Host Controller supports Programmable Clock
1184 * Mode.
1185 */
1186 if (host->clk_mul) {
52983382
KL		 1187 for (div = 1; div <= 1024; div++) {
1188 if ((host->max_clk * host->clk_mul / div)
1189 <= clock)
1190 break;
1191 }
c3ed3877 1192 /*
52983382
KL		 1193 * Set Programmable Clock Mode in the Clock
1194 * Control register.
c3ed3877 1195 */
52983382
KL		 1196 clk = SDHCI_PROG_CLOCK_MODE;
1197 real_div = div;
1198 clk_mul = host->clk_mul;
1199 div--;
c3ed3877
AN		 1200 } else {
1201 /* Version 3.00 divisors must be a multiple of 2. */
1202 if (host->max_clk <= clock)
1203 div = 1;
1204 else {
1205 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1206 div += 2) {
1207 if ((host->max_clk / div) <= clock)
1208 break;
1209 }
85105c53 1210 }
df16219f 1211 real_div = div;
c3ed3877 1212 div >>= 1;
85105c53
ZG		 1213 }
1214 } else {
1215 /* Version 2.00 divisors must be a power of 2. */
0397526d 1216 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1217 if ((host->max_clk / div) <= clock)
1218 break;
1219 }
df16219f 1220 real_div = div;
c3ed3877 1221 div >>= 1;
d129bceb 1222 }
d129bceb 1223
52983382 1224clock_set:
df16219f
GC		 1225 if (real_div)
1226 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1227
c3ed3877 1228 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1229 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1230 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1231 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1232 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1233
27f6cb16
CB		 1234 /* Wait max 20 ms */
1235 timeout = 20;
4e4141a5 1236 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1237 & SDHCI_CLOCK_INT_STABLE)) {
1238 if (timeout == 0) {
a3c76eb9 1239 pr_err("%s: Internal clock never "
acf1da45 1240 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1241 sdhci_dumpregs(host);
1242 return;
1243 }
7cb2c76f
PO		 1244 timeout--;
1245 mdelay(1);
1246 }
d129bceb
PO		 1247
1248 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1249 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1250
1251out:
1252 host->clock = clock;
1253}
1254
8213af3b
AS		 1255static inline void sdhci_update_clock(struct sdhci_host *host)
1256{
1257 unsigned int clock;
1258
1259 clock = host->clock;
1260 host->clock = 0;
1261 sdhci_set_clock(host, clock);
1262}
1263
ceb6143b 1264static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1265{
8364248a 1266 u8 pwr = 0;
146ad66e 1267
8364248a 1268 if (power != (unsigned short)-1) {
ae628903
PO		 1269 switch (1 << power) {
1270 case MMC_VDD_165_195:
1271 pwr = SDHCI_POWER_180;
1272 break;
1273 case MMC_VDD_29_30:
1274 case MMC_VDD_30_31:
1275 pwr = SDHCI_POWER_300;
1276 break;
1277 case MMC_VDD_32_33:
1278 case MMC_VDD_33_34:
1279 pwr = SDHCI_POWER_330;
1280 break;
1281 default:
1282 BUG();
1283 }
1284 }
1285
1286 if (host->pwr == pwr)
ceb6143b 1287 return -1;
146ad66e 1288
ae628903
PO		 1289 host->pwr = pwr;
1290
1291 if (pwr == 0) {
4e4141a5 1292 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1293 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1294 sdhci_runtime_pm_bus_off(host);
ceb6143b 1295 return 0;
9e9dc5f2
DS		 1296 }
1297
1298 /*
1299 * Spec says that we should clear the power reg before setting
1300 * a new value. Some controllers don't seem to like this though.
1301 */
b8c86fc5 1302 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1303 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1304
e08c1694 1305 /*
c71f6512 1306 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1307 * and set turn on power at the same time, so set the voltage first.
1308 */
11a2f1b7 1309 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1310 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1311
ae628903 1312 pwr |= SDHCI_POWER_ON;
146ad66e 1313
ae628903 1314 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1315
f0710a55
AH		 1316 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1317 sdhci_runtime_pm_bus_on(host);
1318
557b0697
HW		 1319 /*
1320 * Some controllers need an extra 10ms delay of 10ms before they
1321 * can apply clock after applying power
1322 */
11a2f1b7 1323 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1324 mdelay(10);
ceb6143b
AH		 1325
1326 return power;
146ad66e
PO		 1327}
1328
d129bceb
PO		 1329/*****************************************************************************\
1330 * *
1331 * MMC callbacks *
1332 * *
1333\*****************************************************************************/
1334
1335static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1336{
1337 struct sdhci_host *host;
505a8680 1338 int present;
d129bceb 1339 unsigned long flags;
473b095a 1340 u32 tuning_opcode;
d129bceb
PO		 1341
1342 host = mmc_priv(mmc);
1343
66fd8ad5
AH		 1344 sdhci_runtime_pm_get(host);
1345
d129bceb
PO		 1346 spin_lock_irqsave(&host->lock, flags);
1347
1348 WARN_ON(host->mrq != NULL);
1349
f9134319 1350#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1351 sdhci_activate_led(host);
2f730fec 1352#endif
e89d456f
AW		 1353
1354 /*
1355 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1356 * requests if Auto-CMD12 is enabled.
1357 */
1358 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1359 if (mrq->stop) {
1360 mrq->data->stop = NULL;
1361 mrq->stop = NULL;
1362 }
1363 }
d129bceb
PO		 1364
1365 host->mrq = mrq;
1366
505a8680
SG		 1367 /*
1368 * Firstly check card presence from cd-gpio. The return could
1369 * be one of the following possibilities:
1370 * negative: cd-gpio is not available
1371 * zero: cd-gpio is used, and card is removed
1372 * one: cd-gpio is used, and card is present
1373 */
1374 present = mmc_gpio_get_cd(host->mmc);
1375 if (present < 0) {
1376 /* If polling, assume that the card is always present. */
1377 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1378 present = 1;
1379 else
1380 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1381 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1382 }
1383
68d1fb7e 1384 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1385 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1386 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1387 } else {
1388 u32 present_state;
1389
1390 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1391 /*
1392 * Check if the re-tuning timer has already expired and there
1393 * is no on-going data transfer. If so, we need to execute
1394 * tuning procedure before sending command.
1395 */
1396 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1397 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1398 if (mmc->card) {
1399 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1400 tuning_opcode =
1401 mmc->card->type == MMC_TYPE_MMC ?
1402 MMC_SEND_TUNING_BLOCK_HS200 :
1403 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1404
1405 /* Here we need to set the host->mrq to NULL,
1406 * in case the pending finish_tasklet
1407 * finishes it incorrectly.
1408 */
1409 host->mrq = NULL;
1410
14efd957
CB		 1411 spin_unlock_irqrestore(&host->lock, flags);
1412 sdhci_execute_tuning(mmc, tuning_opcode);
1413 spin_lock_irqsave(&host->lock, flags);
1414
1415 /* Restore original mmc_request structure */
1416 host->mrq = mrq;
1417 }
cf2b5eea
AN		 1418 }
1419
8edf6371 1420 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1421 sdhci_send_command(host, mrq->sbc);
1422 else
1423 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1424 }
d129bceb 1425
5f25a66f 1426 mmiowb();
d129bceb
PO		 1427 spin_unlock_irqrestore(&host->lock, flags);
1428}
1429
66fd8ad5 1430static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1431{
d129bceb 1432 unsigned long flags;
ceb6143b 1433 int vdd_bit = -1;
d129bceb
PO		 1434 u8 ctrl;
1435
d129bceb
PO		 1436 spin_lock_irqsave(&host->lock, flags);
1437
ceb6143b
AH		 1438 if (host->flags & SDHCI_DEVICE_DEAD) {
1439 spin_unlock_irqrestore(&host->lock, flags);
1440 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1441 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1442 return;
1443 }
1e72859e 1444
d129bceb
PO		 1445 /*
1446 * Reset the chip on each power off.
1447 * Should clear out any weird states.
1448 */
1449 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1450 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1451 sdhci_reinit(host);
d129bceb
PO		 1452 }
1453
52983382 1454 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1455 (ios->power_mode == MMC_POWER_UP) &&
1456 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1457 sdhci_enable_preset_value(host, false);
1458
d129bceb
PO		 1459 sdhci_set_clock(host, ios->clock);
1460
1461 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1462 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1463 else
ceb6143b
AH		 1464 vdd_bit = sdhci_set_power(host, ios->vdd);
1465
1466 if (host->vmmc && vdd_bit != -1) {
1467 spin_unlock_irqrestore(&host->lock, flags);
1468 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1469 spin_lock_irqsave(&host->lock, flags);
1470 }
d129bceb 1471
643a81ff
PR		 1472 if (host->ops->platform_send_init_74_clocks)
1473 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1474
15ec4461
PR		 1475 /*
1476 * If your platform has 8-bit width support but is not a v3 controller,
1477 * or if it requires special setup code, you should implement that in
7bc088d3 1478 * platform_bus_width().
15ec4461 1479 */
7bc088d3
SH		 1480 if (host->ops->platform_bus_width) {
1481 host->ops->platform_bus_width(host, ios->bus_width);
1482 } else {
15ec4461
PR		 1483 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1484 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1485 ctrl &= ~SDHCI_CTRL_4BITBUS;
1486 if (host->version >= SDHCI_SPEC_300)
1487 ctrl |= SDHCI_CTRL_8BITBUS;
1488 } else {
1489 if (host->version >= SDHCI_SPEC_300)
1490 ctrl &= ~SDHCI_CTRL_8BITBUS;
1491 if (ios->bus_width == MMC_BUS_WIDTH_4)
1492 ctrl |= SDHCI_CTRL_4BITBUS;
1493 else
1494 ctrl &= ~SDHCI_CTRL_4BITBUS;
1495 }
1496 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1497 }
ae6d6c92 1498
15ec4461 1499 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1500
3ab9c8da
PR		 1501 if ((ios->timing == MMC_TIMING_SD_HS ||
1502 ios->timing == MMC_TIMING_MMC_HS)
1503 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1504 ctrl |= SDHCI_CTRL_HISPD;
1505 else
1506 ctrl &= ~SDHCI_CTRL_HISPD;
1507
d6d50a15 1508 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1509 u16 clk, ctrl_2;
49c468fc
AN		 1510
1511 /* In case of UHS-I modes, set High Speed Enable */
069c9f14 1512 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1513 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1514 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1515 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1516 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1517 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1518 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1519
1520 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1521 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1522 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1523 /*
1524 * We only need to set Driver Strength if the
1525 * preset value enable is not set.
1526 */
1527 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1528 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1529 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1530 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1531 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1532
1533 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1534 } else {
1535 /*
1536 * According to SDHC Spec v3.00, if the Preset Value
1537 * Enable in the Host Control 2 register is set, we
1538 * need to reset SD Clock Enable before changing High
1539 * Speed Enable to avoid generating clock gliches.
1540 */
758535c4
AN		 1541
1542 /* Reset SD Clock Enable */
1543 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1544 clk &= ~SDHCI_CLOCK_CARD_EN;
1545 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1546
1547 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1548
1549 /* Re-enable SD Clock */
8213af3b 1550 sdhci_update_clock(host);
d6d50a15 1551 }
49c468fc 1552
49c468fc
AN		 1553
1554 /* Reset SD Clock Enable */
1555 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1556 clk &= ~SDHCI_CLOCK_CARD_EN;
1557 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1558
6322cdd0
PR		 1559 if (host->ops->set_uhs_signaling)
1560 host->ops->set_uhs_signaling(host, ios->timing);
1561 else {
1562 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1563 /* Select Bus Speed Mode for host */
1564 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
59911568
GC		 1565 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1566 (ios->timing == MMC_TIMING_UHS_SDR104))
1567 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
069c9f14 1568 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1569 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1570 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1571 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1572 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1573 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
bb8175a8
SJ		 1574 else if ((ios->timing == MMC_TIMING_UHS_DDR50) ||
1575 (ios->timing == MMC_TIMING_MMC_DDR52))
6322cdd0
PR		 1576 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1577 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1578 }
49c468fc 1579
52983382
KL		 1580 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1581 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1582 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1583 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1584 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1585 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1586 u16 preset;
1587
1588 sdhci_enable_preset_value(host, true);
1589 preset = sdhci_get_preset_value(host);
1590 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1591 >> SDHCI_PRESET_DRV_SHIFT;
1592 }
1593
49c468fc 1594 /* Re-enable SD Clock */
8213af3b 1595 sdhci_update_clock(host);
758535c4
AN		 1596 } else
1597 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1598
b8352260
LD		 1599 /*
1600 * Some (ENE) controllers go apeshit on some ios operation,
1601 * signalling timeout and CRC errors even on CMD0. Resetting
1602 * it on each ios seems to solve the problem.
1603 */
b8c86fc5 1604 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1605 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1606
5f25a66f 1607 mmiowb();
d129bceb
PO		 1608 spin_unlock_irqrestore(&host->lock, flags);
1609}
1610
66fd8ad5
AH		 1611static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1612{
1613 struct sdhci_host *host = mmc_priv(mmc);
1614
1615 sdhci_runtime_pm_get(host);
1616 sdhci_do_set_ios(host, ios);
1617 sdhci_runtime_pm_put(host);
1618}
1619
94144a46
KL		 1620static int sdhci_do_get_cd(struct sdhci_host *host)
1621{
1622 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1623
1624 if (host->flags & SDHCI_DEVICE_DEAD)
1625 return 0;
1626
1627 /* If polling/nonremovable, assume that the card is always present. */
1628 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1629 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1630 return 1;
1631
1632 /* Try slot gpio detect */
1633 if (!IS_ERR_VALUE(gpio_cd))
1634 return !!gpio_cd;
1635
1636 /* Host native card detect */
1637 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1638}
1639
1640static int sdhci_get_cd(struct mmc_host *mmc)
1641{
1642 struct sdhci_host *host = mmc_priv(mmc);
1643 int ret;
1644
1645 sdhci_runtime_pm_get(host);
1646 ret = sdhci_do_get_cd(host);
1647 sdhci_runtime_pm_put(host);
1648 return ret;
1649}
1650
66fd8ad5 1651static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1652{
d129bceb 1653 unsigned long flags;
2dfb579c 1654 int is_readonly;
d129bceb 1655
d129bceb
PO		 1656 spin_lock_irqsave(&host->lock, flags);
1657
1e72859e 1658 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1659 is_readonly = 0;
1660 else if (host->ops->get_ro)
1661 is_readonly = host->ops->get_ro(host);
1e72859e 1662 else
2dfb579c
WS		 1663 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1664 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1665
1666 spin_unlock_irqrestore(&host->lock, flags);
1667
2dfb579c
WS		 1668 /* This quirk needs to be replaced by a callback-function later */
1669 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1670 !is_readonly : is_readonly;
d129bceb
PO		 1671}
1672
82b0e23a
TI		 1673#define SAMPLE_COUNT 5
1674
66fd8ad5 1675static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1676{
82b0e23a
TI		 1677 int i, ro_count;
1678
82b0e23a 1679 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1680 return sdhci_check_ro(host);
82b0e23a
TI		 1681
1682 ro_count = 0;
1683 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1684 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1685 if (++ro_count > SAMPLE_COUNT / 2)
1686 return 1;
1687 }
1688 msleep(30);
1689 }
1690 return 0;
1691}
1692
20758b66
AH		 1693static void sdhci_hw_reset(struct mmc_host *mmc)
1694{
1695 struct sdhci_host *host = mmc_priv(mmc);
1696
1697 if (host->ops && host->ops->hw_reset)
1698 host->ops->hw_reset(host);
1699}
1700
66fd8ad5 1701static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1702{
66fd8ad5
AH		 1703 struct sdhci_host *host = mmc_priv(mmc);
1704 int ret;
f75979b7 1705
66fd8ad5
AH		 1706 sdhci_runtime_pm_get(host);
1707 ret = sdhci_do_get_ro(host);
1708 sdhci_runtime_pm_put(host);
1709 return ret;
1710}
f75979b7 1711
66fd8ad5
AH		 1712static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1713{
66fd8ad5 1714 /* SDIO IRQ will be enabled as appropriate in runtime resume */
ef104333
RK		 1715 if (!(host->flags & SDHCI_DEVICE_DEAD) || host->runtime_suspended) {
1716 if (enable)
1717 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1718 else
1719 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1720 mmiowb();
1721 }
66fd8ad5
AH		 1722}
1723
1724static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1725{
1726 struct sdhci_host *host = mmc_priv(mmc);
1727 unsigned long flags;
f75979b7 1728
ef104333
RK		 1729 sdhci_runtime_pm_get(host);
1730
66fd8ad5 1731 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1732 if (enable)
1733 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1734 else
1735 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1736
66fd8ad5 1737 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1738 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1739
1740 sdhci_runtime_pm_put(host);
f75979b7
PO		 1741}
1742
20b92a30 1743static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1744 struct mmc_ios *ios)
f2119df6 1745{
20b92a30 1746 u16 ctrl;
6231f3de 1747 int ret;
f2119df6 1748
20b92a30
KL		 1749 /*
1750 * Signal Voltage Switching is only applicable for Host Controllers
1751 * v3.00 and above.
1752 */
1753 if (host->version < SDHCI_SPEC_300)
1754 return 0;
6231f3de 1755
f2119df6 1756 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1757
21f5998f 1758 switch (ios->signal_voltage) {
20b92a30
KL		 1759 case MMC_SIGNAL_VOLTAGE_330:
1760 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1761 ctrl &= ~SDHCI_CTRL_VDD_180;
1762 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1763
20b92a30
KL		 1764 if (host->vqmmc) {
1765 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1766 if (ret) {
1767 pr_warning("%s: Switching to 3.3V signalling voltage "
1768 " failed\n", mmc_hostname(host->mmc));
1769 return -EIO;
1770 }
1771 }
1772 /* Wait for 5ms */
1773 usleep_range(5000, 5500);
f2119df6 1774
20b92a30
KL		 1775 /* 3.3V regulator output should be stable within 5 ms */
1776 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1777 if (!(ctrl & SDHCI_CTRL_VDD_180))
1778 return 0;
6231f3de 1779
20b92a30
KL		 1780 pr_warning("%s: 3.3V regulator output did not became stable\n",
1781 mmc_hostname(host->mmc));
1782
1783 return -EAGAIN;
1784 case MMC_SIGNAL_VOLTAGE_180:
1785 if (host->vqmmc) {
1786 ret = regulator_set_voltage(host->vqmmc,
1787 1700000, 1950000);
1788 if (ret) {
1789 pr_warning("%s: Switching to 1.8V signalling voltage "
1790 " failed\n", mmc_hostname(host->mmc));
1791 return -EIO;
1792 }
1793 }
6231f3de 1794
6231f3de
PR		 1795 /*
1796 * Enable 1.8V Signal Enable in the Host Control2
1797 * register
1798 */
20b92a30
KL		 1799 ctrl |= SDHCI_CTRL_VDD_180;
1800 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1801
20b92a30
KL		 1802 /* Wait for 5ms */
1803 usleep_range(5000, 5500);
f2119df6 1804
20b92a30
KL		 1805 /* 1.8V regulator output should be stable within 5 ms */
1806 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1807 if (ctrl & SDHCI_CTRL_VDD_180)
1808 return 0;
f2119df6 1809
20b92a30
KL		 1810 pr_warning("%s: 1.8V regulator output did not became stable\n",
1811 mmc_hostname(host->mmc));
f2119df6 1812
20b92a30
KL		 1813 return -EAGAIN;
1814 case MMC_SIGNAL_VOLTAGE_120:
1815 if (host->vqmmc) {
1816 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1817 if (ret) {
1818 pr_warning("%s: Switching to 1.2V signalling voltage "
1819 " failed\n", mmc_hostname(host->mmc));
1820 return -EIO;
f2119df6
AN		 1821 }
1822 }
6231f3de 1823 return 0;
20b92a30 1824 default:
f2119df6
AN		 1825 /* No signal voltage switch required */
1826 return 0;
20b92a30 1827 }
f2119df6
AN		 1828}
1829
66fd8ad5 1830static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1831 struct mmc_ios *ios)
66fd8ad5
AH		 1832{
1833 struct sdhci_host *host = mmc_priv(mmc);
1834 int err;
1835
1836 if (host->version < SDHCI_SPEC_300)
1837 return 0;
1838 sdhci_runtime_pm_get(host);
21f5998f 1839 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1840 sdhci_runtime_pm_put(host);
1841 return err;
1842}
1843
20b92a30
KL		 1844static int sdhci_card_busy(struct mmc_host *mmc)
1845{
1846 struct sdhci_host *host = mmc_priv(mmc);
1847 u32 present_state;
1848
1849 sdhci_runtime_pm_get(host);
1850 /* Check whether DAT[3:0] is 0000 */
1851 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1852 sdhci_runtime_pm_put(host);
1853
1854 return !(present_state & SDHCI_DATA_LVL_MASK);
1855}
1856
069c9f14 1857static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1858{
1859 struct sdhci_host *host;
1860 u16 ctrl;
1861 u32 ier;
1862 int tuning_loop_counter = MAX_TUNING_LOOP;
1863 unsigned long timeout;
1864 int err = 0;
069c9f14 1865 bool requires_tuning_nonuhs = false;
2b35bd83 1866 unsigned long flags;
b513ea25
AN		 1867
1868 host = mmc_priv(mmc);
1869
66fd8ad5 1870 sdhci_runtime_pm_get(host);
2b35bd83 1871 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1872
1873 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1874
1875 /*
069c9f14
G		 1876 * The Host Controller needs tuning only in case of SDR104 mode
1877 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1878 * Capabilities register.
069c9f14
G		 1879 * If the Host Controller supports the HS200 mode then the
1880 * tuning function has to be executed.
b513ea25 1881 */
069c9f14
G		 1882 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1883 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
156e14b1 1884 host->flags & SDHCI_SDR104_NEEDS_TUNING))
069c9f14
G		 1885 requires_tuning_nonuhs = true;
1886
b513ea25 1887 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1888 requires_tuning_nonuhs)
b513ea25
AN		 1889 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1890 else {
2b35bd83 1891 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 1892 sdhci_runtime_pm_put(host);
b513ea25
AN		 1893 return 0;
1894 }
1895
45251812 1896 if (host->ops->platform_execute_tuning) {
2b35bd83 1897 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1898 err = host->ops->platform_execute_tuning(host, opcode);
1899 sdhci_runtime_pm_put(host);
1900 return err;
1901 }
1902
b513ea25
AN		 1903 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1904
1905 /*
1906 * As per the Host Controller spec v3.00, tuning command
1907 * generates Buffer Read Ready interrupt, so enable that.
1908 *
1909 * Note: The spec clearly says that when tuning sequence
1910 * is being performed, the controller does not generate
1911 * interrupts other than Buffer Read Ready interrupt. But
1912 * to make sure we don't hit a controller bug, we _only_
1913 * enable Buffer Read Ready interrupt here.
1914 */
1915 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1916 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1917
1918 /*
1919 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1920 * of loops reaches 40 times or a timeout of 150ms occurs.
1921 */
1922 timeout = 150;
1923 do {
1924 struct mmc_command cmd = {0};
66fd8ad5 1925 struct mmc_request mrq = {NULL};
b513ea25
AN		 1926
1927 if (!tuning_loop_counter && !timeout)
1928 break;
1929
069c9f14 1930 cmd.opcode = opcode;
b513ea25
AN		 1931 cmd.arg = 0;
1932 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1933 cmd.retries = 0;
1934 cmd.data = NULL;
1935 cmd.error = 0;
1936
1937 mrq.cmd = &cmd;
1938 host->mrq = &mrq;
1939
1940 /*
1941 * In response to CMD19, the card sends 64 bytes of tuning
1942 * block to the Host Controller. So we set the block size
1943 * to 64 here.
1944 */
069c9f14
G		 1945 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1946 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1947 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1948 SDHCI_BLOCK_SIZE);
1949 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1950 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1951 SDHCI_BLOCK_SIZE);
1952 } else {
1953 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1954 SDHCI_BLOCK_SIZE);
1955 }
b513ea25
AN		 1956
1957 /*
1958 * The tuning block is sent by the card to the host controller.
1959 * So we set the TRNS_READ bit in the Transfer Mode register.
1960 * This also takes care of setting DMA Enable and Multi Block
1961 * Select in the same register to 0.
1962 */
1963 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1964
1965 sdhci_send_command(host, &cmd);
1966
1967 host->cmd = NULL;
1968 host->mrq = NULL;
1969
2b35bd83 1970 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1971 /* Wait for Buffer Read Ready interrupt */
1972 wait_event_interruptible_timeout(host->buf_ready_int,
1973 (host->tuning_done == 1),
1974 msecs_to_jiffies(50));
2b35bd83 1975 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1976
1977 if (!host->tuning_done) {
a3c76eb9 1978 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1979 "Buffer Read Ready interrupt during tuning "
1980 "procedure, falling back to fixed sampling "
1981 "clock\n");
1982 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1983 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1984 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1985 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1986
1987 err = -EIO;
1988 goto out;
1989 }
1990
1991 host->tuning_done = 0;
1992
1993 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1994 tuning_loop_counter--;
1995 timeout--;
197160d5
NS		 1996
1997 /* eMMC spec does not require a delay between tuning cycles */
1998 if (opcode == MMC_SEND_TUNING_BLOCK)
1999 mdelay(1);
b513ea25
AN		 2000 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2001
2002 /*
2003 * The Host Driver has exhausted the maximum number of loops allowed,
2004 * so use fixed sampling frequency.
2005 */
2006 if (!tuning_loop_counter || !timeout) {
2007 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2008 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
114f2bf6 2009 err = -EIO;
b513ea25
AN		 2010 } else {
2011 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 2012 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 2013 " failed, falling back to fixed sampling"
2014 " clock\n");
2015 err = -EIO;
2016 }
2017 }
2018
2019out:
cf2b5eea
AN		 2020 /*
2021 * If this is the very first time we are here, we start the retuning
2022 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2023 * flag won't be set, we check this condition before actually starting
2024 * the timer.
2025 */
2026 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2027 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 2028 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 2029 mod_timer(&host->tuning_timer, jiffies +
2030 host->tuning_count * HZ);
2031 /* Tuning mode 1 limits the maximum data length to 4MB */
2032 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2bc02485 2033 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
cf2b5eea
AN		 2034 host->flags &= ~SDHCI_NEEDS_RETUNING;
2035 /* Reload the new initial value for timer */
2bc02485
AS		 2036 mod_timer(&host->tuning_timer, jiffies +
2037 host->tuning_count * HZ);
cf2b5eea
AN		 2038 }
2039
2040 /*
2041 * In case tuning fails, host controllers which support re-tuning can
2042 * try tuning again at a later time, when the re-tuning timer expires.
2043 * So for these controllers, we return 0. Since there might be other
2044 * controllers who do not have this capability, we return error for
973905fe
AL		 2045 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2046 * a retuning timer to do the retuning for the card.
cf2b5eea 2047 */
973905fe 2048 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2049 err = 0;
2050
b513ea25 2051 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2b35bd83 2052 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2053 sdhci_runtime_pm_put(host);
b513ea25
AN		 2054
2055 return err;
2056}
2057
52983382
KL		 2058
2059static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2060{
4d55c5a1 2061 u16 ctrl;
4d55c5a1 2062
4d55c5a1
AN		 2063 /* Host Controller v3.00 defines preset value registers */
2064 if (host->version < SDHCI_SPEC_300)
2065 return;
2066
4d55c5a1
AN		 2067 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2068
2069 /*
2070 * We only enable or disable Preset Value if they are not already
2071 * enabled or disabled respectively. Otherwise, we bail out.
2072 */
2073 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2074 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2075 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2076 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 2077 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2078 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2079 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2080 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1 2081 }
66fd8ad5
AH		 2082}
2083
71e69211 2084static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2085{
71e69211 2086 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2087 unsigned long flags;
2088
722e1280
CD		 2089 /* First check if client has provided their own card event */
2090 if (host->ops->card_event)
2091 host->ops->card_event(host);
2092
d129bceb
PO		 2093 spin_lock_irqsave(&host->lock, flags);
2094
66fd8ad5 2095 /* Check host->mrq first in case we are runtime suspended */
9668d765 2096 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2097 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2098 mmc_hostname(host->mmc));
a3c76eb9 2099 pr_err("%s: Resetting controller.\n",
66fd8ad5 2100 mmc_hostname(host->mmc));
d129bceb 2101
66fd8ad5
AH		 2102 sdhci_reset(host, SDHCI_RESET_CMD);
2103 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 2104
66fd8ad5
AH		 2105 host->mrq->cmd->error = -ENOMEDIUM;
2106 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2107 }
2108
2109 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2110}
2111
2112static const struct mmc_host_ops sdhci_ops = {
2113 .request = sdhci_request,
2114 .set_ios = sdhci_set_ios,
94144a46 2115 .get_cd = sdhci_get_cd,
71e69211
GL		 2116 .get_ro = sdhci_get_ro,
2117 .hw_reset = sdhci_hw_reset,
2118 .enable_sdio_irq = sdhci_enable_sdio_irq,
2119 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2120 .execute_tuning = sdhci_execute_tuning,
71e69211 2121 .card_event = sdhci_card_event,
20b92a30 2122 .card_busy = sdhci_card_busy,
71e69211
GL		 2123};
2124
2125/*****************************************************************************\
2126 * *
2127 * Tasklets *
2128 * *
2129\*****************************************************************************/
2130
2131static void sdhci_tasklet_card(unsigned long param)
2132{
2133 struct sdhci_host *host = (struct sdhci_host*)param;
2134
2135 sdhci_card_event(host->mmc);
d129bceb 2136
04cf585d 2137 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 2138}
2139
2140static void sdhci_tasklet_finish(unsigned long param)
2141{
2142 struct sdhci_host *host;
2143 unsigned long flags;
2144 struct mmc_request *mrq;
2145
2146 host = (struct sdhci_host*)param;
2147
66fd8ad5
AH		 2148 spin_lock_irqsave(&host->lock, flags);
2149
0c9c99a7
CB		 2150 /*
2151 * If this tasklet gets rescheduled while running, it will
2152 * be run again afterwards but without any active request.
2153 */
66fd8ad5
AH		 2154 if (!host->mrq) {
2155 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2156 return;
66fd8ad5 2157 }
d129bceb
PO		 2158
2159 del_timer(&host->timer);
2160
2161 mrq = host->mrq;
2162
d129bceb
PO		 2163 /*
2164 * The controller needs a reset of internal state machines
2165 * upon error conditions.
2166 */
1e72859e 2167 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2168 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2169 (mrq->data && (mrq->data->error ||
2170 (mrq->data->stop && mrq->data->stop->error))) ||
2171 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2172
2173 /* Some controllers need this kick or reset won't work here */
8213af3b 2174 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2175 /* This is to force an update */
8213af3b 2176 sdhci_update_clock(host);
645289dc
PO		 2177
2178 /* Spec says we should do both at the same time, but Ricoh
2179 controllers do not like that. */
d129bceb
PO		 2180 sdhci_reset(host, SDHCI_RESET_CMD);
2181 sdhci_reset(host, SDHCI_RESET_DATA);
2182 }
2183
2184 host->mrq = NULL;
2185 host->cmd = NULL;
2186 host->data = NULL;
2187
f9134319 2188#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2189 sdhci_deactivate_led(host);
2f730fec 2190#endif
d129bceb 2191
5f25a66f 2192 mmiowb();
d129bceb
PO		 2193 spin_unlock_irqrestore(&host->lock, flags);
2194
2195 mmc_request_done(host->mmc, mrq);
66fd8ad5 2196 sdhci_runtime_pm_put(host);
d129bceb
PO		 2197}
2198
2199static void sdhci_timeout_timer(unsigned long data)
2200{
2201 struct sdhci_host *host;
2202 unsigned long flags;
2203
2204 host = (struct sdhci_host*)data;
2205
2206 spin_lock_irqsave(&host->lock, flags);
2207
2208 if (host->mrq) {
a3c76eb9 2209 pr_err("%s: Timeout waiting for hardware "
acf1da45 2210 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2211 sdhci_dumpregs(host);
2212
2213 if (host->data) {
17b0429d 2214 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2215 sdhci_finish_data(host);
2216 } else {
2217 if (host->cmd)
17b0429d 2218 host->cmd->error = -ETIMEDOUT;
d129bceb 2219 else
17b0429d 2220 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2221
2222 tasklet_schedule(&host->finish_tasklet);
2223 }
2224 }
2225
5f25a66f 2226 mmiowb();
d129bceb
PO		 2227 spin_unlock_irqrestore(&host->lock, flags);
2228}
2229
cf2b5eea
AN		 2230static void sdhci_tuning_timer(unsigned long data)
2231{
2232 struct sdhci_host *host;
2233 unsigned long flags;
2234
2235 host = (struct sdhci_host *)data;
2236
2237 spin_lock_irqsave(&host->lock, flags);
2238
2239 host->flags |= SDHCI_NEEDS_RETUNING;
2240
2241 spin_unlock_irqrestore(&host->lock, flags);
2242}
2243
d129bceb
PO		 2244/*****************************************************************************\
2245 * *
2246 * Interrupt handling *
2247 * *
2248\*****************************************************************************/
2249
2250static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2251{
2252 BUG_ON(intmask == 0);
2253
2254 if (!host->cmd) {
a3c76eb9 2255 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2256 "though no command operation was in progress.\n",
2257 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2258 sdhci_dumpregs(host);
2259 return;
2260 }
2261
43b58b36 2262 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2263 host->cmd->error = -ETIMEDOUT;
2264 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2265 SDHCI_INT_INDEX))
2266 host->cmd->error = -EILSEQ;
43b58b36 2267
e809517f 2268 if (host->cmd->error) {
d129bceb 2269 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2270 return;
2271 }
2272
2273 /*
2274 * The host can send and interrupt when the busy state has
2275 * ended, allowing us to wait without wasting CPU cycles.
2276 * Unfortunately this is overloaded on the "data complete"
2277 * interrupt, so we need to take some care when handling
2278 * it.
2279 *
2280 * Note: The 1.0 specification is a bit ambiguous about this
2281 * feature so there might be some problems with older
2282 * controllers.
2283 */
2284 if (host->cmd->flags & MMC_RSP_BUSY) {
2285 if (host->cmd->data)
2286 DBG("Cannot wait for busy signal when also "
2287 "doing a data transfer");
f945405c 2288 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2289 return;
f945405c
BD		 2290
2291 /* The controller does not support the end-of-busy IRQ,
2292 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2293 }
2294
2295 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2296 sdhci_finish_command(host);
d129bceb
PO		 2297}
2298
0957c333 2299#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2300static void sdhci_show_adma_error(struct sdhci_host *host)
2301{
2302 const char *name = mmc_hostname(host->mmc);
2303 u8 *desc = host->adma_desc;
2304 __le32 *dma;
2305 __le16 *len;
2306 u8 attr;
2307
2308 sdhci_dumpregs(host);
2309
2310 while (true) {
2311 dma = (__le32 *)(desc + 4);
2312 len = (__le16 *)(desc + 2);
2313 attr = *desc;
2314
2315 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2316 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2317
2318 desc += 8;
2319
2320 if (attr & 2)
2321 break;
2322 }
2323}
2324#else
2325static void sdhci_show_adma_error(struct sdhci_host *host) { }
2326#endif
2327
d129bceb
PO		 2328static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2329{
069c9f14 2330 u32 command;
d129bceb
PO		 2331 BUG_ON(intmask == 0);
2332
b513ea25
AN		 2333 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2334 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2335 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2336 if (command == MMC_SEND_TUNING_BLOCK ||
2337 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2338 host->tuning_done = 1;
2339 wake_up(&host->buf_ready_int);
2340 return;
2341 }
2342 }
2343
d129bceb
PO		 2344 if (!host->data) {
2345 /*
e809517f
PO		 2346 * The "data complete" interrupt is also used to
2347 * indicate that a busy state has ended. See comment
2348 * above in sdhci_cmd_irq().
d129bceb 2349 */
e809517f
PO		 2350 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2351 if (intmask & SDHCI_INT_DATA_END) {
2352 sdhci_finish_command(host);
2353 return;
2354 }
2355 }
d129bceb 2356
a3c76eb9 2357 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2358 "though no data operation was in progress.\n",
2359 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2360 sdhci_dumpregs(host);
2361
2362 return;
2363 }
2364
2365 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2366 host->data->error = -ETIMEDOUT;
22113efd
AL		 2367 else if (intmask & SDHCI_INT_DATA_END_BIT)
2368 host->data->error = -EILSEQ;
2369 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2370 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2371 != MMC_BUS_TEST_R)
17b0429d 2372 host->data->error = -EILSEQ;
6882a8c0 2373 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2374 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2375 sdhci_show_adma_error(host);
2134a922 2376 host->data->error = -EIO;
a4071fbb
HZ		 2377 if (host->ops->adma_workaround)
2378 host->ops->adma_workaround(host, intmask);
6882a8c0 2379 }
d129bceb 2380
17b0429d 2381 if (host->data->error)
d129bceb
PO		 2382 sdhci_finish_data(host);
2383 else {
a406f5a3 2384 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2385 sdhci_transfer_pio(host);
2386
6ba736a1
PO		 2387 /*
2388 * We currently don't do anything fancy with DMA
2389 * boundaries, but as we can't disable the feature
2390 * we need to at least restart the transfer.
f6a03cbf
MV		 2391 *
2392 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2393 * should return a valid address to continue from, but as
2394 * some controllers are faulty, don't trust them.
6ba736a1 2395 */
f6a03cbf
MV		 2396 if (intmask & SDHCI_INT_DMA_END) {
2397 u32 dmastart, dmanow;
2398 dmastart = sg_dma_address(host->data->sg);
2399 dmanow = dmastart + host->data->bytes_xfered;
2400 /*
2401 * Force update to the next DMA block boundary.
2402 */
2403 dmanow = (dmanow &
2404 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2405 SDHCI_DEFAULT_BOUNDARY_SIZE;
2406 host->data->bytes_xfered = dmanow - dmastart;
2407 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2408 " next 0x%08x\n",
2409 mmc_hostname(host->mmc), dmastart,
2410 host->data->bytes_xfered, dmanow);
2411 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2412 }
6ba736a1 2413
e538fbe8
PO		 2414 if (intmask & SDHCI_INT_DATA_END) {
2415 if (host->cmd) {
2416 /*
2417 * Data managed to finish before the
2418 * command completed. Make sure we do
2419 * things in the proper order.
2420 */
2421 host->data_early = 1;
2422 } else {
2423 sdhci_finish_data(host);
2424 }
2425 }
d129bceb
PO		 2426 }
2427}
2428
7d12e780 2429static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2430{
781e989c 2431 irqreturn_t result = IRQ_NONE;
66fd8ad5 2432 struct sdhci_host *host = dev_id;
41005003 2433 u32 intmask, mask, unexpected = 0;
781e989c 2434 int max_loops = 16;
d129bceb
PO		 2435
2436 spin_lock(&host->lock);
2437
66fd8ad5
AH		 2438 if (host->runtime_suspended) {
2439 spin_unlock(&host->lock);
655bca76 2440 return IRQ_NONE;
66fd8ad5
AH		 2441 }
2442
4e4141a5 2443 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2444 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2445 result = IRQ_NONE;
2446 goto out;
2447 }
2448
41005003
RK		 2449 do {
2450 /* Clear selected interrupts. */
2451 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2452 SDHCI_INT_BUS_POWER);
2453 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2454
41005003
RK		 2455 DBG("*** %s got interrupt: 0x%08x\n",
2456 mmc_hostname(host->mmc), intmask);
d129bceb 2457
41005003
RK		 2458 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2459 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2460 SDHCI_CARD_PRESENT;
d129bceb 2461
41005003
RK		 2462 /*
2463 * There is a observation on i.mx esdhc. INSERT
2464 * bit will be immediately set again when it gets
2465 * cleared, if a card is inserted. We have to mask
2466 * the irq to prevent interrupt storm which will
2467 * freeze the system. And the REMOVE gets the
2468 * same situation.
2469 *
2470 * More testing are needed here to ensure it works
2471 * for other platforms though.
2472 */
2473 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2474 SDHCI_INT_CARD_REMOVE);
2475 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2476 SDHCI_INT_CARD_INSERT);
2477
2478 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2479 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2480 tasklet_schedule(&host->card_tasklet);
2481 }
d129bceb 2482
41005003
RK		 2483 if (intmask & SDHCI_INT_CMD_MASK)
2484 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
964f9ce2 2485
41005003
RK		 2486 if (intmask & SDHCI_INT_DATA_MASK)
2487 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2488
41005003
RK		 2489 if (intmask & SDHCI_INT_BUS_POWER)
2490 pr_err("%s: Card is consuming too much power!\n",
2491 mmc_hostname(host->mmc));
3192a28f 2492
781e989c
RK		 2493 if (intmask & SDHCI_INT_CARD_INT) {
2494 sdhci_enable_sdio_irq_nolock(host, false);
2495 host->thread_isr |= SDHCI_INT_CARD_INT;
2496 result = IRQ_WAKE_THREAD;
2497 }
f75979b7 2498
41005003
RK		 2499 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2500 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2501 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2502 SDHCI_INT_CARD_INT);
f75979b7 2503
41005003
RK		 2504 if (intmask) {
2505 unexpected |= intmask;
2506 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2507 }
d129bceb 2508
781e989c
RK		 2509 if (result == IRQ_NONE)
2510 result = IRQ_HANDLED;
d129bceb 2511
41005003 2512 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2513 } while (intmask && --max_loops);
d129bceb
PO		 2514out:
2515 spin_unlock(&host->lock);
2516
6379b237
AS		 2517 if (unexpected) {
2518 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2519 mmc_hostname(host->mmc), unexpected);
2520 sdhci_dumpregs(host);
2521 }
f75979b7 2522
d129bceb
PO		 2523 return result;
2524}
2525
781e989c
RK		 2526static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2527{
2528 struct sdhci_host *host = dev_id;
2529 unsigned long flags;
2530 u32 isr;
2531
2532 spin_lock_irqsave(&host->lock, flags);
2533 isr = host->thread_isr;
2534 host->thread_isr = 0;
2535 spin_unlock_irqrestore(&host->lock, flags);
2536
2537 if (isr & SDHCI_INT_CARD_INT) {
2538 sdio_run_irqs(host->mmc);
2539
2540 spin_lock_irqsave(&host->lock, flags);
2541 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2542 sdhci_enable_sdio_irq_nolock(host, true);
2543 spin_unlock_irqrestore(&host->lock, flags);
2544 }
2545
2546 return isr ? IRQ_HANDLED : IRQ_NONE;
2547}
2548
d129bceb
PO		 2549/*****************************************************************************\
2550 * *
2551 * Suspend/resume *
2552 * *
2553\*****************************************************************************/
2554
2555#ifdef CONFIG_PM
ad080d79
KL		 2556void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2557{
2558 u8 val;
2559 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2560 | SDHCI_WAKE_ON_INT;
2561
2562 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2563 val |= mask ;
2564 /* Avoid fake wake up */
2565 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2566 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2567 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2568}
2569EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2570
2571void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2572{
2573 u8 val;
2574 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2575 | SDHCI_WAKE_ON_INT;
2576
2577 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2578 val &= ~mask;
2579 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2580}
2581EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2582
29495aa0 2583int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2584{
a1b13b4e
CB		 2585 if (host->ops->platform_suspend)
2586 host->ops->platform_suspend(host);
2587
7260cf5e
AV		 2588 sdhci_disable_card_detection(host);
2589
cf2b5eea 2590 /* Disable tuning since we are suspending */
973905fe 2591 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2592 del_timer_sync(&host->tuning_timer);
cf2b5eea 2593 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2594 }
2595
ad080d79
KL		 2596 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2597 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2598 free_irq(host->irq, host);
2599 } else {
2600 sdhci_enable_irq_wakeups(host);
2601 enable_irq_wake(host->irq);
2602 }
4ee14ec6 2603 return 0;
d129bceb
PO		 2604}
2605
b8c86fc5 2606EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2607
b8c86fc5
PO		 2608int sdhci_resume_host(struct sdhci_host *host)
2609{
4ee14ec6 2610 int ret = 0;
d129bceb 2611
a13abc7b 2612 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2613 if (host->ops->enable_dma)
2614 host->ops->enable_dma(host);
2615 }
d129bceb 2616
ad080d79 2617 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2618 ret = request_threaded_irq(host->irq, sdhci_irq,
2619 sdhci_thread_irq, IRQF_SHARED,
2620 mmc_hostname(host->mmc), host);
ad080d79
KL		 2621 if (ret)
2622 return ret;
2623 } else {
2624 sdhci_disable_irq_wakeups(host);
2625 disable_irq_wake(host->irq);
2626 }
d129bceb 2627
6308d290
AH		 2628 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2629 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2630 /* Card keeps power but host controller does not */
2631 sdhci_init(host, 0);
2632 host->pwr = 0;
2633 host->clock = 0;
2634 sdhci_do_set_ios(host, &host->mmc->ios);
2635 } else {
2636 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2637 mmiowb();
2638 }
b8c86fc5 2639
7260cf5e
AV		 2640 sdhci_enable_card_detection(host);
2641
a1b13b4e
CB		 2642 if (host->ops->platform_resume)
2643 host->ops->platform_resume(host);
2644
cf2b5eea 2645 /* Set the re-tuning expiration flag */
973905fe 2646 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2647 host->flags |= SDHCI_NEEDS_RETUNING;
2648
2f4cbb3d 2649 return ret;
d129bceb
PO		 2650}
2651
b8c86fc5 2652EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2653#endif /* CONFIG_PM */
2654
66fd8ad5
AH		 2655#ifdef CONFIG_PM_RUNTIME
2656
2657static int sdhci_runtime_pm_get(struct sdhci_host *host)
2658{
2659 return pm_runtime_get_sync(host->mmc->parent);
2660}
2661
2662static int sdhci_runtime_pm_put(struct sdhci_host *host)
2663{
2664 pm_runtime_mark_last_busy(host->mmc->parent);
2665 return pm_runtime_put_autosuspend(host->mmc->parent);
2666}
2667
f0710a55
AH		 2668static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2669{
2670 if (host->runtime_suspended || host->bus_on)
2671 return;
2672 host->bus_on = true;
2673 pm_runtime_get_noresume(host->mmc->parent);
2674}
2675
2676static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2677{
2678 if (host->runtime_suspended || !host->bus_on)
2679 return;
2680 host->bus_on = false;
2681 pm_runtime_put_noidle(host->mmc->parent);
2682}
2683
66fd8ad5
AH		 2684int sdhci_runtime_suspend_host(struct sdhci_host *host)
2685{
2686 unsigned long flags;
2687 int ret = 0;
2688
2689 /* Disable tuning since we are suspending */
973905fe 2690 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2691 del_timer_sync(&host->tuning_timer);
2692 host->flags &= ~SDHCI_NEEDS_RETUNING;
2693 }
2694
2695 spin_lock_irqsave(&host->lock, flags);
2696 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2697 spin_unlock_irqrestore(&host->lock, flags);
2698
781e989c 2699 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2700
2701 spin_lock_irqsave(&host->lock, flags);
2702 host->runtime_suspended = true;
2703 spin_unlock_irqrestore(&host->lock, flags);
2704
2705 return ret;
2706}
2707EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2708
2709int sdhci_runtime_resume_host(struct sdhci_host *host)
2710{
2711 unsigned long flags;
2712 int ret = 0, host_flags = host->flags;
2713
2714 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2715 if (host->ops->enable_dma)
2716 host->ops->enable_dma(host);
2717 }
2718
2719 sdhci_init(host, 0);
2720
2721 /* Force clock and power re-program */
2722 host->pwr = 0;
2723 host->clock = 0;
2724 sdhci_do_set_ios(host, &host->mmc->ios);
2725
2726 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2727 if ((host_flags & SDHCI_PV_ENABLED) &&
2728 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2729 spin_lock_irqsave(&host->lock, flags);
2730 sdhci_enable_preset_value(host, true);
2731 spin_unlock_irqrestore(&host->lock, flags);
2732 }
66fd8ad5
AH		 2733
2734 /* Set the re-tuning expiration flag */
973905fe 2735 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2736 host->flags |= SDHCI_NEEDS_RETUNING;
2737
2738 spin_lock_irqsave(&host->lock, flags);
2739
2740 host->runtime_suspended = false;
2741
2742 /* Enable SDIO IRQ */
ef104333 2743 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2744 sdhci_enable_sdio_irq_nolock(host, true);
2745
2746 /* Enable Card Detection */
2747 sdhci_enable_card_detection(host);
2748
2749 spin_unlock_irqrestore(&host->lock, flags);
2750
2751 return ret;
2752}
2753EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2754
2755#endif
2756
d129bceb
PO		 2757/*****************************************************************************\
2758 * *
b8c86fc5 2759 * Device allocation/registration *
d129bceb
PO		 2760 * *
2761\*****************************************************************************/
2762
b8c86fc5
PO		 2763struct sdhci_host *sdhci_alloc_host(struct device *dev,
2764 size_t priv_size)
d129bceb 2765{
d129bceb
PO		 2766 struct mmc_host *mmc;
2767 struct sdhci_host *host;
2768
b8c86fc5 2769 WARN_ON(dev == NULL);
d129bceb 2770
b8c86fc5 2771 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2772 if (!mmc)
b8c86fc5 2773 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2774
2775 host = mmc_priv(mmc);
2776 host->mmc = mmc;
2777
b8c86fc5
PO		 2778 return host;
2779}
8a4da143 2780
b8c86fc5 2781EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2782
b8c86fc5
PO		 2783int sdhci_add_host(struct sdhci_host *host)
2784{
2785 struct mmc_host *mmc;
bd6a8c30 2786 u32 caps[2] = {0, 0};
f2119df6
AN		 2787 u32 max_current_caps;
2788 unsigned int ocr_avail;
b8c86fc5 2789 int ret;
d129bceb 2790
b8c86fc5
PO		 2791 WARN_ON(host == NULL);
2792 if (host == NULL)
2793 return -EINVAL;
d129bceb 2794
b8c86fc5 2795 mmc = host->mmc;
d129bceb 2796
b8c86fc5
PO		 2797 if (debug_quirks)
2798 host->quirks = debug_quirks;
66fd8ad5
AH		 2799 if (debug_quirks2)
2800 host->quirks2 = debug_quirks2;
d129bceb 2801
d96649ed
PO		 2802 sdhci_reset(host, SDHCI_RESET_ALL);
2803
4e4141a5 2804 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2805 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2806 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2807 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2808 pr_err("%s: Unknown controller version (%d). "
b69c9058 2809 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2810 host->version);
4a965505
PO		 2811 }
2812
f2119df6 2813 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2814 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2815
bd6a8c30
PR		 2816 if (host->version >= SDHCI_SPEC_300)
2817 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2818 host->caps1 :
2819 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2820
b8c86fc5 2821 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2822 host->flags |= SDHCI_USE_SDMA;
f2119df6 2823 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2824 DBG("Controller doesn't have SDMA capability\n");
67435274 2825 else
a13abc7b 2826 host->flags |= SDHCI_USE_SDMA;
d129bceb 2827
b8c86fc5 2828 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2829 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2830 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2831 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2832 }
2833
f2119df6
AN		 2834 if ((host->version >= SDHCI_SPEC_200) &&
2835 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2836 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2837
2838 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2839 (host->flags & SDHCI_USE_ADMA)) {
2840 DBG("Disabling ADMA as it is marked broken\n");
2841 host->flags &= ~SDHCI_USE_ADMA;
2842 }
2843
a13abc7b 2844 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2845 if (host->ops->enable_dma) {
2846 if (host->ops->enable_dma(host)) {
a3c76eb9 2847 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2848 "available. Falling back to PIO.\n",
2849 mmc_hostname(mmc));
a13abc7b
RR		 2850 host->flags &=
2851 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2852 }
d129bceb
PO		 2853 }
2854 }
2855
2134a922
PO		 2856 if (host->flags & SDHCI_USE_ADMA) {
2857 /*
2858 * We need to allocate descriptors for all sg entries
2859 * (128) and potentially one alignment transfer for
2860 * each of those entries.
2861 */
2862 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2863 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2864 if (!host->adma_desc || !host->align_buffer) {
2865 kfree(host->adma_desc);
2866 kfree(host->align_buffer);
a3c76eb9 2867 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2868 "buffers. Falling back to standard DMA.\n",
2869 mmc_hostname(mmc));
2870 host->flags &= ~SDHCI_USE_ADMA;
2871 }
2872 }
2873
7659150c
PO		 2874 /*
2875 * If we use DMA, then it's up to the caller to set the DMA
2876 * mask, but PIO does not need the hw shim so we set a new
2877 * mask here in that case.
2878 */
a13abc7b 2879 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2880 host->dma_mask = DMA_BIT_MASK(64);
2881 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2882 }
d129bceb 2883
c4687d5f 2884 if (host->version >= SDHCI_SPEC_300)
f2119df6 2885 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2886 >> SDHCI_CLOCK_BASE_SHIFT;
2887 else
f2119df6 2888 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2889 >> SDHCI_CLOCK_BASE_SHIFT;
2890
4240ff0a 2891 host->max_clk *= 1000000;
f27f47ef
AV		 2892 if (host->max_clk == 0 || host->quirks &
2893 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2894 if (!host->ops->get_max_clock) {
a3c76eb9 2895 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2896 "frequency.\n", mmc_hostname(mmc));
2897 return -ENODEV;
2898 }
2899 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2900 }
d129bceb 2901
c3ed3877
AN		 2902 /*
2903 * In case of Host Controller v3.00, find out whether clock
2904 * multiplier is supported.
2905 */
2906 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2907 SDHCI_CLOCK_MUL_SHIFT;
2908
2909 /*
2910 * In case the value in Clock Multiplier is 0, then programmable
2911 * clock mode is not supported, otherwise the actual clock
2912 * multiplier is one more than the value of Clock Multiplier
2913 * in the Capabilities Register.
2914 */
2915 if (host->clk_mul)
2916 host->clk_mul += 1;
2917
d129bceb
PO		 2918 /*
2919 * Set host parameters.
2920 */
2921 mmc->ops = &sdhci_ops;
c3ed3877 2922 mmc->f_max = host->max_clk;
ce5f036b 2923 if (host->ops->get_min_clock)
a9e58f25 2924 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2925 else if (host->version >= SDHCI_SPEC_300) {
2926 if (host->clk_mul) {
2927 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2928 mmc->f_max = host->max_clk * host->clk_mul;
2929 } else
2930 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2931 } else
0397526d 2932 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2933
272308ca
AS		 2934 host->timeout_clk =
2935 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2936 if (host->timeout_clk == 0) {
2937 if (host->ops->get_timeout_clock) {
2938 host->timeout_clk = host->ops->get_timeout_clock(host);
2939 } else if (!(host->quirks &
2940 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2941 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2942 "frequency.\n", mmc_hostname(mmc));
2943 return -ENODEV;
2944 }
2945 }
2946 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2947 host->timeout_clk *= 1000;
2948
2949 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2950 host->timeout_clk = mmc->f_max / 1000;
272308ca 2951
68eb80e0 2952 mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
58d1246d 2953
e89d456f 2954 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 2955 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 2956
2957 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2958 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2959
8edf6371 2960 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2961 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2962 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2963 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2964 host->flags |= SDHCI_AUTO_CMD23;
2965 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2966 } else {
2967 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2968 }
2969
15ec4461
PR		 2970 /*
2971 * A controller may support 8-bit width, but the board itself
2972 * might not have the pins brought out. Boards that support
2973 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2974 * their platform code before calling sdhci_add_host(), and we
2975 * won't assume 8-bit width for hosts without that CAP.
2976 */
5fe23c7f 2977 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2978 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2979
63ef5d8c
JH		 2980 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2981 mmc->caps &= ~MMC_CAP_CMD23;
2982
f2119df6 2983 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2984 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2985
176d1ed4 2986 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2987 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2988 mmc->caps |= MMC_CAP_NEEDS_POLL;
2989
6231f3de 2990 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
462849aa 2991 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2992 if (IS_ERR_OR_NULL(host->vqmmc)) {
2993 if (PTR_ERR(host->vqmmc) < 0) {
2994 pr_info("%s: no vqmmc regulator found\n",
2995 mmc_hostname(mmc));
2996 host->vqmmc = NULL;
2997 }
8363c374 2998 } else {
a3361aba 2999 ret = regulator_enable(host->vqmmc);
cec2e216
KL		 3000 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
3001 1950000))
8363c374
KL		 3002 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3003 SDHCI_SUPPORT_SDR50 |
3004 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3005 if (ret) {
3006 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3007 mmc_hostname(mmc), ret);
3008 host->vqmmc = NULL;
3009 }
8363c374 3010 }
6231f3de 3011
6a66180a
DD		 3012 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3013 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3014 SDHCI_SUPPORT_DDR50);
3015
4188bba0
AC		 3016 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3017 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3018 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3019 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3020
3021 /* SDR104 supports also implies SDR50 support */
156e14b1 3022 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3023 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3024 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3025 * field can be promoted to support HS200.
3026 */
13868bf2
DC		 3027 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3028 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3029 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3030 mmc->caps |= MMC_CAP_UHS_SDR50;
3031
9107ebbf
MC		 3032 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3033 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3034 mmc->caps |= MMC_CAP_UHS_DDR50;
3035
069c9f14 3036 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3037 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3038 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3039
156e14b1 3040 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3041 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3042 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3043
d6d50a15
AN		 3044 /* Driver Type(s) (A, C, D) supported by the host */
3045 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3046 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3047 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3048 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3049 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3050 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3051
cf2b5eea
AN		 3052 /* Initial value for re-tuning timer count */
3053 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3054 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3055
3056 /*
3057 * In case Re-tuning Timer is not disabled, the actual value of
3058 * re-tuning timer will be 2 ^ (n - 1).
3059 */
3060 if (host->tuning_count)
3061 host->tuning_count = 1 << (host->tuning_count - 1);
3062
3063 /* Re-tuning mode supported by the Host Controller */
3064 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3065 SDHCI_RETUNING_MODE_SHIFT;
3066
8f230f45 3067 ocr_avail = 0;
bad37e1a 3068
462849aa 3069 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
657d5982
KL		 3070 if (IS_ERR_OR_NULL(host->vmmc)) {
3071 if (PTR_ERR(host->vmmc) < 0) {
3072 pr_info("%s: no vmmc regulator found\n",
3073 mmc_hostname(mmc));
3074 host->vmmc = NULL;
3075 }
8363c374 3076 }
bad37e1a 3077
68737043 3078#ifdef CONFIG_REGULATOR
a4f8f257
MS		 3079 /*
3080 * Voltage range check makes sense only if regulator reports
3081 * any voltage value.
3082 */
3083 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
cec2e216
KL		 3084 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3085 3600000);
68737043
PR		 3086 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3087 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 3088 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3089 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 3090 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3091 1950000);
68737043
PR		 3092 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3093 caps[0] &= ~SDHCI_CAN_VDD_180;
3094 }
3095#endif /* CONFIG_REGULATOR */
3096
f2119df6
AN		 3097 /*
3098 * According to SD Host Controller spec v3.00, if the Host System
3099 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3100 * the value is meaningful only if Voltage Support in the Capabilities
3101 * register is set. The actual current value is 4 times the register
3102 * value.
3103 */
3104 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 3105 if (!max_current_caps && host->vmmc) {
3106 u32 curr = regulator_get_current_limit(host->vmmc);
3107 if (curr > 0) {
3108
3109 /* convert to SDHCI_MAX_CURRENT format */
3110 curr = curr/1000; /* convert to mA */
3111 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3112
3113 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3114 max_current_caps =
3115 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3116 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3117 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3118 }
3119 }
f2119df6
AN		 3120
3121 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3122 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3123
55c4665e 3124 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3125 SDHCI_MAX_CURRENT_330_MASK) >>
3126 SDHCI_MAX_CURRENT_330_SHIFT) *
3127 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3128 }
3129 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3130 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3131
55c4665e 3132 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3133 SDHCI_MAX_CURRENT_300_MASK) >>
3134 SDHCI_MAX_CURRENT_300_SHIFT) *
3135 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3136 }
3137 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3138 ocr_avail |= MMC_VDD_165_195;
3139
55c4665e 3140 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3141 SDHCI_MAX_CURRENT_180_MASK) >>
3142 SDHCI_MAX_CURRENT_180_SHIFT) *
3143 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3144 }
3145
c0b887b6
HZ		 3146 if (host->ocr_mask)
3147 ocr_avail = host->ocr_mask;
3148
8f230f45
TI		 3149 mmc->ocr_avail = ocr_avail;
3150 mmc->ocr_avail_sdio = ocr_avail;
3151 if (host->ocr_avail_sdio)
3152 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3153 mmc->ocr_avail_sd = ocr_avail;
3154 if (host->ocr_avail_sd)
3155 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3156 else /* normal SD controllers don't support 1.8V */
3157 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3158 mmc->ocr_avail_mmc = ocr_avail;
3159 if (host->ocr_avail_mmc)
3160 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3161
3162 if (mmc->ocr_avail == 0) {
a3c76eb9 3163 pr_err("%s: Hardware doesn't report any "
b69c9058 3164 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3165 return -ENODEV;
146ad66e
PO		 3166 }
3167
d129bceb
PO		 3168 spin_lock_init(&host->lock);
3169
3170 /*
2134a922
PO		 3171 * Maximum number of segments. Depends on if the hardware
3172 * can do scatter/gather or not.
d129bceb 3173 */
2134a922 3174 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3175 mmc->max_segs = 128;
a13abc7b 3176 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3177 mmc->max_segs = 1;
2134a922 3178 else /* PIO */
a36274e0 3179 mmc->max_segs = 128;
d129bceb
PO		 3180
3181 /*
bab76961 3182 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3183 * size (512KiB).
d129bceb 3184 */
55db890a 3185 mmc->max_req_size = 524288;
d129bceb
PO		 3186
3187 /*
3188 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3189 * of bytes. When doing hardware scatter/gather, each entry cannot
3190 * be larger than 64 KiB though.
d129bceb 3191 */
30652aa3
OJ		 3192 if (host->flags & SDHCI_USE_ADMA) {
3193 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3194 mmc->max_seg_size = 65535;
3195 else
3196 mmc->max_seg_size = 65536;
3197 } else {
2134a922 3198 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3199 }
d129bceb 3200
fe4a3c7a
PO		 3201 /*
3202 * Maximum block size. This varies from controller to controller and
3203 * is specified in the capabilities register.
3204 */
0633f654
AV		 3205 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3206 mmc->max_blk_size = 2;
3207 } else {
f2119df6 3208 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3209 SDHCI_MAX_BLOCK_SHIFT;
3210 if (mmc->max_blk_size >= 3) {
a3c76eb9 3211 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3212 "assuming 512 bytes\n", mmc_hostname(mmc));
3213 mmc->max_blk_size = 0;
3214 }
3215 }
3216
3217 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3218
55db890a
PO		 3219 /*
3220 * Maximum block count.
3221 */
1388eefd 3222 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3223
d129bceb
PO		 3224 /*
3225 * Init tasklets.
3226 */
3227 tasklet_init(&host->card_tasklet,
3228 sdhci_tasklet_card, (unsigned long)host);
3229 tasklet_init(&host->finish_tasklet,
3230 sdhci_tasklet_finish, (unsigned long)host);
3231
e4cad1b5 3232 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3233
cf2b5eea 3234 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3235 init_waitqueue_head(&host->buf_ready_int);
3236
cf2b5eea
AN		 3237 /* Initialize re-tuning timer */
3238 init_timer(&host->tuning_timer);
3239 host->tuning_timer.data = (unsigned long)host;
3240 host->tuning_timer.function = sdhci_tuning_timer;
3241 }
3242
2af502ca
SG		 3243 sdhci_init(host, 0);
3244
781e989c
RK		 3245 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3246 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3247 if (ret) {
3248 pr_err("%s: Failed to request IRQ %d: %d\n",
3249 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3250 goto untasklet;
0fc81ee3 3251 }
d129bceb 3252
d129bceb
PO		 3253#ifdef CONFIG_MMC_DEBUG
3254 sdhci_dumpregs(host);
3255#endif
3256
f9134319 3257#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3258 snprintf(host->led_name, sizeof(host->led_name),
3259 "%s::", mmc_hostname(mmc));
3260 host->led.name = host->led_name;
2f730fec
PO		 3261 host->led.brightness = LED_OFF;
3262 host->led.default_trigger = mmc_hostname(mmc);
3263 host->led.brightness_set = sdhci_led_control;
3264
b8c86fc5 3265 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3266 if (ret) {
3267 pr_err("%s: Failed to register LED device: %d\n",
3268 mmc_hostname(mmc), ret);
2f730fec 3269 goto reset;
0fc81ee3 3270 }
2f730fec
PO		 3271#endif
3272
5f25a66f
PO		 3273 mmiowb();
3274
d129bceb
PO		 3275 mmc_add_host(mmc);
3276
a3c76eb9 3277 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3278 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3279 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3280 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3281
7260cf5e
AV		 3282 sdhci_enable_card_detection(host);
3283
d129bceb
PO		 3284 return 0;
3285
f9134319 3286#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3287reset:
3288 sdhci_reset(host, SDHCI_RESET_ALL);
b0a8dece 3289 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2f730fec
PO		 3290 free_irq(host->irq, host);
3291#endif
8ef1a143 3292untasklet:
d129bceb
PO		 3293 tasklet_kill(&host->card_tasklet);
3294 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3295
3296 return ret;
3297}
3298
b8c86fc5 3299EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3300
1e72859e 3301void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3302{
1e72859e
PO		 3303 unsigned long flags;
3304
3305 if (dead) {
3306 spin_lock_irqsave(&host->lock, flags);
3307
3308 host->flags |= SDHCI_DEVICE_DEAD;
3309
3310 if (host->mrq) {
a3c76eb9 3311 pr_err("%s: Controller removed during "
1e72859e
PO		 3312 " transfer!\n", mmc_hostname(host->mmc));
3313
3314 host->mrq->cmd->error = -ENOMEDIUM;
3315 tasklet_schedule(&host->finish_tasklet);
3316 }
3317
3318 spin_unlock_irqrestore(&host->lock, flags);
3319 }
3320
7260cf5e
AV		 3321 sdhci_disable_card_detection(host);
3322
b8c86fc5 3323 mmc_remove_host(host->mmc);
d129bceb 3324
f9134319 3325#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3326 led_classdev_unregister(&host->led);
3327#endif
3328
1e72859e
PO		 3329 if (!dead)
3330 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 3331
b0a8dece 3332 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
d129bceb
PO		 3333 free_irq(host->irq, host);
3334
3335 del_timer_sync(&host->timer);
3336
3337 tasklet_kill(&host->card_tasklet);
3338 tasklet_kill(&host->finish_tasklet);
2134a922 3339
77dcb3f4
PR		 3340 if (host->vmmc) {
3341 regulator_disable(host->vmmc);
9bea3c85 3342 regulator_put(host->vmmc);
77dcb3f4 3343 }
9bea3c85 3344
6231f3de
PR		 3345 if (host->vqmmc) {
3346 regulator_disable(host->vqmmc);
3347 regulator_put(host->vqmmc);
3348 }
3349
2134a922
PO		 3350 kfree(host->adma_desc);
3351 kfree(host->align_buffer);
3352
3353 host->adma_desc = NULL;
3354 host->align_buffer = NULL;
d129bceb
PO		 3355}
3356
b8c86fc5 3357EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3358
b8c86fc5 3359void sdhci_free_host(struct sdhci_host *host)
d129bceb 3360{
b8c86fc5 3361 mmc_free_host(host->mmc);
d129bceb
PO		 3362}
3363
b8c86fc5 3364EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3365
3366/*****************************************************************************\
3367 * *
3368 * Driver init/exit *
3369 * *
3370\*****************************************************************************/
3371
3372static int __init sdhci_drv_init(void)
3373{
a3c76eb9 3374 pr_info(DRIVER_NAME
52fbf9c9 3375 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3376 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3377
b8c86fc5 3378 return 0;
d129bceb
PO		 3379}
3380
3381static void __exit sdhci_drv_exit(void)
3382{
d129bceb
PO		 3383}
3384
3385module_init(sdhci_drv_init);
3386module_exit(sdhci_drv_exit);
3387
df673b22 3388module_param(debug_quirks, uint, 0444);
66fd8ad5 3389module_param(debug_quirks2, uint, 0444);
67435274 3390
32710e8f 3391MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3392MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3393MODULE_LICENSE("GPL");
67435274 3394
df673b22 3395MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3396MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux 6.x block layer and io_uring tree(s)