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mmc: host: mxcmmc: Simplify a trivial if-return sequence
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
f9134319
PO		 41#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43#define SDHCI_USE_LEDS_CLASS
44#endif
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
d129bceb 53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
348487cb
HC		 56static int sdhci_pre_dma_transfer(struct sdhci_host *host,
57 struct mmc_data *data,
58 struct sdhci_host_next *next);
04e079cf 59static int sdhci_do_get_cd(struct sdhci_host *host);
d129bceb 60
162d6f98 61#ifdef CONFIG_PM
66fd8ad5
AH		 62static int sdhci_runtime_pm_get(struct sdhci_host *host);
63static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 64static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
65static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 66#else
67static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
68{
69 return 0;
70}
71static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
72{
73 return 0;
74}
f0710a55
AH		 75static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
76{
77}
78static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
79{
80}
66fd8ad5
AH		 81#endif
82
d129bceb
PO		 83static void sdhci_dumpregs(struct sdhci_host *host)
84{
a3c76eb9 85 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 86 mmc_hostname(host->mmc));
d129bceb 87
a3c76eb9 88 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 89 sdhci_readl(host, SDHCI_DMA_ADDRESS),
90 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 91 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 92 sdhci_readw(host, SDHCI_BLOCK_SIZE),
93 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 94 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 95 sdhci_readl(host, SDHCI_ARGUMENT),
96 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 97 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 98 sdhci_readl(host, SDHCI_PRESENT_STATE),
99 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 100 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 101 sdhci_readb(host, SDHCI_POWER_CONTROL),
102 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 103 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 104 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
105 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 106 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 107 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
108 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 109 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 110 sdhci_readl(host, SDHCI_INT_ENABLE),
111 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 112 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 113 sdhci_readw(host, SDHCI_ACMD12_ERR),
114 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 115 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 116 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 117 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 118 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 119 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 120 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 121 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 122 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 123
e57a5f61
AH		 124 if (host->flags & SDHCI_USE_ADMA) {
125 if (host->flags & SDHCI_USE_64_BIT_DMA)
126 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
127 readl(host->ioaddr + SDHCI_ADMA_ERROR),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
130 else
131 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
132 readl(host->ioaddr + SDHCI_ADMA_ERROR),
133 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
134 }
be3f4ae0 135
a3c76eb9 136 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 137}
138
139/*****************************************************************************\
140 * *
141 * Low level functions *
142 * *
143\*****************************************************************************/
144
7260cf5e
AV		 145static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
146{
5b4f1f6c 147 u32 present;
7260cf5e 148
c79396c1 149 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 150 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 151 return;
152
5b4f1f6c
RK		 153 if (enable) {
154 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
155 SDHCI_CARD_PRESENT;
d25928d1 156
5b4f1f6c
RK		 157 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
158 SDHCI_INT_CARD_INSERT;
159 } else {
160 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
161 }
b537f94c
RK		 162
163 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
164 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 165}
166
167static void sdhci_enable_card_detection(struct sdhci_host *host)
168{
169 sdhci_set_card_detection(host, true);
170}
171
172static void sdhci_disable_card_detection(struct sdhci_host *host)
173{
174 sdhci_set_card_detection(host, false);
175}
176
03231f9b 177void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 178{
e16514d8 179 unsigned long timeout;
393c1a34 180
4e4141a5 181 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 182
f0710a55 183 if (mask & SDHCI_RESET_ALL) {
d129bceb 184 host->clock = 0;
f0710a55
AH		 185 /* Reset-all turns off SD Bus Power */
186 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
187 sdhci_runtime_pm_bus_off(host);
188 }
d129bceb 189
e16514d8
PO		 190 /* Wait max 100 ms */
191 timeout = 100;
192
193 /* hw clears the bit when it's done */
4e4141a5 194 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 195 if (timeout == 0) {
a3c76eb9 196 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 197 mmc_hostname(host->mmc), (int)mask);
198 sdhci_dumpregs(host);
199 return;
200 }
201 timeout--;
202 mdelay(1);
d129bceb 203 }
03231f9b
RK		 204}
205EXPORT_SYMBOL_GPL(sdhci_reset);
206
207static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
208{
209 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
210 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
211 SDHCI_CARD_PRESENT))
212 return;
213 }
063a9dbb 214
03231f9b 215 host->ops->reset(host, mask);
393c1a34 216
da91a8f9
RK		 217 if (mask & SDHCI_RESET_ALL) {
218 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
219 if (host->ops->enable_dma)
220 host->ops->enable_dma(host);
221 }
222
223 /* Resetting the controller clears many */
224 host->preset_enabled = false;
3abc1e80 225 }
d129bceb
PO		 226}
227
2f4cbb3d
NP		 228static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
229
230static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 231{
2f4cbb3d 232 if (soft)
03231f9b 233 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 234 else
03231f9b 235 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 236
b537f94c
RK		 237 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
238 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
239 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
240 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
241 SDHCI_INT_RESPONSE;
242
243 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
244 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 245
246 if (soft) {
247 /* force clock reconfiguration */
248 host->clock = 0;
249 sdhci_set_ios(host->mmc, &host->mmc->ios);
250 }
7260cf5e 251}
d129bceb 252
7260cf5e
AV		 253static void sdhci_reinit(struct sdhci_host *host)
254{
2f4cbb3d 255 sdhci_init(host, 0);
7260cf5e 256 sdhci_enable_card_detection(host);
d129bceb
PO		 257}
258
259static void sdhci_activate_led(struct sdhci_host *host)
260{
261 u8 ctrl;
262
4e4141a5 263 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 264 ctrl |= SDHCI_CTRL_LED;
4e4141a5 265 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 266}
267
268static void sdhci_deactivate_led(struct sdhci_host *host)
269{
270 u8 ctrl;
271
4e4141a5 272 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 273 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 274 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 275}
276
f9134319 277#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 278static void sdhci_led_control(struct led_classdev *led,
279 enum led_brightness brightness)
280{
281 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
282 unsigned long flags;
283
284 spin_lock_irqsave(&host->lock, flags);
285
66fd8ad5
AH		 286 if (host->runtime_suspended)
287 goto out;
288
2f730fec
PO		 289 if (brightness == LED_OFF)
290 sdhci_deactivate_led(host);
291 else
292 sdhci_activate_led(host);
66fd8ad5 293out:
2f730fec
PO		 294 spin_unlock_irqrestore(&host->lock, flags);
295}
296#endif
297
d129bceb
PO		 298/*****************************************************************************\
299 * *
300 * Core functions *
301 * *
302\*****************************************************************************/
303
a406f5a3 304static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 305{
7659150c
PO		 306 unsigned long flags;
307 size_t blksize, len, chunk;
7244b85b 308 u32 uninitialized_var(scratch);
7659150c 309 u8 *buf;
d129bceb 310
a406f5a3 311 DBG("PIO reading\n");
d129bceb 312
a406f5a3 313 blksize = host->data->blksz;
7659150c 314 chunk = 0;
d129bceb 315
7659150c 316 local_irq_save(flags);
d129bceb 317
a406f5a3 318 while (blksize) {
7659150c
PO		 319 if (!sg_miter_next(&host->sg_miter))
320 BUG();
d129bceb 321
7659150c 322 len = min(host->sg_miter.length, blksize);
d129bceb 323
7659150c
PO		 324 blksize -= len;
325 host->sg_miter.consumed = len;
14d836e7 326
7659150c 327 buf = host->sg_miter.addr;
d129bceb 328
7659150c
PO		 329 while (len) {
330 if (chunk == 0) {
4e4141a5 331 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 332 chunk = 4;
a406f5a3 333 }
7659150c
PO		 334
335 *buf = scratch & 0xFF;
336
337 buf++;
338 scratch >>= 8;
339 chunk--;
340 len--;
d129bceb 341 }
a406f5a3 342 }
7659150c
PO		 343
344 sg_miter_stop(&host->sg_miter);
345
346 local_irq_restore(flags);
a406f5a3 347}
d129bceb 348
a406f5a3
PO		 349static void sdhci_write_block_pio(struct sdhci_host *host)
350{
7659150c
PO		 351 unsigned long flags;
352 size_t blksize, len, chunk;
353 u32 scratch;
354 u8 *buf;
d129bceb 355
a406f5a3
PO		 356 DBG("PIO writing\n");
357
358 blksize = host->data->blksz;
7659150c
PO		 359 chunk = 0;
360 scratch = 0;
d129bceb 361
7659150c 362 local_irq_save(flags);
d129bceb 363
a406f5a3 364 while (blksize) {
7659150c
PO		 365 if (!sg_miter_next(&host->sg_miter))
366 BUG();
a406f5a3 367
7659150c
PO		 368 len = min(host->sg_miter.length, blksize);
369
370 blksize -= len;
371 host->sg_miter.consumed = len;
372
373 buf = host->sg_miter.addr;
d129bceb 374
7659150c
PO		 375 while (len) {
376 scratch |= (u32)*buf << (chunk * 8);
377
378 buf++;
379 chunk++;
380 len--;
381
382 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 383 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 384 chunk = 0;
385 scratch = 0;
d129bceb 386 }
d129bceb
PO		 387 }
388 }
7659150c
PO		 389
390 sg_miter_stop(&host->sg_miter);
391
392 local_irq_restore(flags);
a406f5a3
PO		 393}
394
395static void sdhci_transfer_pio(struct sdhci_host *host)
396{
397 u32 mask;
398
399 BUG_ON(!host->data);
400
7659150c 401 if (host->blocks == 0)
a406f5a3
PO		 402 return;
403
404 if (host->data->flags & MMC_DATA_READ)
405 mask = SDHCI_DATA_AVAILABLE;
406 else
407 mask = SDHCI_SPACE_AVAILABLE;
408
4a3cba32
PO		 409 /*
410 * Some controllers (JMicron JMB38x) mess up the buffer bits
411 * for transfers < 4 bytes. As long as it is just one block,
412 * we can ignore the bits.
413 */
414 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
415 (host->data->blocks == 1))
416 mask = ~0;
417
4e4141a5 418 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 419 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
420 udelay(100);
421
a406f5a3
PO		 422 if (host->data->flags & MMC_DATA_READ)
423 sdhci_read_block_pio(host);
424 else
425 sdhci_write_block_pio(host);
d129bceb 426
7659150c
PO		 427 host->blocks--;
428 if (host->blocks == 0)
a406f5a3 429 break;
a406f5a3 430 }
d129bceb 431
a406f5a3 432 DBG("PIO transfer complete.\n");
d129bceb
PO		 433}
434
2134a922
PO		 435static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
436{
437 local_irq_save(*flags);
482fce99 438 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 439}
440
441static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
442{
482fce99 443 kunmap_atomic(buffer);
2134a922
PO		 444 local_irq_restore(*flags);
445}
446
e57a5f61
AH		 447static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
448 dma_addr_t addr, int len, unsigned cmd)
118cd17d 449{
e57a5f61 450 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 451
e57a5f61 452 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 453 dma_desc->cmd = cpu_to_le16(cmd);
454 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 455 dma_desc->addr_lo = cpu_to_le32((u32)addr);
456
457 if (host->flags & SDHCI_USE_64_BIT_DMA)
458 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 459}
460
b5ffa674
AH		 461static void sdhci_adma_mark_end(void *desc)
462{
e57a5f61 463 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 464
e57a5f61 465 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 466 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 467}
468
8f1934ce 469static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 470 struct mmc_data *data)
471{
472 int direction;
473
1c3d5f6d
AH		 474 void *desc;
475 void *align;
2134a922
PO		 476 dma_addr_t addr;
477 dma_addr_t align_addr;
478 int len, offset;
479
480 struct scatterlist *sg;
481 int i;
482 char *buffer;
483 unsigned long flags;
484
485 /*
486 * The spec does not specify endianness of descriptor table.
487 * We currently guess that it is LE.
488 */
489
490 if (data->flags & MMC_DATA_READ)
491 direction = DMA_FROM_DEVICE;
492 else
493 direction = DMA_TO_DEVICE;
494
2134a922 495 host->align_addr = dma_map_single(mmc_dev(host->mmc),
76fe379a 496 host->align_buffer, host->align_buffer_sz, direction);
8d8bb39b 497 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 498 goto fail;
76fe379a 499 BUG_ON(host->align_addr & host->align_mask);
2134a922 500
348487cb
HC		 501 host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
502 if (host->sg_count < 0)
8f1934ce 503 goto unmap_align;
2134a922 504
4efaa6fb 505 desc = host->adma_table;
2134a922
PO		 506 align = host->align_buffer;
507
508 align_addr = host->align_addr;
509
510 for_each_sg(data->sg, sg, host->sg_count, i) {
511 addr = sg_dma_address(sg);
512 len = sg_dma_len(sg);
513
514 /*
515 * The SDHCI specification states that ADMA
516 * addresses must be 32-bit aligned. If they
517 * aren't, then we use a bounce buffer for
518 * the (up to three) bytes that screw up the
519 * alignment.
520 */
76fe379a
AH		 521 offset = (host->align_sz - (addr & host->align_mask)) &
522 host->align_mask;
2134a922
PO		 523 if (offset) {
524 if (data->flags & MMC_DATA_WRITE) {
525 buffer = sdhci_kmap_atomic(sg, &flags);
526 memcpy(align, buffer, offset);
527 sdhci_kunmap_atomic(buffer, &flags);
528 }
529
118cd17d 530 /* tran, valid */
e57a5f61 531 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 532 ADMA2_TRAN_VALID);
2134a922
PO		 533
534 BUG_ON(offset > 65536);
535
76fe379a
AH		 536 align += host->align_sz;
537 align_addr += host->align_sz;
2134a922 538
76fe379a 539 desc += host->desc_sz;
2134a922
PO		 540
541 addr += offset;
542 len -= offset;
543 }
544
2134a922
PO		 545 BUG_ON(len > 65536);
546
118cd17d 547 /* tran, valid */
e57a5f61 548 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
76fe379a 549 desc += host->desc_sz;
2134a922
PO		 550
551 /*
552 * If this triggers then we have a calculation bug
553 * somewhere. :/
554 */
76fe379a 555 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 556 }
557
70764a90
TA		 558 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
559 /*
560 * Mark the last descriptor as the terminating descriptor
561 */
4efaa6fb 562 if (desc != host->adma_table) {
76fe379a 563 desc -= host->desc_sz;
b5ffa674 564 sdhci_adma_mark_end(desc);
70764a90
TA		 565 }
566 } else {
567 /*
568 * Add a terminating entry.
569 */
2134a922 570
70764a90 571 /* nop, end, valid */
e57a5f61 572 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 573 }
2134a922
PO		 574
575 /*
576 * Resync align buffer as we might have changed it.
577 */
578 if (data->flags & MMC_DATA_WRITE) {
579 dma_sync_single_for_device(mmc_dev(host->mmc),
76fe379a 580 host->align_addr, host->align_buffer_sz, direction);
2134a922
PO		 581 }
582
8f1934ce
PO		 583 return 0;
584
8f1934ce
PO		 585unmap_align:
586 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 587 host->align_buffer_sz, direction);
8f1934ce
PO		 588fail:
589 return -EINVAL;
2134a922
PO		 590}
591
592static void sdhci_adma_table_post(struct sdhci_host *host,
593 struct mmc_data *data)
594{
595 int direction;
596
597 struct scatterlist *sg;
598 int i, size;
1c3d5f6d 599 void *align;
2134a922
PO		 600 char *buffer;
601 unsigned long flags;
de0b65a7 602 bool has_unaligned;
2134a922
PO		 603
604 if (data->flags & MMC_DATA_READ)
605 direction = DMA_FROM_DEVICE;
606 else
607 direction = DMA_TO_DEVICE;
608
2134a922 609 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 610 host->align_buffer_sz, direction);
2134a922 611
de0b65a7
RK		 612 /* Do a quick scan of the SG list for any unaligned mappings */
613 has_unaligned = false;
614 for_each_sg(data->sg, sg, host->sg_count, i)
76fe379a 615 if (sg_dma_address(sg) & host->align_mask) {
de0b65a7
RK		 616 has_unaligned = true;
617 break;
618 }
619
620 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 621 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
622 data->sg_len, direction);
623
624 align = host->align_buffer;
625
626 for_each_sg(data->sg, sg, host->sg_count, i) {
76fe379a
AH		 627 if (sg_dma_address(sg) & host->align_mask) {
628 size = host->align_sz -
629 (sg_dma_address(sg) & host->align_mask);
2134a922
PO		 630
631 buffer = sdhci_kmap_atomic(sg, &flags);
632 memcpy(buffer, align, size);
633 sdhci_kunmap_atomic(buffer, &flags);
634
76fe379a 635 align += host->align_sz;
2134a922
PO		 636 }
637 }
638 }
639
348487cb
HC		 640 if (!data->host_cookie)
641 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
642 data->sg_len, direction);
2134a922
PO		 643}
644
a3c7778f 645static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 646{
1c8cde92 647 u8 count;
a3c7778f 648 struct mmc_data *data = cmd->data;
1c8cde92 649 unsigned target_timeout, current_timeout;
d129bceb 650
ee53ab5d
PO		 651 /*
652 * If the host controller provides us with an incorrect timeout
653 * value, just skip the check and use 0xE. The hardware may take
654 * longer to time out, but that's much better than having a too-short
655 * timeout value.
656 */
11a2f1b7 657 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 658 return 0xE;
e538fbe8 659
a3c7778f 660 /* Unspecified timeout, assume max */
1d4d7744 661 if (!data && !cmd->busy_timeout)
a3c7778f 662 return 0xE;
d129bceb 663
a3c7778f
AW		 664 /* timeout in us */
665 if (!data)
1d4d7744 666 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 667 else {
668 target_timeout = data->timeout_ns / 1000;
669 if (host->clock)
670 target_timeout += data->timeout_clks / host->clock;
671 }
81b39802 672
1c8cde92
PO		 673 /*
674 * Figure out needed cycles.
675 * We do this in steps in order to fit inside a 32 bit int.
676 * The first step is the minimum timeout, which will have a
677 * minimum resolution of 6 bits:
678 * (1) 2^13*1000 > 2^22,
679 * (2) host->timeout_clk < 2^16
680 * =>
681 * (1) / (2) > 2^6
682 */
683 count = 0;
684 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
685 while (current_timeout < target_timeout) {
686 count++;
687 current_timeout <<= 1;
688 if (count >= 0xF)
689 break;
690 }
691
692 if (count >= 0xF) {
09eeff52
CB		 693 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
694 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 695 count = 0xE;
696 }
697
ee53ab5d
PO		 698 return count;
699}
700
6aa943ab
AV		 701static void sdhci_set_transfer_irqs(struct sdhci_host *host)
702{
703 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
704 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
705
706 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 707 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 708 else
b537f94c
RK		 709 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
710
711 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
712 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 713}
714
b45e668a 715static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 716{
717 u8 count;
b45e668a
AD		 718
719 if (host->ops->set_timeout) {
720 host->ops->set_timeout(host, cmd);
721 } else {
722 count = sdhci_calc_timeout(host, cmd);
723 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
724 }
725}
726
727static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
728{
2134a922 729 u8 ctrl;
a3c7778f 730 struct mmc_data *data = cmd->data;
8f1934ce 731 int ret;
ee53ab5d
PO		 732
733 WARN_ON(host->data);
734
b45e668a
AD		 735 if (data || (cmd->flags & MMC_RSP_BUSY))
736 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 737
738 if (!data)
ee53ab5d
PO		 739 return;
740
741 /* Sanity checks */
742 BUG_ON(data->blksz * data->blocks > 524288);
743 BUG_ON(data->blksz > host->mmc->max_blk_size);
744 BUG_ON(data->blocks > 65535);
745
746 host->data = data;
747 host->data_early = 0;
f6a03cbf 748 host->data->bytes_xfered = 0;
ee53ab5d 749
a13abc7b 750 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 751 host->flags |= SDHCI_REQ_USE_DMA;
752
2134a922
PO		 753 /*
754 * FIXME: This doesn't account for merging when mapping the
755 * scatterlist.
756 */
757 if (host->flags & SDHCI_REQ_USE_DMA) {
758 int broken, i;
759 struct scatterlist *sg;
760
761 broken = 0;
762 if (host->flags & SDHCI_USE_ADMA) {
763 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
764 broken = 1;
765 } else {
766 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
767 broken = 1;
768 }
769
770 if (unlikely(broken)) {
771 for_each_sg(data->sg, sg, data->sg_len, i) {
772 if (sg->length & 0x3) {
773 DBG("Reverting to PIO because of "
774 "transfer size (%d)\n",
775 sg->length);
776 host->flags &= ~SDHCI_REQ_USE_DMA;
777 break;
778 }
779 }
780 }
c9fddbc4
PO		 781 }
782
783 /*
784 * The assumption here being that alignment is the same after
785 * translation to device address space.
786 */
2134a922
PO		 787 if (host->flags & SDHCI_REQ_USE_DMA) {
788 int broken, i;
789 struct scatterlist *sg;
790
791 broken = 0;
792 if (host->flags & SDHCI_USE_ADMA) {
793 /*
794 * As we use 3 byte chunks to work around
795 * alignment problems, we need to check this
796 * quirk.
797 */
798 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
799 broken = 1;
800 } else {
801 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
802 broken = 1;
803 }
804
805 if (unlikely(broken)) {
806 for_each_sg(data->sg, sg, data->sg_len, i) {
807 if (sg->offset & 0x3) {
808 DBG("Reverting to PIO because of "
809 "bad alignment\n");
810 host->flags &= ~SDHCI_REQ_USE_DMA;
811 break;
812 }
813 }
814 }
815 }
816
8f1934ce
PO		 817 if (host->flags & SDHCI_REQ_USE_DMA) {
818 if (host->flags & SDHCI_USE_ADMA) {
819 ret = sdhci_adma_table_pre(host, data);
820 if (ret) {
821 /*
822 * This only happens when someone fed
823 * us an invalid request.
824 */
825 WARN_ON(1);
ebd6d357 826 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 827 } else {
4e4141a5
AV		 828 sdhci_writel(host, host->adma_addr,
829 SDHCI_ADMA_ADDRESS);
e57a5f61
AH		 830 if (host->flags & SDHCI_USE_64_BIT_DMA)
831 sdhci_writel(host,
832 (u64)host->adma_addr >> 32,
833 SDHCI_ADMA_ADDRESS_HI);
8f1934ce
PO		 834 }
835 } else {
c8b3e02e 836 int sg_cnt;
8f1934ce 837
348487cb 838 sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
c8b3e02e 839 if (sg_cnt == 0) {
8f1934ce
PO		 840 /*
841 * This only happens when someone fed
842 * us an invalid request.
843 */
844 WARN_ON(1);
ebd6d357 845 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 846 } else {
719a61b4 847 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 848 sdhci_writel(host, sg_dma_address(data->sg),
849 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 850 }
851 }
852 }
853
2134a922
PO		 854 /*
855 * Always adjust the DMA selection as some controllers
856 * (e.g. JMicron) can't do PIO properly when the selection
857 * is ADMA.
858 */
859 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 860 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 861 ctrl &= ~SDHCI_CTRL_DMA_MASK;
862 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 863 (host->flags & SDHCI_USE_ADMA)) {
864 if (host->flags & SDHCI_USE_64_BIT_DMA)
865 ctrl |= SDHCI_CTRL_ADMA64;
866 else
867 ctrl |= SDHCI_CTRL_ADMA32;
868 } else {
2134a922 869 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 870 }
4e4141a5 871 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 872 }
873
8f1934ce 874 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 875 int flags;
876
877 flags = SG_MITER_ATOMIC;
878 if (host->data->flags & MMC_DATA_READ)
879 flags |= SG_MITER_TO_SG;
880 else
881 flags |= SG_MITER_FROM_SG;
882 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 883 host->blocks = data->blocks;
d129bceb 884 }
c7fa9963 885
6aa943ab
AV		 886 sdhci_set_transfer_irqs(host);
887
f6a03cbf
MV		 888 /* Set the DMA boundary value and block size */
889 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
890 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 891 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 892}
893
894static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 895 struct mmc_command *cmd)
c7fa9963 896{
d3fc5d71 897 u16 mode = 0;
e89d456f 898 struct mmc_data *data = cmd->data;
c7fa9963 899
2b558c13 900 if (data == NULL) {
9b8ffea6
VW		 901 if (host->quirks2 &
902 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
903 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
904 } else {
2b558c13 905 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 906 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
907 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 908 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 909 }
c7fa9963 910 return;
2b558c13 911 }
c7fa9963 912
e538fbe8
PO		 913 WARN_ON(!host->data);
914
d3fc5d71
VY		 915 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
916 mode = SDHCI_TRNS_BLK_CNT_EN;
917
e89d456f 918 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 919 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 920 /*
921 * If we are sending CMD23, CMD12 never gets sent
922 * on successful completion (so no Auto-CMD12).
923 */
85cc1c33
CD		 924 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
925 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 926 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 927 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
928 mode |= SDHCI_TRNS_AUTO_CMD23;
929 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
930 }
c4512f79 931 }
8edf6371 932
c7fa9963
PO		 933 if (data->flags & MMC_DATA_READ)
934 mode |= SDHCI_TRNS_READ;
c9fddbc4 935 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 936 mode |= SDHCI_TRNS_DMA;
937
4e4141a5 938 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 939}
940
941static void sdhci_finish_data(struct sdhci_host *host)
942{
943 struct mmc_data *data;
d129bceb
PO		 944
945 BUG_ON(!host->data);
946
947 data = host->data;
948 host->data = NULL;
949
c9fddbc4 950 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 951 if (host->flags & SDHCI_USE_ADMA)
952 sdhci_adma_table_post(host, data);
953 else {
348487cb
HC		 954 if (!data->host_cookie)
955 dma_unmap_sg(mmc_dev(host->mmc),
956 data->sg, data->sg_len,
957 (data->flags & MMC_DATA_READ) ?
2134a922
PO		 958 DMA_FROM_DEVICE : DMA_TO_DEVICE);
959 }
d129bceb
PO		 960 }
961
962 /*
c9b74c5b
PO		 963 * The specification states that the block count register must
964 * be updated, but it does not specify at what point in the
965 * data flow. That makes the register entirely useless to read
966 * back so we have to assume that nothing made it to the card
967 * in the event of an error.
d129bceb 968 */
c9b74c5b
PO		 969 if (data->error)
970 data->bytes_xfered = 0;
d129bceb 971 else
c9b74c5b 972 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 973
e89d456f
AW		 974 /*
975 * Need to send CMD12 if -
976 * a) open-ended multiblock transfer (no CMD23)
977 * b) error in multiblock transfer
978 */
979 if (data->stop &&
980 (data->error ||
981 !host->mrq->sbc)) {
982
d129bceb
PO		 983 /*
984 * The controller needs a reset of internal state machines
985 * upon error conditions.
986 */
17b0429d 987 if (data->error) {
03231f9b
RK		 988 sdhci_do_reset(host, SDHCI_RESET_CMD);
989 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 990 }
991
992 sdhci_send_command(host, data->stop);
993 } else
994 tasklet_schedule(&host->finish_tasklet);
995}
996
c0e55129 997void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 998{
999 int flags;
fd2208d7 1000 u32 mask;
7cb2c76f 1001 unsigned long timeout;
d129bceb
PO		 1002
1003 WARN_ON(host->cmd);
1004
d129bceb 1005 /* Wait max 10 ms */
7cb2c76f 1006 timeout = 10;
fd2208d7
PO		 1007
1008 mask = SDHCI_CMD_INHIBIT;
1009 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1010 mask |= SDHCI_DATA_INHIBIT;
1011
1012 /* We shouldn't wait for data inihibit for stop commands, even
1013 though they might use busy signaling */
1014 if (host->mrq->data && (cmd == host->mrq->data->stop))
1015 mask &= ~SDHCI_DATA_INHIBIT;
1016
4e4141a5 1017 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1018 if (timeout == 0) {
a3c76eb9 1019 pr_err("%s: Controller never released "
acf1da45 1020 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 1021 sdhci_dumpregs(host);
17b0429d 1022 cmd->error = -EIO;
d129bceb
PO		 1023 tasklet_schedule(&host->finish_tasklet);
1024 return;
1025 }
7cb2c76f
PO		 1026 timeout--;
1027 mdelay(1);
1028 }
d129bceb 1029
3e1a6892 1030 timeout = jiffies;
1d4d7744
UH		 1031 if (!cmd->data && cmd->busy_timeout > 9000)
1032 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1033 else
1034 timeout += 10 * HZ;
1035 mod_timer(&host->timer, timeout);
d129bceb
PO		 1036
1037 host->cmd = cmd;
e99783a4 1038 host->busy_handle = 0;
d129bceb 1039
a3c7778f 1040 sdhci_prepare_data(host, cmd);
d129bceb 1041
4e4141a5 1042 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1043
e89d456f 1044 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1045
d129bceb 1046 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1047 pr_err("%s: Unsupported response type!\n",
d129bceb 1048 mmc_hostname(host->mmc));
17b0429d 1049 cmd->error = -EINVAL;
d129bceb
PO		 1050 tasklet_schedule(&host->finish_tasklet);
1051 return;
1052 }
1053
1054 if (!(cmd->flags & MMC_RSP_PRESENT))
1055 flags = SDHCI_CMD_RESP_NONE;
1056 else if (cmd->flags & MMC_RSP_136)
1057 flags = SDHCI_CMD_RESP_LONG;
1058 else if (cmd->flags & MMC_RSP_BUSY)
1059 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1060 else
1061 flags = SDHCI_CMD_RESP_SHORT;
1062
1063 if (cmd->flags & MMC_RSP_CRC)
1064 flags |= SDHCI_CMD_CRC;
1065 if (cmd->flags & MMC_RSP_OPCODE)
1066 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1067
1068 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1069 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1070 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1071 flags |= SDHCI_CMD_DATA;
1072
4e4141a5 1073 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1074}
c0e55129 1075EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1076
1077static void sdhci_finish_command(struct sdhci_host *host)
1078{
1079 int i;
1080
1081 BUG_ON(host->cmd == NULL);
1082
1083 if (host->cmd->flags & MMC_RSP_PRESENT) {
1084 if (host->cmd->flags & MMC_RSP_136) {
1085 /* CRC is stripped so we need to do some shifting. */
1086 for (i = 0;i < 4;i++) {
4e4141a5 1087 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1088 SDHCI_RESPONSE + (3-i)*4) << 8;
1089 if (i != 3)
1090 host->cmd->resp[i] |=
4e4141a5 1091 sdhci_readb(host,
d129bceb
PO		 1092 SDHCI_RESPONSE + (3-i)*4-1);
1093 }
1094 } else {
4e4141a5 1095 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1096 }
1097 }
1098
17b0429d 1099 host->cmd->error = 0;
d129bceb 1100
e89d456f
AW		 1101 /* Finished CMD23, now send actual command. */
1102 if (host->cmd == host->mrq->sbc) {
1103 host->cmd = NULL;
1104 sdhci_send_command(host, host->mrq->cmd);
1105 } else {
e538fbe8 1106
e89d456f
AW		 1107 /* Processed actual command. */
1108 if (host->data && host->data_early)
1109 sdhci_finish_data(host);
d129bceb 1110
e89d456f
AW		 1111 if (!host->cmd->data)
1112 tasklet_schedule(&host->finish_tasklet);
1113
1114 host->cmd = NULL;
1115 }
d129bceb
PO		 1116}
1117
52983382
KL		 1118static u16 sdhci_get_preset_value(struct sdhci_host *host)
1119{
d975f121 1120 u16 preset = 0;
52983382 1121
d975f121
RK		 1122 switch (host->timing) {
1123 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1124 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1125 break;
d975f121 1126 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1127 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1128 break;
d975f121 1129 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1130 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1131 break;
d975f121
RK		 1132 case MMC_TIMING_UHS_SDR104:
1133 case MMC_TIMING_MMC_HS200:
52983382
KL		 1134 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1135 break;
d975f121 1136 case MMC_TIMING_UHS_DDR50:
52983382
KL		 1137 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1138 break;
e9fb05d5
AH		 1139 case MMC_TIMING_MMC_HS400:
1140 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1141 break;
52983382
KL		 1142 default:
1143 pr_warn("%s: Invalid UHS-I mode selected\n",
1144 mmc_hostname(host->mmc));
1145 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1146 break;
1147 }
1148 return preset;
1149}
1150
1771059c 1151void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1152{
c3ed3877 1153 int div = 0; /* Initialized for compiler warning */
df16219f 1154 int real_div = div, clk_mul = 1;
c3ed3877 1155 u16 clk = 0;
7cb2c76f 1156 unsigned long timeout;
d129bceb 1157
1650d0c7
RK		 1158 host->mmc->actual_clock = 0;
1159
4e4141a5 1160 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1161
1162 if (clock == 0)
373073ef 1163 return;
d129bceb 1164
85105c53 1165 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1166 if (host->preset_enabled) {
52983382
KL		 1167 u16 pre_val;
1168
1169 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1170 pre_val = sdhci_get_preset_value(host);
1171 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1172 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1173 if (host->clk_mul &&
1174 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1175 clk = SDHCI_PROG_CLOCK_MODE;
1176 real_div = div + 1;
1177 clk_mul = host->clk_mul;
1178 } else {
1179 real_div = max_t(int, 1, div << 1);
1180 }
1181 goto clock_set;
1182 }
1183
c3ed3877
AN		 1184 /*
1185 * Check if the Host Controller supports Programmable Clock
1186 * Mode.
1187 */
1188 if (host->clk_mul) {
52983382
KL		 1189 for (div = 1; div <= 1024; div++) {
1190 if ((host->max_clk * host->clk_mul / div)
1191 <= clock)
1192 break;
1193 }
c3ed3877 1194 /*
52983382
KL		 1195 * Set Programmable Clock Mode in the Clock
1196 * Control register.
c3ed3877 1197 */
52983382
KL		 1198 clk = SDHCI_PROG_CLOCK_MODE;
1199 real_div = div;
1200 clk_mul = host->clk_mul;
1201 div--;
c3ed3877
AN		 1202 } else {
1203 /* Version 3.00 divisors must be a multiple of 2. */
1204 if (host->max_clk <= clock)
1205 div = 1;
1206 else {
1207 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1208 div += 2) {
1209 if ((host->max_clk / div) <= clock)
1210 break;
1211 }
85105c53 1212 }
df16219f 1213 real_div = div;
c3ed3877 1214 div >>= 1;
85105c53
ZG		 1215 }
1216 } else {
1217 /* Version 2.00 divisors must be a power of 2. */
0397526d 1218 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1219 if ((host->max_clk / div) <= clock)
1220 break;
1221 }
df16219f 1222 real_div = div;
c3ed3877 1223 div >>= 1;
d129bceb 1224 }
d129bceb 1225
52983382 1226clock_set:
03d6f5ff 1227 if (real_div)
df16219f 1228 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1229 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1230 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1231 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1232 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1233 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1234
27f6cb16
CB		 1235 /* Wait max 20 ms */
1236 timeout = 20;
4e4141a5 1237 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1238 & SDHCI_CLOCK_INT_STABLE)) {
1239 if (timeout == 0) {
a3c76eb9 1240 pr_err("%s: Internal clock never "
acf1da45 1241 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1242 sdhci_dumpregs(host);
1243 return;
1244 }
7cb2c76f
PO		 1245 timeout--;
1246 mdelay(1);
1247 }
d129bceb
PO		 1248
1249 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1250 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1251}
1771059c 1252EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1253
24fbb3ca
RK		 1254static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1255 unsigned short vdd)
146ad66e 1256{
3a48edc4 1257 struct mmc_host *mmc = host->mmc;
8364248a 1258 u8 pwr = 0;
146ad66e 1259
52221610
TK		 1260 if (!IS_ERR(mmc->supply.vmmc)) {
1261 spin_unlock_irq(&host->lock);
4e743f1f 1262 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
52221610 1263 spin_lock_irq(&host->lock);
3cbc6123
TK		 1264
1265 if (mode != MMC_POWER_OFF)
1266 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1267 else
1268 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1269
52221610
TK		 1270 return;
1271 }
1272
24fbb3ca
RK		 1273 if (mode != MMC_POWER_OFF) {
1274 switch (1 << vdd) {
ae628903
PO		 1275 case MMC_VDD_165_195:
1276 pwr = SDHCI_POWER_180;
1277 break;
1278 case MMC_VDD_29_30:
1279 case MMC_VDD_30_31:
1280 pwr = SDHCI_POWER_300;
1281 break;
1282 case MMC_VDD_32_33:
1283 case MMC_VDD_33_34:
1284 pwr = SDHCI_POWER_330;
1285 break;
1286 default:
1287 BUG();
1288 }
1289 }
1290
1291 if (host->pwr == pwr)
e921a8b6 1292 return;
146ad66e 1293
ae628903
PO		 1294 host->pwr = pwr;
1295
1296 if (pwr == 0) {
4e4141a5 1297 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1298 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1299 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1300 vdd = 0;
e921a8b6
RK		 1301 } else {
1302 /*
1303 * Spec says that we should clear the power reg before setting
1304 * a new value. Some controllers don't seem to like this though.
1305 */
1306 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1307 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1308
e921a8b6
RK		 1309 /*
1310 * At least the Marvell CaFe chip gets confused if we set the
1311 * voltage and set turn on power at the same time, so set the
1312 * voltage first.
1313 */
1314 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1315 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1316
e921a8b6 1317 pwr |= SDHCI_POWER_ON;
146ad66e 1318
e921a8b6 1319 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1320
e921a8b6
RK		 1321 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1322 sdhci_runtime_pm_bus_on(host);
f0710a55 1323
e921a8b6
RK		 1324 /*
1325 * Some controllers need an extra 10ms delay of 10ms before
1326 * they can apply clock after applying power
1327 */
1328 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1329 mdelay(10);
1330 }
146ad66e
PO		 1331}
1332
d129bceb
PO		 1333/*****************************************************************************\
1334 * *
1335 * MMC callbacks *
1336 * *
1337\*****************************************************************************/
1338
1339static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1340{
1341 struct sdhci_host *host;
505a8680 1342 int present;
d129bceb
PO		 1343 unsigned long flags;
1344
1345 host = mmc_priv(mmc);
1346
66fd8ad5
AH		 1347 sdhci_runtime_pm_get(host);
1348
04e079cf
SB		 1349 /* Firstly check card presence */
1350 present = sdhci_do_get_cd(host);
2836766a 1351
d129bceb
PO		 1352 spin_lock_irqsave(&host->lock, flags);
1353
1354 WARN_ON(host->mrq != NULL);
1355
f9134319 1356#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1357 sdhci_activate_led(host);
2f730fec 1358#endif
e89d456f
AW		 1359
1360 /*
1361 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1362 * requests if Auto-CMD12 is enabled.
1363 */
1364 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1365 if (mrq->stop) {
1366 mrq->data->stop = NULL;
1367 mrq->stop = NULL;
1368 }
1369 }
d129bceb
PO		 1370
1371 host->mrq = mrq;
1372
68d1fb7e 1373 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1374 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1375 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1376 } else {
8edf6371 1377 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1378 sdhci_send_command(host, mrq->sbc);
1379 else
1380 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1381 }
d129bceb 1382
5f25a66f 1383 mmiowb();
d129bceb
PO		 1384 spin_unlock_irqrestore(&host->lock, flags);
1385}
1386
2317f56c
RK		 1387void sdhci_set_bus_width(struct sdhci_host *host, int width)
1388{
1389 u8 ctrl;
1390
1391 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1392 if (width == MMC_BUS_WIDTH_8) {
1393 ctrl &= ~SDHCI_CTRL_4BITBUS;
1394 if (host->version >= SDHCI_SPEC_300)
1395 ctrl |= SDHCI_CTRL_8BITBUS;
1396 } else {
1397 if (host->version >= SDHCI_SPEC_300)
1398 ctrl &= ~SDHCI_CTRL_8BITBUS;
1399 if (width == MMC_BUS_WIDTH_4)
1400 ctrl |= SDHCI_CTRL_4BITBUS;
1401 else
1402 ctrl &= ~SDHCI_CTRL_4BITBUS;
1403 }
1404 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1405}
1406EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1407
96d7b78c
RK		 1408void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1409{
1410 u16 ctrl_2;
1411
1412 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1413 /* Select Bus Speed Mode for host */
1414 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1415 if ((timing == MMC_TIMING_MMC_HS200) ||
1416 (timing == MMC_TIMING_UHS_SDR104))
1417 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1418 else if (timing == MMC_TIMING_UHS_SDR12)
1419 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1420 else if (timing == MMC_TIMING_UHS_SDR25)
1421 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1422 else if (timing == MMC_TIMING_UHS_SDR50)
1423 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1424 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1425 (timing == MMC_TIMING_MMC_DDR52))
1426 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1427 else if (timing == MMC_TIMING_MMC_HS400)
1428 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1429 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1430}
1431EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1432
66fd8ad5 1433static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1434{
d129bceb
PO		 1435 unsigned long flags;
1436 u8 ctrl;
3a48edc4 1437 struct mmc_host *mmc = host->mmc;
d129bceb 1438
d129bceb
PO		 1439 spin_lock_irqsave(&host->lock, flags);
1440
ceb6143b
AH		 1441 if (host->flags & SDHCI_DEVICE_DEAD) {
1442 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1443 if (!IS_ERR(mmc->supply.vmmc) &&
1444 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1445 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1446 return;
1447 }
1e72859e 1448
d129bceb
PO		 1449 /*
1450 * Reset the chip on each power off.
1451 * Should clear out any weird states.
1452 */
1453 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1454 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1455 sdhci_reinit(host);
d129bceb
PO		 1456 }
1457
52983382 1458 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1459 (ios->power_mode == MMC_POWER_UP) &&
1460 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1461 sdhci_enable_preset_value(host, false);
1462
373073ef 1463 if (!ios->clock || ios->clock != host->clock) {
1771059c 1464 host->ops->set_clock(host, ios->clock);
373073ef 1465 host->clock = ios->clock;
03d6f5ff
AD		 1466
1467 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1468 host->clock) {
1469 host->timeout_clk = host->mmc->actual_clock ?
1470 host->mmc->actual_clock / 1000 :
1471 host->clock / 1000;
1472 host->mmc->max_busy_timeout =
1473 host->ops->get_max_timeout_count ?
1474 host->ops->get_max_timeout_count(host) :
1475 1 << 27;
1476 host->mmc->max_busy_timeout /= host->timeout_clk;
1477 }
373073ef 1478 }
d129bceb 1479
24fbb3ca 1480 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1481
643a81ff
PR		 1482 if (host->ops->platform_send_init_74_clocks)
1483 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1484
2317f56c 1485 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1486
15ec4461 1487 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1488
3ab9c8da
PR		 1489 if ((ios->timing == MMC_TIMING_SD_HS ||
1490 ios->timing == MMC_TIMING_MMC_HS)
1491 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1492 ctrl |= SDHCI_CTRL_HISPD;
1493 else
1494 ctrl &= ~SDHCI_CTRL_HISPD;
1495
d6d50a15 1496 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1497 u16 clk, ctrl_2;
49c468fc
AN		 1498
1499 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1500 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1501 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1502 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1503 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1504 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1505 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1506 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1507 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1508
da91a8f9 1509 if (!host->preset_enabled) {
758535c4 1510 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1511 /*
1512 * We only need to set Driver Strength if the
1513 * preset value enable is not set.
1514 */
da91a8f9 1515 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1516 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1517 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1518 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1519 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1520 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1521
1522 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1523 } else {
1524 /*
1525 * According to SDHC Spec v3.00, if the Preset Value
1526 * Enable in the Host Control 2 register is set, we
1527 * need to reset SD Clock Enable before changing High
1528 * Speed Enable to avoid generating clock gliches.
1529 */
758535c4
AN		 1530
1531 /* Reset SD Clock Enable */
1532 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1533 clk &= ~SDHCI_CLOCK_CARD_EN;
1534 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1535
1536 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1537
1538 /* Re-enable SD Clock */
1771059c 1539 host->ops->set_clock(host, host->clock);
d6d50a15 1540 }
49c468fc 1541
49c468fc
AN		 1542 /* Reset SD Clock Enable */
1543 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1544 clk &= ~SDHCI_CLOCK_CARD_EN;
1545 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1546
96d7b78c 1547 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1548 host->timing = ios->timing;
49c468fc 1549
52983382
KL		 1550 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1551 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1552 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1553 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1554 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1555 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1556 u16 preset;
1557
1558 sdhci_enable_preset_value(host, true);
1559 preset = sdhci_get_preset_value(host);
1560 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1561 >> SDHCI_PRESET_DRV_SHIFT;
1562 }
1563
49c468fc 1564 /* Re-enable SD Clock */
1771059c 1565 host->ops->set_clock(host, host->clock);
758535c4
AN		 1566 } else
1567 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1568
b8352260
LD		 1569 /*
1570 * Some (ENE) controllers go apeshit on some ios operation,
1571 * signalling timeout and CRC errors even on CMD0. Resetting
1572 * it on each ios seems to solve the problem.
1573 */
c63705e1 1574 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1575 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1576
5f25a66f 1577 mmiowb();
d129bceb
PO		 1578 spin_unlock_irqrestore(&host->lock, flags);
1579}
1580
66fd8ad5
AH		 1581static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1582{
1583 struct sdhci_host *host = mmc_priv(mmc);
1584
1585 sdhci_runtime_pm_get(host);
1586 sdhci_do_set_ios(host, ios);
1587 sdhci_runtime_pm_put(host);
1588}
1589
94144a46
KL		 1590static int sdhci_do_get_cd(struct sdhci_host *host)
1591{
1592 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1593
1594 if (host->flags & SDHCI_DEVICE_DEAD)
1595 return 0;
1596
1597 /* If polling/nonremovable, assume that the card is always present. */
1598 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1599 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1600 return 1;
1601
1602 /* Try slot gpio detect */
1603 if (!IS_ERR_VALUE(gpio_cd))
1604 return !!gpio_cd;
1605
1606 /* Host native card detect */
1607 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1608}
1609
1610static int sdhci_get_cd(struct mmc_host *mmc)
1611{
1612 struct sdhci_host *host = mmc_priv(mmc);
1613 int ret;
1614
1615 sdhci_runtime_pm_get(host);
1616 ret = sdhci_do_get_cd(host);
1617 sdhci_runtime_pm_put(host);
1618 return ret;
1619}
1620
66fd8ad5 1621static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1622{
d129bceb 1623 unsigned long flags;
2dfb579c 1624 int is_readonly;
d129bceb 1625
d129bceb
PO		 1626 spin_lock_irqsave(&host->lock, flags);
1627
1e72859e 1628 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1629 is_readonly = 0;
1630 else if (host->ops->get_ro)
1631 is_readonly = host->ops->get_ro(host);
1e72859e 1632 else
2dfb579c
WS		 1633 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1634 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1635
1636 spin_unlock_irqrestore(&host->lock, flags);
1637
2dfb579c
WS		 1638 /* This quirk needs to be replaced by a callback-function later */
1639 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1640 !is_readonly : is_readonly;
d129bceb
PO		 1641}
1642
82b0e23a
TI		 1643#define SAMPLE_COUNT 5
1644
66fd8ad5 1645static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1646{
82b0e23a
TI		 1647 int i, ro_count;
1648
82b0e23a 1649 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1650 return sdhci_check_ro(host);
82b0e23a
TI		 1651
1652 ro_count = 0;
1653 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1654 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1655 if (++ro_count > SAMPLE_COUNT / 2)
1656 return 1;
1657 }
1658 msleep(30);
1659 }
1660 return 0;
1661}
1662
20758b66
AH		 1663static void sdhci_hw_reset(struct mmc_host *mmc)
1664{
1665 struct sdhci_host *host = mmc_priv(mmc);
1666
1667 if (host->ops && host->ops->hw_reset)
1668 host->ops->hw_reset(host);
1669}
1670
66fd8ad5 1671static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1672{
66fd8ad5
AH		 1673 struct sdhci_host *host = mmc_priv(mmc);
1674 int ret;
f75979b7 1675
66fd8ad5
AH		 1676 sdhci_runtime_pm_get(host);
1677 ret = sdhci_do_get_ro(host);
1678 sdhci_runtime_pm_put(host);
1679 return ret;
1680}
f75979b7 1681
66fd8ad5
AH		 1682static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1683{
be138554 1684 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1685 if (enable)
b537f94c 1686 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1687 else
b537f94c
RK		 1688 host->ier &= ~SDHCI_INT_CARD_INT;
1689
1690 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1691 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1692 mmiowb();
1693 }
66fd8ad5
AH		 1694}
1695
1696static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1697{
1698 struct sdhci_host *host = mmc_priv(mmc);
1699 unsigned long flags;
f75979b7 1700
ef104333
RK		 1701 sdhci_runtime_pm_get(host);
1702
66fd8ad5 1703 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1704 if (enable)
1705 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1706 else
1707 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1708
66fd8ad5 1709 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1710 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1711
1712 sdhci_runtime_pm_put(host);
f75979b7
PO		 1713}
1714
20b92a30 1715static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1716 struct mmc_ios *ios)
f2119df6 1717{
3a48edc4 1718 struct mmc_host *mmc = host->mmc;
20b92a30 1719 u16 ctrl;
6231f3de 1720 int ret;
f2119df6 1721
20b92a30
KL		 1722 /*
1723 * Signal Voltage Switching is only applicable for Host Controllers
1724 * v3.00 and above.
1725 */
1726 if (host->version < SDHCI_SPEC_300)
1727 return 0;
6231f3de 1728
f2119df6 1729 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1730
21f5998f 1731 switch (ios->signal_voltage) {
20b92a30
KL		 1732 case MMC_SIGNAL_VOLTAGE_330:
1733 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1734 ctrl &= ~SDHCI_CTRL_VDD_180;
1735 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1736
3a48edc4
TK		 1737 if (!IS_ERR(mmc->supply.vqmmc)) {
1738 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1739 3600000);
20b92a30 1740 if (ret) {
6606110d
JP		 1741 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1742 mmc_hostname(mmc));
20b92a30
KL		 1743 return -EIO;
1744 }
1745 }
1746 /* Wait for 5ms */
1747 usleep_range(5000, 5500);
f2119df6 1748
20b92a30
KL		 1749 /* 3.3V regulator output should be stable within 5 ms */
1750 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1751 if (!(ctrl & SDHCI_CTRL_VDD_180))
1752 return 0;
6231f3de 1753
6606110d
JP		 1754 pr_warn("%s: 3.3V regulator output did not became stable\n",
1755 mmc_hostname(mmc));
20b92a30
KL		 1756
1757 return -EAGAIN;
1758 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1759 if (!IS_ERR(mmc->supply.vqmmc)) {
1760 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1761 1700000, 1950000);
1762 if (ret) {
6606110d
JP		 1763 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1764 mmc_hostname(mmc));
20b92a30
KL		 1765 return -EIO;
1766 }
1767 }
6231f3de 1768
6231f3de
PR		 1769 /*
1770 * Enable 1.8V Signal Enable in the Host Control2
1771 * register
1772 */
20b92a30
KL		 1773 ctrl |= SDHCI_CTRL_VDD_180;
1774 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1775
9d967a61
VY		 1776 /* Some controller need to do more when switching */
1777 if (host->ops->voltage_switch)
1778 host->ops->voltage_switch(host);
1779
20b92a30
KL		 1780 /* 1.8V regulator output should be stable within 5 ms */
1781 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1782 if (ctrl & SDHCI_CTRL_VDD_180)
1783 return 0;
f2119df6 1784
6606110d
JP		 1785 pr_warn("%s: 1.8V regulator output did not became stable\n",
1786 mmc_hostname(mmc));
f2119df6 1787
20b92a30
KL		 1788 return -EAGAIN;
1789 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1790 if (!IS_ERR(mmc->supply.vqmmc)) {
1791 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1792 1300000);
20b92a30 1793 if (ret) {
6606110d
JP		 1794 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1795 mmc_hostname(mmc));
20b92a30 1796 return -EIO;
f2119df6
AN		 1797 }
1798 }
6231f3de 1799 return 0;
20b92a30 1800 default:
f2119df6
AN		 1801 /* No signal voltage switch required */
1802 return 0;
20b92a30 1803 }
f2119df6
AN		 1804}
1805
66fd8ad5 1806static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1807 struct mmc_ios *ios)
66fd8ad5
AH		 1808{
1809 struct sdhci_host *host = mmc_priv(mmc);
1810 int err;
1811
1812 if (host->version < SDHCI_SPEC_300)
1813 return 0;
1814 sdhci_runtime_pm_get(host);
21f5998f 1815 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1816 sdhci_runtime_pm_put(host);
1817 return err;
1818}
1819
20b92a30
KL		 1820static int sdhci_card_busy(struct mmc_host *mmc)
1821{
1822 struct sdhci_host *host = mmc_priv(mmc);
1823 u32 present_state;
1824
1825 sdhci_runtime_pm_get(host);
1826 /* Check whether DAT[3:0] is 0000 */
1827 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1828 sdhci_runtime_pm_put(host);
1829
1830 return !(present_state & SDHCI_DATA_LVL_MASK);
1831}
1832
b5540ce1
AH		 1833static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1834{
1835 struct sdhci_host *host = mmc_priv(mmc);
1836 unsigned long flags;
1837
1838 spin_lock_irqsave(&host->lock, flags);
1839 host->flags |= SDHCI_HS400_TUNING;
1840 spin_unlock_irqrestore(&host->lock, flags);
1841
1842 return 0;
1843}
1844
069c9f14 1845static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1846{
4b6f37d3 1847 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1848 u16 ctrl;
b513ea25 1849 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1850 int err = 0;
2b35bd83 1851 unsigned long flags;
38e40bf5 1852 unsigned int tuning_count = 0;
b5540ce1 1853 bool hs400_tuning;
b513ea25 1854
66fd8ad5 1855 sdhci_runtime_pm_get(host);
2b35bd83 1856 spin_lock_irqsave(&host->lock, flags);
b513ea25 1857
b5540ce1
AH		 1858 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1859 host->flags &= ~SDHCI_HS400_TUNING;
1860
38e40bf5
AH		 1861 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1862 tuning_count = host->tuning_count;
1863
b513ea25 1864 /*
069c9f14
G		 1865 * The Host Controller needs tuning only in case of SDR104 mode
1866 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1867 * Capabilities register.
069c9f14
G		 1868 * If the Host Controller supports the HS200 mode then the
1869 * tuning function has to be executed.
b513ea25 1870 */
4b6f37d3 1871 switch (host->timing) {
b5540ce1 1872 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1873 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1874 err = -EINVAL;
1875 goto out_unlock;
1876
4b6f37d3 1877 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1878 /*
1879 * Periodic re-tuning for HS400 is not expected to be needed, so
1880 * disable it here.
1881 */
1882 if (hs400_tuning)
1883 tuning_count = 0;
1884 break;
1885
4b6f37d3
RK		 1886 case MMC_TIMING_UHS_SDR104:
1887 break;
1888
1889 case MMC_TIMING_UHS_SDR50:
1890 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1891 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1892 break;
1893 /* FALLTHROUGH */
1894
1895 default:
d519c863 1896 goto out_unlock;
b513ea25
AN		 1897 }
1898
45251812 1899 if (host->ops->platform_execute_tuning) {
2b35bd83 1900 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1901 err = host->ops->platform_execute_tuning(host, opcode);
1902 sdhci_runtime_pm_put(host);
1903 return err;
1904 }
1905
4b6f37d3
RK		 1906 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1907 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1908 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1909 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1910 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1911
1912 /*
1913 * As per the Host Controller spec v3.00, tuning command
1914 * generates Buffer Read Ready interrupt, so enable that.
1915 *
1916 * Note: The spec clearly says that when tuning sequence
1917 * is being performed, the controller does not generate
1918 * interrupts other than Buffer Read Ready interrupt. But
1919 * to make sure we don't hit a controller bug, we _only_
1920 * enable Buffer Read Ready interrupt here.
1921 */
b537f94c
RK		 1922 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1923 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1924
1925 /*
1926 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1927 * of loops reaches 40 times or a timeout of 150ms occurs.
1928 */
b513ea25
AN		 1929 do {
1930 struct mmc_command cmd = {0};
66fd8ad5 1931 struct mmc_request mrq = {NULL};
b513ea25 1932
069c9f14 1933 cmd.opcode = opcode;
b513ea25
AN		 1934 cmd.arg = 0;
1935 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1936 cmd.retries = 0;
1937 cmd.data = NULL;
1938 cmd.error = 0;
1939
7ce45e95
AC		 1940 if (tuning_loop_counter-- == 0)
1941 break;
1942
b513ea25
AN		 1943 mrq.cmd = &cmd;
1944 host->mrq = &mrq;
1945
1946 /*
1947 * In response to CMD19, the card sends 64 bytes of tuning
1948 * block to the Host Controller. So we set the block size
1949 * to 64 here.
1950 */
069c9f14
G		 1951 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1952 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1953 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1954 SDHCI_BLOCK_SIZE);
1955 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1956 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1957 SDHCI_BLOCK_SIZE);
1958 } else {
1959 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1960 SDHCI_BLOCK_SIZE);
1961 }
b513ea25
AN		 1962
1963 /*
1964 * The tuning block is sent by the card to the host controller.
1965 * So we set the TRNS_READ bit in the Transfer Mode register.
1966 * This also takes care of setting DMA Enable and Multi Block
1967 * Select in the same register to 0.
1968 */
1969 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1970
1971 sdhci_send_command(host, &cmd);
1972
1973 host->cmd = NULL;
1974 host->mrq = NULL;
1975
2b35bd83 1976 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1977 /* Wait for Buffer Read Ready interrupt */
1978 wait_event_interruptible_timeout(host->buf_ready_int,
1979 (host->tuning_done == 1),
1980 msecs_to_jiffies(50));
2b35bd83 1981 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1982
1983 if (!host->tuning_done) {
a3c76eb9 1984 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1985 "Buffer Read Ready interrupt during tuning "
1986 "procedure, falling back to fixed sampling "
1987 "clock\n");
1988 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1989 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1990 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1991 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1992
1993 err = -EIO;
1994 goto out;
1995 }
1996
1997 host->tuning_done = 0;
1998
1999 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2000
2001 /* eMMC spec does not require a delay between tuning cycles */
2002 if (opcode == MMC_SEND_TUNING_BLOCK)
2003 mdelay(1);
b513ea25
AN		 2004 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2005
2006 /*
2007 * The Host Driver has exhausted the maximum number of loops allowed,
2008 * so use fixed sampling frequency.
2009 */
7ce45e95 2010 if (tuning_loop_counter < 0) {
b513ea25
AN		 2011 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2012 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2013 }
2014 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2015 pr_info(DRIVER_NAME ": Tuning procedure"
2016 " failed, falling back to fixed sampling"
2017 " clock\n");
114f2bf6 2018 err = -EIO;
b513ea25
AN		 2019 }
2020
2021out:
38e40bf5 2022 if (tuning_count) {
66c39dfc
AH		 2023 /*
2024 * In case tuning fails, host controllers which support
2025 * re-tuning can try tuning again at a later time, when the
2026 * re-tuning timer expires. So for these controllers, we
2027 * return 0. Since there might be other controllers who do not
2028 * have this capability, we return error for them.
2029 */
2030 err = 0;
cf2b5eea
AN		 2031 }
2032
66c39dfc 2033 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2034
b537f94c
RK		 2035 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2036 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2037out_unlock:
2b35bd83 2038 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2039 sdhci_runtime_pm_put(host);
b513ea25
AN		 2040
2041 return err;
2042}
2043
52983382
KL		 2044
2045static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2046{
4d55c5a1
AN		 2047 /* Host Controller v3.00 defines preset value registers */
2048 if (host->version < SDHCI_SPEC_300)
2049 return;
2050
4d55c5a1
AN		 2051 /*
2052 * We only enable or disable Preset Value if they are not already
2053 * enabled or disabled respectively. Otherwise, we bail out.
2054 */
da91a8f9
RK		 2055 if (host->preset_enabled != enable) {
2056 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2057
2058 if (enable)
2059 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2060 else
2061 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2062
4d55c5a1 2063 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2064
2065 if (enable)
2066 host->flags |= SDHCI_PV_ENABLED;
2067 else
2068 host->flags &= ~SDHCI_PV_ENABLED;
2069
2070 host->preset_enabled = enable;
4d55c5a1 2071 }
66fd8ad5
AH		 2072}
2073
348487cb
HC		 2074static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2075 int err)
2076{
2077 struct sdhci_host *host = mmc_priv(mmc);
2078 struct mmc_data *data = mrq->data;
2079
2080 if (host->flags & SDHCI_REQ_USE_DMA) {
2081 if (data->host_cookie)
2082 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2083 data->flags & MMC_DATA_WRITE ?
2084 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2085 mrq->data->host_cookie = 0;
2086 }
2087}
2088
2089static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2090 struct mmc_data *data,
2091 struct sdhci_host_next *next)
2092{
2093 int sg_count;
2094
2095 if (!next && data->host_cookie &&
2096 data->host_cookie != host->next_data.cookie) {
2097 pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
2098 __func__, data->host_cookie, host->next_data.cookie);
2099 data->host_cookie = 0;
2100 }
2101
2102 /* Check if next job is already prepared */
2103 if (next ||
2104 (!next && data->host_cookie != host->next_data.cookie)) {
2105 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
2106 data->sg_len,
2107 data->flags & MMC_DATA_WRITE ?
2108 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2109
2110 } else {
2111 sg_count = host->next_data.sg_count;
2112 host->next_data.sg_count = 0;
2113 }
2114
2115
2116 if (sg_count == 0)
2117 return -EINVAL;
2118
2119 if (next) {
2120 next->sg_count = sg_count;
2121 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
2122 } else
2123 host->sg_count = sg_count;
2124
2125 return sg_count;
2126}
2127
2128static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2129 bool is_first_req)
2130{
2131 struct sdhci_host *host = mmc_priv(mmc);
2132
2133 if (mrq->data->host_cookie) {
2134 mrq->data->host_cookie = 0;
2135 return;
2136 }
2137
2138 if (host->flags & SDHCI_REQ_USE_DMA)
2139 if (sdhci_pre_dma_transfer(host,
2140 mrq->data,
2141 &host->next_data) < 0)
2142 mrq->data->host_cookie = 0;
2143}
2144
71e69211 2145static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2146{
71e69211 2147 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2148 unsigned long flags;
2836766a 2149 int present;
d129bceb 2150
722e1280
CD		 2151 /* First check if client has provided their own card event */
2152 if (host->ops->card_event)
2153 host->ops->card_event(host);
2154
2836766a
KK		 2155 present = sdhci_do_get_cd(host);
2156
d129bceb
PO		 2157 spin_lock_irqsave(&host->lock, flags);
2158
66fd8ad5 2159 /* Check host->mrq first in case we are runtime suspended */
2836766a 2160 if (host->mrq && !present) {
a3c76eb9 2161 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2162 mmc_hostname(host->mmc));
a3c76eb9 2163 pr_err("%s: Resetting controller.\n",
66fd8ad5 2164 mmc_hostname(host->mmc));
d129bceb 2165
03231f9b
RK		 2166 sdhci_do_reset(host, SDHCI_RESET_CMD);
2167 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2168
66fd8ad5
AH		 2169 host->mrq->cmd->error = -ENOMEDIUM;
2170 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2171 }
2172
2173 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2174}
2175
2176static const struct mmc_host_ops sdhci_ops = {
2177 .request = sdhci_request,
348487cb
HC		 2178 .post_req = sdhci_post_req,
2179 .pre_req = sdhci_pre_req,
71e69211 2180 .set_ios = sdhci_set_ios,
94144a46 2181 .get_cd = sdhci_get_cd,
71e69211
GL		 2182 .get_ro = sdhci_get_ro,
2183 .hw_reset = sdhci_hw_reset,
2184 .enable_sdio_irq = sdhci_enable_sdio_irq,
2185 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2186 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2187 .execute_tuning = sdhci_execute_tuning,
71e69211 2188 .card_event = sdhci_card_event,
20b92a30 2189 .card_busy = sdhci_card_busy,
71e69211
GL		 2190};
2191
2192/*****************************************************************************\
2193 * *
2194 * Tasklets *
2195 * *
2196\*****************************************************************************/
2197
d129bceb
PO		 2198static void sdhci_tasklet_finish(unsigned long param)
2199{
2200 struct sdhci_host *host;
2201 unsigned long flags;
2202 struct mmc_request *mrq;
2203
2204 host = (struct sdhci_host*)param;
2205
66fd8ad5
AH		 2206 spin_lock_irqsave(&host->lock, flags);
2207
0c9c99a7
CB		 2208 /*
2209 * If this tasklet gets rescheduled while running, it will
2210 * be run again afterwards but without any active request.
2211 */
66fd8ad5
AH		 2212 if (!host->mrq) {
2213 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2214 return;
66fd8ad5 2215 }
d129bceb
PO		 2216
2217 del_timer(&host->timer);
2218
2219 mrq = host->mrq;
2220
d129bceb
PO		 2221 /*
2222 * The controller needs a reset of internal state machines
2223 * upon error conditions.
2224 */
1e72859e 2225 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2226 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2227 (mrq->sbc && mrq->sbc->error) ||
2228 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2229 (mrq->data->stop && mrq->data->stop->error))) ||
2230 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2231
2232 /* Some controllers need this kick or reset won't work here */
8213af3b 2233 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2234 /* This is to force an update */
1771059c 2235 host->ops->set_clock(host, host->clock);
645289dc
PO		 2236
2237 /* Spec says we should do both at the same time, but Ricoh
2238 controllers do not like that. */
03231f9b
RK		 2239 sdhci_do_reset(host, SDHCI_RESET_CMD);
2240 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2241 }
2242
2243 host->mrq = NULL;
2244 host->cmd = NULL;
2245 host->data = NULL;
2246
f9134319 2247#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2248 sdhci_deactivate_led(host);
2f730fec 2249#endif
d129bceb 2250
5f25a66f 2251 mmiowb();
d129bceb
PO		 2252 spin_unlock_irqrestore(&host->lock, flags);
2253
2254 mmc_request_done(host->mmc, mrq);
66fd8ad5 2255 sdhci_runtime_pm_put(host);
d129bceb
PO		 2256}
2257
2258static void sdhci_timeout_timer(unsigned long data)
2259{
2260 struct sdhci_host *host;
2261 unsigned long flags;
2262
2263 host = (struct sdhci_host*)data;
2264
2265 spin_lock_irqsave(&host->lock, flags);
2266
2267 if (host->mrq) {
a3c76eb9 2268 pr_err("%s: Timeout waiting for hardware "
acf1da45 2269 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2270 sdhci_dumpregs(host);
2271
2272 if (host->data) {
17b0429d 2273 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2274 sdhci_finish_data(host);
2275 } else {
2276 if (host->cmd)
17b0429d 2277 host->cmd->error = -ETIMEDOUT;
d129bceb 2278 else
17b0429d 2279 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2280
2281 tasklet_schedule(&host->finish_tasklet);
2282 }
2283 }
2284
5f25a66f 2285 mmiowb();
d129bceb
PO		 2286 spin_unlock_irqrestore(&host->lock, flags);
2287}
2288
2289/*****************************************************************************\
2290 * *
2291 * Interrupt handling *
2292 * *
2293\*****************************************************************************/
2294
61541397 2295static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2296{
2297 BUG_ON(intmask == 0);
2298
2299 if (!host->cmd) {
a3c76eb9 2300 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2301 "though no command operation was in progress.\n",
2302 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2303 sdhci_dumpregs(host);
2304 return;
2305 }
2306
43b58b36 2307 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2308 host->cmd->error = -ETIMEDOUT;
2309 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2310 SDHCI_INT_INDEX))
2311 host->cmd->error = -EILSEQ;
43b58b36 2312
e809517f 2313 if (host->cmd->error) {
d129bceb 2314 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2315 return;
2316 }
2317
2318 /*
2319 * The host can send and interrupt when the busy state has
2320 * ended, allowing us to wait without wasting CPU cycles.
2321 * Unfortunately this is overloaded on the "data complete"
2322 * interrupt, so we need to take some care when handling
2323 * it.
2324 *
2325 * Note: The 1.0 specification is a bit ambiguous about this
2326 * feature so there might be some problems with older
2327 * controllers.
2328 */
2329 if (host->cmd->flags & MMC_RSP_BUSY) {
2330 if (host->cmd->data)
2331 DBG("Cannot wait for busy signal when also "
2332 "doing a data transfer");
e99783a4
CM		 2333 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2334 && !host->busy_handle) {
2335 /* Mark that command complete before busy is ended */
2336 host->busy_handle = 1;
e809517f 2337 return;
e99783a4 2338 }
f945405c
BD		 2339
2340 /* The controller does not support the end-of-busy IRQ,
2341 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2342 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2343 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2344 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2345 }
2346
2347 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2348 sdhci_finish_command(host);
d129bceb
PO		 2349}
2350
0957c333 2351#ifdef CONFIG_MMC_DEBUG
08621b18 2352static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2353{
2354 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2355 void *desc = host->adma_table;
6882a8c0
BD		 2356
2357 sdhci_dumpregs(host);
2358
2359 while (true) {
e57a5f61
AH		 2360 struct sdhci_adma2_64_desc *dma_desc = desc;
2361
2362 if (host->flags & SDHCI_USE_64_BIT_DMA)
2363 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2364 name, desc, le32_to_cpu(dma_desc->addr_hi),
2365 le32_to_cpu(dma_desc->addr_lo),
2366 le16_to_cpu(dma_desc->len),
2367 le16_to_cpu(dma_desc->cmd));
2368 else
2369 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2370 name, desc, le32_to_cpu(dma_desc->addr_lo),
2371 le16_to_cpu(dma_desc->len),
2372 le16_to_cpu(dma_desc->cmd));
6882a8c0 2373
76fe379a 2374 desc += host->desc_sz;
6882a8c0 2375
0545230f 2376 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2377 break;
2378 }
2379}
2380#else
08621b18 2381static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2382#endif
2383
d129bceb
PO		 2384static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2385{
069c9f14 2386 u32 command;
d129bceb
PO		 2387 BUG_ON(intmask == 0);
2388
b513ea25
AN		 2389 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2390 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2391 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2392 if (command == MMC_SEND_TUNING_BLOCK ||
2393 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2394 host->tuning_done = 1;
2395 wake_up(&host->buf_ready_int);
2396 return;
2397 }
2398 }
2399
d129bceb
PO		 2400 if (!host->data) {
2401 /*
e809517f
PO		 2402 * The "data complete" interrupt is also used to
2403 * indicate that a busy state has ended. See comment
2404 * above in sdhci_cmd_irq().
d129bceb 2405 */
e809517f 2406 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2407 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2408 host->cmd->error = -ETIMEDOUT;
2409 tasklet_schedule(&host->finish_tasklet);
2410 return;
2411 }
e809517f 2412 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2413 /*
2414 * Some cards handle busy-end interrupt
2415 * before the command completed, so make
2416 * sure we do things in the proper order.
2417 */
2418 if (host->busy_handle)
2419 sdhci_finish_command(host);
2420 else
2421 host->busy_handle = 1;
e809517f
PO		 2422 return;
2423 }
2424 }
d129bceb 2425
a3c76eb9 2426 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2427 "though no data operation was in progress.\n",
2428 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2429 sdhci_dumpregs(host);
2430
2431 return;
2432 }
2433
2434 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2435 host->data->error = -ETIMEDOUT;
22113efd
AL		 2436 else if (intmask & SDHCI_INT_DATA_END_BIT)
2437 host->data->error = -EILSEQ;
2438 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2439 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2440 != MMC_BUS_TEST_R)
17b0429d 2441 host->data->error = -EILSEQ;
6882a8c0 2442 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2443 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2444 sdhci_adma_show_error(host);
2134a922 2445 host->data->error = -EIO;
a4071fbb
HZ		 2446 if (host->ops->adma_workaround)
2447 host->ops->adma_workaround(host, intmask);
6882a8c0 2448 }
d129bceb 2449
17b0429d 2450 if (host->data->error)
d129bceb
PO		 2451 sdhci_finish_data(host);
2452 else {
a406f5a3 2453 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2454 sdhci_transfer_pio(host);
2455
6ba736a1
PO		 2456 /*
2457 * We currently don't do anything fancy with DMA
2458 * boundaries, but as we can't disable the feature
2459 * we need to at least restart the transfer.
f6a03cbf
MV		 2460 *
2461 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2462 * should return a valid address to continue from, but as
2463 * some controllers are faulty, don't trust them.
6ba736a1 2464 */
f6a03cbf
MV		 2465 if (intmask & SDHCI_INT_DMA_END) {
2466 u32 dmastart, dmanow;
2467 dmastart = sg_dma_address(host->data->sg);
2468 dmanow = dmastart + host->data->bytes_xfered;
2469 /*
2470 * Force update to the next DMA block boundary.
2471 */
2472 dmanow = (dmanow &
2473 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2474 SDHCI_DEFAULT_BOUNDARY_SIZE;
2475 host->data->bytes_xfered = dmanow - dmastart;
2476 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2477 " next 0x%08x\n",
2478 mmc_hostname(host->mmc), dmastart,
2479 host->data->bytes_xfered, dmanow);
2480 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2481 }
6ba736a1 2482
e538fbe8
PO		 2483 if (intmask & SDHCI_INT_DATA_END) {
2484 if (host->cmd) {
2485 /*
2486 * Data managed to finish before the
2487 * command completed. Make sure we do
2488 * things in the proper order.
2489 */
2490 host->data_early = 1;
2491 } else {
2492 sdhci_finish_data(host);
2493 }
2494 }
d129bceb
PO		 2495 }
2496}
2497
7d12e780 2498static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2499{
781e989c 2500 irqreturn_t result = IRQ_NONE;
66fd8ad5 2501 struct sdhci_host *host = dev_id;
41005003 2502 u32 intmask, mask, unexpected = 0;
781e989c 2503 int max_loops = 16;
d129bceb
PO		 2504
2505 spin_lock(&host->lock);
2506
be138554 2507 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2508 spin_unlock(&host->lock);
655bca76 2509 return IRQ_NONE;
66fd8ad5
AH		 2510 }
2511
4e4141a5 2512 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2513 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2514 result = IRQ_NONE;
2515 goto out;
2516 }
2517
41005003
RK		 2518 do {
2519 /* Clear selected interrupts. */
2520 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2521 SDHCI_INT_BUS_POWER);
2522 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2523
41005003
RK		 2524 DBG("*** %s got interrupt: 0x%08x\n",
2525 mmc_hostname(host->mmc), intmask);
d129bceb 2526
41005003
RK		 2527 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2528 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2529 SDHCI_CARD_PRESENT;
d129bceb 2530
41005003
RK		 2531 /*
2532 * There is a observation on i.mx esdhc. INSERT
2533 * bit will be immediately set again when it gets
2534 * cleared, if a card is inserted. We have to mask
2535 * the irq to prevent interrupt storm which will
2536 * freeze the system. And the REMOVE gets the
2537 * same situation.
2538 *
2539 * More testing are needed here to ensure it works
2540 * for other platforms though.
2541 */
b537f94c
RK		 2542 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2543 SDHCI_INT_CARD_REMOVE);
2544 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2545 SDHCI_INT_CARD_INSERT;
2546 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2547 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2548
2549 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2550 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2551
2552 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2553 SDHCI_INT_CARD_REMOVE);
2554 result = IRQ_WAKE_THREAD;
41005003 2555 }
d129bceb 2556
41005003 2557 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2558 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2559 &intmask);
964f9ce2 2560
41005003
RK		 2561 if (intmask & SDHCI_INT_DATA_MASK)
2562 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2563
41005003
RK		 2564 if (intmask & SDHCI_INT_BUS_POWER)
2565 pr_err("%s: Card is consuming too much power!\n",
2566 mmc_hostname(host->mmc));
3192a28f 2567
781e989c
RK		 2568 if (intmask & SDHCI_INT_CARD_INT) {
2569 sdhci_enable_sdio_irq_nolock(host, false);
2570 host->thread_isr |= SDHCI_INT_CARD_INT;
2571 result = IRQ_WAKE_THREAD;
2572 }
f75979b7 2573
41005003
RK		 2574 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2575 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2576 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2577 SDHCI_INT_CARD_INT);
f75979b7 2578
41005003
RK		 2579 if (intmask) {
2580 unexpected |= intmask;
2581 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2582 }
d129bceb 2583
781e989c
RK		 2584 if (result == IRQ_NONE)
2585 result = IRQ_HANDLED;
d129bceb 2586
41005003 2587 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2588 } while (intmask && --max_loops);
d129bceb
PO		 2589out:
2590 spin_unlock(&host->lock);
2591
6379b237
AS		 2592 if (unexpected) {
2593 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2594 mmc_hostname(host->mmc), unexpected);
2595 sdhci_dumpregs(host);
2596 }
f75979b7 2597
d129bceb
PO		 2598 return result;
2599}
2600
781e989c
RK		 2601static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2602{
2603 struct sdhci_host *host = dev_id;
2604 unsigned long flags;
2605 u32 isr;
2606
2607 spin_lock_irqsave(&host->lock, flags);
2608 isr = host->thread_isr;
2609 host->thread_isr = 0;
2610 spin_unlock_irqrestore(&host->lock, flags);
2611
3560db8e
RK		 2612 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2613 sdhci_card_event(host->mmc);
2614 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2615 }
2616
781e989c
RK		 2617 if (isr & SDHCI_INT_CARD_INT) {
2618 sdio_run_irqs(host->mmc);
2619
2620 spin_lock_irqsave(&host->lock, flags);
2621 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2622 sdhci_enable_sdio_irq_nolock(host, true);
2623 spin_unlock_irqrestore(&host->lock, flags);
2624 }
2625
2626 return isr ? IRQ_HANDLED : IRQ_NONE;
2627}
2628
d129bceb
PO		 2629/*****************************************************************************\
2630 * *
2631 * Suspend/resume *
2632 * *
2633\*****************************************************************************/
2634
2635#ifdef CONFIG_PM
ad080d79
KL		 2636void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2637{
2638 u8 val;
2639 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2640 | SDHCI_WAKE_ON_INT;
2641
2642 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2643 val |= mask ;
2644 /* Avoid fake wake up */
2645 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2646 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2647 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2648}
2649EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2650
0b10f478 2651static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2652{
2653 u8 val;
2654 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2655 | SDHCI_WAKE_ON_INT;
2656
2657 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2658 val &= ~mask;
2659 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2660}
d129bceb 2661
29495aa0 2662int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2663{
7260cf5e
AV		 2664 sdhci_disable_card_detection(host);
2665
66c39dfc
AH		 2666 mmc_retune_timer_stop(host->mmc);
2667 mmc_retune_needed(host->mmc);
cf2b5eea 2668
ad080d79 2669 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2670 host->ier = 0;
2671 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2672 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2673 free_irq(host->irq, host);
2674 } else {
2675 sdhci_enable_irq_wakeups(host);
2676 enable_irq_wake(host->irq);
2677 }
4ee14ec6 2678 return 0;
d129bceb
PO		 2679}
2680
b8c86fc5 2681EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2682
b8c86fc5
PO		 2683int sdhci_resume_host(struct sdhci_host *host)
2684{
4ee14ec6 2685 int ret = 0;
d129bceb 2686
a13abc7b 2687 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2688 if (host->ops->enable_dma)
2689 host->ops->enable_dma(host);
2690 }
d129bceb 2691
ad080d79 2692 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2693 ret = request_threaded_irq(host->irq, sdhci_irq,
2694 sdhci_thread_irq, IRQF_SHARED,
2695 mmc_hostname(host->mmc), host);
ad080d79
KL		 2696 if (ret)
2697 return ret;
2698 } else {
2699 sdhci_disable_irq_wakeups(host);
2700 disable_irq_wake(host->irq);
2701 }
d129bceb 2702
6308d290
AH		 2703 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2704 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2705 /* Card keeps power but host controller does not */
2706 sdhci_init(host, 0);
2707 host->pwr = 0;
2708 host->clock = 0;
2709 sdhci_do_set_ios(host, &host->mmc->ios);
2710 } else {
2711 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2712 mmiowb();
2713 }
b8c86fc5 2714
7260cf5e
AV		 2715 sdhci_enable_card_detection(host);
2716
2f4cbb3d 2717 return ret;
d129bceb
PO		 2718}
2719
b8c86fc5 2720EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2721
2722static int sdhci_runtime_pm_get(struct sdhci_host *host)
2723{
2724 return pm_runtime_get_sync(host->mmc->parent);
2725}
2726
2727static int sdhci_runtime_pm_put(struct sdhci_host *host)
2728{
2729 pm_runtime_mark_last_busy(host->mmc->parent);
2730 return pm_runtime_put_autosuspend(host->mmc->parent);
2731}
2732
f0710a55
AH		 2733static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2734{
2735 if (host->runtime_suspended || host->bus_on)
2736 return;
2737 host->bus_on = true;
2738 pm_runtime_get_noresume(host->mmc->parent);
2739}
2740
2741static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2742{
2743 if (host->runtime_suspended || !host->bus_on)
2744 return;
2745 host->bus_on = false;
2746 pm_runtime_put_noidle(host->mmc->parent);
2747}
2748
66fd8ad5
AH		 2749int sdhci_runtime_suspend_host(struct sdhci_host *host)
2750{
2751 unsigned long flags;
66fd8ad5 2752
66c39dfc
AH		 2753 mmc_retune_timer_stop(host->mmc);
2754 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2755
2756 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2757 host->ier &= SDHCI_INT_CARD_INT;
2758 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2759 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2760 spin_unlock_irqrestore(&host->lock, flags);
2761
781e989c 2762 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2763
2764 spin_lock_irqsave(&host->lock, flags);
2765 host->runtime_suspended = true;
2766 spin_unlock_irqrestore(&host->lock, flags);
2767
8a125bad 2768 return 0;
66fd8ad5
AH		 2769}
2770EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2771
2772int sdhci_runtime_resume_host(struct sdhci_host *host)
2773{
2774 unsigned long flags;
8a125bad 2775 int host_flags = host->flags;
66fd8ad5
AH		 2776
2777 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2778 if (host->ops->enable_dma)
2779 host->ops->enable_dma(host);
2780 }
2781
2782 sdhci_init(host, 0);
2783
2784 /* Force clock and power re-program */
2785 host->pwr = 0;
2786 host->clock = 0;
3396e736 2787 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
66fd8ad5
AH		 2788 sdhci_do_set_ios(host, &host->mmc->ios);
2789
52983382
KL		 2790 if ((host_flags & SDHCI_PV_ENABLED) &&
2791 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2792 spin_lock_irqsave(&host->lock, flags);
2793 sdhci_enable_preset_value(host, true);
2794 spin_unlock_irqrestore(&host->lock, flags);
2795 }
66fd8ad5 2796
66fd8ad5
AH		 2797 spin_lock_irqsave(&host->lock, flags);
2798
2799 host->runtime_suspended = false;
2800
2801 /* Enable SDIO IRQ */
ef104333 2802 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2803 sdhci_enable_sdio_irq_nolock(host, true);
2804
2805 /* Enable Card Detection */
2806 sdhci_enable_card_detection(host);
2807
2808 spin_unlock_irqrestore(&host->lock, flags);
2809
8a125bad 2810 return 0;
66fd8ad5
AH		 2811}
2812EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2813
162d6f98 2814#endif /* CONFIG_PM */
66fd8ad5 2815
d129bceb
PO		 2816/*****************************************************************************\
2817 * *
b8c86fc5 2818 * Device allocation/registration *
d129bceb
PO		 2819 * *
2820\*****************************************************************************/
2821
b8c86fc5
PO		 2822struct sdhci_host *sdhci_alloc_host(struct device *dev,
2823 size_t priv_size)
d129bceb 2824{
d129bceb
PO		 2825 struct mmc_host *mmc;
2826 struct sdhci_host *host;
2827
b8c86fc5 2828 WARN_ON(dev == NULL);
d129bceb 2829
b8c86fc5 2830 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2831 if (!mmc)
b8c86fc5 2832 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2833
2834 host = mmc_priv(mmc);
2835 host->mmc = mmc;
2836
b8c86fc5
PO		 2837 return host;
2838}
8a4da143 2839
b8c86fc5 2840EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2841
b8c86fc5
PO		 2842int sdhci_add_host(struct sdhci_host *host)
2843{
2844 struct mmc_host *mmc;
bd6a8c30 2845 u32 caps[2] = {0, 0};
f2119df6
AN		 2846 u32 max_current_caps;
2847 unsigned int ocr_avail;
f5fa92e5 2848 unsigned int override_timeout_clk;
b8c86fc5 2849 int ret;
d129bceb 2850
b8c86fc5
PO		 2851 WARN_ON(host == NULL);
2852 if (host == NULL)
2853 return -EINVAL;
d129bceb 2854
b8c86fc5 2855 mmc = host->mmc;
d129bceb 2856
b8c86fc5
PO		 2857 if (debug_quirks)
2858 host->quirks = debug_quirks;
66fd8ad5
AH		 2859 if (debug_quirks2)
2860 host->quirks2 = debug_quirks2;
d129bceb 2861
f5fa92e5
AH		 2862 override_timeout_clk = host->timeout_clk;
2863
03231f9b 2864 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2865
4e4141a5 2866 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2867 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2868 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2869 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2870 pr_err("%s: Unknown controller version (%d). "
b69c9058 2871 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2872 host->version);
4a965505
PO		 2873 }
2874
f2119df6 2875 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2876 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2877
bd6a8c30
PR		 2878 if (host->version >= SDHCI_SPEC_300)
2879 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2880 host->caps1 :
2881 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2882
b8c86fc5 2883 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2884 host->flags |= SDHCI_USE_SDMA;
f2119df6 2885 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2886 DBG("Controller doesn't have SDMA capability\n");
67435274 2887 else
a13abc7b 2888 host->flags |= SDHCI_USE_SDMA;
d129bceb 2889
b8c86fc5 2890 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2891 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2892 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2893 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2894 }
2895
f2119df6
AN		 2896 if ((host->version >= SDHCI_SPEC_200) &&
2897 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2898 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2899
2900 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2901 (host->flags & SDHCI_USE_ADMA)) {
2902 DBG("Disabling ADMA as it is marked broken\n");
2903 host->flags &= ~SDHCI_USE_ADMA;
2904 }
2905
e57a5f61
AH		 2906 /*
2907 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2908 * and *must* do 64-bit DMA. A driver has the opportunity to change
2909 * that during the first call to ->enable_dma(). Similarly
2910 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2911 * implement.
2912 */
2913 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2914 host->flags |= SDHCI_USE_64_BIT_DMA;
2915
a13abc7b 2916 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2917 if (host->ops->enable_dma) {
2918 if (host->ops->enable_dma(host)) {
6606110d 2919 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2920 mmc_hostname(mmc));
a13abc7b
RR		 2921 host->flags &=
2922 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2923 }
d129bceb
PO		 2924 }
2925 }
2926
e57a5f61
AH		 2927 /* SDMA does not support 64-bit DMA */
2928 if (host->flags & SDHCI_USE_64_BIT_DMA)
2929 host->flags &= ~SDHCI_USE_SDMA;
2930
2134a922
PO		 2931 if (host->flags & SDHCI_USE_ADMA) {
2932 /*
76fe379a
AH		 2933 * The DMA descriptor table size is calculated as the maximum
2934 * number of segments times 2, to allow for an alignment
2935 * descriptor for each segment, plus 1 for a nop end descriptor,
2936 * all multipled by the descriptor size.
2134a922 2937 */
e57a5f61
AH		 2938 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2939 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2940 SDHCI_ADMA2_64_DESC_SZ;
2941 host->align_buffer_sz = SDHCI_MAX_SEGS *
2942 SDHCI_ADMA2_64_ALIGN;
2943 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2944 host->align_sz = SDHCI_ADMA2_64_ALIGN;
2945 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2946 } else {
2947 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2948 SDHCI_ADMA2_32_DESC_SZ;
2949 host->align_buffer_sz = SDHCI_MAX_SEGS *
2950 SDHCI_ADMA2_32_ALIGN;
2951 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2952 host->align_sz = SDHCI_ADMA2_32_ALIGN;
2953 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2954 }
4efaa6fb 2955 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
76fe379a 2956 host->adma_table_sz,
4efaa6fb
AH		 2957 &host->adma_addr,
2958 GFP_KERNEL);
76fe379a 2959 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
4efaa6fb 2960 if (!host->adma_table || !host->align_buffer) {
76fe379a 2961 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 2962 host->adma_table, host->adma_addr);
2134a922 2963 kfree(host->align_buffer);
6606110d 2964 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2965 mmc_hostname(mmc));
2966 host->flags &= ~SDHCI_USE_ADMA;
4efaa6fb 2967 host->adma_table = NULL;
d1e49f77 2968 host->align_buffer = NULL;
76fe379a 2969 } else if (host->adma_addr & host->align_mask) {
6606110d
JP		 2970 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2971 mmc_hostname(mmc));
d1e49f77 2972 host->flags &= ~SDHCI_USE_ADMA;
76fe379a 2973 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 2974 host->adma_table, host->adma_addr);
d1e49f77 2975 kfree(host->align_buffer);
4efaa6fb 2976 host->adma_table = NULL;
d1e49f77 2977 host->align_buffer = NULL;
2134a922
PO		 2978 }
2979 }
2980
7659150c
PO		 2981 /*
2982 * If we use DMA, then it's up to the caller to set the DMA
2983 * mask, but PIO does not need the hw shim so we set a new
2984 * mask here in that case.
2985 */
a13abc7b 2986 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 2987 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 2988 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 2989 }
d129bceb 2990
c4687d5f 2991 if (host->version >= SDHCI_SPEC_300)
f2119df6 2992 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2993 >> SDHCI_CLOCK_BASE_SHIFT;
2994 else
f2119df6 2995 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2996 >> SDHCI_CLOCK_BASE_SHIFT;
2997
4240ff0a 2998 host->max_clk *= 1000000;
f27f47ef
AV		 2999 if (host->max_clk == 0 || host->quirks &
3000 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3001 if (!host->ops->get_max_clock) {
a3c76eb9 3002 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 3003 "frequency.\n", mmc_hostname(mmc));
3004 return -ENODEV;
3005 }
3006 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3007 }
d129bceb 3008
348487cb 3009 host->next_data.cookie = 1;
c3ed3877
AN		 3010 /*
3011 * In case of Host Controller v3.00, find out whether clock
3012 * multiplier is supported.
3013 */
3014 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3015 SDHCI_CLOCK_MUL_SHIFT;
3016
3017 /*
3018 * In case the value in Clock Multiplier is 0, then programmable
3019 * clock mode is not supported, otherwise the actual clock
3020 * multiplier is one more than the value of Clock Multiplier
3021 * in the Capabilities Register.
3022 */
3023 if (host->clk_mul)
3024 host->clk_mul += 1;
3025
d129bceb
PO		 3026 /*
3027 * Set host parameters.
3028 */
3029 mmc->ops = &sdhci_ops;
c3ed3877 3030 mmc->f_max = host->max_clk;
ce5f036b 3031 if (host->ops->get_min_clock)
a9e58f25 3032 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3033 else if (host->version >= SDHCI_SPEC_300) {
3034 if (host->clk_mul) {
3035 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3036 mmc->f_max = host->max_clk * host->clk_mul;
3037 } else
3038 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3039 } else
0397526d 3040 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3041
28aab053
AD		 3042 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3043 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3044 SDHCI_TIMEOUT_CLK_SHIFT;
3045 if (host->timeout_clk == 0) {
3046 if (host->ops->get_timeout_clock) {
3047 host->timeout_clk =
3048 host->ops->get_timeout_clock(host);
3049 } else {
3050 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3051 mmc_hostname(mmc));
3052 return -ENODEV;
3053 }
272308ca 3054 }
272308ca 3055
28aab053
AD		 3056 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3057 host->timeout_clk *= 1000;
272308ca 3058
28aab053 3059 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3060 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3061 mmc->max_busy_timeout /= host->timeout_clk;
3062 }
58d1246d 3063
f5fa92e5
AH		 3064 if (override_timeout_clk)
3065 host->timeout_clk = override_timeout_clk;
3066
e89d456f 3067 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3068 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3069
3070 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3071 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3072
8edf6371 3073 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3074 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3075 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3076 !(host->flags & SDHCI_USE_SDMA)) &&
3077 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3078 host->flags |= SDHCI_AUTO_CMD23;
3079 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3080 } else {
3081 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3082 }
3083
15ec4461
PR		 3084 /*
3085 * A controller may support 8-bit width, but the board itself
3086 * might not have the pins brought out. Boards that support
3087 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3088 * their platform code before calling sdhci_add_host(), and we
3089 * won't assume 8-bit width for hosts without that CAP.
3090 */
5fe23c7f 3091 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3092 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3093
63ef5d8c
JH		 3094 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3095 mmc->caps &= ~MMC_CAP_CMD23;
3096
f2119df6 3097 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3098 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3099
176d1ed4 3100 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4e743f1f 3101 !(mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 3102 mmc->caps |= MMC_CAP_NEEDS_POLL;
3103
3a48edc4
TK		 3104 /* If there are external regulators, get them */
3105 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3106 return -EPROBE_DEFER;
3107
6231f3de 3108 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3109 if (!IS_ERR(mmc->supply.vqmmc)) {
3110 ret = regulator_enable(mmc->supply.vqmmc);
3111 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3112 1950000))
8363c374
KL		 3113 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3114 SDHCI_SUPPORT_SDR50 |
3115 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3116 if (ret) {
3117 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3118 mmc_hostname(mmc), ret);
4bb74313 3119 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3120 }
8363c374 3121 }
6231f3de 3122
6a66180a
DD		 3123 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3124 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3125 SDHCI_SUPPORT_DDR50);
3126
4188bba0
AC		 3127 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3128 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3129 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3130 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3131
3132 /* SDR104 supports also implies SDR50 support */
156e14b1 3133 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3134 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3135 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3136 * field can be promoted to support HS200.
3137 */
549c0b18 3138 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3139 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3140 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3141 mmc->caps |= MMC_CAP_UHS_SDR50;
3142
e9fb05d5
AH		 3143 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3144 (caps[1] & SDHCI_SUPPORT_HS400))
3145 mmc->caps2 |= MMC_CAP2_HS400;
3146
549c0b18
AH		 3147 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3148 (IS_ERR(mmc->supply.vqmmc) ||
3149 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3150 1300000)))
3151 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3152
9107ebbf
MC		 3153 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3154 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3155 mmc->caps |= MMC_CAP_UHS_DDR50;
3156
069c9f14 3157 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3158 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3159 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3160
156e14b1 3161 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3162 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3163 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3164
d6d50a15
AN		 3165 /* Driver Type(s) (A, C, D) supported by the host */
3166 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3167 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3168 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3169 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3170 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3171 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3172
cf2b5eea
AN		 3173 /* Initial value for re-tuning timer count */
3174 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3175 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3176
3177 /*
3178 * In case Re-tuning Timer is not disabled, the actual value of
3179 * re-tuning timer will be 2 ^ (n - 1).
3180 */
3181 if (host->tuning_count)
3182 host->tuning_count = 1 << (host->tuning_count - 1);
3183
3184 /* Re-tuning mode supported by the Host Controller */
3185 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3186 SDHCI_RETUNING_MODE_SHIFT;
3187
8f230f45 3188 ocr_avail = 0;
bad37e1a 3189
f2119df6
AN		 3190 /*
3191 * According to SD Host Controller spec v3.00, if the Host System
3192 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3193 * the value is meaningful only if Voltage Support in the Capabilities
3194 * register is set. The actual current value is 4 times the register
3195 * value.
3196 */
3197 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3198 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3199 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3200 if (curr > 0) {
3201
3202 /* convert to SDHCI_MAX_CURRENT format */
3203 curr = curr/1000; /* convert to mA */
3204 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3205
3206 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3207 max_current_caps =
3208 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3209 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3210 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3211 }
3212 }
f2119df6
AN		 3213
3214 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3215 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3216
55c4665e 3217 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3218 SDHCI_MAX_CURRENT_330_MASK) >>
3219 SDHCI_MAX_CURRENT_330_SHIFT) *
3220 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3221 }
3222 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3223 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3224
55c4665e 3225 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3226 SDHCI_MAX_CURRENT_300_MASK) >>
3227 SDHCI_MAX_CURRENT_300_SHIFT) *
3228 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3229 }
3230 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3231 ocr_avail |= MMC_VDD_165_195;
3232
55c4665e 3233 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3234 SDHCI_MAX_CURRENT_180_MASK) >>
3235 SDHCI_MAX_CURRENT_180_SHIFT) *
3236 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3237 }
3238
52221610 3239 /* If OCR set by external regulators, use it instead */
3a48edc4 3240 if (mmc->ocr_avail)
52221610 3241 ocr_avail = mmc->ocr_avail;
3a48edc4 3242
c0b887b6 3243 if (host->ocr_mask)
3a48edc4 3244 ocr_avail &= host->ocr_mask;
c0b887b6 3245
8f230f45
TI		 3246 mmc->ocr_avail = ocr_avail;
3247 mmc->ocr_avail_sdio = ocr_avail;
3248 if (host->ocr_avail_sdio)
3249 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3250 mmc->ocr_avail_sd = ocr_avail;
3251 if (host->ocr_avail_sd)
3252 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3253 else /* normal SD controllers don't support 1.8V */
3254 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3255 mmc->ocr_avail_mmc = ocr_avail;
3256 if (host->ocr_avail_mmc)
3257 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3258
3259 if (mmc->ocr_avail == 0) {
a3c76eb9 3260 pr_err("%s: Hardware doesn't report any "
b69c9058 3261 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3262 return -ENODEV;
146ad66e
PO		 3263 }
3264
d129bceb
PO		 3265 spin_lock_init(&host->lock);
3266
3267 /*
2134a922
PO		 3268 * Maximum number of segments. Depends on if the hardware
3269 * can do scatter/gather or not.
d129bceb 3270 */
2134a922 3271 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3272 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3273 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3274 mmc->max_segs = 1;
2134a922 3275 else /* PIO */
4fb213f8 3276 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3277
3278 /*
ac00531d
AH		 3279 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3280 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3281 * is less anyway.
d129bceb 3282 */
55db890a 3283 mmc->max_req_size = 524288;
d129bceb
PO		 3284
3285 /*
3286 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3287 * of bytes. When doing hardware scatter/gather, each entry cannot
3288 * be larger than 64 KiB though.
d129bceb 3289 */
30652aa3
OJ		 3290 if (host->flags & SDHCI_USE_ADMA) {
3291 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3292 mmc->max_seg_size = 65535;
3293 else
3294 mmc->max_seg_size = 65536;
3295 } else {
2134a922 3296 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3297 }
d129bceb 3298
fe4a3c7a
PO		 3299 /*
3300 * Maximum block size. This varies from controller to controller and
3301 * is specified in the capabilities register.
3302 */
0633f654
AV		 3303 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3304 mmc->max_blk_size = 2;
3305 } else {
f2119df6 3306 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3307 SDHCI_MAX_BLOCK_SHIFT;
3308 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3309 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3310 mmc_hostname(mmc));
0633f654
AV		 3311 mmc->max_blk_size = 0;
3312 }
3313 }
3314
3315 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3316
55db890a
PO		 3317 /*
3318 * Maximum block count.
3319 */
1388eefd 3320 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3321
d129bceb
PO		 3322 /*
3323 * Init tasklets.
3324 */
d129bceb
PO		 3325 tasklet_init(&host->finish_tasklet,
3326 sdhci_tasklet_finish, (unsigned long)host);
3327
e4cad1b5 3328 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3329
250fb7b4 3330 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3331
2af502ca
SG		 3332 sdhci_init(host, 0);
3333
781e989c
RK		 3334 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3335 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3336 if (ret) {
3337 pr_err("%s: Failed to request IRQ %d: %d\n",
3338 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3339 goto untasklet;
0fc81ee3 3340 }
d129bceb 3341
d129bceb
PO		 3342#ifdef CONFIG_MMC_DEBUG
3343 sdhci_dumpregs(host);
3344#endif
3345
f9134319 3346#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3347 snprintf(host->led_name, sizeof(host->led_name),
3348 "%s::", mmc_hostname(mmc));
3349 host->led.name = host->led_name;
2f730fec
PO		 3350 host->led.brightness = LED_OFF;
3351 host->led.default_trigger = mmc_hostname(mmc);
3352 host->led.brightness_set = sdhci_led_control;
3353
b8c86fc5 3354 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3355 if (ret) {
3356 pr_err("%s: Failed to register LED device: %d\n",
3357 mmc_hostname(mmc), ret);
2f730fec 3358 goto reset;
0fc81ee3 3359 }
2f730fec
PO		 3360#endif
3361
5f25a66f
PO		 3362 mmiowb();
3363
d129bceb
PO		 3364 mmc_add_host(mmc);
3365
a3c76eb9 3366 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3367 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3368 (host->flags & SDHCI_USE_ADMA) ?
3369 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3370 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3371
7260cf5e
AV		 3372 sdhci_enable_card_detection(host);
3373
d129bceb
PO		 3374 return 0;
3375
f9134319 3376#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3377reset:
03231f9b 3378 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3379 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3380 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3381 free_irq(host->irq, host);
3382#endif
8ef1a143 3383untasklet:
d129bceb 3384 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3385
3386 return ret;
3387}
3388
b8c86fc5 3389EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3390
1e72859e 3391void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3392{
3a48edc4 3393 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3394 unsigned long flags;
3395
3396 if (dead) {
3397 spin_lock_irqsave(&host->lock, flags);
3398
3399 host->flags |= SDHCI_DEVICE_DEAD;
3400
3401 if (host->mrq) {
a3c76eb9 3402 pr_err("%s: Controller removed during "
4e743f1f 3403 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3404
3405 host->mrq->cmd->error = -ENOMEDIUM;
3406 tasklet_schedule(&host->finish_tasklet);
3407 }
3408
3409 spin_unlock_irqrestore(&host->lock, flags);
3410 }
3411
7260cf5e
AV		 3412 sdhci_disable_card_detection(host);
3413
4e743f1f 3414 mmc_remove_host(mmc);
d129bceb 3415
f9134319 3416#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3417 led_classdev_unregister(&host->led);
3418#endif
3419
1e72859e 3420 if (!dead)
03231f9b 3421 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3422
b537f94c
RK		 3423 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3424 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3425 free_irq(host->irq, host);
3426
3427 del_timer_sync(&host->timer);
3428
d129bceb 3429 tasklet_kill(&host->finish_tasklet);
2134a922 3430
3a48edc4
TK		 3431 if (!IS_ERR(mmc->supply.vqmmc))
3432 regulator_disable(mmc->supply.vqmmc);
6231f3de 3433
4efaa6fb 3434 if (host->adma_table)
76fe379a 3435 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3436 host->adma_table, host->adma_addr);
2134a922
PO		 3437 kfree(host->align_buffer);
3438
4efaa6fb 3439 host->adma_table = NULL;
2134a922 3440 host->align_buffer = NULL;
d129bceb
PO		 3441}
3442
b8c86fc5 3443EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3444
b8c86fc5 3445void sdhci_free_host(struct sdhci_host *host)
d129bceb 3446{
b8c86fc5 3447 mmc_free_host(host->mmc);
d129bceb
PO		 3448}
3449
b8c86fc5 3450EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3451
3452/*****************************************************************************\
3453 * *
3454 * Driver init/exit *
3455 * *
3456\*****************************************************************************/
3457
3458static int __init sdhci_drv_init(void)
3459{
a3c76eb9 3460 pr_info(DRIVER_NAME
52fbf9c9 3461 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3462 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3463
b8c86fc5 3464 return 0;
d129bceb
PO		 3465}
3466
3467static void __exit sdhci_drv_exit(void)
3468{
d129bceb
PO		 3469}
3470
3471module_init(sdhci_drv_init);
3472module_exit(sdhci_drv_exit);
3473
df673b22 3474module_param(debug_quirks, uint, 0444);
66fd8ad5 3475module_param(debug_quirks2, uint, 0444);
67435274 3476
32710e8f 3477MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3478MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3479MODULE_LICENSE("GPL");
67435274 3480
df673b22 3481MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3482MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux 6.x block layer and io_uring tree(s)