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mmc: sdhci-esdhc-imx: add preset value quirk for mx6
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
d129bceb 52static void sdhci_finish_command(struct sdhci_host *);
069c9f14 53static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 54static void sdhci_tuning_timer(unsigned long data);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 56
66fd8ad5
AH		 57#ifdef CONFIG_PM_RUNTIME
58static int sdhci_runtime_pm_get(struct sdhci_host *host);
59static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 60static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
61static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 62#else
63static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
64{
65 return 0;
66}
67static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
68{
69 return 0;
70}
f0710a55
AH		 71static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
72{
73}
74static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
75{
76}
66fd8ad5
AH		 77#endif
78
d129bceb
PO		 79static void sdhci_dumpregs(struct sdhci_host *host)
80{
a3c76eb9 81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 82 mmc_hostname(host->mmc));
d129bceb 83
a3c76eb9 84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 85 sdhci_readl(host, SDHCI_DMA_ADDRESS),
86 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readw(host, SDHCI_BLOCK_SIZE),
89 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readl(host, SDHCI_ARGUMENT),
92 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readl(host, SDHCI_PRESENT_STATE),
95 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readb(host, SDHCI_POWER_CONTROL),
98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
101 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
104 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 106 sdhci_readl(host, SDHCI_INT_ENABLE),
107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 109 sdhci_readw(host, SDHCI_ACMD12_ERR),
110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 112 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 113 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 115 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 116 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 118 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 119
be3f4ae0 120 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 121 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 122 readl(host->ioaddr + SDHCI_ADMA_ERROR),
123 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
124
a3c76eb9 125 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 126}
127
128/*****************************************************************************\
129 * *
130 * Low level functions *
131 * *
132\*****************************************************************************/
133
7260cf5e
AV		 134static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
135{
136 u32 ier;
137
138 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
139 ier &= ~clear;
140 ier |= set;
141 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
142 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
143}
144
145static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
146{
147 sdhci_clear_set_irqs(host, 0, irqs);
148}
149
150static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
151{
152 sdhci_clear_set_irqs(host, irqs, 0);
153}
154
155static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
156{
d25928d1 157 u32 present, irqs;
7260cf5e 158
c79396c1 159 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 160 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 161 return;
162
d25928d1
SG		 163 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
164 SDHCI_CARD_PRESENT;
165 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
166
7260cf5e
AV		 167 if (enable)
168 sdhci_unmask_irqs(host, irqs);
169 else
170 sdhci_mask_irqs(host, irqs);
171}
172
173static void sdhci_enable_card_detection(struct sdhci_host *host)
174{
175 sdhci_set_card_detection(host, true);
176}
177
178static void sdhci_disable_card_detection(struct sdhci_host *host)
179{
180 sdhci_set_card_detection(host, false);
181}
182
d129bceb
PO		 183static void sdhci_reset(struct sdhci_host *host, u8 mask)
184{
e16514d8 185 unsigned long timeout;
063a9dbb 186 u32 uninitialized_var(ier);
e16514d8 187
b8c86fc5 188 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 189 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 190 SDHCI_CARD_PRESENT))
191 return;
192 }
193
063a9dbb
AV		 194 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
195 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
196
393c1a34
PR		 197 if (host->ops->platform_reset_enter)
198 host->ops->platform_reset_enter(host, mask);
199
4e4141a5 200 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 201
f0710a55 202 if (mask & SDHCI_RESET_ALL) {
d129bceb 203 host->clock = 0;
f0710a55
AH		 204 /* Reset-all turns off SD Bus Power */
205 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
206 sdhci_runtime_pm_bus_off(host);
207 }
d129bceb 208
e16514d8
PO		 209 /* Wait max 100 ms */
210 timeout = 100;
211
212 /* hw clears the bit when it's done */
4e4141a5 213 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 214 if (timeout == 0) {
a3c76eb9 215 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 216 mmc_hostname(host->mmc), (int)mask);
217 sdhci_dumpregs(host);
218 return;
219 }
220 timeout--;
221 mdelay(1);
d129bceb 222 }
063a9dbb 223
393c1a34
PR		 224 if (host->ops->platform_reset_exit)
225 host->ops->platform_reset_exit(host, mask);
226
063a9dbb
AV		 227 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
228 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
3abc1e80
SX		 229
230 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
231 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
232 host->ops->enable_dma(host);
233 }
d129bceb
PO		 234}
235
2f4cbb3d
NP		 236static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
237
238static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 239{
2f4cbb3d
NP		 240 if (soft)
241 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
242 else
243 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 244
7260cf5e
AV		 245 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
246 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 247 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
248 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 249 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 250
251 if (soft) {
252 /* force clock reconfiguration */
253 host->clock = 0;
254 sdhci_set_ios(host->mmc, &host->mmc->ios);
255 }
7260cf5e 256}
d129bceb 257
7260cf5e
AV		 258static void sdhci_reinit(struct sdhci_host *host)
259{
2f4cbb3d 260 sdhci_init(host, 0);
b67c6b41
AL		 261 /*
262 * Retuning stuffs are affected by different cards inserted and only
263 * applicable to UHS-I cards. So reset these fields to their initial
264 * value when card is removed.
265 */
973905fe
AL		 266 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
267 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
268
b67c6b41
AL		 269 del_timer_sync(&host->tuning_timer);
270 host->flags &= ~SDHCI_NEEDS_RETUNING;
271 host->mmc->max_blk_count =
272 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
273 }
7260cf5e 274 sdhci_enable_card_detection(host);
d129bceb
PO		 275}
276
277static void sdhci_activate_led(struct sdhci_host *host)
278{
279 u8 ctrl;
280
4e4141a5 281 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 282 ctrl |= SDHCI_CTRL_LED;
4e4141a5 283 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 284}
285
286static void sdhci_deactivate_led(struct sdhci_host *host)
287{
288 u8 ctrl;
289
4e4141a5 290 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 291 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 292 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 293}
294
f9134319 295#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 296static void sdhci_led_control(struct led_classdev *led,
297 enum led_brightness brightness)
298{
299 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
300 unsigned long flags;
301
302 spin_lock_irqsave(&host->lock, flags);
303
66fd8ad5
AH		 304 if (host->runtime_suspended)
305 goto out;
306
2f730fec
PO		 307 if (brightness == LED_OFF)
308 sdhci_deactivate_led(host);
309 else
310 sdhci_activate_led(host);
66fd8ad5 311out:
2f730fec
PO		 312 spin_unlock_irqrestore(&host->lock, flags);
313}
314#endif
315
d129bceb
PO		 316/*****************************************************************************\
317 * *
318 * Core functions *
319 * *
320\*****************************************************************************/
321
a406f5a3 322static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 323{
7659150c
PO		 324 unsigned long flags;
325 size_t blksize, len, chunk;
7244b85b 326 u32 uninitialized_var(scratch);
7659150c 327 u8 *buf;
d129bceb 328
a406f5a3 329 DBG("PIO reading\n");
d129bceb 330
a406f5a3 331 blksize = host->data->blksz;
7659150c 332 chunk = 0;
d129bceb 333
7659150c 334 local_irq_save(flags);
d129bceb 335
a406f5a3 336 while (blksize) {
7659150c
PO		 337 if (!sg_miter_next(&host->sg_miter))
338 BUG();
d129bceb 339
7659150c 340 len = min(host->sg_miter.length, blksize);
d129bceb 341
7659150c
PO		 342 blksize -= len;
343 host->sg_miter.consumed = len;
14d836e7 344
7659150c 345 buf = host->sg_miter.addr;
d129bceb 346
7659150c
PO		 347 while (len) {
348 if (chunk == 0) {
4e4141a5 349 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 350 chunk = 4;
a406f5a3 351 }
7659150c
PO		 352
353 *buf = scratch & 0xFF;
354
355 buf++;
356 scratch >>= 8;
357 chunk--;
358 len--;
d129bceb 359 }
a406f5a3 360 }
7659150c
PO		 361
362 sg_miter_stop(&host->sg_miter);
363
364 local_irq_restore(flags);
a406f5a3 365}
d129bceb 366
a406f5a3
PO		 367static void sdhci_write_block_pio(struct sdhci_host *host)
368{
7659150c
PO		 369 unsigned long flags;
370 size_t blksize, len, chunk;
371 u32 scratch;
372 u8 *buf;
d129bceb 373
a406f5a3
PO		 374 DBG("PIO writing\n");
375
376 blksize = host->data->blksz;
7659150c
PO		 377 chunk = 0;
378 scratch = 0;
d129bceb 379
7659150c 380 local_irq_save(flags);
d129bceb 381
a406f5a3 382 while (blksize) {
7659150c
PO		 383 if (!sg_miter_next(&host->sg_miter))
384 BUG();
a406f5a3 385
7659150c
PO		 386 len = min(host->sg_miter.length, blksize);
387
388 blksize -= len;
389 host->sg_miter.consumed = len;
390
391 buf = host->sg_miter.addr;
d129bceb 392
7659150c
PO		 393 while (len) {
394 scratch |= (u32)*buf << (chunk * 8);
395
396 buf++;
397 chunk++;
398 len--;
399
400 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 401 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 402 chunk = 0;
403 scratch = 0;
d129bceb 404 }
d129bceb
PO		 405 }
406 }
7659150c
PO		 407
408 sg_miter_stop(&host->sg_miter);
409
410 local_irq_restore(flags);
a406f5a3
PO		 411}
412
413static void sdhci_transfer_pio(struct sdhci_host *host)
414{
415 u32 mask;
416
417 BUG_ON(!host->data);
418
7659150c 419 if (host->blocks == 0)
a406f5a3
PO		 420 return;
421
422 if (host->data->flags & MMC_DATA_READ)
423 mask = SDHCI_DATA_AVAILABLE;
424 else
425 mask = SDHCI_SPACE_AVAILABLE;
426
4a3cba32
PO		 427 /*
428 * Some controllers (JMicron JMB38x) mess up the buffer bits
429 * for transfers < 4 bytes. As long as it is just one block,
430 * we can ignore the bits.
431 */
432 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
433 (host->data->blocks == 1))
434 mask = ~0;
435
4e4141a5 436 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 437 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
438 udelay(100);
439
a406f5a3
PO		 440 if (host->data->flags & MMC_DATA_READ)
441 sdhci_read_block_pio(host);
442 else
443 sdhci_write_block_pio(host);
d129bceb 444
7659150c
PO		 445 host->blocks--;
446 if (host->blocks == 0)
a406f5a3 447 break;
a406f5a3 448 }
d129bceb 449
a406f5a3 450 DBG("PIO transfer complete.\n");
d129bceb
PO		 451}
452
2134a922
PO		 453static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
454{
455 local_irq_save(*flags);
482fce99 456 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 457}
458
459static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
460{
482fce99 461 kunmap_atomic(buffer);
2134a922
PO		 462 local_irq_restore(*flags);
463}
464
118cd17d
BD		 465static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
466{
9e506f35
BD		 467 __le32 *dataddr = (__le32 __force *)(desc + 4);
468 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 469
9e506f35
BD		 470 /* SDHCI specification says ADMA descriptors should be 4 byte
471 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 472
9e506f35
BD		 473 cmdlen[0] = cpu_to_le16(cmd);
474 cmdlen[1] = cpu_to_le16(len);
475
476 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 477}
478
8f1934ce 479static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 480 struct mmc_data *data)
481{
482 int direction;
483
484 u8 *desc;
485 u8 *align;
486 dma_addr_t addr;
487 dma_addr_t align_addr;
488 int len, offset;
489
490 struct scatterlist *sg;
491 int i;
492 char *buffer;
493 unsigned long flags;
494
495 /*
496 * The spec does not specify endianness of descriptor table.
497 * We currently guess that it is LE.
498 */
499
500 if (data->flags & MMC_DATA_READ)
501 direction = DMA_FROM_DEVICE;
502 else
503 direction = DMA_TO_DEVICE;
504
505 /*
506 * The ADMA descriptor table is mapped further down as we
507 * need to fill it with data first.
508 */
509
510 host->align_addr = dma_map_single(mmc_dev(host->mmc),
511 host->align_buffer, 128 * 4, direction);
8d8bb39b 512 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 513 goto fail;
2134a922
PO		 514 BUG_ON(host->align_addr & 0x3);
515
516 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
517 data->sg, data->sg_len, direction);
8f1934ce
PO		 518 if (host->sg_count == 0)
519 goto unmap_align;
2134a922
PO		 520
521 desc = host->adma_desc;
522 align = host->align_buffer;
523
524 align_addr = host->align_addr;
525
526 for_each_sg(data->sg, sg, host->sg_count, i) {
527 addr = sg_dma_address(sg);
528 len = sg_dma_len(sg);
529
530 /*
531 * The SDHCI specification states that ADMA
532 * addresses must be 32-bit aligned. If they
533 * aren't, then we use a bounce buffer for
534 * the (up to three) bytes that screw up the
535 * alignment.
536 */
537 offset = (4 - (addr & 0x3)) & 0x3;
538 if (offset) {
539 if (data->flags & MMC_DATA_WRITE) {
540 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 541 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 542 memcpy(align, buffer, offset);
543 sdhci_kunmap_atomic(buffer, &flags);
544 }
545
118cd17d
BD		 546 /* tran, valid */
547 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 548
549 BUG_ON(offset > 65536);
550
2134a922
PO		 551 align += 4;
552 align_addr += 4;
553
554 desc += 8;
555
556 addr += offset;
557 len -= offset;
558 }
559
2134a922
PO		 560 BUG_ON(len > 65536);
561
118cd17d
BD		 562 /* tran, valid */
563 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 564 desc += 8;
565
566 /*
567 * If this triggers then we have a calculation bug
568 * somewhere. :/
569 */
570 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
571 }
572
70764a90
TA		 573 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
574 /*
575 * Mark the last descriptor as the terminating descriptor
576 */
577 if (desc != host->adma_desc) {
578 desc -= 8;
579 desc[0] |= 0x2; /* end */
580 }
581 } else {
582 /*
583 * Add a terminating entry.
584 */
2134a922 585
70764a90
TA		 586 /* nop, end, valid */
587 sdhci_set_adma_desc(desc, 0, 0, 0x3);
588 }
2134a922
PO		 589
590 /*
591 * Resync align buffer as we might have changed it.
592 */
593 if (data->flags & MMC_DATA_WRITE) {
594 dma_sync_single_for_device(mmc_dev(host->mmc),
595 host->align_addr, 128 * 4, direction);
596 }
597
598 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
599 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 600 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 601 goto unmap_entries;
2134a922 602 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 603
604 return 0;
605
606unmap_entries:
607 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
608 data->sg_len, direction);
609unmap_align:
610 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
611 128 * 4, direction);
612fail:
613 return -EINVAL;
2134a922
PO		 614}
615
616static void sdhci_adma_table_post(struct sdhci_host *host,
617 struct mmc_data *data)
618{
619 int direction;
620
621 struct scatterlist *sg;
622 int i, size;
623 u8 *align;
624 char *buffer;
625 unsigned long flags;
626
627 if (data->flags & MMC_DATA_READ)
628 direction = DMA_FROM_DEVICE;
629 else
630 direction = DMA_TO_DEVICE;
631
632 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
633 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
634
635 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
636 128 * 4, direction);
637
638 if (data->flags & MMC_DATA_READ) {
639 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
640 data->sg_len, direction);
641
642 align = host->align_buffer;
643
644 for_each_sg(data->sg, sg, host->sg_count, i) {
645 if (sg_dma_address(sg) & 0x3) {
646 size = 4 - (sg_dma_address(sg) & 0x3);
647
648 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 649 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 650 memcpy(buffer, align, size);
651 sdhci_kunmap_atomic(buffer, &flags);
652
653 align += 4;
654 }
655 }
656 }
657
658 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
659 data->sg_len, direction);
660}
661
a3c7778f 662static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 663{
1c8cde92 664 u8 count;
a3c7778f 665 struct mmc_data *data = cmd->data;
1c8cde92 666 unsigned target_timeout, current_timeout;
d129bceb 667
ee53ab5d
PO		 668 /*
669 * If the host controller provides us with an incorrect timeout
670 * value, just skip the check and use 0xE. The hardware may take
671 * longer to time out, but that's much better than having a too-short
672 * timeout value.
673 */
11a2f1b7 674 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 675 return 0xE;
e538fbe8 676
a3c7778f
AW		 677 /* Unspecified timeout, assume max */
678 if (!data && !cmd->cmd_timeout_ms)
679 return 0xE;
d129bceb 680
a3c7778f
AW		 681 /* timeout in us */
682 if (!data)
683 target_timeout = cmd->cmd_timeout_ms * 1000;
78a2ca27
AS		 684 else {
685 target_timeout = data->timeout_ns / 1000;
686 if (host->clock)
687 target_timeout += data->timeout_clks / host->clock;
688 }
81b39802 689
1c8cde92
PO		 690 /*
691 * Figure out needed cycles.
692 * We do this in steps in order to fit inside a 32 bit int.
693 * The first step is the minimum timeout, which will have a
694 * minimum resolution of 6 bits:
695 * (1) 2^13*1000 > 2^22,
696 * (2) host->timeout_clk < 2^16
697 * =>
698 * (1) / (2) > 2^6
699 */
700 count = 0;
701 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
702 while (current_timeout < target_timeout) {
703 count++;
704 current_timeout <<= 1;
705 if (count >= 0xF)
706 break;
707 }
708
709 if (count >= 0xF) {
09eeff52
CB		 710 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
711 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 712 count = 0xE;
713 }
714
ee53ab5d
PO		 715 return count;
716}
717
6aa943ab
AV		 718static void sdhci_set_transfer_irqs(struct sdhci_host *host)
719{
720 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
721 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
722
723 if (host->flags & SDHCI_REQ_USE_DMA)
724 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
725 else
726 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
727}
728
a3c7778f 729static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 730{
731 u8 count;
2134a922 732 u8 ctrl;
a3c7778f 733 struct mmc_data *data = cmd->data;
8f1934ce 734 int ret;
ee53ab5d
PO		 735
736 WARN_ON(host->data);
737
a3c7778f
AW		 738 if (data || (cmd->flags & MMC_RSP_BUSY)) {
739 count = sdhci_calc_timeout(host, cmd);
740 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
741 }
742
743 if (!data)
ee53ab5d
PO		 744 return;
745
746 /* Sanity checks */
747 BUG_ON(data->blksz * data->blocks > 524288);
748 BUG_ON(data->blksz > host->mmc->max_blk_size);
749 BUG_ON(data->blocks > 65535);
750
751 host->data = data;
752 host->data_early = 0;
f6a03cbf 753 host->data->bytes_xfered = 0;
ee53ab5d 754
a13abc7b 755 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 756 host->flags |= SDHCI_REQ_USE_DMA;
757
2134a922
PO		 758 /*
759 * FIXME: This doesn't account for merging when mapping the
760 * scatterlist.
761 */
762 if (host->flags & SDHCI_REQ_USE_DMA) {
763 int broken, i;
764 struct scatterlist *sg;
765
766 broken = 0;
767 if (host->flags & SDHCI_USE_ADMA) {
768 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
769 broken = 1;
770 } else {
771 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
772 broken = 1;
773 }
774
775 if (unlikely(broken)) {
776 for_each_sg(data->sg, sg, data->sg_len, i) {
777 if (sg->length & 0x3) {
778 DBG("Reverting to PIO because of "
779 "transfer size (%d)\n",
780 sg->length);
781 host->flags &= ~SDHCI_REQ_USE_DMA;
782 break;
783 }
784 }
785 }
c9fddbc4
PO		 786 }
787
788 /*
789 * The assumption here being that alignment is the same after
790 * translation to device address space.
791 */
2134a922
PO		 792 if (host->flags & SDHCI_REQ_USE_DMA) {
793 int broken, i;
794 struct scatterlist *sg;
795
796 broken = 0;
797 if (host->flags & SDHCI_USE_ADMA) {
798 /*
799 * As we use 3 byte chunks to work around
800 * alignment problems, we need to check this
801 * quirk.
802 */
803 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
804 broken = 1;
805 } else {
806 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
807 broken = 1;
808 }
809
810 if (unlikely(broken)) {
811 for_each_sg(data->sg, sg, data->sg_len, i) {
812 if (sg->offset & 0x3) {
813 DBG("Reverting to PIO because of "
814 "bad alignment\n");
815 host->flags &= ~SDHCI_REQ_USE_DMA;
816 break;
817 }
818 }
819 }
820 }
821
8f1934ce
PO		 822 if (host->flags & SDHCI_REQ_USE_DMA) {
823 if (host->flags & SDHCI_USE_ADMA) {
824 ret = sdhci_adma_table_pre(host, data);
825 if (ret) {
826 /*
827 * This only happens when someone fed
828 * us an invalid request.
829 */
830 WARN_ON(1);
ebd6d357 831 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 832 } else {
4e4141a5
AV		 833 sdhci_writel(host, host->adma_addr,
834 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 835 }
836 } else {
c8b3e02e 837 int sg_cnt;
8f1934ce 838
c8b3e02e 839 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 840 data->sg, data->sg_len,
841 (data->flags & MMC_DATA_READ) ?
842 DMA_FROM_DEVICE :
843 DMA_TO_DEVICE);
c8b3e02e 844 if (sg_cnt == 0) {
8f1934ce
PO		 845 /*
846 * This only happens when someone fed
847 * us an invalid request.
848 */
849 WARN_ON(1);
ebd6d357 850 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 851 } else {
719a61b4 852 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 853 sdhci_writel(host, sg_dma_address(data->sg),
854 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 855 }
856 }
857 }
858
2134a922
PO		 859 /*
860 * Always adjust the DMA selection as some controllers
861 * (e.g. JMicron) can't do PIO properly when the selection
862 * is ADMA.
863 */
864 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 865 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 866 ctrl &= ~SDHCI_CTRL_DMA_MASK;
867 if ((host->flags & SDHCI_REQ_USE_DMA) &&
868 (host->flags & SDHCI_USE_ADMA))
869 ctrl |= SDHCI_CTRL_ADMA32;
870 else
871 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 872 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 873 }
874
8f1934ce 875 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 876 int flags;
877
878 flags = SG_MITER_ATOMIC;
879 if (host->data->flags & MMC_DATA_READ)
880 flags |= SG_MITER_TO_SG;
881 else
882 flags |= SG_MITER_FROM_SG;
883 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 884 host->blocks = data->blocks;
d129bceb 885 }
c7fa9963 886
6aa943ab
AV		 887 sdhci_set_transfer_irqs(host);
888
f6a03cbf
MV		 889 /* Set the DMA boundary value and block size */
890 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
891 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 892 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 893}
894
895static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 896 struct mmc_command *cmd)
c7fa9963
PO		 897{
898 u16 mode;
e89d456f 899 struct mmc_data *data = cmd->data;
c7fa9963 900
c7fa9963
PO		 901 if (data == NULL)
902 return;
903
e538fbe8
PO		 904 WARN_ON(!host->data);
905
c7fa9963 906 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 907 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
908 mode |= SDHCI_TRNS_MULTI;
909 /*
910 * If we are sending CMD23, CMD12 never gets sent
911 * on successful completion (so no Auto-CMD12).
912 */
913 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
914 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 915 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
916 mode |= SDHCI_TRNS_AUTO_CMD23;
917 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
918 }
c4512f79 919 }
8edf6371 920
c7fa9963
PO		 921 if (data->flags & MMC_DATA_READ)
922 mode |= SDHCI_TRNS_READ;
c9fddbc4 923 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 924 mode |= SDHCI_TRNS_DMA;
925
4e4141a5 926 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 927}
928
929static void sdhci_finish_data(struct sdhci_host *host)
930{
931 struct mmc_data *data;
d129bceb
PO		 932
933 BUG_ON(!host->data);
934
935 data = host->data;
936 host->data = NULL;
937
c9fddbc4 938 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 939 if (host->flags & SDHCI_USE_ADMA)
940 sdhci_adma_table_post(host, data);
941 else {
942 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
943 data->sg_len, (data->flags & MMC_DATA_READ) ?
944 DMA_FROM_DEVICE : DMA_TO_DEVICE);
945 }
d129bceb
PO		 946 }
947
948 /*
c9b74c5b
PO		 949 * The specification states that the block count register must
950 * be updated, but it does not specify at what point in the
951 * data flow. That makes the register entirely useless to read
952 * back so we have to assume that nothing made it to the card
953 * in the event of an error.
d129bceb 954 */
c9b74c5b
PO		 955 if (data->error)
956 data->bytes_xfered = 0;
d129bceb 957 else
c9b74c5b 958 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 959
e89d456f
AW		 960 /*
961 * Need to send CMD12 if -
962 * a) open-ended multiblock transfer (no CMD23)
963 * b) error in multiblock transfer
964 */
965 if (data->stop &&
966 (data->error ||
967 !host->mrq->sbc)) {
968
d129bceb
PO		 969 /*
970 * The controller needs a reset of internal state machines
971 * upon error conditions.
972 */
17b0429d 973 if (data->error) {
d129bceb
PO		 974 sdhci_reset(host, SDHCI_RESET_CMD);
975 sdhci_reset(host, SDHCI_RESET_DATA);
976 }
977
978 sdhci_send_command(host, data->stop);
979 } else
980 tasklet_schedule(&host->finish_tasklet);
981}
982
c0e55129 983void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 984{
985 int flags;
fd2208d7 986 u32 mask;
7cb2c76f 987 unsigned long timeout;
d129bceb
PO		 988
989 WARN_ON(host->cmd);
990
d129bceb 991 /* Wait max 10 ms */
7cb2c76f 992 timeout = 10;
fd2208d7
PO		 993
994 mask = SDHCI_CMD_INHIBIT;
995 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
996 mask |= SDHCI_DATA_INHIBIT;
997
998 /* We shouldn't wait for data inihibit for stop commands, even
999 though they might use busy signaling */
1000 if (host->mrq->data && (cmd == host->mrq->data->stop))
1001 mask &= ~SDHCI_DATA_INHIBIT;
1002
4e4141a5 1003 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1004 if (timeout == 0) {
a3c76eb9 1005 pr_err("%s: Controller never released "
acf1da45 1006 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 1007 sdhci_dumpregs(host);
17b0429d 1008 cmd->error = -EIO;
d129bceb
PO		 1009 tasklet_schedule(&host->finish_tasklet);
1010 return;
1011 }
7cb2c76f
PO		 1012 timeout--;
1013 mdelay(1);
1014 }
d129bceb
PO		 1015
1016 mod_timer(&host->timer, jiffies + 10 * HZ);
1017
1018 host->cmd = cmd;
1019
a3c7778f 1020 sdhci_prepare_data(host, cmd);
d129bceb 1021
4e4141a5 1022 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1023
e89d456f 1024 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1025
d129bceb 1026 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1027 pr_err("%s: Unsupported response type!\n",
d129bceb 1028 mmc_hostname(host->mmc));
17b0429d 1029 cmd->error = -EINVAL;
d129bceb
PO		 1030 tasklet_schedule(&host->finish_tasklet);
1031 return;
1032 }
1033
1034 if (!(cmd->flags & MMC_RSP_PRESENT))
1035 flags = SDHCI_CMD_RESP_NONE;
1036 else if (cmd->flags & MMC_RSP_136)
1037 flags = SDHCI_CMD_RESP_LONG;
1038 else if (cmd->flags & MMC_RSP_BUSY)
1039 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1040 else
1041 flags = SDHCI_CMD_RESP_SHORT;
1042
1043 if (cmd->flags & MMC_RSP_CRC)
1044 flags |= SDHCI_CMD_CRC;
1045 if (cmd->flags & MMC_RSP_OPCODE)
1046 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1047
1048 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1049 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1050 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1051 flags |= SDHCI_CMD_DATA;
1052
4e4141a5 1053 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1054}
c0e55129 1055EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1056
1057static void sdhci_finish_command(struct sdhci_host *host)
1058{
1059 int i;
1060
1061 BUG_ON(host->cmd == NULL);
1062
1063 if (host->cmd->flags & MMC_RSP_PRESENT) {
1064 if (host->cmd->flags & MMC_RSP_136) {
1065 /* CRC is stripped so we need to do some shifting. */
1066 for (i = 0;i < 4;i++) {
4e4141a5 1067 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1068 SDHCI_RESPONSE + (3-i)*4) << 8;
1069 if (i != 3)
1070 host->cmd->resp[i] |=
4e4141a5 1071 sdhci_readb(host,
d129bceb
PO		 1072 SDHCI_RESPONSE + (3-i)*4-1);
1073 }
1074 } else {
4e4141a5 1075 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1076 }
1077 }
1078
17b0429d 1079 host->cmd->error = 0;
d129bceb 1080
e89d456f
AW		 1081 /* Finished CMD23, now send actual command. */
1082 if (host->cmd == host->mrq->sbc) {
1083 host->cmd = NULL;
1084 sdhci_send_command(host, host->mrq->cmd);
1085 } else {
e538fbe8 1086
e89d456f
AW		 1087 /* Processed actual command. */
1088 if (host->data && host->data_early)
1089 sdhci_finish_data(host);
d129bceb 1090
e89d456f
AW		 1091 if (!host->cmd->data)
1092 tasklet_schedule(&host->finish_tasklet);
1093
1094 host->cmd = NULL;
1095 }
d129bceb
PO		 1096}
1097
52983382
KL		 1098static u16 sdhci_get_preset_value(struct sdhci_host *host)
1099{
1100 u16 ctrl, preset = 0;
1101
1102 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1103
1104 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1105 case SDHCI_CTRL_UHS_SDR12:
1106 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1107 break;
1108 case SDHCI_CTRL_UHS_SDR25:
1109 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1110 break;
1111 case SDHCI_CTRL_UHS_SDR50:
1112 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1113 break;
1114 case SDHCI_CTRL_UHS_SDR104:
1115 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1116 break;
1117 case SDHCI_CTRL_UHS_DDR50:
1118 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1119 break;
1120 default:
1121 pr_warn("%s: Invalid UHS-I mode selected\n",
1122 mmc_hostname(host->mmc));
1123 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1124 break;
1125 }
1126 return preset;
1127}
1128
d129bceb
PO		 1129static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1130{
c3ed3877 1131 int div = 0; /* Initialized for compiler warning */
df16219f 1132 int real_div = div, clk_mul = 1;
c3ed3877 1133 u16 clk = 0;
7cb2c76f 1134 unsigned long timeout;
d129bceb 1135
30832ab5 1136 if (clock && clock == host->clock)
d129bceb
PO		 1137 return;
1138
df16219f
GC		 1139 host->mmc->actual_clock = 0;
1140
8114634c
AV		 1141 if (host->ops->set_clock) {
1142 host->ops->set_clock(host, clock);
1143 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1144 return;
1145 }
1146
4e4141a5 1147 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1148
1149 if (clock == 0)
1150 goto out;
1151
85105c53 1152 if (host->version >= SDHCI_SPEC_300) {
52983382
KL		 1153 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1154 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1155 u16 pre_val;
1156
1157 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1158 pre_val = sdhci_get_preset_value(host);
1159 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1160 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1161 if (host->clk_mul &&
1162 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1163 clk = SDHCI_PROG_CLOCK_MODE;
1164 real_div = div + 1;
1165 clk_mul = host->clk_mul;
1166 } else {
1167 real_div = max_t(int, 1, div << 1);
1168 }
1169 goto clock_set;
1170 }
1171
c3ed3877
AN		 1172 /*
1173 * Check if the Host Controller supports Programmable Clock
1174 * Mode.
1175 */
1176 if (host->clk_mul) {
52983382
KL		 1177 for (div = 1; div <= 1024; div++) {
1178 if ((host->max_clk * host->clk_mul / div)
1179 <= clock)
1180 break;
1181 }
c3ed3877 1182 /*
52983382
KL		 1183 * Set Programmable Clock Mode in the Clock
1184 * Control register.
c3ed3877 1185 */
52983382
KL		 1186 clk = SDHCI_PROG_CLOCK_MODE;
1187 real_div = div;
1188 clk_mul = host->clk_mul;
1189 div--;
c3ed3877
AN		 1190 } else {
1191 /* Version 3.00 divisors must be a multiple of 2. */
1192 if (host->max_clk <= clock)
1193 div = 1;
1194 else {
1195 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1196 div += 2) {
1197 if ((host->max_clk / div) <= clock)
1198 break;
1199 }
85105c53 1200 }
df16219f 1201 real_div = div;
c3ed3877 1202 div >>= 1;
85105c53
ZG		 1203 }
1204 } else {
1205 /* Version 2.00 divisors must be a power of 2. */
0397526d 1206 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1207 if ((host->max_clk / div) <= clock)
1208 break;
1209 }
df16219f 1210 real_div = div;
c3ed3877 1211 div >>= 1;
d129bceb 1212 }
d129bceb 1213
52983382 1214clock_set:
df16219f
GC		 1215 if (real_div)
1216 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1217
c3ed3877 1218 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1219 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1220 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1221 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1222 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1223
27f6cb16
CB		 1224 /* Wait max 20 ms */
1225 timeout = 20;
4e4141a5 1226 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1227 & SDHCI_CLOCK_INT_STABLE)) {
1228 if (timeout == 0) {
a3c76eb9 1229 pr_err("%s: Internal clock never "
acf1da45 1230 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1231 sdhci_dumpregs(host);
1232 return;
1233 }
7cb2c76f
PO		 1234 timeout--;
1235 mdelay(1);
1236 }
d129bceb
PO		 1237
1238 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1239 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1240
1241out:
1242 host->clock = clock;
1243}
1244
8213af3b
AS		 1245static inline void sdhci_update_clock(struct sdhci_host *host)
1246{
1247 unsigned int clock;
1248
1249 clock = host->clock;
1250 host->clock = 0;
1251 sdhci_set_clock(host, clock);
1252}
1253
ceb6143b 1254static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1255{
8364248a 1256 u8 pwr = 0;
146ad66e 1257
8364248a 1258 if (power != (unsigned short)-1) {
ae628903
PO		 1259 switch (1 << power) {
1260 case MMC_VDD_165_195:
1261 pwr = SDHCI_POWER_180;
1262 break;
1263 case MMC_VDD_29_30:
1264 case MMC_VDD_30_31:
1265 pwr = SDHCI_POWER_300;
1266 break;
1267 case MMC_VDD_32_33:
1268 case MMC_VDD_33_34:
1269 pwr = SDHCI_POWER_330;
1270 break;
1271 default:
1272 BUG();
1273 }
1274 }
1275
1276 if (host->pwr == pwr)
ceb6143b 1277 return -1;
146ad66e 1278
ae628903
PO		 1279 host->pwr = pwr;
1280
1281 if (pwr == 0) {
4e4141a5 1282 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1283 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1284 sdhci_runtime_pm_bus_off(host);
ceb6143b 1285 return 0;
9e9dc5f2
DS		 1286 }
1287
1288 /*
1289 * Spec says that we should clear the power reg before setting
1290 * a new value. Some controllers don't seem to like this though.
1291 */
b8c86fc5 1292 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1293 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1294
e08c1694 1295 /*
c71f6512 1296 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1297 * and set turn on power at the same time, so set the voltage first.
1298 */
11a2f1b7 1299 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1300 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1301
ae628903 1302 pwr |= SDHCI_POWER_ON;
146ad66e 1303
ae628903 1304 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1305
f0710a55
AH		 1306 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1307 sdhci_runtime_pm_bus_on(host);
1308
557b0697
HW		 1309 /*
1310 * Some controllers need an extra 10ms delay of 10ms before they
1311 * can apply clock after applying power
1312 */
11a2f1b7 1313 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1314 mdelay(10);
ceb6143b
AH		 1315
1316 return power;
146ad66e
PO		 1317}
1318
d129bceb
PO		 1319/*****************************************************************************\
1320 * *
1321 * MMC callbacks *
1322 * *
1323\*****************************************************************************/
1324
1325static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1326{
1327 struct sdhci_host *host;
505a8680 1328 int present;
d129bceb 1329 unsigned long flags;
473b095a 1330 u32 tuning_opcode;
d129bceb
PO		 1331
1332 host = mmc_priv(mmc);
1333
66fd8ad5
AH		 1334 sdhci_runtime_pm_get(host);
1335
d129bceb
PO		 1336 spin_lock_irqsave(&host->lock, flags);
1337
1338 WARN_ON(host->mrq != NULL);
1339
f9134319 1340#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1341 sdhci_activate_led(host);
2f730fec 1342#endif
e89d456f
AW		 1343
1344 /*
1345 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1346 * requests if Auto-CMD12 is enabled.
1347 */
1348 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1349 if (mrq->stop) {
1350 mrq->data->stop = NULL;
1351 mrq->stop = NULL;
1352 }
1353 }
d129bceb
PO		 1354
1355 host->mrq = mrq;
1356
505a8680
SG		 1357 /*
1358 * Firstly check card presence from cd-gpio. The return could
1359 * be one of the following possibilities:
1360 * negative: cd-gpio is not available
1361 * zero: cd-gpio is used, and card is removed
1362 * one: cd-gpio is used, and card is present
1363 */
1364 present = mmc_gpio_get_cd(host->mmc);
1365 if (present < 0) {
1366 /* If polling, assume that the card is always present. */
1367 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1368 present = 1;
1369 else
1370 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1371 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1372 }
1373
68d1fb7e 1374 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1375 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1376 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1377 } else {
1378 u32 present_state;
1379
1380 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1381 /*
1382 * Check if the re-tuning timer has already expired and there
1383 * is no on-going data transfer. If so, we need to execute
1384 * tuning procedure before sending command.
1385 */
1386 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1387 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1388 if (mmc->card) {
1389 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1390 tuning_opcode =
1391 mmc->card->type == MMC_TYPE_MMC ?
1392 MMC_SEND_TUNING_BLOCK_HS200 :
1393 MMC_SEND_TUNING_BLOCK;
1394 spin_unlock_irqrestore(&host->lock, flags);
1395 sdhci_execute_tuning(mmc, tuning_opcode);
1396 spin_lock_irqsave(&host->lock, flags);
1397
1398 /* Restore original mmc_request structure */
1399 host->mrq = mrq;
1400 }
cf2b5eea
AN		 1401 }
1402
8edf6371 1403 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1404 sdhci_send_command(host, mrq->sbc);
1405 else
1406 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1407 }
d129bceb 1408
5f25a66f 1409 mmiowb();
d129bceb
PO		 1410 spin_unlock_irqrestore(&host->lock, flags);
1411}
1412
66fd8ad5 1413static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1414{
d129bceb 1415 unsigned long flags;
ceb6143b 1416 int vdd_bit = -1;
d129bceb
PO		 1417 u8 ctrl;
1418
d129bceb
PO		 1419 spin_lock_irqsave(&host->lock, flags);
1420
ceb6143b
AH		 1421 if (host->flags & SDHCI_DEVICE_DEAD) {
1422 spin_unlock_irqrestore(&host->lock, flags);
1423 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1424 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1425 return;
1426 }
1e72859e 1427
d129bceb
PO		 1428 /*
1429 * Reset the chip on each power off.
1430 * Should clear out any weird states.
1431 */
1432 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1433 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1434 sdhci_reinit(host);
d129bceb
PO		 1435 }
1436
52983382
KL		 1437 if (host->version >= SDHCI_SPEC_300 &&
1438 (ios->power_mode == MMC_POWER_UP))
1439 sdhci_enable_preset_value(host, false);
1440
d129bceb
PO		 1441 sdhci_set_clock(host, ios->clock);
1442
1443 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1444 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1445 else
ceb6143b
AH		 1446 vdd_bit = sdhci_set_power(host, ios->vdd);
1447
1448 if (host->vmmc && vdd_bit != -1) {
1449 spin_unlock_irqrestore(&host->lock, flags);
1450 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1451 spin_lock_irqsave(&host->lock, flags);
1452 }
d129bceb 1453
643a81ff
PR		 1454 if (host->ops->platform_send_init_74_clocks)
1455 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1456
15ec4461
PR		 1457 /*
1458 * If your platform has 8-bit width support but is not a v3 controller,
1459 * or if it requires special setup code, you should implement that in
7bc088d3 1460 * platform_bus_width().
15ec4461 1461 */
7bc088d3
SH		 1462 if (host->ops->platform_bus_width) {
1463 host->ops->platform_bus_width(host, ios->bus_width);
1464 } else {
15ec4461
PR		 1465 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1466 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1467 ctrl &= ~SDHCI_CTRL_4BITBUS;
1468 if (host->version >= SDHCI_SPEC_300)
1469 ctrl |= SDHCI_CTRL_8BITBUS;
1470 } else {
1471 if (host->version >= SDHCI_SPEC_300)
1472 ctrl &= ~SDHCI_CTRL_8BITBUS;
1473 if (ios->bus_width == MMC_BUS_WIDTH_4)
1474 ctrl |= SDHCI_CTRL_4BITBUS;
1475 else
1476 ctrl &= ~SDHCI_CTRL_4BITBUS;
1477 }
1478 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1479 }
ae6d6c92 1480
15ec4461 1481 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1482
3ab9c8da
PR		 1483 if ((ios->timing == MMC_TIMING_SD_HS ||
1484 ios->timing == MMC_TIMING_MMC_HS)
1485 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1486 ctrl |= SDHCI_CTRL_HISPD;
1487 else
1488 ctrl &= ~SDHCI_CTRL_HISPD;
1489
d6d50a15 1490 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1491 u16 clk, ctrl_2;
49c468fc
AN		 1492
1493 /* In case of UHS-I modes, set High Speed Enable */
069c9f14
G		 1494 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1495 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1496 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1497 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1498 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1499 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1500
1501 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1502 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1503 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1504 /*
1505 * We only need to set Driver Strength if the
1506 * preset value enable is not set.
1507 */
1508 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1509 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1510 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1511 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1512 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1513
1514 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1515 } else {
1516 /*
1517 * According to SDHC Spec v3.00, if the Preset Value
1518 * Enable in the Host Control 2 register is set, we
1519 * need to reset SD Clock Enable before changing High
1520 * Speed Enable to avoid generating clock gliches.
1521 */
758535c4
AN		 1522
1523 /* Reset SD Clock Enable */
1524 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1525 clk &= ~SDHCI_CLOCK_CARD_EN;
1526 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1527
1528 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1529
1530 /* Re-enable SD Clock */
8213af3b 1531 sdhci_update_clock(host);
d6d50a15 1532 }
49c468fc 1533
49c468fc
AN		 1534
1535 /* Reset SD Clock Enable */
1536 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1537 clk &= ~SDHCI_CLOCK_CARD_EN;
1538 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1539
6322cdd0
PR		 1540 if (host->ops->set_uhs_signaling)
1541 host->ops->set_uhs_signaling(host, ios->timing);
1542 else {
1543 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1544 /* Select Bus Speed Mode for host */
1545 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
59911568
GC		 1546 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1547 (ios->timing == MMC_TIMING_UHS_SDR104))
1548 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
069c9f14 1549 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1550 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1551 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1552 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1553 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1554 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
6322cdd0
PR		 1555 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1556 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1557 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1558 }
49c468fc 1559
52983382
KL		 1560 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1561 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1562 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1563 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1564 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1565 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1566 u16 preset;
1567
1568 sdhci_enable_preset_value(host, true);
1569 preset = sdhci_get_preset_value(host);
1570 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1571 >> SDHCI_PRESET_DRV_SHIFT;
1572 }
1573
49c468fc 1574 /* Re-enable SD Clock */
8213af3b 1575 sdhci_update_clock(host);
758535c4
AN		 1576 } else
1577 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1578
b8352260
LD		 1579 /*
1580 * Some (ENE) controllers go apeshit on some ios operation,
1581 * signalling timeout and CRC errors even on CMD0. Resetting
1582 * it on each ios seems to solve the problem.
1583 */
b8c86fc5 1584 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1585 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1586
5f25a66f 1587 mmiowb();
d129bceb
PO		 1588 spin_unlock_irqrestore(&host->lock, flags);
1589}
1590
66fd8ad5
AH		 1591static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1592{
1593 struct sdhci_host *host = mmc_priv(mmc);
1594
1595 sdhci_runtime_pm_get(host);
1596 sdhci_do_set_ios(host, ios);
1597 sdhci_runtime_pm_put(host);
1598}
1599
94144a46
KL		 1600static int sdhci_do_get_cd(struct sdhci_host *host)
1601{
1602 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1603
1604 if (host->flags & SDHCI_DEVICE_DEAD)
1605 return 0;
1606
1607 /* If polling/nonremovable, assume that the card is always present. */
1608 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1609 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1610 return 1;
1611
1612 /* Try slot gpio detect */
1613 if (!IS_ERR_VALUE(gpio_cd))
1614 return !!gpio_cd;
1615
1616 /* Host native card detect */
1617 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1618}
1619
1620static int sdhci_get_cd(struct mmc_host *mmc)
1621{
1622 struct sdhci_host *host = mmc_priv(mmc);
1623 int ret;
1624
1625 sdhci_runtime_pm_get(host);
1626 ret = sdhci_do_get_cd(host);
1627 sdhci_runtime_pm_put(host);
1628 return ret;
1629}
1630
66fd8ad5 1631static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1632{
d129bceb 1633 unsigned long flags;
2dfb579c 1634 int is_readonly;
d129bceb 1635
d129bceb
PO		 1636 spin_lock_irqsave(&host->lock, flags);
1637
1e72859e 1638 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1639 is_readonly = 0;
1640 else if (host->ops->get_ro)
1641 is_readonly = host->ops->get_ro(host);
1e72859e 1642 else
2dfb579c
WS		 1643 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1644 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1645
1646 spin_unlock_irqrestore(&host->lock, flags);
1647
2dfb579c
WS		 1648 /* This quirk needs to be replaced by a callback-function later */
1649 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1650 !is_readonly : is_readonly;
d129bceb
PO		 1651}
1652
82b0e23a
TI		 1653#define SAMPLE_COUNT 5
1654
66fd8ad5 1655static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1656{
82b0e23a
TI		 1657 int i, ro_count;
1658
82b0e23a 1659 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1660 return sdhci_check_ro(host);
82b0e23a
TI		 1661
1662 ro_count = 0;
1663 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1664 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1665 if (++ro_count > SAMPLE_COUNT / 2)
1666 return 1;
1667 }
1668 msleep(30);
1669 }
1670 return 0;
1671}
1672
20758b66
AH		 1673static void sdhci_hw_reset(struct mmc_host *mmc)
1674{
1675 struct sdhci_host *host = mmc_priv(mmc);
1676
1677 if (host->ops && host->ops->hw_reset)
1678 host->ops->hw_reset(host);
1679}
1680
66fd8ad5 1681static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1682{
66fd8ad5
AH		 1683 struct sdhci_host *host = mmc_priv(mmc);
1684 int ret;
f75979b7 1685
66fd8ad5
AH		 1686 sdhci_runtime_pm_get(host);
1687 ret = sdhci_do_get_ro(host);
1688 sdhci_runtime_pm_put(host);
1689 return ret;
1690}
f75979b7 1691
66fd8ad5
AH		 1692static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1693{
1e72859e
PO		 1694 if (host->flags & SDHCI_DEVICE_DEAD)
1695 goto out;
1696
66fd8ad5
AH		 1697 if (enable)
1698 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1699 else
1700 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1701
1702 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1703 if (host->runtime_suspended)
1704 goto out;
1705
f75979b7 1706 if (enable)
7260cf5e
AV		 1707 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1708 else
1709 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1710out:
f75979b7 1711 mmiowb();
66fd8ad5
AH		 1712}
1713
1714static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1715{
1716 struct sdhci_host *host = mmc_priv(mmc);
1717 unsigned long flags;
f75979b7 1718
66fd8ad5
AH		 1719 spin_lock_irqsave(&host->lock, flags);
1720 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1721 spin_unlock_irqrestore(&host->lock, flags);
1722}
1723
20b92a30 1724static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1725 struct mmc_ios *ios)
f2119df6 1726{
20b92a30 1727 u16 ctrl;
6231f3de 1728 int ret;
f2119df6 1729
20b92a30
KL		 1730 /*
1731 * Signal Voltage Switching is only applicable for Host Controllers
1732 * v3.00 and above.
1733 */
1734 if (host->version < SDHCI_SPEC_300)
1735 return 0;
6231f3de 1736
f2119df6 1737 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1738
21f5998f 1739 switch (ios->signal_voltage) {
20b92a30
KL		 1740 case MMC_SIGNAL_VOLTAGE_330:
1741 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1742 ctrl &= ~SDHCI_CTRL_VDD_180;
1743 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1744
20b92a30
KL		 1745 if (host->vqmmc) {
1746 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1747 if (ret) {
1748 pr_warning("%s: Switching to 3.3V signalling voltage "
1749 " failed\n", mmc_hostname(host->mmc));
1750 return -EIO;
1751 }
1752 }
1753 /* Wait for 5ms */
1754 usleep_range(5000, 5500);
f2119df6 1755
20b92a30
KL		 1756 /* 3.3V regulator output should be stable within 5 ms */
1757 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1758 if (!(ctrl & SDHCI_CTRL_VDD_180))
1759 return 0;
6231f3de 1760
20b92a30
KL		 1761 pr_warning("%s: 3.3V regulator output did not became stable\n",
1762 mmc_hostname(host->mmc));
1763
1764 return -EAGAIN;
1765 case MMC_SIGNAL_VOLTAGE_180:
1766 if (host->vqmmc) {
1767 ret = regulator_set_voltage(host->vqmmc,
1768 1700000, 1950000);
1769 if (ret) {
1770 pr_warning("%s: Switching to 1.8V signalling voltage "
1771 " failed\n", mmc_hostname(host->mmc));
1772 return -EIO;
1773 }
1774 }
6231f3de 1775
6231f3de
PR		 1776 /*
1777 * Enable 1.8V Signal Enable in the Host Control2
1778 * register
1779 */
20b92a30
KL		 1780 ctrl |= SDHCI_CTRL_VDD_180;
1781 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1782
20b92a30
KL		 1783 /* Wait for 5ms */
1784 usleep_range(5000, 5500);
f2119df6 1785
20b92a30
KL		 1786 /* 1.8V regulator output should be stable within 5 ms */
1787 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1788 if (ctrl & SDHCI_CTRL_VDD_180)
1789 return 0;
f2119df6 1790
20b92a30
KL		 1791 pr_warning("%s: 1.8V regulator output did not became stable\n",
1792 mmc_hostname(host->mmc));
f2119df6 1793
20b92a30
KL		 1794 return -EAGAIN;
1795 case MMC_SIGNAL_VOLTAGE_120:
1796 if (host->vqmmc) {
1797 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1798 if (ret) {
1799 pr_warning("%s: Switching to 1.2V signalling voltage "
1800 " failed\n", mmc_hostname(host->mmc));
1801 return -EIO;
f2119df6
AN		 1802 }
1803 }
6231f3de 1804 return 0;
20b92a30 1805 default:
f2119df6
AN		 1806 /* No signal voltage switch required */
1807 return 0;
20b92a30 1808 }
f2119df6
AN		 1809}
1810
66fd8ad5 1811static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1812 struct mmc_ios *ios)
66fd8ad5
AH		 1813{
1814 struct sdhci_host *host = mmc_priv(mmc);
1815 int err;
1816
1817 if (host->version < SDHCI_SPEC_300)
1818 return 0;
1819 sdhci_runtime_pm_get(host);
21f5998f 1820 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1821 sdhci_runtime_pm_put(host);
1822 return err;
1823}
1824
20b92a30
KL		 1825static int sdhci_card_busy(struct mmc_host *mmc)
1826{
1827 struct sdhci_host *host = mmc_priv(mmc);
1828 u32 present_state;
1829
1830 sdhci_runtime_pm_get(host);
1831 /* Check whether DAT[3:0] is 0000 */
1832 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1833 sdhci_runtime_pm_put(host);
1834
1835 return !(present_state & SDHCI_DATA_LVL_MASK);
1836}
1837
069c9f14 1838static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1839{
1840 struct sdhci_host *host;
1841 u16 ctrl;
1842 u32 ier;
1843 int tuning_loop_counter = MAX_TUNING_LOOP;
1844 unsigned long timeout;
1845 int err = 0;
069c9f14 1846 bool requires_tuning_nonuhs = false;
b513ea25
AN		 1847
1848 host = mmc_priv(mmc);
1849
66fd8ad5 1850 sdhci_runtime_pm_get(host);
b513ea25
AN		 1851 disable_irq(host->irq);
1852 spin_lock(&host->lock);
1853
1854 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1855
1856 /*
069c9f14
G		 1857 * The Host Controller needs tuning only in case of SDR104 mode
1858 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1859 * Capabilities register.
069c9f14
G		 1860 * If the Host Controller supports the HS200 mode then the
1861 * tuning function has to be executed.
b513ea25 1862 */
069c9f14
G		 1863 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1864 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
156e14b1 1865 host->flags & SDHCI_SDR104_NEEDS_TUNING))
069c9f14
G		 1866 requires_tuning_nonuhs = true;
1867
b513ea25 1868 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1869 requires_tuning_nonuhs)
b513ea25
AN		 1870 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1871 else {
1872 spin_unlock(&host->lock);
1873 enable_irq(host->irq);
66fd8ad5 1874 sdhci_runtime_pm_put(host);
b513ea25
AN		 1875 return 0;
1876 }
1877
45251812
DA		 1878 if (host->ops->platform_execute_tuning) {
1879 spin_unlock(&host->lock);
1880 enable_irq(host->irq);
1881 err = host->ops->platform_execute_tuning(host, opcode);
1882 sdhci_runtime_pm_put(host);
1883 return err;
1884 }
1885
b513ea25
AN		 1886 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1887
1888 /*
1889 * As per the Host Controller spec v3.00, tuning command
1890 * generates Buffer Read Ready interrupt, so enable that.
1891 *
1892 * Note: The spec clearly says that when tuning sequence
1893 * is being performed, the controller does not generate
1894 * interrupts other than Buffer Read Ready interrupt. But
1895 * to make sure we don't hit a controller bug, we _only_
1896 * enable Buffer Read Ready interrupt here.
1897 */
1898 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1899 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1900
1901 /*
1902 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1903 * of loops reaches 40 times or a timeout of 150ms occurs.
1904 */
1905 timeout = 150;
1906 do {
1907 struct mmc_command cmd = {0};
66fd8ad5 1908 struct mmc_request mrq = {NULL};
b513ea25
AN		 1909
1910 if (!tuning_loop_counter && !timeout)
1911 break;
1912
069c9f14 1913 cmd.opcode = opcode;
b513ea25
AN		 1914 cmd.arg = 0;
1915 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1916 cmd.retries = 0;
1917 cmd.data = NULL;
1918 cmd.error = 0;
1919
1920 mrq.cmd = &cmd;
1921 host->mrq = &mrq;
1922
1923 /*
1924 * In response to CMD19, the card sends 64 bytes of tuning
1925 * block to the Host Controller. So we set the block size
1926 * to 64 here.
1927 */
069c9f14
G		 1928 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1929 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1930 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1931 SDHCI_BLOCK_SIZE);
1932 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1933 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1934 SDHCI_BLOCK_SIZE);
1935 } else {
1936 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1937 SDHCI_BLOCK_SIZE);
1938 }
b513ea25
AN		 1939
1940 /*
1941 * The tuning block is sent by the card to the host controller.
1942 * So we set the TRNS_READ bit in the Transfer Mode register.
1943 * This also takes care of setting DMA Enable and Multi Block
1944 * Select in the same register to 0.
1945 */
1946 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1947
1948 sdhci_send_command(host, &cmd);
1949
1950 host->cmd = NULL;
1951 host->mrq = NULL;
1952
1953 spin_unlock(&host->lock);
1954 enable_irq(host->irq);
1955
1956 /* Wait for Buffer Read Ready interrupt */
1957 wait_event_interruptible_timeout(host->buf_ready_int,
1958 (host->tuning_done == 1),
1959 msecs_to_jiffies(50));
1960 disable_irq(host->irq);
1961 spin_lock(&host->lock);
1962
1963 if (!host->tuning_done) {
a3c76eb9 1964 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1965 "Buffer Read Ready interrupt during tuning "
1966 "procedure, falling back to fixed sampling "
1967 "clock\n");
1968 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1969 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1970 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1971 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1972
1973 err = -EIO;
1974 goto out;
1975 }
1976
1977 host->tuning_done = 0;
1978
1979 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1980 tuning_loop_counter--;
1981 timeout--;
1982 mdelay(1);
1983 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1984
1985 /*
1986 * The Host Driver has exhausted the maximum number of loops allowed,
1987 * so use fixed sampling frequency.
1988 */
1989 if (!tuning_loop_counter || !timeout) {
1990 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1991 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
114f2bf6 1992 err = -EIO;
b513ea25
AN		 1993 } else {
1994 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1995 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1996 " failed, falling back to fixed sampling"
1997 " clock\n");
1998 err = -EIO;
1999 }
2000 }
2001
2002out:
cf2b5eea
AN		 2003 /*
2004 * If this is the very first time we are here, we start the retuning
2005 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2006 * flag won't be set, we check this condition before actually starting
2007 * the timer.
2008 */
2009 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2010 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 2011 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 2012 mod_timer(&host->tuning_timer, jiffies +
2013 host->tuning_count * HZ);
2014 /* Tuning mode 1 limits the maximum data length to 4MB */
2015 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2016 } else {
2017 host->flags &= ~SDHCI_NEEDS_RETUNING;
2018 /* Reload the new initial value for timer */
2019 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2020 mod_timer(&host->tuning_timer, jiffies +
2021 host->tuning_count * HZ);
2022 }
2023
2024 /*
2025 * In case tuning fails, host controllers which support re-tuning can
2026 * try tuning again at a later time, when the re-tuning timer expires.
2027 * So for these controllers, we return 0. Since there might be other
2028 * controllers who do not have this capability, we return error for
973905fe
AL		 2029 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2030 * a retuning timer to do the retuning for the card.
cf2b5eea 2031 */
973905fe 2032 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2033 err = 0;
2034
b513ea25
AN		 2035 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2036 spin_unlock(&host->lock);
2037 enable_irq(host->irq);
66fd8ad5 2038 sdhci_runtime_pm_put(host);
b513ea25
AN		 2039
2040 return err;
2041}
2042
52983382
KL		 2043
2044static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2045{
4d55c5a1 2046 u16 ctrl;
4d55c5a1 2047
4d55c5a1
AN		 2048 /* Host Controller v3.00 defines preset value registers */
2049 if (host->version < SDHCI_SPEC_300)
2050 return;
2051
4d55c5a1
AN		 2052 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2053
2054 /*
2055 * We only enable or disable Preset Value if they are not already
2056 * enabled or disabled respectively. Otherwise, we bail out.
2057 */
2058 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2059 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2060 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2061 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 2062 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2063 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2064 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2065 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1 2066 }
66fd8ad5
AH		 2067}
2068
71e69211 2069static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2070{
71e69211 2071 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2072 unsigned long flags;
2073
722e1280
CD		 2074 /* First check if client has provided their own card event */
2075 if (host->ops->card_event)
2076 host->ops->card_event(host);
2077
d129bceb
PO		 2078 spin_lock_irqsave(&host->lock, flags);
2079
66fd8ad5 2080 /* Check host->mrq first in case we are runtime suspended */
9668d765 2081 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2082 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2083 mmc_hostname(host->mmc));
a3c76eb9 2084 pr_err("%s: Resetting controller.\n",
66fd8ad5 2085 mmc_hostname(host->mmc));
d129bceb 2086
66fd8ad5
AH		 2087 sdhci_reset(host, SDHCI_RESET_CMD);
2088 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 2089
66fd8ad5
AH		 2090 host->mrq->cmd->error = -ENOMEDIUM;
2091 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2092 }
2093
2094 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2095}
2096
2097static const struct mmc_host_ops sdhci_ops = {
2098 .request = sdhci_request,
2099 .set_ios = sdhci_set_ios,
94144a46 2100 .get_cd = sdhci_get_cd,
71e69211
GL		 2101 .get_ro = sdhci_get_ro,
2102 .hw_reset = sdhci_hw_reset,
2103 .enable_sdio_irq = sdhci_enable_sdio_irq,
2104 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2105 .execute_tuning = sdhci_execute_tuning,
71e69211 2106 .card_event = sdhci_card_event,
20b92a30 2107 .card_busy = sdhci_card_busy,
71e69211
GL		 2108};
2109
2110/*****************************************************************************\
2111 * *
2112 * Tasklets *
2113 * *
2114\*****************************************************************************/
2115
2116static void sdhci_tasklet_card(unsigned long param)
2117{
2118 struct sdhci_host *host = (struct sdhci_host*)param;
2119
2120 sdhci_card_event(host->mmc);
d129bceb 2121
04cf585d 2122 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 2123}
2124
2125static void sdhci_tasklet_finish(unsigned long param)
2126{
2127 struct sdhci_host *host;
2128 unsigned long flags;
2129 struct mmc_request *mrq;
2130
2131 host = (struct sdhci_host*)param;
2132
66fd8ad5
AH		 2133 spin_lock_irqsave(&host->lock, flags);
2134
0c9c99a7
CB		 2135 /*
2136 * If this tasklet gets rescheduled while running, it will
2137 * be run again afterwards but without any active request.
2138 */
66fd8ad5
AH		 2139 if (!host->mrq) {
2140 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2141 return;
66fd8ad5 2142 }
d129bceb
PO		 2143
2144 del_timer(&host->timer);
2145
2146 mrq = host->mrq;
2147
d129bceb
PO		 2148 /*
2149 * The controller needs a reset of internal state machines
2150 * upon error conditions.
2151 */
1e72859e 2152 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2153 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2154 (mrq->data && (mrq->data->error ||
2155 (mrq->data->stop && mrq->data->stop->error))) ||
2156 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2157
2158 /* Some controllers need this kick or reset won't work here */
8213af3b 2159 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2160 /* This is to force an update */
8213af3b 2161 sdhci_update_clock(host);
645289dc
PO		 2162
2163 /* Spec says we should do both at the same time, but Ricoh
2164 controllers do not like that. */
d129bceb
PO		 2165 sdhci_reset(host, SDHCI_RESET_CMD);
2166 sdhci_reset(host, SDHCI_RESET_DATA);
2167 }
2168
2169 host->mrq = NULL;
2170 host->cmd = NULL;
2171 host->data = NULL;
2172
f9134319 2173#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2174 sdhci_deactivate_led(host);
2f730fec 2175#endif
d129bceb 2176
5f25a66f 2177 mmiowb();
d129bceb
PO		 2178 spin_unlock_irqrestore(&host->lock, flags);
2179
2180 mmc_request_done(host->mmc, mrq);
66fd8ad5 2181 sdhci_runtime_pm_put(host);
d129bceb
PO		 2182}
2183
2184static void sdhci_timeout_timer(unsigned long data)
2185{
2186 struct sdhci_host *host;
2187 unsigned long flags;
2188
2189 host = (struct sdhci_host*)data;
2190
2191 spin_lock_irqsave(&host->lock, flags);
2192
2193 if (host->mrq) {
a3c76eb9 2194 pr_err("%s: Timeout waiting for hardware "
acf1da45 2195 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2196 sdhci_dumpregs(host);
2197
2198 if (host->data) {
17b0429d 2199 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2200 sdhci_finish_data(host);
2201 } else {
2202 if (host->cmd)
17b0429d 2203 host->cmd->error = -ETIMEDOUT;
d129bceb 2204 else
17b0429d 2205 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2206
2207 tasklet_schedule(&host->finish_tasklet);
2208 }
2209 }
2210
5f25a66f 2211 mmiowb();
d129bceb
PO		 2212 spin_unlock_irqrestore(&host->lock, flags);
2213}
2214
cf2b5eea
AN		 2215static void sdhci_tuning_timer(unsigned long data)
2216{
2217 struct sdhci_host *host;
2218 unsigned long flags;
2219
2220 host = (struct sdhci_host *)data;
2221
2222 spin_lock_irqsave(&host->lock, flags);
2223
2224 host->flags |= SDHCI_NEEDS_RETUNING;
2225
2226 spin_unlock_irqrestore(&host->lock, flags);
2227}
2228
d129bceb
PO		 2229/*****************************************************************************\
2230 * *
2231 * Interrupt handling *
2232 * *
2233\*****************************************************************************/
2234
2235static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2236{
2237 BUG_ON(intmask == 0);
2238
2239 if (!host->cmd) {
a3c76eb9 2240 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2241 "though no command operation was in progress.\n",
2242 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2243 sdhci_dumpregs(host);
2244 return;
2245 }
2246
43b58b36 2247 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2248 host->cmd->error = -ETIMEDOUT;
2249 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2250 SDHCI_INT_INDEX))
2251 host->cmd->error = -EILSEQ;
43b58b36 2252
e809517f 2253 if (host->cmd->error) {
d129bceb 2254 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2255 return;
2256 }
2257
2258 /*
2259 * The host can send and interrupt when the busy state has
2260 * ended, allowing us to wait without wasting CPU cycles.
2261 * Unfortunately this is overloaded on the "data complete"
2262 * interrupt, so we need to take some care when handling
2263 * it.
2264 *
2265 * Note: The 1.0 specification is a bit ambiguous about this
2266 * feature so there might be some problems with older
2267 * controllers.
2268 */
2269 if (host->cmd->flags & MMC_RSP_BUSY) {
2270 if (host->cmd->data)
2271 DBG("Cannot wait for busy signal when also "
2272 "doing a data transfer");
f945405c 2273 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2274 return;
f945405c
BD		 2275
2276 /* The controller does not support the end-of-busy IRQ,
2277 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2278 }
2279
2280 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2281 sdhci_finish_command(host);
d129bceb
PO		 2282}
2283
0957c333 2284#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2285static void sdhci_show_adma_error(struct sdhci_host *host)
2286{
2287 const char *name = mmc_hostname(host->mmc);
2288 u8 *desc = host->adma_desc;
2289 __le32 *dma;
2290 __le16 *len;
2291 u8 attr;
2292
2293 sdhci_dumpregs(host);
2294
2295 while (true) {
2296 dma = (__le32 *)(desc + 4);
2297 len = (__le16 *)(desc + 2);
2298 attr = *desc;
2299
2300 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2301 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2302
2303 desc += 8;
2304
2305 if (attr & 2)
2306 break;
2307 }
2308}
2309#else
2310static void sdhci_show_adma_error(struct sdhci_host *host) { }
2311#endif
2312
d129bceb
PO		 2313static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2314{
069c9f14 2315 u32 command;
d129bceb
PO		 2316 BUG_ON(intmask == 0);
2317
b513ea25
AN		 2318 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2319 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2320 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2321 if (command == MMC_SEND_TUNING_BLOCK ||
2322 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2323 host->tuning_done = 1;
2324 wake_up(&host->buf_ready_int);
2325 return;
2326 }
2327 }
2328
d129bceb
PO		 2329 if (!host->data) {
2330 /*
e809517f
PO		 2331 * The "data complete" interrupt is also used to
2332 * indicate that a busy state has ended. See comment
2333 * above in sdhci_cmd_irq().
d129bceb 2334 */
e809517f
PO		 2335 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2336 if (intmask & SDHCI_INT_DATA_END) {
2337 sdhci_finish_command(host);
2338 return;
2339 }
2340 }
d129bceb 2341
a3c76eb9 2342 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2343 "though no data operation was in progress.\n",
2344 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2345 sdhci_dumpregs(host);
2346
2347 return;
2348 }
2349
2350 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2351 host->data->error = -ETIMEDOUT;
22113efd
AL		 2352 else if (intmask & SDHCI_INT_DATA_END_BIT)
2353 host->data->error = -EILSEQ;
2354 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2355 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2356 != MMC_BUS_TEST_R)
17b0429d 2357 host->data->error = -EILSEQ;
6882a8c0 2358 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2359 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2360 sdhci_show_adma_error(host);
2134a922 2361 host->data->error = -EIO;
a4071fbb
HZ		 2362 if (host->ops->adma_workaround)
2363 host->ops->adma_workaround(host, intmask);
6882a8c0 2364 }
d129bceb 2365
17b0429d 2366 if (host->data->error)
d129bceb
PO		 2367 sdhci_finish_data(host);
2368 else {
a406f5a3 2369 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2370 sdhci_transfer_pio(host);
2371
6ba736a1
PO		 2372 /*
2373 * We currently don't do anything fancy with DMA
2374 * boundaries, but as we can't disable the feature
2375 * we need to at least restart the transfer.
f6a03cbf
MV		 2376 *
2377 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2378 * should return a valid address to continue from, but as
2379 * some controllers are faulty, don't trust them.
6ba736a1 2380 */
f6a03cbf
MV		 2381 if (intmask & SDHCI_INT_DMA_END) {
2382 u32 dmastart, dmanow;
2383 dmastart = sg_dma_address(host->data->sg);
2384 dmanow = dmastart + host->data->bytes_xfered;
2385 /*
2386 * Force update to the next DMA block boundary.
2387 */
2388 dmanow = (dmanow &
2389 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2390 SDHCI_DEFAULT_BOUNDARY_SIZE;
2391 host->data->bytes_xfered = dmanow - dmastart;
2392 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2393 " next 0x%08x\n",
2394 mmc_hostname(host->mmc), dmastart,
2395 host->data->bytes_xfered, dmanow);
2396 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2397 }
6ba736a1 2398
e538fbe8
PO		 2399 if (intmask & SDHCI_INT_DATA_END) {
2400 if (host->cmd) {
2401 /*
2402 * Data managed to finish before the
2403 * command completed. Make sure we do
2404 * things in the proper order.
2405 */
2406 host->data_early = 1;
2407 } else {
2408 sdhci_finish_data(host);
2409 }
2410 }
d129bceb
PO		 2411 }
2412}
2413
7d12e780 2414static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2415{
2416 irqreturn_t result;
66fd8ad5 2417 struct sdhci_host *host = dev_id;
6379b237
AS		 2418 u32 intmask, unexpected = 0;
2419 int cardint = 0, max_loops = 16;
d129bceb
PO		 2420
2421 spin_lock(&host->lock);
2422
66fd8ad5
AH		 2423 if (host->runtime_suspended) {
2424 spin_unlock(&host->lock);
a3c76eb9 2425 pr_warning("%s: got irq while runtime suspended\n",
66fd8ad5
AH		 2426 mmc_hostname(host->mmc));
2427 return IRQ_HANDLED;
2428 }
2429
4e4141a5 2430 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2431
62df67a5 2432 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2433 result = IRQ_NONE;
2434 goto out;
2435 }
2436
6379b237 2437again:
b69c9058
PO		 2438 DBG("*** %s got interrupt: 0x%08x\n",
2439 mmc_hostname(host->mmc), intmask);
d129bceb 2440
3192a28f 2441 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2442 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2443 SDHCI_CARD_PRESENT;
2444
2445 /*
2446 * There is a observation on i.mx esdhc. INSERT bit will be
2447 * immediately set again when it gets cleared, if a card is
2448 * inserted. We have to mask the irq to prevent interrupt
2449 * storm which will freeze the system. And the REMOVE gets
2450 * the same situation.
2451 *
2452 * More testing are needed here to ensure it works for other
2453 * platforms though.
2454 */
2455 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2456 SDHCI_INT_CARD_REMOVE);
2457 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2458 SDHCI_INT_CARD_INSERT);
2459
4e4141a5 2460 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2461 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2462 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2463 tasklet_schedule(&host->card_tasklet);
3192a28f 2464 }
d129bceb 2465
3192a28f 2466 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2467 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2468 SDHCI_INT_STATUS);
3192a28f 2469 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2470 }
2471
2472 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2473 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2474 SDHCI_INT_STATUS);
3192a28f 2475 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2476 }
2477
2478 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2479
964f9ce2
PO		 2480 intmask &= ~SDHCI_INT_ERROR;
2481
d129bceb 2482 if (intmask & SDHCI_INT_BUS_POWER) {
a3c76eb9 2483 pr_err("%s: Card is consuming too much power!\n",
d129bceb 2484 mmc_hostname(host->mmc));
4e4141a5 2485 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2486 }
2487
9d26a5d3 2488 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2489
f75979b7
PO		 2490 if (intmask & SDHCI_INT_CARD_INT)
2491 cardint = 1;
2492
2493 intmask &= ~SDHCI_INT_CARD_INT;
2494
3192a28f 2495 if (intmask) {
6379b237 2496 unexpected |= intmask;
4e4141a5 2497 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2498 }
d129bceb
PO		 2499
2500 result = IRQ_HANDLED;
2501
6379b237
AS		 2502 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2503 if (intmask && --max_loops)
2504 goto again;
d129bceb
PO		 2505out:
2506 spin_unlock(&host->lock);
2507
6379b237
AS		 2508 if (unexpected) {
2509 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2510 mmc_hostname(host->mmc), unexpected);
2511 sdhci_dumpregs(host);
2512 }
f75979b7
PO		 2513 /*
2514 * We have to delay this as it calls back into the driver.
2515 */
2516 if (cardint)
2517 mmc_signal_sdio_irq(host->mmc);
2518
d129bceb
PO		 2519 return result;
2520}
2521
2522/*****************************************************************************\
2523 * *
2524 * Suspend/resume *
2525 * *
2526\*****************************************************************************/
2527
2528#ifdef CONFIG_PM
ad080d79
KL		 2529void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2530{
2531 u8 val;
2532 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2533 | SDHCI_WAKE_ON_INT;
2534
2535 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2536 val |= mask ;
2537 /* Avoid fake wake up */
2538 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2539 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2540 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2541}
2542EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2543
2544void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2545{
2546 u8 val;
2547 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2548 | SDHCI_WAKE_ON_INT;
2549
2550 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2551 val &= ~mask;
2552 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2553}
2554EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2555
29495aa0 2556int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2557{
b8c86fc5 2558 int ret;
a715dfc7 2559
a1b13b4e
CB		 2560 if (host->ops->platform_suspend)
2561 host->ops->platform_suspend(host);
2562
7260cf5e
AV		 2563 sdhci_disable_card_detection(host);
2564
cf2b5eea 2565 /* Disable tuning since we are suspending */
973905fe 2566 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2567 del_timer_sync(&host->tuning_timer);
cf2b5eea 2568 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2569 }
2570
1a13f8fa 2571 ret = mmc_suspend_host(host->mmc);
38a60ea2 2572 if (ret) {
973905fe 2573 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
38a60ea2
AL		 2574 host->flags |= SDHCI_NEEDS_RETUNING;
2575 mod_timer(&host->tuning_timer, jiffies +
2576 host->tuning_count * HZ);
2577 }
2578
2579 sdhci_enable_card_detection(host);
2580
b8c86fc5 2581 return ret;
38a60ea2 2582 }
a715dfc7 2583
ad080d79
KL		 2584 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2585 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2586 free_irq(host->irq, host);
2587 } else {
2588 sdhci_enable_irq_wakeups(host);
2589 enable_irq_wake(host->irq);
2590 }
9bea3c85 2591 return ret;
d129bceb
PO		 2592}
2593
b8c86fc5 2594EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2595
b8c86fc5
PO		 2596int sdhci_resume_host(struct sdhci_host *host)
2597{
2598 int ret;
d129bceb 2599
a13abc7b 2600 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2601 if (host->ops->enable_dma)
2602 host->ops->enable_dma(host);
2603 }
d129bceb 2604
ad080d79
KL		 2605 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2606 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2607 mmc_hostname(host->mmc), host);
2608 if (ret)
2609 return ret;
2610 } else {
2611 sdhci_disable_irq_wakeups(host);
2612 disable_irq_wake(host->irq);
2613 }
d129bceb 2614
6308d290
AH		 2615 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2616 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2617 /* Card keeps power but host controller does not */
2618 sdhci_init(host, 0);
2619 host->pwr = 0;
2620 host->clock = 0;
2621 sdhci_do_set_ios(host, &host->mmc->ios);
2622 } else {
2623 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2624 mmiowb();
2625 }
b8c86fc5
PO		 2626
2627 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2628 sdhci_enable_card_detection(host);
2629
a1b13b4e
CB		 2630 if (host->ops->platform_resume)
2631 host->ops->platform_resume(host);
2632
cf2b5eea 2633 /* Set the re-tuning expiration flag */
973905fe 2634 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2635 host->flags |= SDHCI_NEEDS_RETUNING;
2636
2f4cbb3d 2637 return ret;
d129bceb
PO		 2638}
2639
b8c86fc5 2640EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2641#endif /* CONFIG_PM */
2642
66fd8ad5
AH		 2643#ifdef CONFIG_PM_RUNTIME
2644
2645static int sdhci_runtime_pm_get(struct sdhci_host *host)
2646{
2647 return pm_runtime_get_sync(host->mmc->parent);
2648}
2649
2650static int sdhci_runtime_pm_put(struct sdhci_host *host)
2651{
2652 pm_runtime_mark_last_busy(host->mmc->parent);
2653 return pm_runtime_put_autosuspend(host->mmc->parent);
2654}
2655
f0710a55
AH		 2656static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2657{
2658 if (host->runtime_suspended || host->bus_on)
2659 return;
2660 host->bus_on = true;
2661 pm_runtime_get_noresume(host->mmc->parent);
2662}
2663
2664static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2665{
2666 if (host->runtime_suspended || !host->bus_on)
2667 return;
2668 host->bus_on = false;
2669 pm_runtime_put_noidle(host->mmc->parent);
2670}
2671
66fd8ad5
AH		 2672int sdhci_runtime_suspend_host(struct sdhci_host *host)
2673{
2674 unsigned long flags;
2675 int ret = 0;
2676
2677 /* Disable tuning since we are suspending */
973905fe 2678 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2679 del_timer_sync(&host->tuning_timer);
2680 host->flags &= ~SDHCI_NEEDS_RETUNING;
2681 }
2682
2683 spin_lock_irqsave(&host->lock, flags);
2684 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2685 spin_unlock_irqrestore(&host->lock, flags);
2686
2687 synchronize_irq(host->irq);
2688
2689 spin_lock_irqsave(&host->lock, flags);
2690 host->runtime_suspended = true;
2691 spin_unlock_irqrestore(&host->lock, flags);
2692
2693 return ret;
2694}
2695EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2696
2697int sdhci_runtime_resume_host(struct sdhci_host *host)
2698{
2699 unsigned long flags;
2700 int ret = 0, host_flags = host->flags;
2701
2702 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2703 if (host->ops->enable_dma)
2704 host->ops->enable_dma(host);
2705 }
2706
2707 sdhci_init(host, 0);
2708
2709 /* Force clock and power re-program */
2710 host->pwr = 0;
2711 host->clock = 0;
2712 sdhci_do_set_ios(host, &host->mmc->ios);
2713
2714 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2715 if ((host_flags & SDHCI_PV_ENABLED) &&
2716 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2717 spin_lock_irqsave(&host->lock, flags);
2718 sdhci_enable_preset_value(host, true);
2719 spin_unlock_irqrestore(&host->lock, flags);
2720 }
66fd8ad5
AH		 2721
2722 /* Set the re-tuning expiration flag */
973905fe 2723 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2724 host->flags |= SDHCI_NEEDS_RETUNING;
2725
2726 spin_lock_irqsave(&host->lock, flags);
2727
2728 host->runtime_suspended = false;
2729
2730 /* Enable SDIO IRQ */
2731 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2732 sdhci_enable_sdio_irq_nolock(host, true);
2733
2734 /* Enable Card Detection */
2735 sdhci_enable_card_detection(host);
2736
2737 spin_unlock_irqrestore(&host->lock, flags);
2738
2739 return ret;
2740}
2741EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2742
2743#endif
2744
d129bceb
PO		 2745/*****************************************************************************\
2746 * *
b8c86fc5 2747 * Device allocation/registration *
d129bceb
PO		 2748 * *
2749\*****************************************************************************/
2750
b8c86fc5
PO		 2751struct sdhci_host *sdhci_alloc_host(struct device *dev,
2752 size_t priv_size)
d129bceb 2753{
d129bceb
PO		 2754 struct mmc_host *mmc;
2755 struct sdhci_host *host;
2756
b8c86fc5 2757 WARN_ON(dev == NULL);
d129bceb 2758
b8c86fc5 2759 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2760 if (!mmc)
b8c86fc5 2761 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2762
2763 host = mmc_priv(mmc);
2764 host->mmc = mmc;
2765
b8c86fc5
PO		 2766 return host;
2767}
8a4da143 2768
b8c86fc5 2769EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2770
b8c86fc5
PO		 2771int sdhci_add_host(struct sdhci_host *host)
2772{
2773 struct mmc_host *mmc;
bd6a8c30 2774 u32 caps[2] = {0, 0};
f2119df6
AN		 2775 u32 max_current_caps;
2776 unsigned int ocr_avail;
b8c86fc5 2777 int ret;
d129bceb 2778
b8c86fc5
PO		 2779 WARN_ON(host == NULL);
2780 if (host == NULL)
2781 return -EINVAL;
d129bceb 2782
b8c86fc5 2783 mmc = host->mmc;
d129bceb 2784
b8c86fc5
PO		 2785 if (debug_quirks)
2786 host->quirks = debug_quirks;
66fd8ad5
AH		 2787 if (debug_quirks2)
2788 host->quirks2 = debug_quirks2;
d129bceb 2789
d96649ed
PO		 2790 sdhci_reset(host, SDHCI_RESET_ALL);
2791
4e4141a5 2792 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2793 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2794 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2795 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2796 pr_err("%s: Unknown controller version (%d). "
b69c9058 2797 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2798 host->version);
4a965505
PO		 2799 }
2800
f2119df6 2801 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2802 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2803
bd6a8c30
PR		 2804 if (host->version >= SDHCI_SPEC_300)
2805 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2806 host->caps1 :
2807 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2808
b8c86fc5 2809 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2810 host->flags |= SDHCI_USE_SDMA;
f2119df6 2811 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2812 DBG("Controller doesn't have SDMA capability\n");
67435274 2813 else
a13abc7b 2814 host->flags |= SDHCI_USE_SDMA;
d129bceb 2815
b8c86fc5 2816 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2817 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2818 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2819 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2820 }
2821
f2119df6
AN		 2822 if ((host->version >= SDHCI_SPEC_200) &&
2823 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2824 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2825
2826 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2827 (host->flags & SDHCI_USE_ADMA)) {
2828 DBG("Disabling ADMA as it is marked broken\n");
2829 host->flags &= ~SDHCI_USE_ADMA;
2830 }
2831
a13abc7b 2832 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2833 if (host->ops->enable_dma) {
2834 if (host->ops->enable_dma(host)) {
a3c76eb9 2835 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2836 "available. Falling back to PIO.\n",
2837 mmc_hostname(mmc));
a13abc7b
RR		 2838 host->flags &=
2839 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2840 }
d129bceb
PO		 2841 }
2842 }
2843
2134a922
PO		 2844 if (host->flags & SDHCI_USE_ADMA) {
2845 /*
2846 * We need to allocate descriptors for all sg entries
2847 * (128) and potentially one alignment transfer for
2848 * each of those entries.
2849 */
2850 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2851 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2852 if (!host->adma_desc || !host->align_buffer) {
2853 kfree(host->adma_desc);
2854 kfree(host->align_buffer);
a3c76eb9 2855 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2856 "buffers. Falling back to standard DMA.\n",
2857 mmc_hostname(mmc));
2858 host->flags &= ~SDHCI_USE_ADMA;
2859 }
2860 }
2861
7659150c
PO		 2862 /*
2863 * If we use DMA, then it's up to the caller to set the DMA
2864 * mask, but PIO does not need the hw shim so we set a new
2865 * mask here in that case.
2866 */
a13abc7b 2867 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2868 host->dma_mask = DMA_BIT_MASK(64);
2869 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2870 }
d129bceb 2871
c4687d5f 2872 if (host->version >= SDHCI_SPEC_300)
f2119df6 2873 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2874 >> SDHCI_CLOCK_BASE_SHIFT;
2875 else
f2119df6 2876 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2877 >> SDHCI_CLOCK_BASE_SHIFT;
2878
4240ff0a 2879 host->max_clk *= 1000000;
f27f47ef
AV		 2880 if (host->max_clk == 0 || host->quirks &
2881 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2882 if (!host->ops->get_max_clock) {
a3c76eb9 2883 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2884 "frequency.\n", mmc_hostname(mmc));
2885 return -ENODEV;
2886 }
2887 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2888 }
d129bceb 2889
c3ed3877
AN		 2890 /*
2891 * In case of Host Controller v3.00, find out whether clock
2892 * multiplier is supported.
2893 */
2894 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2895 SDHCI_CLOCK_MUL_SHIFT;
2896
2897 /*
2898 * In case the value in Clock Multiplier is 0, then programmable
2899 * clock mode is not supported, otherwise the actual clock
2900 * multiplier is one more than the value of Clock Multiplier
2901 * in the Capabilities Register.
2902 */
2903 if (host->clk_mul)
2904 host->clk_mul += 1;
2905
d129bceb
PO		 2906 /*
2907 * Set host parameters.
2908 */
2909 mmc->ops = &sdhci_ops;
c3ed3877 2910 mmc->f_max = host->max_clk;
ce5f036b 2911 if (host->ops->get_min_clock)
a9e58f25 2912 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2913 else if (host->version >= SDHCI_SPEC_300) {
2914 if (host->clk_mul) {
2915 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2916 mmc->f_max = host->max_clk * host->clk_mul;
2917 } else
2918 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2919 } else
0397526d 2920 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2921
272308ca
AS		 2922 host->timeout_clk =
2923 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2924 if (host->timeout_clk == 0) {
2925 if (host->ops->get_timeout_clock) {
2926 host->timeout_clk = host->ops->get_timeout_clock(host);
2927 } else if (!(host->quirks &
2928 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2929 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2930 "frequency.\n", mmc_hostname(mmc));
2931 return -ENODEV;
2932 }
2933 }
2934 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2935 host->timeout_clk *= 1000;
2936
2937 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2938 host->timeout_clk = mmc->f_max / 1000;
272308ca 2939
65be3fef 2940 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
58d1246d 2941
e89d456f
AW		 2942 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2943
2944 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2945 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2946
8edf6371 2947 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2948 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2949 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2950 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2951 host->flags |= SDHCI_AUTO_CMD23;
2952 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2953 } else {
2954 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2955 }
2956
15ec4461
PR		 2957 /*
2958 * A controller may support 8-bit width, but the board itself
2959 * might not have the pins brought out. Boards that support
2960 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2961 * their platform code before calling sdhci_add_host(), and we
2962 * won't assume 8-bit width for hosts without that CAP.
2963 */
5fe23c7f 2964 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2965 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2966
63ef5d8c
JH		 2967 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2968 mmc->caps &= ~MMC_CAP_CMD23;
2969
f2119df6 2970 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2971 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2972
176d1ed4 2973 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2974 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2975 mmc->caps |= MMC_CAP_NEEDS_POLL;
2976
6231f3de 2977 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
462849aa 2978 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2979 if (IS_ERR_OR_NULL(host->vqmmc)) {
2980 if (PTR_ERR(host->vqmmc) < 0) {
2981 pr_info("%s: no vqmmc regulator found\n",
2982 mmc_hostname(mmc));
2983 host->vqmmc = NULL;
2984 }
8363c374 2985 } else {
a3361aba 2986 ret = regulator_enable(host->vqmmc);
cec2e216
KL		 2987 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2988 1950000))
8363c374
KL		 2989 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2990 SDHCI_SUPPORT_SDR50 |
2991 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 2992 if (ret) {
2993 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2994 mmc_hostname(mmc), ret);
2995 host->vqmmc = NULL;
2996 }
8363c374 2997 }
6231f3de 2998
6a66180a
DD		 2999 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3000 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3001 SDHCI_SUPPORT_DDR50);
3002
4188bba0
AC		 3003 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3004 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3005 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3006 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3007
3008 /* SDR104 supports also implies SDR50 support */
156e14b1 3009 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3010 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3011 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3012 * field can be promoted to support HS200.
3013 */
3014 mmc->caps2 |= MMC_CAP2_HS200;
3015 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3016 mmc->caps |= MMC_CAP_UHS_SDR50;
3017
3018 if (caps[1] & SDHCI_SUPPORT_DDR50)
3019 mmc->caps |= MMC_CAP_UHS_DDR50;
3020
069c9f14 3021 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3022 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3023 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3024
156e14b1 3025 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3026 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3027 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3028
d6d50a15
AN		 3029 /* Driver Type(s) (A, C, D) supported by the host */
3030 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3031 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3032 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3033 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3034 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3035 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3036
cf2b5eea
AN		 3037 /* Initial value for re-tuning timer count */
3038 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3039 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3040
3041 /*
3042 * In case Re-tuning Timer is not disabled, the actual value of
3043 * re-tuning timer will be 2 ^ (n - 1).
3044 */
3045 if (host->tuning_count)
3046 host->tuning_count = 1 << (host->tuning_count - 1);
3047
3048 /* Re-tuning mode supported by the Host Controller */
3049 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3050 SDHCI_RETUNING_MODE_SHIFT;
3051
8f230f45 3052 ocr_avail = 0;
bad37e1a 3053
462849aa 3054 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
657d5982
KL		 3055 if (IS_ERR_OR_NULL(host->vmmc)) {
3056 if (PTR_ERR(host->vmmc) < 0) {
3057 pr_info("%s: no vmmc regulator found\n",
3058 mmc_hostname(mmc));
3059 host->vmmc = NULL;
3060 }
8363c374 3061 }
bad37e1a 3062
68737043 3063#ifdef CONFIG_REGULATOR
a4f8f257
MS		 3064 /*
3065 * Voltage range check makes sense only if regulator reports
3066 * any voltage value.
3067 */
3068 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
cec2e216
KL		 3069 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3070 3600000);
68737043
PR		 3071 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3072 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 3073 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3074 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 3075 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3076 1950000);
68737043
PR		 3077 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3078 caps[0] &= ~SDHCI_CAN_VDD_180;
3079 }
3080#endif /* CONFIG_REGULATOR */
3081
f2119df6
AN		 3082 /*
3083 * According to SD Host Controller spec v3.00, if the Host System
3084 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3085 * the value is meaningful only if Voltage Support in the Capabilities
3086 * register is set. The actual current value is 4 times the register
3087 * value.
3088 */
3089 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 3090 if (!max_current_caps && host->vmmc) {
3091 u32 curr = regulator_get_current_limit(host->vmmc);
3092 if (curr > 0) {
3093
3094 /* convert to SDHCI_MAX_CURRENT format */
3095 curr = curr/1000; /* convert to mA */
3096 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3097
3098 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3099 max_current_caps =
3100 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3101 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3102 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3103 }
3104 }
f2119df6
AN		 3105
3106 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3107 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3108
55c4665e 3109 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3110 SDHCI_MAX_CURRENT_330_MASK) >>
3111 SDHCI_MAX_CURRENT_330_SHIFT) *
3112 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3113 }
3114 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3115 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3116
55c4665e 3117 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3118 SDHCI_MAX_CURRENT_300_MASK) >>
3119 SDHCI_MAX_CURRENT_300_SHIFT) *
3120 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3121 }
3122 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3123 ocr_avail |= MMC_VDD_165_195;
3124
55c4665e 3125 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3126 SDHCI_MAX_CURRENT_180_MASK) >>
3127 SDHCI_MAX_CURRENT_180_SHIFT) *
3128 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3129 }
3130
c0b887b6
HZ		 3131 if (host->ocr_mask)
3132 ocr_avail = host->ocr_mask;
3133
8f230f45
TI		 3134 mmc->ocr_avail = ocr_avail;
3135 mmc->ocr_avail_sdio = ocr_avail;
3136 if (host->ocr_avail_sdio)
3137 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3138 mmc->ocr_avail_sd = ocr_avail;
3139 if (host->ocr_avail_sd)
3140 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3141 else /* normal SD controllers don't support 1.8V */
3142 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3143 mmc->ocr_avail_mmc = ocr_avail;
3144 if (host->ocr_avail_mmc)
3145 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3146
3147 if (mmc->ocr_avail == 0) {
a3c76eb9 3148 pr_err("%s: Hardware doesn't report any "
b69c9058 3149 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3150 return -ENODEV;
146ad66e
PO		 3151 }
3152
d129bceb
PO		 3153 spin_lock_init(&host->lock);
3154
3155 /*
2134a922
PO		 3156 * Maximum number of segments. Depends on if the hardware
3157 * can do scatter/gather or not.
d129bceb 3158 */
2134a922 3159 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3160 mmc->max_segs = 128;
a13abc7b 3161 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3162 mmc->max_segs = 1;
2134a922 3163 else /* PIO */
a36274e0 3164 mmc->max_segs = 128;
d129bceb
PO		 3165
3166 /*
bab76961 3167 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3168 * size (512KiB).
d129bceb 3169 */
55db890a 3170 mmc->max_req_size = 524288;
d129bceb
PO		 3171
3172 /*
3173 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3174 * of bytes. When doing hardware scatter/gather, each entry cannot
3175 * be larger than 64 KiB though.
d129bceb 3176 */
30652aa3
OJ		 3177 if (host->flags & SDHCI_USE_ADMA) {
3178 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3179 mmc->max_seg_size = 65535;
3180 else
3181 mmc->max_seg_size = 65536;
3182 } else {
2134a922 3183 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3184 }
d129bceb 3185
fe4a3c7a
PO		 3186 /*
3187 * Maximum block size. This varies from controller to controller and
3188 * is specified in the capabilities register.
3189 */
0633f654
AV		 3190 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3191 mmc->max_blk_size = 2;
3192 } else {
f2119df6 3193 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3194 SDHCI_MAX_BLOCK_SHIFT;
3195 if (mmc->max_blk_size >= 3) {
a3c76eb9 3196 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3197 "assuming 512 bytes\n", mmc_hostname(mmc));
3198 mmc->max_blk_size = 0;
3199 }
3200 }
3201
3202 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3203
55db890a
PO		 3204 /*
3205 * Maximum block count.
3206 */
1388eefd 3207 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3208
d129bceb
PO		 3209 /*
3210 * Init tasklets.
3211 */
3212 tasklet_init(&host->card_tasklet,
3213 sdhci_tasklet_card, (unsigned long)host);
3214 tasklet_init(&host->finish_tasklet,
3215 sdhci_tasklet_finish, (unsigned long)host);
3216
e4cad1b5 3217 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3218
cf2b5eea 3219 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3220 init_waitqueue_head(&host->buf_ready_int);
3221
cf2b5eea
AN		 3222 /* Initialize re-tuning timer */
3223 init_timer(&host->tuning_timer);
3224 host->tuning_timer.data = (unsigned long)host;
3225 host->tuning_timer.function = sdhci_tuning_timer;
3226 }
3227
2af502ca
SG		 3228 sdhci_init(host, 0);
3229
dace1453 3230 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 3231 mmc_hostname(mmc), host);
0fc81ee3
MB		 3232 if (ret) {
3233 pr_err("%s: Failed to request IRQ %d: %d\n",
3234 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3235 goto untasklet;
0fc81ee3 3236 }
d129bceb 3237
d129bceb
PO		 3238#ifdef CONFIG_MMC_DEBUG
3239 sdhci_dumpregs(host);
3240#endif
3241
f9134319 3242#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3243 snprintf(host->led_name, sizeof(host->led_name),
3244 "%s::", mmc_hostname(mmc));
3245 host->led.name = host->led_name;
2f730fec
PO		 3246 host->led.brightness = LED_OFF;
3247 host->led.default_trigger = mmc_hostname(mmc);
3248 host->led.brightness_set = sdhci_led_control;
3249
b8c86fc5 3250 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3251 if (ret) {
3252 pr_err("%s: Failed to register LED device: %d\n",
3253 mmc_hostname(mmc), ret);
2f730fec 3254 goto reset;
0fc81ee3 3255 }
2f730fec
PO		 3256#endif
3257
5f25a66f
PO		 3258 mmiowb();
3259
d129bceb
PO		 3260 mmc_add_host(mmc);
3261
a3c76eb9 3262 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3263 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3264 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3265 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3266
7260cf5e
AV		 3267 sdhci_enable_card_detection(host);
3268
d129bceb
PO		 3269 return 0;
3270
f9134319 3271#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3272reset:
3273 sdhci_reset(host, SDHCI_RESET_ALL);
b0a8dece 3274 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2f730fec
PO		 3275 free_irq(host->irq, host);
3276#endif
8ef1a143 3277untasklet:
d129bceb
PO		 3278 tasklet_kill(&host->card_tasklet);
3279 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3280
3281 return ret;
3282}
3283
b8c86fc5 3284EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3285
1e72859e 3286void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3287{
1e72859e
PO		 3288 unsigned long flags;
3289
3290 if (dead) {
3291 spin_lock_irqsave(&host->lock, flags);
3292
3293 host->flags |= SDHCI_DEVICE_DEAD;
3294
3295 if (host->mrq) {
a3c76eb9 3296 pr_err("%s: Controller removed during "
1e72859e
PO		 3297 " transfer!\n", mmc_hostname(host->mmc));
3298
3299 host->mrq->cmd->error = -ENOMEDIUM;
3300 tasklet_schedule(&host->finish_tasklet);
3301 }
3302
3303 spin_unlock_irqrestore(&host->lock, flags);
3304 }
3305
7260cf5e
AV		 3306 sdhci_disable_card_detection(host);
3307
b8c86fc5 3308 mmc_remove_host(host->mmc);
d129bceb 3309
f9134319 3310#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3311 led_classdev_unregister(&host->led);
3312#endif
3313
1e72859e
PO		 3314 if (!dead)
3315 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 3316
b0a8dece 3317 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
d129bceb
PO		 3318 free_irq(host->irq, host);
3319
3320 del_timer_sync(&host->timer);
3321
3322 tasklet_kill(&host->card_tasklet);
3323 tasklet_kill(&host->finish_tasklet);
2134a922 3324
77dcb3f4
PR		 3325 if (host->vmmc) {
3326 regulator_disable(host->vmmc);
9bea3c85 3327 regulator_put(host->vmmc);
77dcb3f4 3328 }
9bea3c85 3329
6231f3de
PR		 3330 if (host->vqmmc) {
3331 regulator_disable(host->vqmmc);
3332 regulator_put(host->vqmmc);
3333 }
3334
2134a922
PO		 3335 kfree(host->adma_desc);
3336 kfree(host->align_buffer);
3337
3338 host->adma_desc = NULL;
3339 host->align_buffer = NULL;
d129bceb
PO		 3340}
3341
b8c86fc5 3342EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3343
b8c86fc5 3344void sdhci_free_host(struct sdhci_host *host)
d129bceb 3345{
b8c86fc5 3346 mmc_free_host(host->mmc);
d129bceb
PO		 3347}
3348
b8c86fc5 3349EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3350
3351/*****************************************************************************\
3352 * *
3353 * Driver init/exit *
3354 * *
3355\*****************************************************************************/
3356
3357static int __init sdhci_drv_init(void)
3358{
a3c76eb9 3359 pr_info(DRIVER_NAME
52fbf9c9 3360 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3361 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3362
b8c86fc5 3363 return 0;
d129bceb
PO		 3364}
3365
3366static void __exit sdhci_drv_exit(void)
3367{
d129bceb
PO		 3368}
3369
3370module_init(sdhci_drv_init);
3371module_exit(sdhci_drv_exit);
3372
df673b22 3373module_param(debug_quirks, uint, 0444);
66fd8ad5 3374module_param(debug_quirks2, uint, 0444);
67435274 3375
32710e8f 3376MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3377MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3378MODULE_LICENSE("GPL");
67435274 3379
df673b22 3380MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3381MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux 6.x block layer and io_uring tree(s)