projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: at91_mci: wakeup on card insertion (or removal)
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb
PO		 1/*
2 * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
3 *
14d836e7 4 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
d129bceb
PO		 10 */
11
d129bceb
PO		 12#include <linux/delay.h>
13#include <linux/highmem.h>
14#include <linux/pci.h>
15#include <linux/dma-mapping.h>
16
17#include <linux/mmc/host.h>
d129bceb
PO		 18
19#include <asm/scatterlist.h>
20
21#include "sdhci.h"
22
23#define DRIVER_NAME "sdhci"
d129bceb 24
d129bceb 25#define DBG(f, x...) \
c6563178 26 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 27
67435274
PO		 28static unsigned int debug_nodma = 0;
29static unsigned int debug_forcedma = 0;
df673b22 30static unsigned int debug_quirks = 0;
67435274 31
645289dc 32#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
98608076 33#define SDHCI_QUIRK_FORCE_DMA (1<<1)
8a4da143
PO		 34/* Controller doesn't like some resets when there is no card inserted. */
35#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
9e9dc5f2 36#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
645289dc 37
d129bceb 38static const struct pci_device_id pci_ids[] __devinitdata = {
645289dc
PO		 39 {
40 .vendor = PCI_VENDOR_ID_RICOH,
41 .device = PCI_DEVICE_ID_RICOH_R5C822,
42 .subvendor = PCI_VENDOR_ID_IBM,
43 .subdevice = PCI_ANY_ID,
98608076
PO		 44 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
45 SDHCI_QUIRK_FORCE_DMA,
46 },
47
48 {
49 .vendor = PCI_VENDOR_ID_RICOH,
50 .device = PCI_DEVICE_ID_RICOH_R5C822,
51 .subvendor = PCI_ANY_ID,
52 .subdevice = PCI_ANY_ID,
8a4da143
PO		 53 .driver_data = SDHCI_QUIRK_FORCE_DMA |
54 SDHCI_QUIRK_NO_CARD_NO_RESET,
98608076
PO		 55 },
56
57 {
58 .vendor = PCI_VENDOR_ID_TI,
59 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
60 .subvendor = PCI_ANY_ID,
61 .subdevice = PCI_ANY_ID,
62 .driver_data = SDHCI_QUIRK_FORCE_DMA,
645289dc
PO		 63 },
64
9e9dc5f2
DS		 65 {
66 .vendor = PCI_VENDOR_ID_ENE,
67 .device = PCI_DEVICE_ID_ENE_CB712_SD,
68 .subvendor = PCI_ANY_ID,
69 .subdevice = PCI_ANY_ID,
70 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE,
71 },
72
7de064eb
MK		 73 {
74 .vendor = PCI_VENDOR_ID_ENE,
75 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
76 .subvendor = PCI_ANY_ID,
77 .subdevice = PCI_ANY_ID,
78 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE,
79 },
80
645289dc
PO		 81 { /* Generic SD host controller */
82 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
83 },
84
d129bceb
PO		 85 { /* end: all zeroes */ },
86};
87
88MODULE_DEVICE_TABLE(pci, pci_ids);
89
90static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
91static void sdhci_finish_data(struct sdhci_host *);
92
93static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
94static void sdhci_finish_command(struct sdhci_host *);
95
96static void sdhci_dumpregs(struct sdhci_host *host)
97{
98 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
99
100 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
101 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
102 readw(host->ioaddr + SDHCI_HOST_VERSION));
103 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
104 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
105 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
106 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
107 readl(host->ioaddr + SDHCI_ARGUMENT),
108 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
109 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
110 readl(host->ioaddr + SDHCI_PRESENT_STATE),
111 readb(host->ioaddr + SDHCI_HOST_CONTROL));
112 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
113 readb(host->ioaddr + SDHCI_POWER_CONTROL),
114 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
115 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
116 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
117 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
118 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
119 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
120 readl(host->ioaddr + SDHCI_INT_STATUS));
121 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
122 readl(host->ioaddr + SDHCI_INT_ENABLE),
123 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
124 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
125 readw(host->ioaddr + SDHCI_ACMD12_ERR),
126 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
127 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
128 readl(host->ioaddr + SDHCI_CAPABILITIES),
129 readl(host->ioaddr + SDHCI_MAX_CURRENT));
130
131 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
132}
133
134/*****************************************************************************\
135 * *
136 * Low level functions *
137 * *
138\*****************************************************************************/
139
140static void sdhci_reset(struct sdhci_host *host, u8 mask)
141{
e16514d8
PO		 142 unsigned long timeout;
143
8a4da143
PO		 144 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
145 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
146 SDHCI_CARD_PRESENT))
147 return;
148 }
149
d129bceb
PO		 150 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
151
e16514d8 152 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 153 host->clock = 0;
154
e16514d8
PO		 155 /* Wait max 100 ms */
156 timeout = 100;
157
158 /* hw clears the bit when it's done */
159 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
160 if (timeout == 0) {
acf1da45 161 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 162 mmc_hostname(host->mmc), (int)mask);
163 sdhci_dumpregs(host);
164 return;
165 }
166 timeout--;
167 mdelay(1);
d129bceb
PO		 168 }
169}
170
171static void sdhci_init(struct sdhci_host *host)
172{
173 u32 intmask;
174
175 sdhci_reset(host, SDHCI_RESET_ALL);
176
3192a28f
PO		 177 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
178 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
179 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
180 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 181 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
3192a28f 182 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
d129bceb
PO		 183
184 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
185 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 186}
187
188static void sdhci_activate_led(struct sdhci_host *host)
189{
190 u8 ctrl;
191
192 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
193 ctrl |= SDHCI_CTRL_LED;
194 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
195}
196
197static void sdhci_deactivate_led(struct sdhci_host *host)
198{
199 u8 ctrl;
200
201 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
202 ctrl &= ~SDHCI_CTRL_LED;
203 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
204}
205
206/*****************************************************************************\
207 * *
208 * Core functions *
209 * *
210\*****************************************************************************/
211
2a22b14e 212static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
d129bceb 213{
2a22b14e 214 return page_address(host->cur_sg->page) + host->cur_sg->offset;
d129bceb
PO		 215}
216
217static inline int sdhci_next_sg(struct sdhci_host* host)
218{
219 /*
220 * Skip to next SG entry.
221 */
222 host->cur_sg++;
223 host->num_sg--;
224
225 /*
226 * Any entries left?
227 */
228 if (host->num_sg > 0) {
229 host->offset = 0;
230 host->remain = host->cur_sg->length;
231 }
232
233 return host->num_sg;
234}
235
a406f5a3 236static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 237{
a406f5a3
PO		 238 int blksize, chunk_remain;
239 u32 data;
d129bceb 240 char *buffer;
a406f5a3 241 int size;
d129bceb 242
a406f5a3 243 DBG("PIO reading\n");
d129bceb 244
a406f5a3
PO		 245 blksize = host->data->blksz;
246 chunk_remain = 0;
247 data = 0;
d129bceb 248
2a22b14e 249 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 250
a406f5a3
PO		 251 while (blksize) {
252 if (chunk_remain == 0) {
253 data = readl(host->ioaddr + SDHCI_BUFFER);
254 chunk_remain = min(blksize, 4);
255 }
d129bceb 256
14d836e7 257 size = min(host->remain, chunk_remain);
d129bceb 258
a406f5a3
PO		 259 chunk_remain -= size;
260 blksize -= size;
261 host->offset += size;
262 host->remain -= size;
14d836e7 263
a406f5a3
PO		 264 while (size) {
265 *buffer = data & 0xFF;
266 buffer++;
267 data >>= 8;
268 size--;
269 }
d129bceb 270
a406f5a3 271 if (host->remain == 0) {
a406f5a3
PO		 272 if (sdhci_next_sg(host) == 0) {
273 BUG_ON(blksize != 0);
274 return;
275 }
2a22b14e 276 buffer = sdhci_sg_to_buffer(host);
d129bceb 277 }
a406f5a3 278 }
a406f5a3 279}
d129bceb 280
a406f5a3
PO		 281static void sdhci_write_block_pio(struct sdhci_host *host)
282{
283 int blksize, chunk_remain;
284 u32 data;
285 char *buffer;
286 int bytes, size;
d129bceb 287
a406f5a3
PO		 288 DBG("PIO writing\n");
289
290 blksize = host->data->blksz;
291 chunk_remain = 4;
292 data = 0;
d129bceb 293
a406f5a3 294 bytes = 0;
2a22b14e 295 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 296
a406f5a3 297 while (blksize) {
14d836e7 298 size = min(host->remain, chunk_remain);
a406f5a3
PO		 299
300 chunk_remain -= size;
301 blksize -= size;
d129bceb
PO		 302 host->offset += size;
303 host->remain -= size;
14d836e7 304
a406f5a3
PO		 305 while (size) {
306 data >>= 8;
307 data |= (u32)*buffer << 24;
308 buffer++;
309 size--;
310 }
311
312 if (chunk_remain == 0) {
313 writel(data, host->ioaddr + SDHCI_BUFFER);
314 chunk_remain = min(blksize, 4);
315 }
d129bceb
PO		 316
317 if (host->remain == 0) {
d129bceb 318 if (sdhci_next_sg(host) == 0) {
a406f5a3 319 BUG_ON(blksize != 0);
d129bceb
PO		 320 return;
321 }
2a22b14e 322 buffer = sdhci_sg_to_buffer(host);
d129bceb
PO		 323 }
324 }
a406f5a3
PO		 325}
326
327static void sdhci_transfer_pio(struct sdhci_host *host)
328{
329 u32 mask;
330
331 BUG_ON(!host->data);
332
14d836e7 333 if (host->num_sg == 0)
a406f5a3
PO		 334 return;
335
336 if (host->data->flags & MMC_DATA_READ)
337 mask = SDHCI_DATA_AVAILABLE;
338 else
339 mask = SDHCI_SPACE_AVAILABLE;
340
341 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
342 if (host->data->flags & MMC_DATA_READ)
343 sdhci_read_block_pio(host);
344 else
345 sdhci_write_block_pio(host);
d129bceb 346
14d836e7 347 if (host->num_sg == 0)
a406f5a3 348 break;
a406f5a3 349 }
d129bceb 350
a406f5a3 351 DBG("PIO transfer complete.\n");
d129bceb
PO		 352}
353
354static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
355{
1c8cde92
PO		 356 u8 count;
357 unsigned target_timeout, current_timeout;
d129bceb
PO		 358
359 WARN_ON(host->data);
360
c7fa9963 361 if (data == NULL)
d129bceb 362 return;
d129bceb
PO		 363
364 DBG("blksz %04x blks %04x flags %08x\n",
a3fd4a1b 365 data->blksz, data->blocks, data->flags);
d129bceb
PO		 366 DBG("tsac %d ms nsac %d clk\n",
367 data->timeout_ns / 1000000, data->timeout_clks);
368
bab76961
PO		 369 /* Sanity checks */
370 BUG_ON(data->blksz * data->blocks > 524288);
fe4a3c7a 371 BUG_ON(data->blksz > host->mmc->max_blk_size);
1d676e02 372 BUG_ON(data->blocks > 65535);
d129bceb 373
1c8cde92
PO		 374 /* timeout in us */
375 target_timeout = data->timeout_ns / 1000 +
376 data->timeout_clks / host->clock;
d129bceb 377
1c8cde92
PO		 378 /*
379 * Figure out needed cycles.
380 * We do this in steps in order to fit inside a 32 bit int.
381 * The first step is the minimum timeout, which will have a
382 * minimum resolution of 6 bits:
383 * (1) 2^13*1000 > 2^22,
384 * (2) host->timeout_clk < 2^16
385 * =>
386 * (1) / (2) > 2^6
387 */
388 count = 0;
389 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
390 while (current_timeout < target_timeout) {
391 count++;
392 current_timeout <<= 1;
393 if (count >= 0xF)
394 break;
395 }
396
397 if (count >= 0xF) {
398 printk(KERN_WARNING "%s: Too large timeout requested!\n",
399 mmc_hostname(host->mmc));
400 count = 0xE;
401 }
402
403 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
d129bceb
PO		 404
405 if (host->flags & SDHCI_USE_DMA) {
406 int count;
407
408 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
409 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
410 BUG_ON(count != 1);
411
412 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
413 } else {
d129bceb
PO		 414 host->cur_sg = data->sg;
415 host->num_sg = data->sg_len;
416
417 host->offset = 0;
418 host->remain = host->cur_sg->length;
419 }
c7fa9963 420
bab76961
PO		 421 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
422 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
423 host->ioaddr + SDHCI_BLOCK_SIZE);
c7fa9963
PO		 424 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
425}
426
427static void sdhci_set_transfer_mode(struct sdhci_host *host,
428 struct mmc_data *data)
429{
430 u16 mode;
431
432 WARN_ON(host->data);
433
434 if (data == NULL)
435 return;
436
437 mode = SDHCI_TRNS_BLK_CNT_EN;
438 if (data->blocks > 1)
439 mode |= SDHCI_TRNS_MULTI;
440 if (data->flags & MMC_DATA_READ)
441 mode |= SDHCI_TRNS_READ;
442 if (host->flags & SDHCI_USE_DMA)
443 mode |= SDHCI_TRNS_DMA;
444
445 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
d129bceb
PO		 446}
447
448static void sdhci_finish_data(struct sdhci_host *host)
449{
450 struct mmc_data *data;
d129bceb
PO		 451 u16 blocks;
452
453 BUG_ON(!host->data);
454
455 data = host->data;
456 host->data = NULL;
457
458 if (host->flags & SDHCI_USE_DMA) {
459 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
460 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
d129bceb
PO		 461 }
462
463 /*
464 * Controller doesn't count down when in single block mode.
465 */
466 if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
467 blocks = 0;
468 else
469 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
a3fd4a1b 470 data->bytes_xfered = data->blksz * (data->blocks - blocks);
d129bceb
PO		 471
472 if ((data->error == MMC_ERR_NONE) && blocks) {
473 printk(KERN_ERR "%s: Controller signalled completion even "
acf1da45
PO		 474 "though there were blocks left.\n",
475 mmc_hostname(host->mmc));
d129bceb 476 data->error = MMC_ERR_FAILED;
d129bceb
PO		 477 }
478
479 DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
480
481 if (data->stop) {
482 /*
483 * The controller needs a reset of internal state machines
484 * upon error conditions.
485 */
486 if (data->error != MMC_ERR_NONE) {
487 sdhci_reset(host, SDHCI_RESET_CMD);
488 sdhci_reset(host, SDHCI_RESET_DATA);
489 }
490
491 sdhci_send_command(host, data->stop);
492 } else
493 tasklet_schedule(&host->finish_tasklet);
494}
495
496static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
497{
498 int flags;
fd2208d7 499 u32 mask;
7cb2c76f 500 unsigned long timeout;
d129bceb
PO		 501
502 WARN_ON(host->cmd);
503
504 DBG("Sending cmd (%x)\n", cmd->opcode);
505
506 /* Wait max 10 ms */
7cb2c76f 507 timeout = 10;
fd2208d7
PO		 508
509 mask = SDHCI_CMD_INHIBIT;
510 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
511 mask |= SDHCI_DATA_INHIBIT;
512
513 /* We shouldn't wait for data inihibit for stop commands, even
514 though they might use busy signaling */
515 if (host->mrq->data && (cmd == host->mrq->data->stop))
516 mask &= ~SDHCI_DATA_INHIBIT;
517
518 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 519 if (timeout == 0) {
d129bceb 520 printk(KERN_ERR "%s: Controller never released "
acf1da45 521 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb
PO		 522 sdhci_dumpregs(host);
523 cmd->error = MMC_ERR_FAILED;
524 tasklet_schedule(&host->finish_tasklet);
525 return;
526 }
7cb2c76f
PO		 527 timeout--;
528 mdelay(1);
529 }
d129bceb
PO		 530
531 mod_timer(&host->timer, jiffies + 10 * HZ);
532
533 host->cmd = cmd;
534
535 sdhci_prepare_data(host, cmd->data);
536
537 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
538
c7fa9963
PO		 539 sdhci_set_transfer_mode(host, cmd->data);
540
d129bceb 541 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 542 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb
PO		 543 mmc_hostname(host->mmc));
544 cmd->error = MMC_ERR_INVALID;
545 tasklet_schedule(&host->finish_tasklet);
546 return;
547 }
548
549 if (!(cmd->flags & MMC_RSP_PRESENT))
550 flags = SDHCI_CMD_RESP_NONE;
551 else if (cmd->flags & MMC_RSP_136)
552 flags = SDHCI_CMD_RESP_LONG;
553 else if (cmd->flags & MMC_RSP_BUSY)
554 flags = SDHCI_CMD_RESP_SHORT_BUSY;
555 else
556 flags = SDHCI_CMD_RESP_SHORT;
557
558 if (cmd->flags & MMC_RSP_CRC)
559 flags |= SDHCI_CMD_CRC;
560 if (cmd->flags & MMC_RSP_OPCODE)
561 flags |= SDHCI_CMD_INDEX;
562 if (cmd->data)
563 flags |= SDHCI_CMD_DATA;
564
fb61e289 565 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
d129bceb
PO		 566 host->ioaddr + SDHCI_COMMAND);
567}
568
569static void sdhci_finish_command(struct sdhci_host *host)
570{
571 int i;
572
573 BUG_ON(host->cmd == NULL);
574
575 if (host->cmd->flags & MMC_RSP_PRESENT) {
576 if (host->cmd->flags & MMC_RSP_136) {
577 /* CRC is stripped so we need to do some shifting. */
578 for (i = 0;i < 4;i++) {
579 host->cmd->resp[i] = readl(host->ioaddr +
580 SDHCI_RESPONSE + (3-i)*4) << 8;
581 if (i != 3)
582 host->cmd->resp[i] |=
583 readb(host->ioaddr +
584 SDHCI_RESPONSE + (3-i)*4-1);
585 }
586 } else {
587 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
588 }
589 }
590
591 host->cmd->error = MMC_ERR_NONE;
592
593 DBG("Ending cmd (%x)\n", host->cmd->opcode);
594
3192a28f 595 if (host->cmd->data)
d129bceb 596 host->data = host->cmd->data;
3192a28f 597 else
d129bceb
PO		 598 tasklet_schedule(&host->finish_tasklet);
599
600 host->cmd = NULL;
601}
602
603static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
604{
605 int div;
606 u16 clk;
7cb2c76f 607 unsigned long timeout;
d129bceb
PO		 608
609 if (clock == host->clock)
610 return;
611
612 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
613
614 if (clock == 0)
615 goto out;
616
617 for (div = 1;div < 256;div *= 2) {
618 if ((host->max_clk / div) <= clock)
619 break;
620 }
621 div >>= 1;
622
623 clk = div << SDHCI_DIVIDER_SHIFT;
624 clk |= SDHCI_CLOCK_INT_EN;
625 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
626
627 /* Wait max 10 ms */
7cb2c76f
PO		 628 timeout = 10;
629 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
630 & SDHCI_CLOCK_INT_STABLE)) {
631 if (timeout == 0) {
acf1da45
PO		 632 printk(KERN_ERR "%s: Internal clock never "
633 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 634 sdhci_dumpregs(host);
635 return;
636 }
7cb2c76f
PO		 637 timeout--;
638 mdelay(1);
639 }
d129bceb
PO		 640
641 clk |= SDHCI_CLOCK_CARD_EN;
642 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
643
644out:
645 host->clock = clock;
646}
647
146ad66e
PO		 648static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
649{
650 u8 pwr;
651
652 if (host->power == power)
653 return;
654
9e9dc5f2
DS		 655 if (power == (unsigned short)-1) {
656 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e 657 goto out;
9e9dc5f2
DS		 658 }
659
660 /*
661 * Spec says that we should clear the power reg before setting
662 * a new value. Some controllers don't seem to like this though.
663 */
664 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
665 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e
PO		 666
667 pwr = SDHCI_POWER_ON;
668
4be34c99 669 switch (1 << power) {
55556da0 670 case MMC_VDD_165_195:
146ad66e
PO		 671 pwr |= SDHCI_POWER_180;
672 break;
4be34c99
PL		 673 case MMC_VDD_29_30:
674 case MMC_VDD_30_31:
146ad66e
PO		 675 pwr |= SDHCI_POWER_300;
676 break;
4be34c99
PL		 677 case MMC_VDD_32_33:
678 case MMC_VDD_33_34:
146ad66e
PO		 679 pwr |= SDHCI_POWER_330;
680 break;
681 default:
682 BUG();
683 }
684
685 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
686
687out:
688 host->power = power;
689}
690
d129bceb
PO		 691/*****************************************************************************\
692 * *
693 * MMC callbacks *
694 * *
695\*****************************************************************************/
696
697static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
698{
699 struct sdhci_host *host;
700 unsigned long flags;
701
702 host = mmc_priv(mmc);
703
704 spin_lock_irqsave(&host->lock, flags);
705
706 WARN_ON(host->mrq != NULL);
707
708 sdhci_activate_led(host);
709
710 host->mrq = mrq;
711
712 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
713 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
714 tasklet_schedule(&host->finish_tasklet);
715 } else
716 sdhci_send_command(host, mrq->cmd);
717
5f25a66f 718 mmiowb();
d129bceb
PO		 719 spin_unlock_irqrestore(&host->lock, flags);
720}
721
722static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
723{
724 struct sdhci_host *host;
725 unsigned long flags;
726 u8 ctrl;
727
728 host = mmc_priv(mmc);
729
730 spin_lock_irqsave(&host->lock, flags);
731
d129bceb
PO		 732 /*
733 * Reset the chip on each power off.
734 * Should clear out any weird states.
735 */
736 if (ios->power_mode == MMC_POWER_OFF) {
737 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb 738 sdhci_init(host);
d129bceb
PO		 739 }
740
741 sdhci_set_clock(host, ios->clock);
742
743 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 744 sdhci_set_power(host, -1);
d129bceb 745 else
146ad66e 746 sdhci_set_power(host, ios->vdd);
d129bceb
PO		 747
748 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
cd9277c0 749
d129bceb
PO		 750 if (ios->bus_width == MMC_BUS_WIDTH_4)
751 ctrl |= SDHCI_CTRL_4BITBUS;
752 else
753 ctrl &= ~SDHCI_CTRL_4BITBUS;
cd9277c0
PO		 754
755 if (ios->timing == MMC_TIMING_SD_HS)
756 ctrl |= SDHCI_CTRL_HISPD;
757 else
758 ctrl &= ~SDHCI_CTRL_HISPD;
759
d129bceb
PO		 760 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
761
5f25a66f 762 mmiowb();
d129bceb
PO		 763 spin_unlock_irqrestore(&host->lock, flags);
764}
765
766static int sdhci_get_ro(struct mmc_host *mmc)
767{
768 struct sdhci_host *host;
769 unsigned long flags;
770 int present;
771
772 host = mmc_priv(mmc);
773
774 spin_lock_irqsave(&host->lock, flags);
775
776 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
777
778 spin_unlock_irqrestore(&host->lock, flags);
779
780 return !(present & SDHCI_WRITE_PROTECT);
781}
782
ab7aefd0 783static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 784 .request = sdhci_request,
785 .set_ios = sdhci_set_ios,
786 .get_ro = sdhci_get_ro,
787};
788
789/*****************************************************************************\
790 * *
791 * Tasklets *
792 * *
793\*****************************************************************************/
794
795static void sdhci_tasklet_card(unsigned long param)
796{
797 struct sdhci_host *host;
798 unsigned long flags;
799
800 host = (struct sdhci_host*)param;
801
802 spin_lock_irqsave(&host->lock, flags);
803
804 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
805 if (host->mrq) {
806 printk(KERN_ERR "%s: Card removed during transfer!\n",
807 mmc_hostname(host->mmc));
808 printk(KERN_ERR "%s: Resetting controller.\n",
809 mmc_hostname(host->mmc));
810
811 sdhci_reset(host, SDHCI_RESET_CMD);
812 sdhci_reset(host, SDHCI_RESET_DATA);
813
814 host->mrq->cmd->error = MMC_ERR_FAILED;
815 tasklet_schedule(&host->finish_tasklet);
816 }
817 }
818
819 spin_unlock_irqrestore(&host->lock, flags);
820
821 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
822}
823
824static void sdhci_tasklet_finish(unsigned long param)
825{
826 struct sdhci_host *host;
827 unsigned long flags;
828 struct mmc_request *mrq;
829
830 host = (struct sdhci_host*)param;
831
832 spin_lock_irqsave(&host->lock, flags);
833
834 del_timer(&host->timer);
835
836 mrq = host->mrq;
837
838 DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
839
840 /*
841 * The controller needs a reset of internal state machines
842 * upon error conditions.
843 */
844 if ((mrq->cmd->error != MMC_ERR_NONE) ||
845 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
846 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
645289dc
PO		 847
848 /* Some controllers need this kick or reset won't work here */
849 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
850 unsigned int clock;
851
852 /* This is to force an update */
853 clock = host->clock;
854 host->clock = 0;
855 sdhci_set_clock(host, clock);
856 }
857
858 /* Spec says we should do both at the same time, but Ricoh
859 controllers do not like that. */
d129bceb
PO		 860 sdhci_reset(host, SDHCI_RESET_CMD);
861 sdhci_reset(host, SDHCI_RESET_DATA);
862 }
863
864 host->mrq = NULL;
865 host->cmd = NULL;
866 host->data = NULL;
867
868 sdhci_deactivate_led(host);
869
5f25a66f 870 mmiowb();
d129bceb
PO		 871 spin_unlock_irqrestore(&host->lock, flags);
872
873 mmc_request_done(host->mmc, mrq);
874}
875
876static void sdhci_timeout_timer(unsigned long data)
877{
878 struct sdhci_host *host;
879 unsigned long flags;
880
881 host = (struct sdhci_host*)data;
882
883 spin_lock_irqsave(&host->lock, flags);
884
885 if (host->mrq) {
acf1da45
PO		 886 printk(KERN_ERR "%s: Timeout waiting for hardware "
887 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 888 sdhci_dumpregs(host);
889
890 if (host->data) {
891 host->data->error = MMC_ERR_TIMEOUT;
892 sdhci_finish_data(host);
893 } else {
894 if (host->cmd)
895 host->cmd->error = MMC_ERR_TIMEOUT;
896 else
897 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
898
899 tasklet_schedule(&host->finish_tasklet);
900 }
901 }
902
5f25a66f 903 mmiowb();
d129bceb
PO		 904 spin_unlock_irqrestore(&host->lock, flags);
905}
906
907/*****************************************************************************\
908 * *
909 * Interrupt handling *
910 * *
911\*****************************************************************************/
912
913static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
914{
915 BUG_ON(intmask == 0);
916
917 if (!host->cmd) {
918 printk(KERN_ERR "%s: Got command interrupt even though no "
919 "command operation was in progress.\n",
920 mmc_hostname(host->mmc));
d129bceb
PO		 921 sdhci_dumpregs(host);
922 return;
923 }
924
925 if (intmask & SDHCI_INT_RESPONSE)
926 sdhci_finish_command(host);
927 else {
928 if (intmask & SDHCI_INT_TIMEOUT)
929 host->cmd->error = MMC_ERR_TIMEOUT;
930 else if (intmask & SDHCI_INT_CRC)
931 host->cmd->error = MMC_ERR_BADCRC;
932 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
933 host->cmd->error = MMC_ERR_FAILED;
934 else
935 host->cmd->error = MMC_ERR_INVALID;
936
937 tasklet_schedule(&host->finish_tasklet);
938 }
939}
940
941static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
942{
943 BUG_ON(intmask == 0);
944
945 if (!host->data) {
946 /*
947 * A data end interrupt is sent together with the response
948 * for the stop command.
949 */
950 if (intmask & SDHCI_INT_DATA_END)
951 return;
952
953 printk(KERN_ERR "%s: Got data interrupt even though no "
954 "data operation was in progress.\n",
955 mmc_hostname(host->mmc));
d129bceb
PO		 956 sdhci_dumpregs(host);
957
958 return;
959 }
960
961 if (intmask & SDHCI_INT_DATA_TIMEOUT)
962 host->data->error = MMC_ERR_TIMEOUT;
963 else if (intmask & SDHCI_INT_DATA_CRC)
964 host->data->error = MMC_ERR_BADCRC;
965 else if (intmask & SDHCI_INT_DATA_END_BIT)
966 host->data->error = MMC_ERR_FAILED;
967
968 if (host->data->error != MMC_ERR_NONE)
969 sdhci_finish_data(host);
970 else {
a406f5a3 971 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 972 sdhci_transfer_pio(host);
973
6ba736a1
PO		 974 /*
975 * We currently don't do anything fancy with DMA
976 * boundaries, but as we can't disable the feature
977 * we need to at least restart the transfer.
978 */
979 if (intmask & SDHCI_INT_DMA_END)
980 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
981 host->ioaddr + SDHCI_DMA_ADDRESS);
982
d129bceb
PO		 983 if (intmask & SDHCI_INT_DATA_END)
984 sdhci_finish_data(host);
985 }
986}
987
7d12e780 988static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 989{
990 irqreturn_t result;
991 struct sdhci_host* host = dev_id;
992 u32 intmask;
993
994 spin_lock(&host->lock);
995
996 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
997
62df67a5 998 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 999 result = IRQ_NONE;
1000 goto out;
1001 }
1002
1003 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1004
3192a28f
PO		 1005 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1006 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1007 host->ioaddr + SDHCI_INT_STATUS);
d129bceb 1008 tasklet_schedule(&host->card_tasklet);
3192a28f 1009 }
d129bceb 1010
3192a28f 1011 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1012
3192a28f 1013 if (intmask & SDHCI_INT_CMD_MASK) {
d129bceb
PO		 1014 writel(intmask & SDHCI_INT_CMD_MASK,
1015 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1016 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1017 }
1018
1019 if (intmask & SDHCI_INT_DATA_MASK) {
d129bceb
PO		 1020 writel(intmask & SDHCI_INT_DATA_MASK,
1021 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1022 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1023 }
1024
1025 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1026
d129bceb 1027 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1028 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1029 mmc_hostname(host->mmc));
3192a28f 1030 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
d129bceb
PO		 1031 }
1032
9d26a5d3 1033 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f
PO		 1034
1035 if (intmask) {
acf1da45 1036 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1037 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1038 sdhci_dumpregs(host);
1039
d129bceb 1040 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1041 }
d129bceb
PO		 1042
1043 result = IRQ_HANDLED;
1044
5f25a66f 1045 mmiowb();
d129bceb
PO		 1046out:
1047 spin_unlock(&host->lock);
1048
1049 return result;
1050}
1051
1052/*****************************************************************************\
1053 * *
1054 * Suspend/resume *
1055 * *
1056\*****************************************************************************/
1057
1058#ifdef CONFIG_PM
1059
1060static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1061{
1062 struct sdhci_chip *chip;
1063 int i, ret;
1064
1065 chip = pci_get_drvdata(pdev);
1066 if (!chip)
1067 return 0;
1068
1069 DBG("Suspending...\n");
1070
1071 for (i = 0;i < chip->num_slots;i++) {
1072 if (!chip->hosts[i])
1073 continue;
1074 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1075 if (ret) {
1076 for (i--;i >= 0;i--)
1077 mmc_resume_host(chip->hosts[i]->mmc);
1078 return ret;
1079 }
1080 }
1081
1082 pci_save_state(pdev);
1083 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
a715dfc7
PO		 1084
1085 for (i = 0;i < chip->num_slots;i++) {
1086 if (!chip->hosts[i])
1087 continue;
1088 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1089 }
1090
d129bceb
PO		 1091 pci_disable_device(pdev);
1092 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1093
1094 return 0;
1095}
1096
1097static int sdhci_resume (struct pci_dev *pdev)
1098{
1099 struct sdhci_chip *chip;
1100 int i, ret;
1101
1102 chip = pci_get_drvdata(pdev);
1103 if (!chip)
1104 return 0;
1105
1106 DBG("Resuming...\n");
1107
1108 pci_set_power_state(pdev, PCI_D0);
1109 pci_restore_state(pdev);
df1c4b7b
PO		 1110 ret = pci_enable_device(pdev);
1111 if (ret)
1112 return ret;
d129bceb
PO		 1113
1114 for (i = 0;i < chip->num_slots;i++) {
1115 if (!chip->hosts[i])
1116 continue;
1117 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1118 pci_set_master(pdev);
a715dfc7
PO		 1119 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1120 IRQF_SHARED, chip->hosts[i]->slot_descr,
1121 chip->hosts[i]);
1122 if (ret)
1123 return ret;
d129bceb 1124 sdhci_init(chip->hosts[i]);
5f25a66f 1125 mmiowb();
d129bceb
PO		 1126 ret = mmc_resume_host(chip->hosts[i]->mmc);
1127 if (ret)
1128 return ret;
1129 }
1130
1131 return 0;
1132}
1133
1134#else /* CONFIG_PM */
1135
1136#define sdhci_suspend NULL
1137#define sdhci_resume NULL
1138
1139#endif /* CONFIG_PM */
1140
1141/*****************************************************************************\
1142 * *
1143 * Device probing/removal *
1144 * *
1145\*****************************************************************************/
1146
1147static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1148{
1149 int ret;
4a965505 1150 unsigned int version;
d129bceb
PO		 1151 struct sdhci_chip *chip;
1152 struct mmc_host *mmc;
1153 struct sdhci_host *host;
1154
1155 u8 first_bar;
1156 unsigned int caps;
1157
1158 chip = pci_get_drvdata(pdev);
1159 BUG_ON(!chip);
1160
1161 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1162 if (ret)
1163 return ret;
1164
1165 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1166
1167 if (first_bar > 5) {
1168 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1169 return -ENODEV;
1170 }
1171
1172 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1173 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1174 return -ENODEV;
1175 }
1176
1177 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
a98087cf
PO		 1178 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1179 "You may experience problems.\n");
d129bceb
PO		 1180 }
1181
67435274
PO		 1182 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1183 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1184 return -ENODEV;
1185 }
1186
1187 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1188 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1189 return -ENODEV;
1190 }
1191
d129bceb
PO		 1192 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1193 if (!mmc)
1194 return -ENOMEM;
1195
1196 host = mmc_priv(mmc);
1197 host->mmc = mmc;
1198
8a4da143
PO		 1199 host->chip = chip;
1200 chip->hosts[slot] = host;
1201
d129bceb
PO		 1202 host->bar = first_bar + slot;
1203
1204 host->addr = pci_resource_start(pdev, host->bar);
1205 host->irq = pdev->irq;
1206
1207 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1208
1209 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1210
1211 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1212 if (ret)
1213 goto free;
1214
1215 host->ioaddr = ioremap_nocache(host->addr,
1216 pci_resource_len(pdev, host->bar));
1217 if (!host->ioaddr) {
1218 ret = -ENOMEM;
1219 goto release;
1220 }
1221
d96649ed
PO		 1222 sdhci_reset(host, SDHCI_RESET_ALL);
1223
4a965505
PO		 1224 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1225 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1226 if (version != 0) {
1227 printk(KERN_ERR "%s: Unknown controller version (%d). "
8b1b2185 1228 "You may experience problems.\n", host->slot_descr,
4a965505 1229 version);
4a965505
PO		 1230 }
1231
d129bceb
PO		 1232 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1233
67435274
PO		 1234 if (debug_nodma)
1235 DBG("DMA forced off\n");
1236 else if (debug_forcedma) {
1237 DBG("DMA forced on\n");
1238 host->flags |= SDHCI_USE_DMA;
98608076
PO		 1239 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1240 host->flags |= SDHCI_USE_DMA;
1241 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
67435274
PO		 1242 DBG("Controller doesn't have DMA interface\n");
1243 else if (!(caps & SDHCI_CAN_DO_DMA))
1244 DBG("Controller doesn't have DMA capability\n");
1245 else
d129bceb
PO		 1246 host->flags |= SDHCI_USE_DMA;
1247
1248 if (host->flags & SDHCI_USE_DMA) {
1249 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1250 printk(KERN_WARNING "%s: No suitable DMA available. "
1251 "Falling back to PIO.\n", host->slot_descr);
1252 host->flags &= ~SDHCI_USE_DMA;
1253 }
1254 }
1255
1256 if (host->flags & SDHCI_USE_DMA)
1257 pci_set_master(pdev);
1258 else /* XXX: Hack to get MMC layer to avoid highmem */
1259 pdev->dma_mask = 0;
1260
8ef1a143
PO		 1261 host->max_clk =
1262 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1263 if (host->max_clk == 0) {
1264 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1265 "frequency.\n", host->slot_descr);
1266 ret = -ENODEV;
1267 goto unmap;
1268 }
d129bceb
PO		 1269 host->max_clk *= 1000000;
1270
1c8cde92
PO		 1271 host->timeout_clk =
1272 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1273 if (host->timeout_clk == 0) {
1274 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1275 "frequency.\n", host->slot_descr);
1276 ret = -ENODEV;
1277 goto unmap;
1278 }
1279 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1280 host->timeout_clk *= 1000;
d129bceb
PO		 1281
1282 /*
1283 * Set host parameters.
1284 */
1285 mmc->ops = &sdhci_ops;
1286 mmc->f_min = host->max_clk / 256;
1287 mmc->f_max = host->max_clk;
42431acb 1288 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
d129bceb 1289
cd9277c0
PO		 1290 if (caps & SDHCI_CAN_DO_HISPD)
1291 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1292
146ad66e
PO		 1293 mmc->ocr_avail = 0;
1294 if (caps & SDHCI_CAN_VDD_330)
1295 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1296 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1297 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1298 if (caps & SDHCI_CAN_VDD_180)
55556da0 1299 mmc->ocr_avail |= MMC_VDD_165_195;
146ad66e
PO		 1300
1301 if (mmc->ocr_avail == 0) {
1302 printk(KERN_ERR "%s: Hardware doesn't report any "
1303 "support voltages.\n", host->slot_descr);
1304 ret = -ENODEV;
1305 goto unmap;
1306 }
1307
d129bceb
PO		 1308 spin_lock_init(&host->lock);
1309
1310 /*
1311 * Maximum number of segments. Hardware cannot do scatter lists.
1312 */
1313 if (host->flags & SDHCI_USE_DMA)
1314 mmc->max_hw_segs = 1;
1315 else
1316 mmc->max_hw_segs = 16;
1317 mmc->max_phys_segs = 16;
1318
1319 /*
bab76961 1320 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1321 * size (512KiB).
d129bceb 1322 */
55db890a 1323 mmc->max_req_size = 524288;
d129bceb
PO		 1324
1325 /*
1326 * Maximum segment size. Could be one segment with the maximum number
55db890a 1327 * of bytes.
d129bceb 1328 */
55db890a 1329 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1330
fe4a3c7a
PO		 1331 /*
1332 * Maximum block size. This varies from controller to controller and
1333 * is specified in the capabilities register.
1334 */
1335 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1336 if (mmc->max_blk_size >= 3) {
1337 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1338 host->slot_descr);
1339 ret = -ENODEV;
1340 goto unmap;
1341 }
1342 mmc->max_blk_size = 512 << mmc->max_blk_size;
1343
55db890a
PO		 1344 /*
1345 * Maximum block count.
1346 */
1347 mmc->max_blk_count = 65535;
1348
d129bceb
PO		 1349 /*
1350 * Init tasklets.
1351 */
1352 tasklet_init(&host->card_tasklet,
1353 sdhci_tasklet_card, (unsigned long)host);
1354 tasklet_init(&host->finish_tasklet,
1355 sdhci_tasklet_finish, (unsigned long)host);
1356
e4cad1b5 1357 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1358
dace1453 1359 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
d129bceb
PO		 1360 host->slot_descr, host);
1361 if (ret)
8ef1a143 1362 goto untasklet;
d129bceb
PO		 1363
1364 sdhci_init(host);
1365
1366#ifdef CONFIG_MMC_DEBUG
1367 sdhci_dumpregs(host);
1368#endif
1369
5f25a66f
PO		 1370 mmiowb();
1371
d129bceb
PO		 1372 mmc_add_host(mmc);
1373
1374 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1375 host->addr, host->irq,
1376 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1377
1378 return 0;
1379
8ef1a143 1380untasklet:
d129bceb
PO		 1381 tasklet_kill(&host->card_tasklet);
1382 tasklet_kill(&host->finish_tasklet);
8ef1a143 1383unmap:
d129bceb
PO		 1384 iounmap(host->ioaddr);
1385release:
1386 pci_release_region(pdev, host->bar);
1387free:
1388 mmc_free_host(mmc);
1389
1390 return ret;
1391}
1392
1393static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1394{
1395 struct sdhci_chip *chip;
1396 struct mmc_host *mmc;
1397 struct sdhci_host *host;
1398
1399 chip = pci_get_drvdata(pdev);
1400 host = chip->hosts[slot];
1401 mmc = host->mmc;
1402
1403 chip->hosts[slot] = NULL;
1404
1405 mmc_remove_host(mmc);
1406
1407 sdhci_reset(host, SDHCI_RESET_ALL);
1408
1409 free_irq(host->irq, host);
1410
1411 del_timer_sync(&host->timer);
1412
1413 tasklet_kill(&host->card_tasklet);
1414 tasklet_kill(&host->finish_tasklet);
1415
1416 iounmap(host->ioaddr);
1417
1418 pci_release_region(pdev, host->bar);
1419
1420 mmc_free_host(mmc);
1421}
1422
1423static int __devinit sdhci_probe(struct pci_dev *pdev,
1424 const struct pci_device_id *ent)
1425{
1426 int ret, i;
51f82bc0 1427 u8 slots, rev;
d129bceb
PO		 1428 struct sdhci_chip *chip;
1429
1430 BUG_ON(pdev == NULL);
1431 BUG_ON(ent == NULL);
1432
51f82bc0
PO		 1433 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1434
1435 printk(KERN_INFO DRIVER_NAME
1436 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1437 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1438 (int)rev);
d129bceb
PO		 1439
1440 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1441 if (ret)
1442 return ret;
1443
1444 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1445 DBG("found %d slot(s)\n", slots);
1446 if (slots == 0)
1447 return -ENODEV;
1448
1449 ret = pci_enable_device(pdev);
1450 if (ret)
1451 return ret;
1452
1453 chip = kzalloc(sizeof(struct sdhci_chip) +
1454 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1455 if (!chip) {
1456 ret = -ENOMEM;
1457 goto err;
1458 }
1459
1460 chip->pdev = pdev;
df673b22
PO		 1461 chip->quirks = ent->driver_data;
1462
1463 if (debug_quirks)
1464 chip->quirks = debug_quirks;
d129bceb
PO		 1465
1466 chip->num_slots = slots;
1467 pci_set_drvdata(pdev, chip);
1468
1469 for (i = 0;i < slots;i++) {
1470 ret = sdhci_probe_slot(pdev, i);
1471 if (ret) {
1472 for (i--;i >= 0;i--)
1473 sdhci_remove_slot(pdev, i);
1474 goto free;
1475 }
1476 }
1477
1478 return 0;
1479
1480free:
1481 pci_set_drvdata(pdev, NULL);
1482 kfree(chip);
1483
1484err:
1485 pci_disable_device(pdev);
1486 return ret;
1487}
1488
1489static void __devexit sdhci_remove(struct pci_dev *pdev)
1490{
1491 int i;
1492 struct sdhci_chip *chip;
1493
1494 chip = pci_get_drvdata(pdev);
1495
1496 if (chip) {
1497 for (i = 0;i < chip->num_slots;i++)
1498 sdhci_remove_slot(pdev, i);
1499
1500 pci_set_drvdata(pdev, NULL);
1501
1502 kfree(chip);
1503 }
1504
1505 pci_disable_device(pdev);
1506}
1507
1508static struct pci_driver sdhci_driver = {
1509 .name = DRIVER_NAME,
1510 .id_table = pci_ids,
1511 .probe = sdhci_probe,
1512 .remove = __devexit_p(sdhci_remove),
1513 .suspend = sdhci_suspend,
1514 .resume = sdhci_resume,
1515};
1516
1517/*****************************************************************************\
1518 * *
1519 * Driver init/exit *
1520 * *
1521\*****************************************************************************/
1522
1523static int __init sdhci_drv_init(void)
1524{
1525 printk(KERN_INFO DRIVER_NAME
52fbf9c9 1526 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 1527 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1528
1529 return pci_register_driver(&sdhci_driver);
1530}
1531
1532static void __exit sdhci_drv_exit(void)
1533{
1534 DBG("Exiting\n");
1535
1536 pci_unregister_driver(&sdhci_driver);
1537}
1538
1539module_init(sdhci_drv_init);
1540module_exit(sdhci_drv_exit);
1541
67435274
PO		 1542module_param(debug_nodma, uint, 0444);
1543module_param(debug_forcedma, uint, 0444);
df673b22 1544module_param(debug_quirks, uint, 0444);
67435274 1545
d129bceb
PO		 1546MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1547MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
d129bceb 1548MODULE_LICENSE("GPL");
67435274
PO		 1549
1550MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1551MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
df673b22 1552MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux 6.x block layer and io_uring tree(s)