Commit | Line | Data |
---|---|---|
d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
b8c86fc5 | 18 | #include <linux/io.h> |
88b47679 | 19 | #include <linux/module.h> |
d129bceb | 20 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
11763609 | 22 | #include <linux/scatterlist.h> |
9bea3c85 | 23 | #include <linux/regulator/consumer.h> |
66fd8ad5 | 24 | #include <linux/pm_runtime.h> |
d129bceb | 25 | |
2f730fec PO |
26 | #include <linux/leds.h> |
27 | ||
22113efd | 28 | #include <linux/mmc/mmc.h> |
d129bceb | 29 | #include <linux/mmc/host.h> |
473b095a | 30 | #include <linux/mmc/card.h> |
bec9d4e5 | 31 | #include <linux/mmc/slot-gpio.h> |
d129bceb | 32 | |
d129bceb PO |
33 | #include "sdhci.h" |
34 | ||
35 | #define DRIVER_NAME "sdhci" | |
d129bceb | 36 | |
d129bceb | 37 | #define DBG(f, x...) \ |
c6563178 | 38 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 39 | |
f9134319 PO |
40 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
41 | defined(CONFIG_MMC_SDHCI_MODULE)) | |
42 | #define SDHCI_USE_LEDS_CLASS | |
43 | #endif | |
44 | ||
b513ea25 AN |
45 | #define MAX_TUNING_LOOP 40 |
46 | ||
df673b22 | 47 | static unsigned int debug_quirks = 0; |
66fd8ad5 | 48 | static unsigned int debug_quirks2; |
67435274 | 49 | |
d129bceb PO |
50 | static void sdhci_finish_data(struct sdhci_host *); |
51 | ||
d129bceb | 52 | static void sdhci_finish_command(struct sdhci_host *); |
069c9f14 | 53 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); |
cf2b5eea | 54 | static void sdhci_tuning_timer(unsigned long data); |
52983382 | 55 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); |
d129bceb | 56 | |
66fd8ad5 AH |
57 | #ifdef CONFIG_PM_RUNTIME |
58 | static int sdhci_runtime_pm_get(struct sdhci_host *host); | |
59 | static int sdhci_runtime_pm_put(struct sdhci_host *host); | |
f0710a55 AH |
60 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host); |
61 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host); | |
66fd8ad5 AH |
62 | #else |
63 | static inline int sdhci_runtime_pm_get(struct sdhci_host *host) | |
64 | { | |
65 | return 0; | |
66 | } | |
67 | static inline int sdhci_runtime_pm_put(struct sdhci_host *host) | |
68 | { | |
69 | return 0; | |
70 | } | |
f0710a55 AH |
71 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
72 | { | |
73 | } | |
74 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) | |
75 | { | |
76 | } | |
66fd8ad5 AH |
77 | #endif |
78 | ||
d129bceb PO |
79 | static void sdhci_dumpregs(struct sdhci_host *host) |
80 | { | |
a3c76eb9 | 81 | pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", |
412ab659 | 82 | mmc_hostname(host->mmc)); |
d129bceb | 83 | |
a3c76eb9 | 84 | pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", |
4e4141a5 AV |
85 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
86 | sdhci_readw(host, SDHCI_HOST_VERSION)); | |
a3c76eb9 | 87 | pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
4e4141a5 AV |
88 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
89 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); | |
a3c76eb9 | 90 | pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
4e4141a5 AV |
91 | sdhci_readl(host, SDHCI_ARGUMENT), |
92 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); | |
a3c76eb9 | 93 | pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
4e4141a5 AV |
94 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
95 | sdhci_readb(host, SDHCI_HOST_CONTROL)); | |
a3c76eb9 | 96 | pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
4e4141a5 AV |
97 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
98 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); | |
a3c76eb9 | 99 | pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
4e4141a5 AV |
100 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
101 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); | |
a3c76eb9 | 102 | pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
4e4141a5 AV |
103 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
104 | sdhci_readl(host, SDHCI_INT_STATUS)); | |
a3c76eb9 | 105 | pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
4e4141a5 AV |
106 | sdhci_readl(host, SDHCI_INT_ENABLE), |
107 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); | |
a3c76eb9 | 108 | pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
4e4141a5 AV |
109 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
110 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); | |
a3c76eb9 | 111 | pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", |
4e4141a5 | 112 | sdhci_readl(host, SDHCI_CAPABILITIES), |
e8120ad1 | 113 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
a3c76eb9 | 114 | pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", |
e8120ad1 | 115 | sdhci_readw(host, SDHCI_COMMAND), |
4e4141a5 | 116 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
a3c76eb9 | 117 | pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", |
f2119df6 | 118 | sdhci_readw(host, SDHCI_HOST_CONTROL2)); |
d129bceb | 119 | |
be3f4ae0 | 120 | if (host->flags & SDHCI_USE_ADMA) |
a3c76eb9 | 121 | pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", |
be3f4ae0 BD |
122 | readl(host->ioaddr + SDHCI_ADMA_ERROR), |
123 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
124 | ||
a3c76eb9 | 125 | pr_debug(DRIVER_NAME ": ===========================================\n"); |
d129bceb PO |
126 | } |
127 | ||
128 | /*****************************************************************************\ | |
129 | * * | |
130 | * Low level functions * | |
131 | * * | |
132 | \*****************************************************************************/ | |
133 | ||
7260cf5e AV |
134 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) |
135 | { | |
5b4f1f6c | 136 | u32 present; |
7260cf5e | 137 | |
c79396c1 | 138 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || |
87b87a3f | 139 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) |
66fd8ad5 AH |
140 | return; |
141 | ||
5b4f1f6c RK |
142 | if (enable) { |
143 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
144 | SDHCI_CARD_PRESENT; | |
d25928d1 | 145 | |
5b4f1f6c RK |
146 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
147 | SDHCI_INT_CARD_INSERT; | |
148 | } else { | |
149 | host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); | |
150 | } | |
b537f94c RK |
151 | |
152 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
153 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
7260cf5e AV |
154 | } |
155 | ||
156 | static void sdhci_enable_card_detection(struct sdhci_host *host) | |
157 | { | |
158 | sdhci_set_card_detection(host, true); | |
159 | } | |
160 | ||
161 | static void sdhci_disable_card_detection(struct sdhci_host *host) | |
162 | { | |
163 | sdhci_set_card_detection(host, false); | |
164 | } | |
165 | ||
d129bceb PO |
166 | static void sdhci_reset(struct sdhci_host *host, u8 mask) |
167 | { | |
e16514d8 | 168 | unsigned long timeout; |
b8c86fc5 | 169 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
4e4141a5 | 170 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & |
8a4da143 PO |
171 | SDHCI_CARD_PRESENT)) |
172 | return; | |
173 | } | |
174 | ||
393c1a34 PR |
175 | if (host->ops->platform_reset_enter) |
176 | host->ops->platform_reset_enter(host, mask); | |
177 | ||
4e4141a5 | 178 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
d129bceb | 179 | |
f0710a55 | 180 | if (mask & SDHCI_RESET_ALL) { |
d129bceb | 181 | host->clock = 0; |
f0710a55 AH |
182 | /* Reset-all turns off SD Bus Power */ |
183 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) | |
184 | sdhci_runtime_pm_bus_off(host); | |
185 | } | |
d129bceb | 186 | |
e16514d8 PO |
187 | /* Wait max 100 ms */ |
188 | timeout = 100; | |
189 | ||
190 | /* hw clears the bit when it's done */ | |
4e4141a5 | 191 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
e16514d8 | 192 | if (timeout == 0) { |
a3c76eb9 | 193 | pr_err("%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
194 | mmc_hostname(host->mmc), (int)mask); |
195 | sdhci_dumpregs(host); | |
196 | return; | |
197 | } | |
198 | timeout--; | |
199 | mdelay(1); | |
d129bceb | 200 | } |
063a9dbb | 201 | |
393c1a34 PR |
202 | if (host->ops->platform_reset_exit) |
203 | host->ops->platform_reset_exit(host, mask); | |
204 | ||
b537f94c RK |
205 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) { |
206 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
207 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
208 | } | |
3abc1e80 SX |
209 | |
210 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { | |
211 | if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL)) | |
212 | host->ops->enable_dma(host); | |
213 | } | |
d129bceb PO |
214 | } |
215 | ||
2f4cbb3d NP |
216 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
217 | ||
218 | static void sdhci_init(struct sdhci_host *host, int soft) | |
d129bceb | 219 | { |
2f4cbb3d NP |
220 | if (soft) |
221 | sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); | |
222 | else | |
223 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb | 224 | |
b537f94c RK |
225 | host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
226 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | | |
227 | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | | |
228 | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | | |
229 | SDHCI_INT_RESPONSE; | |
230 | ||
231 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
232 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
2f4cbb3d NP |
233 | |
234 | if (soft) { | |
235 | /* force clock reconfiguration */ | |
236 | host->clock = 0; | |
237 | sdhci_set_ios(host->mmc, &host->mmc->ios); | |
238 | } | |
7260cf5e | 239 | } |
d129bceb | 240 | |
7260cf5e AV |
241 | static void sdhci_reinit(struct sdhci_host *host) |
242 | { | |
2f4cbb3d | 243 | sdhci_init(host, 0); |
b67c6b41 AL |
244 | /* |
245 | * Retuning stuffs are affected by different cards inserted and only | |
246 | * applicable to UHS-I cards. So reset these fields to their initial | |
247 | * value when card is removed. | |
248 | */ | |
973905fe AL |
249 | if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
250 | host->flags &= ~SDHCI_USING_RETUNING_TIMER; | |
251 | ||
b67c6b41 AL |
252 | del_timer_sync(&host->tuning_timer); |
253 | host->flags &= ~SDHCI_NEEDS_RETUNING; | |
254 | host->mmc->max_blk_count = | |
255 | (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; | |
256 | } | |
7260cf5e | 257 | sdhci_enable_card_detection(host); |
d129bceb PO |
258 | } |
259 | ||
260 | static void sdhci_activate_led(struct sdhci_host *host) | |
261 | { | |
262 | u8 ctrl; | |
263 | ||
4e4141a5 | 264 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 265 | ctrl |= SDHCI_CTRL_LED; |
4e4141a5 | 266 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
267 | } |
268 | ||
269 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
270 | { | |
271 | u8 ctrl; | |
272 | ||
4e4141a5 | 273 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 274 | ctrl &= ~SDHCI_CTRL_LED; |
4e4141a5 | 275 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
276 | } |
277 | ||
f9134319 | 278 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
279 | static void sdhci_led_control(struct led_classdev *led, |
280 | enum led_brightness brightness) | |
281 | { | |
282 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
283 | unsigned long flags; | |
284 | ||
285 | spin_lock_irqsave(&host->lock, flags); | |
286 | ||
66fd8ad5 AH |
287 | if (host->runtime_suspended) |
288 | goto out; | |
289 | ||
2f730fec PO |
290 | if (brightness == LED_OFF) |
291 | sdhci_deactivate_led(host); | |
292 | else | |
293 | sdhci_activate_led(host); | |
66fd8ad5 | 294 | out: |
2f730fec PO |
295 | spin_unlock_irqrestore(&host->lock, flags); |
296 | } | |
297 | #endif | |
298 | ||
d129bceb PO |
299 | /*****************************************************************************\ |
300 | * * | |
301 | * Core functions * | |
302 | * * | |
303 | \*****************************************************************************/ | |
304 | ||
a406f5a3 | 305 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 306 | { |
7659150c PO |
307 | unsigned long flags; |
308 | size_t blksize, len, chunk; | |
7244b85b | 309 | u32 uninitialized_var(scratch); |
7659150c | 310 | u8 *buf; |
d129bceb | 311 | |
a406f5a3 | 312 | DBG("PIO reading\n"); |
d129bceb | 313 | |
a406f5a3 | 314 | blksize = host->data->blksz; |
7659150c | 315 | chunk = 0; |
d129bceb | 316 | |
7659150c | 317 | local_irq_save(flags); |
d129bceb | 318 | |
a406f5a3 | 319 | while (blksize) { |
7659150c PO |
320 | if (!sg_miter_next(&host->sg_miter)) |
321 | BUG(); | |
d129bceb | 322 | |
7659150c | 323 | len = min(host->sg_miter.length, blksize); |
d129bceb | 324 | |
7659150c PO |
325 | blksize -= len; |
326 | host->sg_miter.consumed = len; | |
14d836e7 | 327 | |
7659150c | 328 | buf = host->sg_miter.addr; |
d129bceb | 329 | |
7659150c PO |
330 | while (len) { |
331 | if (chunk == 0) { | |
4e4141a5 | 332 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
7659150c | 333 | chunk = 4; |
a406f5a3 | 334 | } |
7659150c PO |
335 | |
336 | *buf = scratch & 0xFF; | |
337 | ||
338 | buf++; | |
339 | scratch >>= 8; | |
340 | chunk--; | |
341 | len--; | |
d129bceb | 342 | } |
a406f5a3 | 343 | } |
7659150c PO |
344 | |
345 | sg_miter_stop(&host->sg_miter); | |
346 | ||
347 | local_irq_restore(flags); | |
a406f5a3 | 348 | } |
d129bceb | 349 | |
a406f5a3 PO |
350 | static void sdhci_write_block_pio(struct sdhci_host *host) |
351 | { | |
7659150c PO |
352 | unsigned long flags; |
353 | size_t blksize, len, chunk; | |
354 | u32 scratch; | |
355 | u8 *buf; | |
d129bceb | 356 | |
a406f5a3 PO |
357 | DBG("PIO writing\n"); |
358 | ||
359 | blksize = host->data->blksz; | |
7659150c PO |
360 | chunk = 0; |
361 | scratch = 0; | |
d129bceb | 362 | |
7659150c | 363 | local_irq_save(flags); |
d129bceb | 364 | |
a406f5a3 | 365 | while (blksize) { |
7659150c PO |
366 | if (!sg_miter_next(&host->sg_miter)) |
367 | BUG(); | |
a406f5a3 | 368 | |
7659150c PO |
369 | len = min(host->sg_miter.length, blksize); |
370 | ||
371 | blksize -= len; | |
372 | host->sg_miter.consumed = len; | |
373 | ||
374 | buf = host->sg_miter.addr; | |
d129bceb | 375 | |
7659150c PO |
376 | while (len) { |
377 | scratch |= (u32)*buf << (chunk * 8); | |
378 | ||
379 | buf++; | |
380 | chunk++; | |
381 | len--; | |
382 | ||
383 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { | |
4e4141a5 | 384 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
7659150c PO |
385 | chunk = 0; |
386 | scratch = 0; | |
d129bceb | 387 | } |
d129bceb PO |
388 | } |
389 | } | |
7659150c PO |
390 | |
391 | sg_miter_stop(&host->sg_miter); | |
392 | ||
393 | local_irq_restore(flags); | |
a406f5a3 PO |
394 | } |
395 | ||
396 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
397 | { | |
398 | u32 mask; | |
399 | ||
400 | BUG_ON(!host->data); | |
401 | ||
7659150c | 402 | if (host->blocks == 0) |
a406f5a3 PO |
403 | return; |
404 | ||
405 | if (host->data->flags & MMC_DATA_READ) | |
406 | mask = SDHCI_DATA_AVAILABLE; | |
407 | else | |
408 | mask = SDHCI_SPACE_AVAILABLE; | |
409 | ||
4a3cba32 PO |
410 | /* |
411 | * Some controllers (JMicron JMB38x) mess up the buffer bits | |
412 | * for transfers < 4 bytes. As long as it is just one block, | |
413 | * we can ignore the bits. | |
414 | */ | |
415 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && | |
416 | (host->data->blocks == 1)) | |
417 | mask = ~0; | |
418 | ||
4e4141a5 | 419 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
3e3bf207 AV |
420 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
421 | udelay(100); | |
422 | ||
a406f5a3 PO |
423 | if (host->data->flags & MMC_DATA_READ) |
424 | sdhci_read_block_pio(host); | |
425 | else | |
426 | sdhci_write_block_pio(host); | |
d129bceb | 427 | |
7659150c PO |
428 | host->blocks--; |
429 | if (host->blocks == 0) | |
a406f5a3 | 430 | break; |
a406f5a3 | 431 | } |
d129bceb | 432 | |
a406f5a3 | 433 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
434 | } |
435 | ||
2134a922 PO |
436 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
437 | { | |
438 | local_irq_save(*flags); | |
482fce99 | 439 | return kmap_atomic(sg_page(sg)) + sg->offset; |
2134a922 PO |
440 | } |
441 | ||
442 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) | |
443 | { | |
482fce99 | 444 | kunmap_atomic(buffer); |
2134a922 PO |
445 | local_irq_restore(*flags); |
446 | } | |
447 | ||
118cd17d BD |
448 | static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) |
449 | { | |
9e506f35 BD |
450 | __le32 *dataddr = (__le32 __force *)(desc + 4); |
451 | __le16 *cmdlen = (__le16 __force *)desc; | |
118cd17d | 452 | |
9e506f35 BD |
453 | /* SDHCI specification says ADMA descriptors should be 4 byte |
454 | * aligned, so using 16 or 32bit operations should be safe. */ | |
118cd17d | 455 | |
9e506f35 BD |
456 | cmdlen[0] = cpu_to_le16(cmd); |
457 | cmdlen[1] = cpu_to_le16(len); | |
458 | ||
459 | dataddr[0] = cpu_to_le32(addr); | |
118cd17d BD |
460 | } |
461 | ||
8f1934ce | 462 | static int sdhci_adma_table_pre(struct sdhci_host *host, |
2134a922 PO |
463 | struct mmc_data *data) |
464 | { | |
465 | int direction; | |
466 | ||
467 | u8 *desc; | |
468 | u8 *align; | |
469 | dma_addr_t addr; | |
470 | dma_addr_t align_addr; | |
471 | int len, offset; | |
472 | ||
473 | struct scatterlist *sg; | |
474 | int i; | |
475 | char *buffer; | |
476 | unsigned long flags; | |
477 | ||
478 | /* | |
479 | * The spec does not specify endianness of descriptor table. | |
480 | * We currently guess that it is LE. | |
481 | */ | |
482 | ||
483 | if (data->flags & MMC_DATA_READ) | |
484 | direction = DMA_FROM_DEVICE; | |
485 | else | |
486 | direction = DMA_TO_DEVICE; | |
487 | ||
488 | /* | |
489 | * The ADMA descriptor table is mapped further down as we | |
490 | * need to fill it with data first. | |
491 | */ | |
492 | ||
493 | host->align_addr = dma_map_single(mmc_dev(host->mmc), | |
494 | host->align_buffer, 128 * 4, direction); | |
8d8bb39b | 495 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) |
8f1934ce | 496 | goto fail; |
2134a922 PO |
497 | BUG_ON(host->align_addr & 0x3); |
498 | ||
499 | host->sg_count = dma_map_sg(mmc_dev(host->mmc), | |
500 | data->sg, data->sg_len, direction); | |
8f1934ce PO |
501 | if (host->sg_count == 0) |
502 | goto unmap_align; | |
2134a922 PO |
503 | |
504 | desc = host->adma_desc; | |
505 | align = host->align_buffer; | |
506 | ||
507 | align_addr = host->align_addr; | |
508 | ||
509 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
510 | addr = sg_dma_address(sg); | |
511 | len = sg_dma_len(sg); | |
512 | ||
513 | /* | |
514 | * The SDHCI specification states that ADMA | |
515 | * addresses must be 32-bit aligned. If they | |
516 | * aren't, then we use a bounce buffer for | |
517 | * the (up to three) bytes that screw up the | |
518 | * alignment. | |
519 | */ | |
520 | offset = (4 - (addr & 0x3)) & 0x3; | |
521 | if (offset) { | |
522 | if (data->flags & MMC_DATA_WRITE) { | |
523 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 524 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
525 | memcpy(align, buffer, offset); |
526 | sdhci_kunmap_atomic(buffer, &flags); | |
527 | } | |
528 | ||
118cd17d BD |
529 | /* tran, valid */ |
530 | sdhci_set_adma_desc(desc, align_addr, offset, 0x21); | |
2134a922 PO |
531 | |
532 | BUG_ON(offset > 65536); | |
533 | ||
2134a922 PO |
534 | align += 4; |
535 | align_addr += 4; | |
536 | ||
537 | desc += 8; | |
538 | ||
539 | addr += offset; | |
540 | len -= offset; | |
541 | } | |
542 | ||
2134a922 PO |
543 | BUG_ON(len > 65536); |
544 | ||
118cd17d BD |
545 | /* tran, valid */ |
546 | sdhci_set_adma_desc(desc, addr, len, 0x21); | |
2134a922 PO |
547 | desc += 8; |
548 | ||
549 | /* | |
550 | * If this triggers then we have a calculation bug | |
551 | * somewhere. :/ | |
552 | */ | |
553 | WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); | |
554 | } | |
555 | ||
70764a90 TA |
556 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
557 | /* | |
558 | * Mark the last descriptor as the terminating descriptor | |
559 | */ | |
560 | if (desc != host->adma_desc) { | |
561 | desc -= 8; | |
562 | desc[0] |= 0x2; /* end */ | |
563 | } | |
564 | } else { | |
565 | /* | |
566 | * Add a terminating entry. | |
567 | */ | |
2134a922 | 568 | |
70764a90 TA |
569 | /* nop, end, valid */ |
570 | sdhci_set_adma_desc(desc, 0, 0, 0x3); | |
571 | } | |
2134a922 PO |
572 | |
573 | /* | |
574 | * Resync align buffer as we might have changed it. | |
575 | */ | |
576 | if (data->flags & MMC_DATA_WRITE) { | |
577 | dma_sync_single_for_device(mmc_dev(host->mmc), | |
578 | host->align_addr, 128 * 4, direction); | |
579 | } | |
580 | ||
581 | host->adma_addr = dma_map_single(mmc_dev(host->mmc), | |
582 | host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
980167b7 | 583 | if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) |
8f1934ce | 584 | goto unmap_entries; |
2134a922 | 585 | BUG_ON(host->adma_addr & 0x3); |
8f1934ce PO |
586 | |
587 | return 0; | |
588 | ||
589 | unmap_entries: | |
590 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
591 | data->sg_len, direction); | |
592 | unmap_align: | |
593 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
594 | 128 * 4, direction); | |
595 | fail: | |
596 | return -EINVAL; | |
2134a922 PO |
597 | } |
598 | ||
599 | static void sdhci_adma_table_post(struct sdhci_host *host, | |
600 | struct mmc_data *data) | |
601 | { | |
602 | int direction; | |
603 | ||
604 | struct scatterlist *sg; | |
605 | int i, size; | |
606 | u8 *align; | |
607 | char *buffer; | |
608 | unsigned long flags; | |
609 | ||
610 | if (data->flags & MMC_DATA_READ) | |
611 | direction = DMA_FROM_DEVICE; | |
612 | else | |
613 | direction = DMA_TO_DEVICE; | |
614 | ||
615 | dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, | |
616 | (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
617 | ||
618 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
619 | 128 * 4, direction); | |
620 | ||
621 | if (data->flags & MMC_DATA_READ) { | |
622 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, | |
623 | data->sg_len, direction); | |
624 | ||
625 | align = host->align_buffer; | |
626 | ||
627 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
628 | if (sg_dma_address(sg) & 0x3) { | |
629 | size = 4 - (sg_dma_address(sg) & 0x3); | |
630 | ||
631 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 632 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
633 | memcpy(buffer, align, size); |
634 | sdhci_kunmap_atomic(buffer, &flags); | |
635 | ||
636 | align += 4; | |
637 | } | |
638 | } | |
639 | } | |
640 | ||
641 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
642 | data->sg_len, direction); | |
643 | } | |
644 | ||
a3c7778f | 645 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb | 646 | { |
1c8cde92 | 647 | u8 count; |
a3c7778f | 648 | struct mmc_data *data = cmd->data; |
1c8cde92 | 649 | unsigned target_timeout, current_timeout; |
d129bceb | 650 | |
ee53ab5d PO |
651 | /* |
652 | * If the host controller provides us with an incorrect timeout | |
653 | * value, just skip the check and use 0xE. The hardware may take | |
654 | * longer to time out, but that's much better than having a too-short | |
655 | * timeout value. | |
656 | */ | |
11a2f1b7 | 657 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
ee53ab5d | 658 | return 0xE; |
e538fbe8 | 659 | |
a3c7778f | 660 | /* Unspecified timeout, assume max */ |
1d4d7744 | 661 | if (!data && !cmd->busy_timeout) |
a3c7778f | 662 | return 0xE; |
d129bceb | 663 | |
a3c7778f AW |
664 | /* timeout in us */ |
665 | if (!data) | |
1d4d7744 | 666 | target_timeout = cmd->busy_timeout * 1000; |
78a2ca27 AS |
667 | else { |
668 | target_timeout = data->timeout_ns / 1000; | |
669 | if (host->clock) | |
670 | target_timeout += data->timeout_clks / host->clock; | |
671 | } | |
81b39802 | 672 | |
1c8cde92 PO |
673 | /* |
674 | * Figure out needed cycles. | |
675 | * We do this in steps in order to fit inside a 32 bit int. | |
676 | * The first step is the minimum timeout, which will have a | |
677 | * minimum resolution of 6 bits: | |
678 | * (1) 2^13*1000 > 2^22, | |
679 | * (2) host->timeout_clk < 2^16 | |
680 | * => | |
681 | * (1) / (2) > 2^6 | |
682 | */ | |
683 | count = 0; | |
684 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
685 | while (current_timeout < target_timeout) { | |
686 | count++; | |
687 | current_timeout <<= 1; | |
688 | if (count >= 0xF) | |
689 | break; | |
690 | } | |
691 | ||
692 | if (count >= 0xF) { | |
09eeff52 CB |
693 | DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", |
694 | mmc_hostname(host->mmc), count, cmd->opcode); | |
1c8cde92 PO |
695 | count = 0xE; |
696 | } | |
697 | ||
ee53ab5d PO |
698 | return count; |
699 | } | |
700 | ||
6aa943ab AV |
701 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
702 | { | |
703 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; | |
704 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; | |
705 | ||
706 | if (host->flags & SDHCI_REQ_USE_DMA) | |
b537f94c | 707 | host->ier = (host->ier & ~pio_irqs) | dma_irqs; |
6aa943ab | 708 | else |
b537f94c RK |
709 | host->ier = (host->ier & ~dma_irqs) | pio_irqs; |
710 | ||
711 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
712 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
6aa943ab AV |
713 | } |
714 | ||
a3c7778f | 715 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) |
ee53ab5d PO |
716 | { |
717 | u8 count; | |
2134a922 | 718 | u8 ctrl; |
a3c7778f | 719 | struct mmc_data *data = cmd->data; |
8f1934ce | 720 | int ret; |
ee53ab5d PO |
721 | |
722 | WARN_ON(host->data); | |
723 | ||
a3c7778f AW |
724 | if (data || (cmd->flags & MMC_RSP_BUSY)) { |
725 | count = sdhci_calc_timeout(host, cmd); | |
726 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); | |
727 | } | |
728 | ||
729 | if (!data) | |
ee53ab5d PO |
730 | return; |
731 | ||
732 | /* Sanity checks */ | |
733 | BUG_ON(data->blksz * data->blocks > 524288); | |
734 | BUG_ON(data->blksz > host->mmc->max_blk_size); | |
735 | BUG_ON(data->blocks > 65535); | |
736 | ||
737 | host->data = data; | |
738 | host->data_early = 0; | |
f6a03cbf | 739 | host->data->bytes_xfered = 0; |
ee53ab5d | 740 | |
a13abc7b | 741 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) |
c9fddbc4 PO |
742 | host->flags |= SDHCI_REQ_USE_DMA; |
743 | ||
2134a922 PO |
744 | /* |
745 | * FIXME: This doesn't account for merging when mapping the | |
746 | * scatterlist. | |
747 | */ | |
748 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
749 | int broken, i; | |
750 | struct scatterlist *sg; | |
751 | ||
752 | broken = 0; | |
753 | if (host->flags & SDHCI_USE_ADMA) { | |
754 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
755 | broken = 1; | |
756 | } else { | |
757 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) | |
758 | broken = 1; | |
759 | } | |
760 | ||
761 | if (unlikely(broken)) { | |
762 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
763 | if (sg->length & 0x3) { | |
764 | DBG("Reverting to PIO because of " | |
765 | "transfer size (%d)\n", | |
766 | sg->length); | |
767 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
768 | break; | |
769 | } | |
770 | } | |
771 | } | |
c9fddbc4 PO |
772 | } |
773 | ||
774 | /* | |
775 | * The assumption here being that alignment is the same after | |
776 | * translation to device address space. | |
777 | */ | |
2134a922 PO |
778 | if (host->flags & SDHCI_REQ_USE_DMA) { |
779 | int broken, i; | |
780 | struct scatterlist *sg; | |
781 | ||
782 | broken = 0; | |
783 | if (host->flags & SDHCI_USE_ADMA) { | |
784 | /* | |
785 | * As we use 3 byte chunks to work around | |
786 | * alignment problems, we need to check this | |
787 | * quirk. | |
788 | */ | |
789 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
790 | broken = 1; | |
791 | } else { | |
792 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) | |
793 | broken = 1; | |
794 | } | |
795 | ||
796 | if (unlikely(broken)) { | |
797 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
798 | if (sg->offset & 0x3) { | |
799 | DBG("Reverting to PIO because of " | |
800 | "bad alignment\n"); | |
801 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
802 | break; | |
803 | } | |
804 | } | |
805 | } | |
806 | } | |
807 | ||
8f1934ce PO |
808 | if (host->flags & SDHCI_REQ_USE_DMA) { |
809 | if (host->flags & SDHCI_USE_ADMA) { | |
810 | ret = sdhci_adma_table_pre(host, data); | |
811 | if (ret) { | |
812 | /* | |
813 | * This only happens when someone fed | |
814 | * us an invalid request. | |
815 | */ | |
816 | WARN_ON(1); | |
ebd6d357 | 817 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 818 | } else { |
4e4141a5 AV |
819 | sdhci_writel(host, host->adma_addr, |
820 | SDHCI_ADMA_ADDRESS); | |
8f1934ce PO |
821 | } |
822 | } else { | |
c8b3e02e | 823 | int sg_cnt; |
8f1934ce | 824 | |
c8b3e02e | 825 | sg_cnt = dma_map_sg(mmc_dev(host->mmc), |
8f1934ce PO |
826 | data->sg, data->sg_len, |
827 | (data->flags & MMC_DATA_READ) ? | |
828 | DMA_FROM_DEVICE : | |
829 | DMA_TO_DEVICE); | |
c8b3e02e | 830 | if (sg_cnt == 0) { |
8f1934ce PO |
831 | /* |
832 | * This only happens when someone fed | |
833 | * us an invalid request. | |
834 | */ | |
835 | WARN_ON(1); | |
ebd6d357 | 836 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 837 | } else { |
719a61b4 | 838 | WARN_ON(sg_cnt != 1); |
4e4141a5 AV |
839 | sdhci_writel(host, sg_dma_address(data->sg), |
840 | SDHCI_DMA_ADDRESS); | |
8f1934ce PO |
841 | } |
842 | } | |
843 | } | |
844 | ||
2134a922 PO |
845 | /* |
846 | * Always adjust the DMA selection as some controllers | |
847 | * (e.g. JMicron) can't do PIO properly when the selection | |
848 | * is ADMA. | |
849 | */ | |
850 | if (host->version >= SDHCI_SPEC_200) { | |
4e4141a5 | 851 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
2134a922 PO |
852 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
853 | if ((host->flags & SDHCI_REQ_USE_DMA) && | |
854 | (host->flags & SDHCI_USE_ADMA)) | |
855 | ctrl |= SDHCI_CTRL_ADMA32; | |
856 | else | |
857 | ctrl |= SDHCI_CTRL_SDMA; | |
4e4141a5 | 858 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
c9fddbc4 PO |
859 | } |
860 | ||
8f1934ce | 861 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
da60a91d SAS |
862 | int flags; |
863 | ||
864 | flags = SG_MITER_ATOMIC; | |
865 | if (host->data->flags & MMC_DATA_READ) | |
866 | flags |= SG_MITER_TO_SG; | |
867 | else | |
868 | flags |= SG_MITER_FROM_SG; | |
869 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
7659150c | 870 | host->blocks = data->blocks; |
d129bceb | 871 | } |
c7fa9963 | 872 | |
6aa943ab AV |
873 | sdhci_set_transfer_irqs(host); |
874 | ||
f6a03cbf MV |
875 | /* Set the DMA boundary value and block size */ |
876 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, | |
877 | data->blksz), SDHCI_BLOCK_SIZE); | |
4e4141a5 | 878 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
c7fa9963 PO |
879 | } |
880 | ||
881 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
e89d456f | 882 | struct mmc_command *cmd) |
c7fa9963 PO |
883 | { |
884 | u16 mode; | |
e89d456f | 885 | struct mmc_data *data = cmd->data; |
c7fa9963 | 886 | |
2b558c13 DA |
887 | if (data == NULL) { |
888 | /* clear Auto CMD settings for no data CMDs */ | |
889 | mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); | |
890 | sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | | |
891 | SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); | |
c7fa9963 | 892 | return; |
2b558c13 | 893 | } |
c7fa9963 | 894 | |
e538fbe8 PO |
895 | WARN_ON(!host->data); |
896 | ||
c7fa9963 | 897 | mode = SDHCI_TRNS_BLK_CNT_EN; |
e89d456f AW |
898 | if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { |
899 | mode |= SDHCI_TRNS_MULTI; | |
900 | /* | |
901 | * If we are sending CMD23, CMD12 never gets sent | |
902 | * on successful completion (so no Auto-CMD12). | |
903 | */ | |
904 | if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) | |
905 | mode |= SDHCI_TRNS_AUTO_CMD12; | |
8edf6371 AW |
906 | else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { |
907 | mode |= SDHCI_TRNS_AUTO_CMD23; | |
908 | sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); | |
909 | } | |
c4512f79 | 910 | } |
8edf6371 | 911 | |
c7fa9963 PO |
912 | if (data->flags & MMC_DATA_READ) |
913 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 914 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
915 | mode |= SDHCI_TRNS_DMA; |
916 | ||
4e4141a5 | 917 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
d129bceb PO |
918 | } |
919 | ||
920 | static void sdhci_finish_data(struct sdhci_host *host) | |
921 | { | |
922 | struct mmc_data *data; | |
d129bceb PO |
923 | |
924 | BUG_ON(!host->data); | |
925 | ||
926 | data = host->data; | |
927 | host->data = NULL; | |
928 | ||
c9fddbc4 | 929 | if (host->flags & SDHCI_REQ_USE_DMA) { |
2134a922 PO |
930 | if (host->flags & SDHCI_USE_ADMA) |
931 | sdhci_adma_table_post(host, data); | |
932 | else { | |
933 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
934 | data->sg_len, (data->flags & MMC_DATA_READ) ? | |
935 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
936 | } | |
d129bceb PO |
937 | } |
938 | ||
939 | /* | |
c9b74c5b PO |
940 | * The specification states that the block count register must |
941 | * be updated, but it does not specify at what point in the | |
942 | * data flow. That makes the register entirely useless to read | |
943 | * back so we have to assume that nothing made it to the card | |
944 | * in the event of an error. | |
d129bceb | 945 | */ |
c9b74c5b PO |
946 | if (data->error) |
947 | data->bytes_xfered = 0; | |
d129bceb | 948 | else |
c9b74c5b | 949 | data->bytes_xfered = data->blksz * data->blocks; |
d129bceb | 950 | |
e89d456f AW |
951 | /* |
952 | * Need to send CMD12 if - | |
953 | * a) open-ended multiblock transfer (no CMD23) | |
954 | * b) error in multiblock transfer | |
955 | */ | |
956 | if (data->stop && | |
957 | (data->error || | |
958 | !host->mrq->sbc)) { | |
959 | ||
d129bceb PO |
960 | /* |
961 | * The controller needs a reset of internal state machines | |
962 | * upon error conditions. | |
963 | */ | |
17b0429d | 964 | if (data->error) { |
d129bceb PO |
965 | sdhci_reset(host, SDHCI_RESET_CMD); |
966 | sdhci_reset(host, SDHCI_RESET_DATA); | |
967 | } | |
968 | ||
969 | sdhci_send_command(host, data->stop); | |
970 | } else | |
971 | tasklet_schedule(&host->finish_tasklet); | |
972 | } | |
973 | ||
c0e55129 | 974 | void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb PO |
975 | { |
976 | int flags; | |
fd2208d7 | 977 | u32 mask; |
7cb2c76f | 978 | unsigned long timeout; |
d129bceb PO |
979 | |
980 | WARN_ON(host->cmd); | |
981 | ||
d129bceb | 982 | /* Wait max 10 ms */ |
7cb2c76f | 983 | timeout = 10; |
fd2208d7 PO |
984 | |
985 | mask = SDHCI_CMD_INHIBIT; | |
986 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
987 | mask |= SDHCI_DATA_INHIBIT; | |
988 | ||
989 | /* We shouldn't wait for data inihibit for stop commands, even | |
990 | though they might use busy signaling */ | |
991 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
992 | mask &= ~SDHCI_DATA_INHIBIT; | |
993 | ||
4e4141a5 | 994 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
7cb2c76f | 995 | if (timeout == 0) { |
a3c76eb9 | 996 | pr_err("%s: Controller never released " |
acf1da45 | 997 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb | 998 | sdhci_dumpregs(host); |
17b0429d | 999 | cmd->error = -EIO; |
d129bceb PO |
1000 | tasklet_schedule(&host->finish_tasklet); |
1001 | return; | |
1002 | } | |
7cb2c76f PO |
1003 | timeout--; |
1004 | mdelay(1); | |
1005 | } | |
d129bceb | 1006 | |
3e1a6892 | 1007 | timeout = jiffies; |
1d4d7744 UH |
1008 | if (!cmd->data && cmd->busy_timeout > 9000) |
1009 | timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; | |
3e1a6892 AH |
1010 | else |
1011 | timeout += 10 * HZ; | |
1012 | mod_timer(&host->timer, timeout); | |
d129bceb PO |
1013 | |
1014 | host->cmd = cmd; | |
1015 | ||
a3c7778f | 1016 | sdhci_prepare_data(host, cmd); |
d129bceb | 1017 | |
4e4141a5 | 1018 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
d129bceb | 1019 | |
e89d456f | 1020 | sdhci_set_transfer_mode(host, cmd); |
c7fa9963 | 1021 | |
d129bceb | 1022 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
a3c76eb9 | 1023 | pr_err("%s: Unsupported response type!\n", |
d129bceb | 1024 | mmc_hostname(host->mmc)); |
17b0429d | 1025 | cmd->error = -EINVAL; |
d129bceb PO |
1026 | tasklet_schedule(&host->finish_tasklet); |
1027 | return; | |
1028 | } | |
1029 | ||
1030 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
1031 | flags = SDHCI_CMD_RESP_NONE; | |
1032 | else if (cmd->flags & MMC_RSP_136) | |
1033 | flags = SDHCI_CMD_RESP_LONG; | |
1034 | else if (cmd->flags & MMC_RSP_BUSY) | |
1035 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
1036 | else | |
1037 | flags = SDHCI_CMD_RESP_SHORT; | |
1038 | ||
1039 | if (cmd->flags & MMC_RSP_CRC) | |
1040 | flags |= SDHCI_CMD_CRC; | |
1041 | if (cmd->flags & MMC_RSP_OPCODE) | |
1042 | flags |= SDHCI_CMD_INDEX; | |
b513ea25 AN |
1043 | |
1044 | /* CMD19 is special in that the Data Present Select should be set */ | |
069c9f14 G |
1045 | if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || |
1046 | cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) | |
d129bceb PO |
1047 | flags |= SDHCI_CMD_DATA; |
1048 | ||
4e4141a5 | 1049 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
d129bceb | 1050 | } |
c0e55129 | 1051 | EXPORT_SYMBOL_GPL(sdhci_send_command); |
d129bceb PO |
1052 | |
1053 | static void sdhci_finish_command(struct sdhci_host *host) | |
1054 | { | |
1055 | int i; | |
1056 | ||
1057 | BUG_ON(host->cmd == NULL); | |
1058 | ||
1059 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
1060 | if (host->cmd->flags & MMC_RSP_136) { | |
1061 | /* CRC is stripped so we need to do some shifting. */ | |
1062 | for (i = 0;i < 4;i++) { | |
4e4141a5 | 1063 | host->cmd->resp[i] = sdhci_readl(host, |
d129bceb PO |
1064 | SDHCI_RESPONSE + (3-i)*4) << 8; |
1065 | if (i != 3) | |
1066 | host->cmd->resp[i] |= | |
4e4141a5 | 1067 | sdhci_readb(host, |
d129bceb PO |
1068 | SDHCI_RESPONSE + (3-i)*4-1); |
1069 | } | |
1070 | } else { | |
4e4141a5 | 1071 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
d129bceb PO |
1072 | } |
1073 | } | |
1074 | ||
17b0429d | 1075 | host->cmd->error = 0; |
d129bceb | 1076 | |
e89d456f AW |
1077 | /* Finished CMD23, now send actual command. */ |
1078 | if (host->cmd == host->mrq->sbc) { | |
1079 | host->cmd = NULL; | |
1080 | sdhci_send_command(host, host->mrq->cmd); | |
1081 | } else { | |
e538fbe8 | 1082 | |
e89d456f AW |
1083 | /* Processed actual command. */ |
1084 | if (host->data && host->data_early) | |
1085 | sdhci_finish_data(host); | |
d129bceb | 1086 | |
e89d456f AW |
1087 | if (!host->cmd->data) |
1088 | tasklet_schedule(&host->finish_tasklet); | |
1089 | ||
1090 | host->cmd = NULL; | |
1091 | } | |
d129bceb PO |
1092 | } |
1093 | ||
52983382 KL |
1094 | static u16 sdhci_get_preset_value(struct sdhci_host *host) |
1095 | { | |
1096 | u16 ctrl, preset = 0; | |
1097 | ||
1098 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1099 | ||
1100 | switch (ctrl & SDHCI_CTRL_UHS_MASK) { | |
1101 | case SDHCI_CTRL_UHS_SDR12: | |
1102 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); | |
1103 | break; | |
1104 | case SDHCI_CTRL_UHS_SDR25: | |
1105 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); | |
1106 | break; | |
1107 | case SDHCI_CTRL_UHS_SDR50: | |
1108 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); | |
1109 | break; | |
1110 | case SDHCI_CTRL_UHS_SDR104: | |
1111 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); | |
1112 | break; | |
1113 | case SDHCI_CTRL_UHS_DDR50: | |
1114 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); | |
1115 | break; | |
1116 | default: | |
1117 | pr_warn("%s: Invalid UHS-I mode selected\n", | |
1118 | mmc_hostname(host->mmc)); | |
1119 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); | |
1120 | break; | |
1121 | } | |
1122 | return preset; | |
1123 | } | |
1124 | ||
d129bceb PO |
1125 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
1126 | { | |
c3ed3877 | 1127 | int div = 0; /* Initialized for compiler warning */ |
df16219f | 1128 | int real_div = div, clk_mul = 1; |
c3ed3877 | 1129 | u16 clk = 0; |
7cb2c76f | 1130 | unsigned long timeout; |
d129bceb | 1131 | |
30832ab5 | 1132 | if (clock && clock == host->clock) |
d129bceb PO |
1133 | return; |
1134 | ||
df16219f GC |
1135 | host->mmc->actual_clock = 0; |
1136 | ||
8114634c AV |
1137 | if (host->ops->set_clock) { |
1138 | host->ops->set_clock(host, clock); | |
1139 | if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) | |
1140 | return; | |
1141 | } | |
1142 | ||
4e4141a5 | 1143 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1144 | |
1145 | if (clock == 0) | |
1146 | goto out; | |
1147 | ||
85105c53 | 1148 | if (host->version >= SDHCI_SPEC_300) { |
52983382 KL |
1149 | if (sdhci_readw(host, SDHCI_HOST_CONTROL2) & |
1150 | SDHCI_CTRL_PRESET_VAL_ENABLE) { | |
1151 | u16 pre_val; | |
1152 | ||
1153 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1154 | pre_val = sdhci_get_preset_value(host); | |
1155 | div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) | |
1156 | >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; | |
1157 | if (host->clk_mul && | |
1158 | (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { | |
1159 | clk = SDHCI_PROG_CLOCK_MODE; | |
1160 | real_div = div + 1; | |
1161 | clk_mul = host->clk_mul; | |
1162 | } else { | |
1163 | real_div = max_t(int, 1, div << 1); | |
1164 | } | |
1165 | goto clock_set; | |
1166 | } | |
1167 | ||
c3ed3877 AN |
1168 | /* |
1169 | * Check if the Host Controller supports Programmable Clock | |
1170 | * Mode. | |
1171 | */ | |
1172 | if (host->clk_mul) { | |
52983382 KL |
1173 | for (div = 1; div <= 1024; div++) { |
1174 | if ((host->max_clk * host->clk_mul / div) | |
1175 | <= clock) | |
1176 | break; | |
1177 | } | |
c3ed3877 | 1178 | /* |
52983382 KL |
1179 | * Set Programmable Clock Mode in the Clock |
1180 | * Control register. | |
c3ed3877 | 1181 | */ |
52983382 KL |
1182 | clk = SDHCI_PROG_CLOCK_MODE; |
1183 | real_div = div; | |
1184 | clk_mul = host->clk_mul; | |
1185 | div--; | |
c3ed3877 AN |
1186 | } else { |
1187 | /* Version 3.00 divisors must be a multiple of 2. */ | |
1188 | if (host->max_clk <= clock) | |
1189 | div = 1; | |
1190 | else { | |
1191 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; | |
1192 | div += 2) { | |
1193 | if ((host->max_clk / div) <= clock) | |
1194 | break; | |
1195 | } | |
85105c53 | 1196 | } |
df16219f | 1197 | real_div = div; |
c3ed3877 | 1198 | div >>= 1; |
85105c53 ZG |
1199 | } |
1200 | } else { | |
1201 | /* Version 2.00 divisors must be a power of 2. */ | |
0397526d | 1202 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
85105c53 ZG |
1203 | if ((host->max_clk / div) <= clock) |
1204 | break; | |
1205 | } | |
df16219f | 1206 | real_div = div; |
c3ed3877 | 1207 | div >>= 1; |
d129bceb | 1208 | } |
d129bceb | 1209 | |
52983382 | 1210 | clock_set: |
df16219f GC |
1211 | if (real_div) |
1212 | host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; | |
1213 | ||
c3ed3877 | 1214 | clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
85105c53 ZG |
1215 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
1216 | << SDHCI_DIVIDER_HI_SHIFT; | |
d129bceb | 1217 | clk |= SDHCI_CLOCK_INT_EN; |
4e4141a5 | 1218 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1219 | |
27f6cb16 CB |
1220 | /* Wait max 20 ms */ |
1221 | timeout = 20; | |
4e4141a5 | 1222 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
7cb2c76f PO |
1223 | & SDHCI_CLOCK_INT_STABLE)) { |
1224 | if (timeout == 0) { | |
a3c76eb9 | 1225 | pr_err("%s: Internal clock never " |
acf1da45 | 1226 | "stabilised.\n", mmc_hostname(host->mmc)); |
d129bceb PO |
1227 | sdhci_dumpregs(host); |
1228 | return; | |
1229 | } | |
7cb2c76f PO |
1230 | timeout--; |
1231 | mdelay(1); | |
1232 | } | |
d129bceb PO |
1233 | |
1234 | clk |= SDHCI_CLOCK_CARD_EN; | |
4e4141a5 | 1235 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1236 | |
1237 | out: | |
1238 | host->clock = clock; | |
1239 | } | |
1240 | ||
8213af3b AS |
1241 | static inline void sdhci_update_clock(struct sdhci_host *host) |
1242 | { | |
1243 | unsigned int clock; | |
1244 | ||
1245 | clock = host->clock; | |
1246 | host->clock = 0; | |
1247 | sdhci_set_clock(host, clock); | |
1248 | } | |
1249 | ||
ceb6143b | 1250 | static int sdhci_set_power(struct sdhci_host *host, unsigned short power) |
146ad66e | 1251 | { |
8364248a | 1252 | u8 pwr = 0; |
146ad66e | 1253 | |
8364248a | 1254 | if (power != (unsigned short)-1) { |
ae628903 PO |
1255 | switch (1 << power) { |
1256 | case MMC_VDD_165_195: | |
1257 | pwr = SDHCI_POWER_180; | |
1258 | break; | |
1259 | case MMC_VDD_29_30: | |
1260 | case MMC_VDD_30_31: | |
1261 | pwr = SDHCI_POWER_300; | |
1262 | break; | |
1263 | case MMC_VDD_32_33: | |
1264 | case MMC_VDD_33_34: | |
1265 | pwr = SDHCI_POWER_330; | |
1266 | break; | |
1267 | default: | |
1268 | BUG(); | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | if (host->pwr == pwr) | |
ceb6143b | 1273 | return -1; |
146ad66e | 1274 | |
ae628903 PO |
1275 | host->pwr = pwr; |
1276 | ||
1277 | if (pwr == 0) { | |
4e4141a5 | 1278 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
f0710a55 AH |
1279 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1280 | sdhci_runtime_pm_bus_off(host); | |
ceb6143b | 1281 | return 0; |
9e9dc5f2 DS |
1282 | } |
1283 | ||
1284 | /* | |
1285 | * Spec says that we should clear the power reg before setting | |
1286 | * a new value. Some controllers don't seem to like this though. | |
1287 | */ | |
b8c86fc5 | 1288 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
4e4141a5 | 1289 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
146ad66e | 1290 | |
e08c1694 | 1291 | /* |
c71f6512 | 1292 | * At least the Marvell CaFe chip gets confused if we set the voltage |
e08c1694 AS |
1293 | * and set turn on power at the same time, so set the voltage first. |
1294 | */ | |
11a2f1b7 | 1295 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) |
ae628903 | 1296 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
e08c1694 | 1297 | |
ae628903 | 1298 | pwr |= SDHCI_POWER_ON; |
146ad66e | 1299 | |
ae628903 | 1300 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
557b0697 | 1301 | |
f0710a55 AH |
1302 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
1303 | sdhci_runtime_pm_bus_on(host); | |
1304 | ||
557b0697 HW |
1305 | /* |
1306 | * Some controllers need an extra 10ms delay of 10ms before they | |
1307 | * can apply clock after applying power | |
1308 | */ | |
11a2f1b7 | 1309 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) |
557b0697 | 1310 | mdelay(10); |
ceb6143b AH |
1311 | |
1312 | return power; | |
146ad66e PO |
1313 | } |
1314 | ||
d129bceb PO |
1315 | /*****************************************************************************\ |
1316 | * * | |
1317 | * MMC callbacks * | |
1318 | * * | |
1319 | \*****************************************************************************/ | |
1320 | ||
1321 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1322 | { | |
1323 | struct sdhci_host *host; | |
505a8680 | 1324 | int present; |
d129bceb | 1325 | unsigned long flags; |
473b095a | 1326 | u32 tuning_opcode; |
d129bceb PO |
1327 | |
1328 | host = mmc_priv(mmc); | |
1329 | ||
66fd8ad5 AH |
1330 | sdhci_runtime_pm_get(host); |
1331 | ||
d129bceb PO |
1332 | spin_lock_irqsave(&host->lock, flags); |
1333 | ||
1334 | WARN_ON(host->mrq != NULL); | |
1335 | ||
f9134319 | 1336 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1337 | sdhci_activate_led(host); |
2f730fec | 1338 | #endif |
e89d456f AW |
1339 | |
1340 | /* | |
1341 | * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED | |
1342 | * requests if Auto-CMD12 is enabled. | |
1343 | */ | |
1344 | if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { | |
c4512f79 JH |
1345 | if (mrq->stop) { |
1346 | mrq->data->stop = NULL; | |
1347 | mrq->stop = NULL; | |
1348 | } | |
1349 | } | |
d129bceb PO |
1350 | |
1351 | host->mrq = mrq; | |
1352 | ||
505a8680 SG |
1353 | /* |
1354 | * Firstly check card presence from cd-gpio. The return could | |
1355 | * be one of the following possibilities: | |
1356 | * negative: cd-gpio is not available | |
1357 | * zero: cd-gpio is used, and card is removed | |
1358 | * one: cd-gpio is used, and card is present | |
1359 | */ | |
1360 | present = mmc_gpio_get_cd(host->mmc); | |
1361 | if (present < 0) { | |
1362 | /* If polling, assume that the card is always present. */ | |
1363 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
1364 | present = 1; | |
1365 | else | |
1366 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
1367 | SDHCI_CARD_PRESENT; | |
bec9d4e5 GL |
1368 | } |
1369 | ||
68d1fb7e | 1370 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { |
17b0429d | 1371 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb | 1372 | tasklet_schedule(&host->finish_tasklet); |
cf2b5eea AN |
1373 | } else { |
1374 | u32 present_state; | |
1375 | ||
1376 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
1377 | /* | |
1378 | * Check if the re-tuning timer has already expired and there | |
1379 | * is no on-going data transfer. If so, we need to execute | |
1380 | * tuning procedure before sending command. | |
1381 | */ | |
1382 | if ((host->flags & SDHCI_NEEDS_RETUNING) && | |
1383 | !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { | |
14efd957 CB |
1384 | if (mmc->card) { |
1385 | /* eMMC uses cmd21 but sd and sdio use cmd19 */ | |
1386 | tuning_opcode = | |
1387 | mmc->card->type == MMC_TYPE_MMC ? | |
1388 | MMC_SEND_TUNING_BLOCK_HS200 : | |
1389 | MMC_SEND_TUNING_BLOCK; | |
63c21180 CL |
1390 | |
1391 | /* Here we need to set the host->mrq to NULL, | |
1392 | * in case the pending finish_tasklet | |
1393 | * finishes it incorrectly. | |
1394 | */ | |
1395 | host->mrq = NULL; | |
1396 | ||
14efd957 CB |
1397 | spin_unlock_irqrestore(&host->lock, flags); |
1398 | sdhci_execute_tuning(mmc, tuning_opcode); | |
1399 | spin_lock_irqsave(&host->lock, flags); | |
1400 | ||
1401 | /* Restore original mmc_request structure */ | |
1402 | host->mrq = mrq; | |
1403 | } | |
cf2b5eea AN |
1404 | } |
1405 | ||
8edf6371 | 1406 | if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) |
e89d456f AW |
1407 | sdhci_send_command(host, mrq->sbc); |
1408 | else | |
1409 | sdhci_send_command(host, mrq->cmd); | |
cf2b5eea | 1410 | } |
d129bceb | 1411 | |
5f25a66f | 1412 | mmiowb(); |
d129bceb PO |
1413 | spin_unlock_irqrestore(&host->lock, flags); |
1414 | } | |
1415 | ||
66fd8ad5 | 1416 | static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) |
d129bceb | 1417 | { |
d129bceb | 1418 | unsigned long flags; |
ceb6143b | 1419 | int vdd_bit = -1; |
d129bceb PO |
1420 | u8 ctrl; |
1421 | ||
d129bceb PO |
1422 | spin_lock_irqsave(&host->lock, flags); |
1423 | ||
ceb6143b AH |
1424 | if (host->flags & SDHCI_DEVICE_DEAD) { |
1425 | spin_unlock_irqrestore(&host->lock, flags); | |
1426 | if (host->vmmc && ios->power_mode == MMC_POWER_OFF) | |
1427 | mmc_regulator_set_ocr(host->mmc, host->vmmc, 0); | |
1428 | return; | |
1429 | } | |
1e72859e | 1430 | |
d129bceb PO |
1431 | /* |
1432 | * Reset the chip on each power off. | |
1433 | * Should clear out any weird states. | |
1434 | */ | |
1435 | if (ios->power_mode == MMC_POWER_OFF) { | |
4e4141a5 | 1436 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
7260cf5e | 1437 | sdhci_reinit(host); |
d129bceb PO |
1438 | } |
1439 | ||
52983382 | 1440 | if (host->version >= SDHCI_SPEC_300 && |
372c4634 DA |
1441 | (ios->power_mode == MMC_POWER_UP) && |
1442 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) | |
52983382 KL |
1443 | sdhci_enable_preset_value(host, false); |
1444 | ||
d129bceb PO |
1445 | sdhci_set_clock(host, ios->clock); |
1446 | ||
1447 | if (ios->power_mode == MMC_POWER_OFF) | |
ceb6143b | 1448 | vdd_bit = sdhci_set_power(host, -1); |
d129bceb | 1449 | else |
ceb6143b AH |
1450 | vdd_bit = sdhci_set_power(host, ios->vdd); |
1451 | ||
1452 | if (host->vmmc && vdd_bit != -1) { | |
1453 | spin_unlock_irqrestore(&host->lock, flags); | |
1454 | mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit); | |
1455 | spin_lock_irqsave(&host->lock, flags); | |
1456 | } | |
d129bceb | 1457 | |
643a81ff PR |
1458 | if (host->ops->platform_send_init_74_clocks) |
1459 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); | |
1460 | ||
15ec4461 PR |
1461 | /* |
1462 | * If your platform has 8-bit width support but is not a v3 controller, | |
1463 | * or if it requires special setup code, you should implement that in | |
7bc088d3 | 1464 | * platform_bus_width(). |
15ec4461 | 1465 | */ |
7bc088d3 SH |
1466 | if (host->ops->platform_bus_width) { |
1467 | host->ops->platform_bus_width(host, ios->bus_width); | |
1468 | } else { | |
15ec4461 PR |
1469 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
1470 | if (ios->bus_width == MMC_BUS_WIDTH_8) { | |
1471 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1472 | if (host->version >= SDHCI_SPEC_300) | |
1473 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1474 | } else { | |
1475 | if (host->version >= SDHCI_SPEC_300) | |
1476 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1477 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
1478 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1479 | else | |
1480 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1481 | } | |
1482 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1483 | } | |
ae6d6c92 | 1484 | |
15ec4461 | 1485 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
cd9277c0 | 1486 | |
3ab9c8da PR |
1487 | if ((ios->timing == MMC_TIMING_SD_HS || |
1488 | ios->timing == MMC_TIMING_MMC_HS) | |
1489 | && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) | |
cd9277c0 PO |
1490 | ctrl |= SDHCI_CTRL_HISPD; |
1491 | else | |
1492 | ctrl &= ~SDHCI_CTRL_HISPD; | |
1493 | ||
d6d50a15 | 1494 | if (host->version >= SDHCI_SPEC_300) { |
49c468fc | 1495 | u16 clk, ctrl_2; |
49c468fc AN |
1496 | |
1497 | /* In case of UHS-I modes, set High Speed Enable */ | |
069c9f14 | 1498 | if ((ios->timing == MMC_TIMING_MMC_HS200) || |
bb8175a8 | 1499 | (ios->timing == MMC_TIMING_MMC_DDR52) || |
069c9f14 | 1500 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
49c468fc AN |
1501 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
1502 | (ios->timing == MMC_TIMING_UHS_DDR50) || | |
dd8df17f | 1503 | (ios->timing == MMC_TIMING_UHS_SDR25)) |
49c468fc | 1504 | ctrl |= SDHCI_CTRL_HISPD; |
d6d50a15 AN |
1505 | |
1506 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1507 | if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { | |
758535c4 | 1508 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d6d50a15 AN |
1509 | /* |
1510 | * We only need to set Driver Strength if the | |
1511 | * preset value enable is not set. | |
1512 | */ | |
1513 | ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; | |
1514 | if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) | |
1515 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; | |
1516 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) | |
1517 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; | |
1518 | ||
1519 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
758535c4 AN |
1520 | } else { |
1521 | /* | |
1522 | * According to SDHC Spec v3.00, if the Preset Value | |
1523 | * Enable in the Host Control 2 register is set, we | |
1524 | * need to reset SD Clock Enable before changing High | |
1525 | * Speed Enable to avoid generating clock gliches. | |
1526 | */ | |
758535c4 AN |
1527 | |
1528 | /* Reset SD Clock Enable */ | |
1529 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1530 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
1531 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1532 | ||
1533 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1534 | ||
1535 | /* Re-enable SD Clock */ | |
8213af3b | 1536 | sdhci_update_clock(host); |
d6d50a15 | 1537 | } |
49c468fc | 1538 | |
49c468fc AN |
1539 | |
1540 | /* Reset SD Clock Enable */ | |
1541 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1542 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
1543 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
1544 | ||
6322cdd0 PR |
1545 | if (host->ops->set_uhs_signaling) |
1546 | host->ops->set_uhs_signaling(host, ios->timing); | |
1547 | else { | |
1548 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1549 | /* Select Bus Speed Mode for host */ | |
1550 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
59911568 GC |
1551 | if ((ios->timing == MMC_TIMING_MMC_HS200) || |
1552 | (ios->timing == MMC_TIMING_UHS_SDR104)) | |
1553 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | |
069c9f14 | 1554 | else if (ios->timing == MMC_TIMING_UHS_SDR12) |
6322cdd0 PR |
1555 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; |
1556 | else if (ios->timing == MMC_TIMING_UHS_SDR25) | |
1557 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
1558 | else if (ios->timing == MMC_TIMING_UHS_SDR50) | |
1559 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | |
bb8175a8 SJ |
1560 | else if ((ios->timing == MMC_TIMING_UHS_DDR50) || |
1561 | (ios->timing == MMC_TIMING_MMC_DDR52)) | |
6322cdd0 PR |
1562 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; |
1563 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
1564 | } | |
49c468fc | 1565 | |
52983382 KL |
1566 | if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && |
1567 | ((ios->timing == MMC_TIMING_UHS_SDR12) || | |
1568 | (ios->timing == MMC_TIMING_UHS_SDR25) || | |
1569 | (ios->timing == MMC_TIMING_UHS_SDR50) || | |
1570 | (ios->timing == MMC_TIMING_UHS_SDR104) || | |
1571 | (ios->timing == MMC_TIMING_UHS_DDR50))) { | |
1572 | u16 preset; | |
1573 | ||
1574 | sdhci_enable_preset_value(host, true); | |
1575 | preset = sdhci_get_preset_value(host); | |
1576 | ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) | |
1577 | >> SDHCI_PRESET_DRV_SHIFT; | |
1578 | } | |
1579 | ||
49c468fc | 1580 | /* Re-enable SD Clock */ |
8213af3b | 1581 | sdhci_update_clock(host); |
758535c4 AN |
1582 | } else |
1583 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
d6d50a15 | 1584 | |
b8352260 LD |
1585 | /* |
1586 | * Some (ENE) controllers go apeshit on some ios operation, | |
1587 | * signalling timeout and CRC errors even on CMD0. Resetting | |
1588 | * it on each ios seems to solve the problem. | |
1589 | */ | |
b8c86fc5 | 1590 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
b8352260 LD |
1591 | sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
1592 | ||
5f25a66f | 1593 | mmiowb(); |
d129bceb PO |
1594 | spin_unlock_irqrestore(&host->lock, flags); |
1595 | } | |
1596 | ||
66fd8ad5 AH |
1597 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
1598 | { | |
1599 | struct sdhci_host *host = mmc_priv(mmc); | |
1600 | ||
1601 | sdhci_runtime_pm_get(host); | |
1602 | sdhci_do_set_ios(host, ios); | |
1603 | sdhci_runtime_pm_put(host); | |
1604 | } | |
1605 | ||
94144a46 KL |
1606 | static int sdhci_do_get_cd(struct sdhci_host *host) |
1607 | { | |
1608 | int gpio_cd = mmc_gpio_get_cd(host->mmc); | |
1609 | ||
1610 | if (host->flags & SDHCI_DEVICE_DEAD) | |
1611 | return 0; | |
1612 | ||
1613 | /* If polling/nonremovable, assume that the card is always present. */ | |
1614 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || | |
1615 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) | |
1616 | return 1; | |
1617 | ||
1618 | /* Try slot gpio detect */ | |
1619 | if (!IS_ERR_VALUE(gpio_cd)) | |
1620 | return !!gpio_cd; | |
1621 | ||
1622 | /* Host native card detect */ | |
1623 | return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); | |
1624 | } | |
1625 | ||
1626 | static int sdhci_get_cd(struct mmc_host *mmc) | |
1627 | { | |
1628 | struct sdhci_host *host = mmc_priv(mmc); | |
1629 | int ret; | |
1630 | ||
1631 | sdhci_runtime_pm_get(host); | |
1632 | ret = sdhci_do_get_cd(host); | |
1633 | sdhci_runtime_pm_put(host); | |
1634 | return ret; | |
1635 | } | |
1636 | ||
66fd8ad5 | 1637 | static int sdhci_check_ro(struct sdhci_host *host) |
d129bceb | 1638 | { |
d129bceb | 1639 | unsigned long flags; |
2dfb579c | 1640 | int is_readonly; |
d129bceb | 1641 | |
d129bceb PO |
1642 | spin_lock_irqsave(&host->lock, flags); |
1643 | ||
1e72859e | 1644 | if (host->flags & SDHCI_DEVICE_DEAD) |
2dfb579c WS |
1645 | is_readonly = 0; |
1646 | else if (host->ops->get_ro) | |
1647 | is_readonly = host->ops->get_ro(host); | |
1e72859e | 1648 | else |
2dfb579c WS |
1649 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
1650 | & SDHCI_WRITE_PROTECT); | |
d129bceb PO |
1651 | |
1652 | spin_unlock_irqrestore(&host->lock, flags); | |
1653 | ||
2dfb579c WS |
1654 | /* This quirk needs to be replaced by a callback-function later */ |
1655 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? | |
1656 | !is_readonly : is_readonly; | |
d129bceb PO |
1657 | } |
1658 | ||
82b0e23a TI |
1659 | #define SAMPLE_COUNT 5 |
1660 | ||
66fd8ad5 | 1661 | static int sdhci_do_get_ro(struct sdhci_host *host) |
82b0e23a | 1662 | { |
82b0e23a TI |
1663 | int i, ro_count; |
1664 | ||
82b0e23a | 1665 | if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) |
66fd8ad5 | 1666 | return sdhci_check_ro(host); |
82b0e23a TI |
1667 | |
1668 | ro_count = 0; | |
1669 | for (i = 0; i < SAMPLE_COUNT; i++) { | |
66fd8ad5 | 1670 | if (sdhci_check_ro(host)) { |
82b0e23a TI |
1671 | if (++ro_count > SAMPLE_COUNT / 2) |
1672 | return 1; | |
1673 | } | |
1674 | msleep(30); | |
1675 | } | |
1676 | return 0; | |
1677 | } | |
1678 | ||
20758b66 AH |
1679 | static void sdhci_hw_reset(struct mmc_host *mmc) |
1680 | { | |
1681 | struct sdhci_host *host = mmc_priv(mmc); | |
1682 | ||
1683 | if (host->ops && host->ops->hw_reset) | |
1684 | host->ops->hw_reset(host); | |
1685 | } | |
1686 | ||
66fd8ad5 | 1687 | static int sdhci_get_ro(struct mmc_host *mmc) |
f75979b7 | 1688 | { |
66fd8ad5 AH |
1689 | struct sdhci_host *host = mmc_priv(mmc); |
1690 | int ret; | |
f75979b7 | 1691 | |
66fd8ad5 AH |
1692 | sdhci_runtime_pm_get(host); |
1693 | ret = sdhci_do_get_ro(host); | |
1694 | sdhci_runtime_pm_put(host); | |
1695 | return ret; | |
1696 | } | |
f75979b7 | 1697 | |
66fd8ad5 AH |
1698 | static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) |
1699 | { | |
be138554 | 1700 | if (!(host->flags & SDHCI_DEVICE_DEAD)) { |
ef104333 | 1701 | if (enable) |
b537f94c | 1702 | host->ier |= SDHCI_INT_CARD_INT; |
ef104333 | 1703 | else |
b537f94c RK |
1704 | host->ier &= ~SDHCI_INT_CARD_INT; |
1705 | ||
1706 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
1707 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
ef104333 RK |
1708 | mmiowb(); |
1709 | } | |
66fd8ad5 AH |
1710 | } |
1711 | ||
1712 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) | |
1713 | { | |
1714 | struct sdhci_host *host = mmc_priv(mmc); | |
1715 | unsigned long flags; | |
f75979b7 | 1716 | |
ef104333 RK |
1717 | sdhci_runtime_pm_get(host); |
1718 | ||
66fd8ad5 | 1719 | spin_lock_irqsave(&host->lock, flags); |
ef104333 RK |
1720 | if (enable) |
1721 | host->flags |= SDHCI_SDIO_IRQ_ENABLED; | |
1722 | else | |
1723 | host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; | |
1724 | ||
66fd8ad5 | 1725 | sdhci_enable_sdio_irq_nolock(host, enable); |
f75979b7 | 1726 | spin_unlock_irqrestore(&host->lock, flags); |
ef104333 RK |
1727 | |
1728 | sdhci_runtime_pm_put(host); | |
f75979b7 PO |
1729 | } |
1730 | ||
20b92a30 | 1731 | static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, |
21f5998f | 1732 | struct mmc_ios *ios) |
f2119df6 | 1733 | { |
20b92a30 | 1734 | u16 ctrl; |
6231f3de | 1735 | int ret; |
f2119df6 | 1736 | |
20b92a30 KL |
1737 | /* |
1738 | * Signal Voltage Switching is only applicable for Host Controllers | |
1739 | * v3.00 and above. | |
1740 | */ | |
1741 | if (host->version < SDHCI_SPEC_300) | |
1742 | return 0; | |
6231f3de | 1743 | |
f2119df6 | 1744 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
f2119df6 | 1745 | |
21f5998f | 1746 | switch (ios->signal_voltage) { |
20b92a30 KL |
1747 | case MMC_SIGNAL_VOLTAGE_330: |
1748 | /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ | |
1749 | ctrl &= ~SDHCI_CTRL_VDD_180; | |
1750 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
f2119df6 | 1751 | |
20b92a30 KL |
1752 | if (host->vqmmc) { |
1753 | ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000); | |
1754 | if (ret) { | |
1755 | pr_warning("%s: Switching to 3.3V signalling voltage " | |
1756 | " failed\n", mmc_hostname(host->mmc)); | |
1757 | return -EIO; | |
1758 | } | |
1759 | } | |
1760 | /* Wait for 5ms */ | |
1761 | usleep_range(5000, 5500); | |
f2119df6 | 1762 | |
20b92a30 KL |
1763 | /* 3.3V regulator output should be stable within 5 ms */ |
1764 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1765 | if (!(ctrl & SDHCI_CTRL_VDD_180)) | |
1766 | return 0; | |
6231f3de | 1767 | |
20b92a30 KL |
1768 | pr_warning("%s: 3.3V regulator output did not became stable\n", |
1769 | mmc_hostname(host->mmc)); | |
1770 | ||
1771 | return -EAGAIN; | |
1772 | case MMC_SIGNAL_VOLTAGE_180: | |
1773 | if (host->vqmmc) { | |
1774 | ret = regulator_set_voltage(host->vqmmc, | |
1775 | 1700000, 1950000); | |
1776 | if (ret) { | |
1777 | pr_warning("%s: Switching to 1.8V signalling voltage " | |
1778 | " failed\n", mmc_hostname(host->mmc)); | |
1779 | return -EIO; | |
1780 | } | |
1781 | } | |
6231f3de | 1782 | |
6231f3de PR |
1783 | /* |
1784 | * Enable 1.8V Signal Enable in the Host Control2 | |
1785 | * register | |
1786 | */ | |
20b92a30 KL |
1787 | ctrl |= SDHCI_CTRL_VDD_180; |
1788 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
6231f3de | 1789 | |
20b92a30 KL |
1790 | /* Wait for 5ms */ |
1791 | usleep_range(5000, 5500); | |
f2119df6 | 1792 | |
20b92a30 KL |
1793 | /* 1.8V regulator output should be stable within 5 ms */ |
1794 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1795 | if (ctrl & SDHCI_CTRL_VDD_180) | |
1796 | return 0; | |
f2119df6 | 1797 | |
20b92a30 KL |
1798 | pr_warning("%s: 1.8V regulator output did not became stable\n", |
1799 | mmc_hostname(host->mmc)); | |
f2119df6 | 1800 | |
20b92a30 KL |
1801 | return -EAGAIN; |
1802 | case MMC_SIGNAL_VOLTAGE_120: | |
1803 | if (host->vqmmc) { | |
1804 | ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000); | |
1805 | if (ret) { | |
1806 | pr_warning("%s: Switching to 1.2V signalling voltage " | |
1807 | " failed\n", mmc_hostname(host->mmc)); | |
1808 | return -EIO; | |
f2119df6 AN |
1809 | } |
1810 | } | |
6231f3de | 1811 | return 0; |
20b92a30 | 1812 | default: |
f2119df6 AN |
1813 | /* No signal voltage switch required */ |
1814 | return 0; | |
20b92a30 | 1815 | } |
f2119df6 AN |
1816 | } |
1817 | ||
66fd8ad5 | 1818 | static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
21f5998f | 1819 | struct mmc_ios *ios) |
66fd8ad5 AH |
1820 | { |
1821 | struct sdhci_host *host = mmc_priv(mmc); | |
1822 | int err; | |
1823 | ||
1824 | if (host->version < SDHCI_SPEC_300) | |
1825 | return 0; | |
1826 | sdhci_runtime_pm_get(host); | |
21f5998f | 1827 | err = sdhci_do_start_signal_voltage_switch(host, ios); |
66fd8ad5 AH |
1828 | sdhci_runtime_pm_put(host); |
1829 | return err; | |
1830 | } | |
1831 | ||
20b92a30 KL |
1832 | static int sdhci_card_busy(struct mmc_host *mmc) |
1833 | { | |
1834 | struct sdhci_host *host = mmc_priv(mmc); | |
1835 | u32 present_state; | |
1836 | ||
1837 | sdhci_runtime_pm_get(host); | |
1838 | /* Check whether DAT[3:0] is 0000 */ | |
1839 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); | |
1840 | sdhci_runtime_pm_put(host); | |
1841 | ||
1842 | return !(present_state & SDHCI_DATA_LVL_MASK); | |
1843 | } | |
1844 | ||
069c9f14 | 1845 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) |
b513ea25 AN |
1846 | { |
1847 | struct sdhci_host *host; | |
1848 | u16 ctrl; | |
b513ea25 AN |
1849 | int tuning_loop_counter = MAX_TUNING_LOOP; |
1850 | unsigned long timeout; | |
1851 | int err = 0; | |
069c9f14 | 1852 | bool requires_tuning_nonuhs = false; |
2b35bd83 | 1853 | unsigned long flags; |
b513ea25 AN |
1854 | |
1855 | host = mmc_priv(mmc); | |
1856 | ||
66fd8ad5 | 1857 | sdhci_runtime_pm_get(host); |
2b35bd83 | 1858 | spin_lock_irqsave(&host->lock, flags); |
b513ea25 AN |
1859 | |
1860 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1861 | ||
1862 | /* | |
069c9f14 G |
1863 | * The Host Controller needs tuning only in case of SDR104 mode |
1864 | * and for SDR50 mode when Use Tuning for SDR50 is set in the | |
b513ea25 | 1865 | * Capabilities register. |
069c9f14 G |
1866 | * If the Host Controller supports the HS200 mode then the |
1867 | * tuning function has to be executed. | |
b513ea25 | 1868 | */ |
069c9f14 G |
1869 | if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) && |
1870 | (host->flags & SDHCI_SDR50_NEEDS_TUNING || | |
156e14b1 | 1871 | host->flags & SDHCI_SDR104_NEEDS_TUNING)) |
069c9f14 G |
1872 | requires_tuning_nonuhs = true; |
1873 | ||
b513ea25 | 1874 | if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) || |
069c9f14 | 1875 | requires_tuning_nonuhs) |
b513ea25 AN |
1876 | ctrl |= SDHCI_CTRL_EXEC_TUNING; |
1877 | else { | |
2b35bd83 | 1878 | spin_unlock_irqrestore(&host->lock, flags); |
66fd8ad5 | 1879 | sdhci_runtime_pm_put(host); |
b513ea25 AN |
1880 | return 0; |
1881 | } | |
1882 | ||
45251812 | 1883 | if (host->ops->platform_execute_tuning) { |
2b35bd83 | 1884 | spin_unlock_irqrestore(&host->lock, flags); |
45251812 DA |
1885 | err = host->ops->platform_execute_tuning(host, opcode); |
1886 | sdhci_runtime_pm_put(host); | |
1887 | return err; | |
1888 | } | |
1889 | ||
b513ea25 AN |
1890 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
1891 | ||
1892 | /* | |
1893 | * As per the Host Controller spec v3.00, tuning command | |
1894 | * generates Buffer Read Ready interrupt, so enable that. | |
1895 | * | |
1896 | * Note: The spec clearly says that when tuning sequence | |
1897 | * is being performed, the controller does not generate | |
1898 | * interrupts other than Buffer Read Ready interrupt. But | |
1899 | * to make sure we don't hit a controller bug, we _only_ | |
1900 | * enable Buffer Read Ready interrupt here. | |
1901 | */ | |
b537f94c RK |
1902 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); |
1903 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); | |
b513ea25 AN |
1904 | |
1905 | /* | |
1906 | * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number | |
1907 | * of loops reaches 40 times or a timeout of 150ms occurs. | |
1908 | */ | |
1909 | timeout = 150; | |
1910 | do { | |
1911 | struct mmc_command cmd = {0}; | |
66fd8ad5 | 1912 | struct mmc_request mrq = {NULL}; |
b513ea25 AN |
1913 | |
1914 | if (!tuning_loop_counter && !timeout) | |
1915 | break; | |
1916 | ||
069c9f14 | 1917 | cmd.opcode = opcode; |
b513ea25 AN |
1918 | cmd.arg = 0; |
1919 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; | |
1920 | cmd.retries = 0; | |
1921 | cmd.data = NULL; | |
1922 | cmd.error = 0; | |
1923 | ||
1924 | mrq.cmd = &cmd; | |
1925 | host->mrq = &mrq; | |
1926 | ||
1927 | /* | |
1928 | * In response to CMD19, the card sends 64 bytes of tuning | |
1929 | * block to the Host Controller. So we set the block size | |
1930 | * to 64 here. | |
1931 | */ | |
069c9f14 G |
1932 | if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { |
1933 | if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
1934 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), | |
1935 | SDHCI_BLOCK_SIZE); | |
1936 | else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) | |
1937 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), | |
1938 | SDHCI_BLOCK_SIZE); | |
1939 | } else { | |
1940 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), | |
1941 | SDHCI_BLOCK_SIZE); | |
1942 | } | |
b513ea25 AN |
1943 | |
1944 | /* | |
1945 | * The tuning block is sent by the card to the host controller. | |
1946 | * So we set the TRNS_READ bit in the Transfer Mode register. | |
1947 | * This also takes care of setting DMA Enable and Multi Block | |
1948 | * Select in the same register to 0. | |
1949 | */ | |
1950 | sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); | |
1951 | ||
1952 | sdhci_send_command(host, &cmd); | |
1953 | ||
1954 | host->cmd = NULL; | |
1955 | host->mrq = NULL; | |
1956 | ||
2b35bd83 | 1957 | spin_unlock_irqrestore(&host->lock, flags); |
b513ea25 AN |
1958 | /* Wait for Buffer Read Ready interrupt */ |
1959 | wait_event_interruptible_timeout(host->buf_ready_int, | |
1960 | (host->tuning_done == 1), | |
1961 | msecs_to_jiffies(50)); | |
2b35bd83 | 1962 | spin_lock_irqsave(&host->lock, flags); |
b513ea25 AN |
1963 | |
1964 | if (!host->tuning_done) { | |
a3c76eb9 | 1965 | pr_info(DRIVER_NAME ": Timeout waiting for " |
b513ea25 AN |
1966 | "Buffer Read Ready interrupt during tuning " |
1967 | "procedure, falling back to fixed sampling " | |
1968 | "clock\n"); | |
1969 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1970 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; | |
1971 | ctrl &= ~SDHCI_CTRL_EXEC_TUNING; | |
1972 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
1973 | ||
1974 | err = -EIO; | |
1975 | goto out; | |
1976 | } | |
1977 | ||
1978 | host->tuning_done = 0; | |
1979 | ||
1980 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1981 | tuning_loop_counter--; | |
1982 | timeout--; | |
197160d5 NS |
1983 | |
1984 | /* eMMC spec does not require a delay between tuning cycles */ | |
1985 | if (opcode == MMC_SEND_TUNING_BLOCK) | |
1986 | mdelay(1); | |
b513ea25 AN |
1987 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); |
1988 | ||
1989 | /* | |
1990 | * The Host Driver has exhausted the maximum number of loops allowed, | |
1991 | * so use fixed sampling frequency. | |
1992 | */ | |
1993 | if (!tuning_loop_counter || !timeout) { | |
1994 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; | |
1995 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
114f2bf6 | 1996 | err = -EIO; |
b513ea25 AN |
1997 | } else { |
1998 | if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { | |
a3c76eb9 | 1999 | pr_info(DRIVER_NAME ": Tuning procedure" |
b513ea25 AN |
2000 | " failed, falling back to fixed sampling" |
2001 | " clock\n"); | |
2002 | err = -EIO; | |
2003 | } | |
2004 | } | |
2005 | ||
2006 | out: | |
cf2b5eea AN |
2007 | /* |
2008 | * If this is the very first time we are here, we start the retuning | |
2009 | * timer. Since only during the first time, SDHCI_NEEDS_RETUNING | |
2010 | * flag won't be set, we check this condition before actually starting | |
2011 | * the timer. | |
2012 | */ | |
2013 | if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && | |
2014 | (host->tuning_mode == SDHCI_TUNING_MODE_1)) { | |
973905fe | 2015 | host->flags |= SDHCI_USING_RETUNING_TIMER; |
cf2b5eea AN |
2016 | mod_timer(&host->tuning_timer, jiffies + |
2017 | host->tuning_count * HZ); | |
2018 | /* Tuning mode 1 limits the maximum data length to 4MB */ | |
2019 | mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; | |
2bc02485 | 2020 | } else if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
cf2b5eea AN |
2021 | host->flags &= ~SDHCI_NEEDS_RETUNING; |
2022 | /* Reload the new initial value for timer */ | |
2bc02485 AS |
2023 | mod_timer(&host->tuning_timer, jiffies + |
2024 | host->tuning_count * HZ); | |
cf2b5eea AN |
2025 | } |
2026 | ||
2027 | /* | |
2028 | * In case tuning fails, host controllers which support re-tuning can | |
2029 | * try tuning again at a later time, when the re-tuning timer expires. | |
2030 | * So for these controllers, we return 0. Since there might be other | |
2031 | * controllers who do not have this capability, we return error for | |
973905fe AL |
2032 | * them. SDHCI_USING_RETUNING_TIMER means the host is currently using |
2033 | * a retuning timer to do the retuning for the card. | |
cf2b5eea | 2034 | */ |
973905fe | 2035 | if (err && (host->flags & SDHCI_USING_RETUNING_TIMER)) |
cf2b5eea AN |
2036 | err = 0; |
2037 | ||
b537f94c RK |
2038 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
2039 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
2b35bd83 | 2040 | spin_unlock_irqrestore(&host->lock, flags); |
66fd8ad5 | 2041 | sdhci_runtime_pm_put(host); |
b513ea25 AN |
2042 | |
2043 | return err; | |
2044 | } | |
2045 | ||
52983382 KL |
2046 | |
2047 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) | |
4d55c5a1 | 2048 | { |
4d55c5a1 | 2049 | u16 ctrl; |
4d55c5a1 | 2050 | |
4d55c5a1 AN |
2051 | /* Host Controller v3.00 defines preset value registers */ |
2052 | if (host->version < SDHCI_SPEC_300) | |
2053 | return; | |
2054 | ||
4d55c5a1 AN |
2055 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
2056 | ||
2057 | /* | |
2058 | * We only enable or disable Preset Value if they are not already | |
2059 | * enabled or disabled respectively. Otherwise, we bail out. | |
2060 | */ | |
2061 | if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { | |
2062 | ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; | |
2063 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
66fd8ad5 | 2064 | host->flags |= SDHCI_PV_ENABLED; |
4d55c5a1 AN |
2065 | } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { |
2066 | ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; | |
2067 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); | |
66fd8ad5 | 2068 | host->flags &= ~SDHCI_PV_ENABLED; |
4d55c5a1 | 2069 | } |
66fd8ad5 AH |
2070 | } |
2071 | ||
71e69211 | 2072 | static void sdhci_card_event(struct mmc_host *mmc) |
d129bceb | 2073 | { |
71e69211 | 2074 | struct sdhci_host *host = mmc_priv(mmc); |
d129bceb PO |
2075 | unsigned long flags; |
2076 | ||
722e1280 CD |
2077 | /* First check if client has provided their own card event */ |
2078 | if (host->ops->card_event) | |
2079 | host->ops->card_event(host); | |
2080 | ||
d129bceb PO |
2081 | spin_lock_irqsave(&host->lock, flags); |
2082 | ||
66fd8ad5 | 2083 | /* Check host->mrq first in case we are runtime suspended */ |
9668d765 | 2084 | if (host->mrq && !sdhci_do_get_cd(host)) { |
a3c76eb9 | 2085 | pr_err("%s: Card removed during transfer!\n", |
66fd8ad5 | 2086 | mmc_hostname(host->mmc)); |
a3c76eb9 | 2087 | pr_err("%s: Resetting controller.\n", |
66fd8ad5 | 2088 | mmc_hostname(host->mmc)); |
d129bceb | 2089 | |
66fd8ad5 AH |
2090 | sdhci_reset(host, SDHCI_RESET_CMD); |
2091 | sdhci_reset(host, SDHCI_RESET_DATA); | |
d129bceb | 2092 | |
66fd8ad5 AH |
2093 | host->mrq->cmd->error = -ENOMEDIUM; |
2094 | tasklet_schedule(&host->finish_tasklet); | |
d129bceb PO |
2095 | } |
2096 | ||
2097 | spin_unlock_irqrestore(&host->lock, flags); | |
71e69211 GL |
2098 | } |
2099 | ||
2100 | static const struct mmc_host_ops sdhci_ops = { | |
2101 | .request = sdhci_request, | |
2102 | .set_ios = sdhci_set_ios, | |
94144a46 | 2103 | .get_cd = sdhci_get_cd, |
71e69211 GL |
2104 | .get_ro = sdhci_get_ro, |
2105 | .hw_reset = sdhci_hw_reset, | |
2106 | .enable_sdio_irq = sdhci_enable_sdio_irq, | |
2107 | .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, | |
2108 | .execute_tuning = sdhci_execute_tuning, | |
71e69211 | 2109 | .card_event = sdhci_card_event, |
20b92a30 | 2110 | .card_busy = sdhci_card_busy, |
71e69211 GL |
2111 | }; |
2112 | ||
2113 | /*****************************************************************************\ | |
2114 | * * | |
2115 | * Tasklets * | |
2116 | * * | |
2117 | \*****************************************************************************/ | |
2118 | ||
d129bceb PO |
2119 | static void sdhci_tasklet_finish(unsigned long param) |
2120 | { | |
2121 | struct sdhci_host *host; | |
2122 | unsigned long flags; | |
2123 | struct mmc_request *mrq; | |
2124 | ||
2125 | host = (struct sdhci_host*)param; | |
2126 | ||
66fd8ad5 AH |
2127 | spin_lock_irqsave(&host->lock, flags); |
2128 | ||
0c9c99a7 CB |
2129 | /* |
2130 | * If this tasklet gets rescheduled while running, it will | |
2131 | * be run again afterwards but without any active request. | |
2132 | */ | |
66fd8ad5 AH |
2133 | if (!host->mrq) { |
2134 | spin_unlock_irqrestore(&host->lock, flags); | |
0c9c99a7 | 2135 | return; |
66fd8ad5 | 2136 | } |
d129bceb PO |
2137 | |
2138 | del_timer(&host->timer); | |
2139 | ||
2140 | mrq = host->mrq; | |
2141 | ||
d129bceb PO |
2142 | /* |
2143 | * The controller needs a reset of internal state machines | |
2144 | * upon error conditions. | |
2145 | */ | |
1e72859e | 2146 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
b7b4d342 | 2147 | ((mrq->cmd && mrq->cmd->error) || |
1e72859e PO |
2148 | (mrq->data && (mrq->data->error || |
2149 | (mrq->data->stop && mrq->data->stop->error))) || | |
2150 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { | |
645289dc PO |
2151 | |
2152 | /* Some controllers need this kick or reset won't work here */ | |
8213af3b | 2153 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) |
645289dc | 2154 | /* This is to force an update */ |
8213af3b | 2155 | sdhci_update_clock(host); |
645289dc PO |
2156 | |
2157 | /* Spec says we should do both at the same time, but Ricoh | |
2158 | controllers do not like that. */ | |
d129bceb PO |
2159 | sdhci_reset(host, SDHCI_RESET_CMD); |
2160 | sdhci_reset(host, SDHCI_RESET_DATA); | |
2161 | } | |
2162 | ||
2163 | host->mrq = NULL; | |
2164 | host->cmd = NULL; | |
2165 | host->data = NULL; | |
2166 | ||
f9134319 | 2167 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 2168 | sdhci_deactivate_led(host); |
2f730fec | 2169 | #endif |
d129bceb | 2170 | |
5f25a66f | 2171 | mmiowb(); |
d129bceb PO |
2172 | spin_unlock_irqrestore(&host->lock, flags); |
2173 | ||
2174 | mmc_request_done(host->mmc, mrq); | |
66fd8ad5 | 2175 | sdhci_runtime_pm_put(host); |
d129bceb PO |
2176 | } |
2177 | ||
2178 | static void sdhci_timeout_timer(unsigned long data) | |
2179 | { | |
2180 | struct sdhci_host *host; | |
2181 | unsigned long flags; | |
2182 | ||
2183 | host = (struct sdhci_host*)data; | |
2184 | ||
2185 | spin_lock_irqsave(&host->lock, flags); | |
2186 | ||
2187 | if (host->mrq) { | |
a3c76eb9 | 2188 | pr_err("%s: Timeout waiting for hardware " |
acf1da45 | 2189 | "interrupt.\n", mmc_hostname(host->mmc)); |
d129bceb PO |
2190 | sdhci_dumpregs(host); |
2191 | ||
2192 | if (host->data) { | |
17b0429d | 2193 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
2194 | sdhci_finish_data(host); |
2195 | } else { | |
2196 | if (host->cmd) | |
17b0429d | 2197 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 2198 | else |
17b0429d | 2199 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
2200 | |
2201 | tasklet_schedule(&host->finish_tasklet); | |
2202 | } | |
2203 | } | |
2204 | ||
5f25a66f | 2205 | mmiowb(); |
d129bceb PO |
2206 | spin_unlock_irqrestore(&host->lock, flags); |
2207 | } | |
2208 | ||
cf2b5eea AN |
2209 | static void sdhci_tuning_timer(unsigned long data) |
2210 | { | |
2211 | struct sdhci_host *host; | |
2212 | unsigned long flags; | |
2213 | ||
2214 | host = (struct sdhci_host *)data; | |
2215 | ||
2216 | spin_lock_irqsave(&host->lock, flags); | |
2217 | ||
2218 | host->flags |= SDHCI_NEEDS_RETUNING; | |
2219 | ||
2220 | spin_unlock_irqrestore(&host->lock, flags); | |
2221 | } | |
2222 | ||
d129bceb PO |
2223 | /*****************************************************************************\ |
2224 | * * | |
2225 | * Interrupt handling * | |
2226 | * * | |
2227 | \*****************************************************************************/ | |
2228 | ||
2229 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
2230 | { | |
2231 | BUG_ON(intmask == 0); | |
2232 | ||
2233 | if (!host->cmd) { | |
a3c76eb9 | 2234 | pr_err("%s: Got command interrupt 0x%08x even " |
b67ac3f3 PO |
2235 | "though no command operation was in progress.\n", |
2236 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
2237 | sdhci_dumpregs(host); |
2238 | return; | |
2239 | } | |
2240 | ||
43b58b36 | 2241 | if (intmask & SDHCI_INT_TIMEOUT) |
17b0429d PO |
2242 | host->cmd->error = -ETIMEDOUT; |
2243 | else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | | |
2244 | SDHCI_INT_INDEX)) | |
2245 | host->cmd->error = -EILSEQ; | |
43b58b36 | 2246 | |
e809517f | 2247 | if (host->cmd->error) { |
d129bceb | 2248 | tasklet_schedule(&host->finish_tasklet); |
e809517f PO |
2249 | return; |
2250 | } | |
2251 | ||
2252 | /* | |
2253 | * The host can send and interrupt when the busy state has | |
2254 | * ended, allowing us to wait without wasting CPU cycles. | |
2255 | * Unfortunately this is overloaded on the "data complete" | |
2256 | * interrupt, so we need to take some care when handling | |
2257 | * it. | |
2258 | * | |
2259 | * Note: The 1.0 specification is a bit ambiguous about this | |
2260 | * feature so there might be some problems with older | |
2261 | * controllers. | |
2262 | */ | |
2263 | if (host->cmd->flags & MMC_RSP_BUSY) { | |
2264 | if (host->cmd->data) | |
2265 | DBG("Cannot wait for busy signal when also " | |
2266 | "doing a data transfer"); | |
f945405c | 2267 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) |
e809517f | 2268 | return; |
f945405c BD |
2269 | |
2270 | /* The controller does not support the end-of-busy IRQ, | |
2271 | * fall through and take the SDHCI_INT_RESPONSE */ | |
e809517f PO |
2272 | } |
2273 | ||
2274 | if (intmask & SDHCI_INT_RESPONSE) | |
43b58b36 | 2275 | sdhci_finish_command(host); |
d129bceb PO |
2276 | } |
2277 | ||
0957c333 | 2278 | #ifdef CONFIG_MMC_DEBUG |
6882a8c0 BD |
2279 | static void sdhci_show_adma_error(struct sdhci_host *host) |
2280 | { | |
2281 | const char *name = mmc_hostname(host->mmc); | |
2282 | u8 *desc = host->adma_desc; | |
2283 | __le32 *dma; | |
2284 | __le16 *len; | |
2285 | u8 attr; | |
2286 | ||
2287 | sdhci_dumpregs(host); | |
2288 | ||
2289 | while (true) { | |
2290 | dma = (__le32 *)(desc + 4); | |
2291 | len = (__le16 *)(desc + 2); | |
2292 | attr = *desc; | |
2293 | ||
2294 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
2295 | name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); | |
2296 | ||
2297 | desc += 8; | |
2298 | ||
2299 | if (attr & 2) | |
2300 | break; | |
2301 | } | |
2302 | } | |
2303 | #else | |
2304 | static void sdhci_show_adma_error(struct sdhci_host *host) { } | |
2305 | #endif | |
2306 | ||
d129bceb PO |
2307 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
2308 | { | |
069c9f14 | 2309 | u32 command; |
d129bceb PO |
2310 | BUG_ON(intmask == 0); |
2311 | ||
b513ea25 AN |
2312 | /* CMD19 generates _only_ Buffer Read Ready interrupt */ |
2313 | if (intmask & SDHCI_INT_DATA_AVAIL) { | |
069c9f14 G |
2314 | command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); |
2315 | if (command == MMC_SEND_TUNING_BLOCK || | |
2316 | command == MMC_SEND_TUNING_BLOCK_HS200) { | |
b513ea25 AN |
2317 | host->tuning_done = 1; |
2318 | wake_up(&host->buf_ready_int); | |
2319 | return; | |
2320 | } | |
2321 | } | |
2322 | ||
d129bceb PO |
2323 | if (!host->data) { |
2324 | /* | |
e809517f PO |
2325 | * The "data complete" interrupt is also used to |
2326 | * indicate that a busy state has ended. See comment | |
2327 | * above in sdhci_cmd_irq(). | |
d129bceb | 2328 | */ |
e809517f PO |
2329 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
2330 | if (intmask & SDHCI_INT_DATA_END) { | |
2331 | sdhci_finish_command(host); | |
2332 | return; | |
2333 | } | |
2334 | } | |
d129bceb | 2335 | |
a3c76eb9 | 2336 | pr_err("%s: Got data interrupt 0x%08x even " |
b67ac3f3 PO |
2337 | "though no data operation was in progress.\n", |
2338 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
2339 | sdhci_dumpregs(host); |
2340 | ||
2341 | return; | |
2342 | } | |
2343 | ||
2344 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d | 2345 | host->data->error = -ETIMEDOUT; |
22113efd AL |
2346 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
2347 | host->data->error = -EILSEQ; | |
2348 | else if ((intmask & SDHCI_INT_DATA_CRC) && | |
2349 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) | |
2350 | != MMC_BUS_TEST_R) | |
17b0429d | 2351 | host->data->error = -EILSEQ; |
6882a8c0 | 2352 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
a3c76eb9 | 2353 | pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); |
6882a8c0 | 2354 | sdhci_show_adma_error(host); |
2134a922 | 2355 | host->data->error = -EIO; |
a4071fbb HZ |
2356 | if (host->ops->adma_workaround) |
2357 | host->ops->adma_workaround(host, intmask); | |
6882a8c0 | 2358 | } |
d129bceb | 2359 | |
17b0429d | 2360 | if (host->data->error) |
d129bceb PO |
2361 | sdhci_finish_data(host); |
2362 | else { | |
a406f5a3 | 2363 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
2364 | sdhci_transfer_pio(host); |
2365 | ||
6ba736a1 PO |
2366 | /* |
2367 | * We currently don't do anything fancy with DMA | |
2368 | * boundaries, but as we can't disable the feature | |
2369 | * we need to at least restart the transfer. | |
f6a03cbf MV |
2370 | * |
2371 | * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) | |
2372 | * should return a valid address to continue from, but as | |
2373 | * some controllers are faulty, don't trust them. | |
6ba736a1 | 2374 | */ |
f6a03cbf MV |
2375 | if (intmask & SDHCI_INT_DMA_END) { |
2376 | u32 dmastart, dmanow; | |
2377 | dmastart = sg_dma_address(host->data->sg); | |
2378 | dmanow = dmastart + host->data->bytes_xfered; | |
2379 | /* | |
2380 | * Force update to the next DMA block boundary. | |
2381 | */ | |
2382 | dmanow = (dmanow & | |
2383 | ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + | |
2384 | SDHCI_DEFAULT_BOUNDARY_SIZE; | |
2385 | host->data->bytes_xfered = dmanow - dmastart; | |
2386 | DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," | |
2387 | " next 0x%08x\n", | |
2388 | mmc_hostname(host->mmc), dmastart, | |
2389 | host->data->bytes_xfered, dmanow); | |
2390 | sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); | |
2391 | } | |
6ba736a1 | 2392 | |
e538fbe8 PO |
2393 | if (intmask & SDHCI_INT_DATA_END) { |
2394 | if (host->cmd) { | |
2395 | /* | |
2396 | * Data managed to finish before the | |
2397 | * command completed. Make sure we do | |
2398 | * things in the proper order. | |
2399 | */ | |
2400 | host->data_early = 1; | |
2401 | } else { | |
2402 | sdhci_finish_data(host); | |
2403 | } | |
2404 | } | |
d129bceb PO |
2405 | } |
2406 | } | |
2407 | ||
7d12e780 | 2408 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb | 2409 | { |
781e989c | 2410 | irqreturn_t result = IRQ_NONE; |
66fd8ad5 | 2411 | struct sdhci_host *host = dev_id; |
41005003 | 2412 | u32 intmask, mask, unexpected = 0; |
781e989c | 2413 | int max_loops = 16; |
d129bceb PO |
2414 | |
2415 | spin_lock(&host->lock); | |
2416 | ||
be138554 | 2417 | if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { |
66fd8ad5 | 2418 | spin_unlock(&host->lock); |
655bca76 | 2419 | return IRQ_NONE; |
66fd8ad5 AH |
2420 | } |
2421 | ||
4e4141a5 | 2422 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
62df67a5 | 2423 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
2424 | result = IRQ_NONE; |
2425 | goto out; | |
2426 | } | |
2427 | ||
41005003 RK |
2428 | do { |
2429 | /* Clear selected interrupts. */ | |
2430 | mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | | |
2431 | SDHCI_INT_BUS_POWER); | |
2432 | sdhci_writel(host, mask, SDHCI_INT_STATUS); | |
d129bceb | 2433 | |
41005003 RK |
2434 | DBG("*** %s got interrupt: 0x%08x\n", |
2435 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 2436 | |
41005003 RK |
2437 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
2438 | u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
2439 | SDHCI_CARD_PRESENT; | |
d129bceb | 2440 | |
41005003 RK |
2441 | /* |
2442 | * There is a observation on i.mx esdhc. INSERT | |
2443 | * bit will be immediately set again when it gets | |
2444 | * cleared, if a card is inserted. We have to mask | |
2445 | * the irq to prevent interrupt storm which will | |
2446 | * freeze the system. And the REMOVE gets the | |
2447 | * same situation. | |
2448 | * | |
2449 | * More testing are needed here to ensure it works | |
2450 | * for other platforms though. | |
2451 | */ | |
b537f94c RK |
2452 | host->ier &= ~(SDHCI_INT_CARD_INSERT | |
2453 | SDHCI_INT_CARD_REMOVE); | |
2454 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : | |
2455 | SDHCI_INT_CARD_INSERT; | |
2456 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
2457 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
41005003 RK |
2458 | |
2459 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | | |
2460 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); | |
3560db8e RK |
2461 | |
2462 | host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | | |
2463 | SDHCI_INT_CARD_REMOVE); | |
2464 | result = IRQ_WAKE_THREAD; | |
41005003 | 2465 | } |
d129bceb | 2466 | |
41005003 RK |
2467 | if (intmask & SDHCI_INT_CMD_MASK) |
2468 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); | |
964f9ce2 | 2469 | |
41005003 RK |
2470 | if (intmask & SDHCI_INT_DATA_MASK) |
2471 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); | |
d129bceb | 2472 | |
41005003 RK |
2473 | if (intmask & SDHCI_INT_BUS_POWER) |
2474 | pr_err("%s: Card is consuming too much power!\n", | |
2475 | mmc_hostname(host->mmc)); | |
3192a28f | 2476 | |
781e989c RK |
2477 | if (intmask & SDHCI_INT_CARD_INT) { |
2478 | sdhci_enable_sdio_irq_nolock(host, false); | |
2479 | host->thread_isr |= SDHCI_INT_CARD_INT; | |
2480 | result = IRQ_WAKE_THREAD; | |
2481 | } | |
f75979b7 | 2482 | |
41005003 RK |
2483 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | |
2484 | SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | | |
2485 | SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | | |
2486 | SDHCI_INT_CARD_INT); | |
f75979b7 | 2487 | |
41005003 RK |
2488 | if (intmask) { |
2489 | unexpected |= intmask; | |
2490 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); | |
2491 | } | |
d129bceb | 2492 | |
781e989c RK |
2493 | if (result == IRQ_NONE) |
2494 | result = IRQ_HANDLED; | |
d129bceb | 2495 | |
41005003 | 2496 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
41005003 | 2497 | } while (intmask && --max_loops); |
d129bceb PO |
2498 | out: |
2499 | spin_unlock(&host->lock); | |
2500 | ||
6379b237 AS |
2501 | if (unexpected) { |
2502 | pr_err("%s: Unexpected interrupt 0x%08x.\n", | |
2503 | mmc_hostname(host->mmc), unexpected); | |
2504 | sdhci_dumpregs(host); | |
2505 | } | |
f75979b7 | 2506 | |
d129bceb PO |
2507 | return result; |
2508 | } | |
2509 | ||
781e989c RK |
2510 | static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) |
2511 | { | |
2512 | struct sdhci_host *host = dev_id; | |
2513 | unsigned long flags; | |
2514 | u32 isr; | |
2515 | ||
2516 | spin_lock_irqsave(&host->lock, flags); | |
2517 | isr = host->thread_isr; | |
2518 | host->thread_isr = 0; | |
2519 | spin_unlock_irqrestore(&host->lock, flags); | |
2520 | ||
3560db8e RK |
2521 | if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
2522 | sdhci_card_event(host->mmc); | |
2523 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | |
2524 | } | |
2525 | ||
781e989c RK |
2526 | if (isr & SDHCI_INT_CARD_INT) { |
2527 | sdio_run_irqs(host->mmc); | |
2528 | ||
2529 | spin_lock_irqsave(&host->lock, flags); | |
2530 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) | |
2531 | sdhci_enable_sdio_irq_nolock(host, true); | |
2532 | spin_unlock_irqrestore(&host->lock, flags); | |
2533 | } | |
2534 | ||
2535 | return isr ? IRQ_HANDLED : IRQ_NONE; | |
2536 | } | |
2537 | ||
d129bceb PO |
2538 | /*****************************************************************************\ |
2539 | * * | |
2540 | * Suspend/resume * | |
2541 | * * | |
2542 | \*****************************************************************************/ | |
2543 | ||
2544 | #ifdef CONFIG_PM | |
ad080d79 KL |
2545 | void sdhci_enable_irq_wakeups(struct sdhci_host *host) |
2546 | { | |
2547 | u8 val; | |
2548 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | |
2549 | | SDHCI_WAKE_ON_INT; | |
2550 | ||
2551 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
2552 | val |= mask ; | |
2553 | /* Avoid fake wake up */ | |
2554 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
2555 | val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); | |
2556 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
2557 | } | |
2558 | EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); | |
2559 | ||
2560 | void sdhci_disable_irq_wakeups(struct sdhci_host *host) | |
2561 | { | |
2562 | u8 val; | |
2563 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE | |
2564 | | SDHCI_WAKE_ON_INT; | |
2565 | ||
2566 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
2567 | val &= ~mask; | |
2568 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
2569 | } | |
2570 | EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups); | |
d129bceb | 2571 | |
29495aa0 | 2572 | int sdhci_suspend_host(struct sdhci_host *host) |
d129bceb | 2573 | { |
a1b13b4e CB |
2574 | if (host->ops->platform_suspend) |
2575 | host->ops->platform_suspend(host); | |
2576 | ||
7260cf5e AV |
2577 | sdhci_disable_card_detection(host); |
2578 | ||
cf2b5eea | 2579 | /* Disable tuning since we are suspending */ |
973905fe | 2580 | if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
c6ced0db | 2581 | del_timer_sync(&host->tuning_timer); |
cf2b5eea | 2582 | host->flags &= ~SDHCI_NEEDS_RETUNING; |
cf2b5eea AN |
2583 | } |
2584 | ||
ad080d79 | 2585 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
b537f94c RK |
2586 | host->ier = 0; |
2587 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); | |
2588 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
ad080d79 KL |
2589 | free_irq(host->irq, host); |
2590 | } else { | |
2591 | sdhci_enable_irq_wakeups(host); | |
2592 | enable_irq_wake(host->irq); | |
2593 | } | |
4ee14ec6 | 2594 | return 0; |
d129bceb PO |
2595 | } |
2596 | ||
b8c86fc5 | 2597 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
d129bceb | 2598 | |
b8c86fc5 PO |
2599 | int sdhci_resume_host(struct sdhci_host *host) |
2600 | { | |
4ee14ec6 | 2601 | int ret = 0; |
d129bceb | 2602 | |
a13abc7b | 2603 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
2604 | if (host->ops->enable_dma) |
2605 | host->ops->enable_dma(host); | |
2606 | } | |
d129bceb | 2607 | |
ad080d79 | 2608 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
781e989c RK |
2609 | ret = request_threaded_irq(host->irq, sdhci_irq, |
2610 | sdhci_thread_irq, IRQF_SHARED, | |
2611 | mmc_hostname(host->mmc), host); | |
ad080d79 KL |
2612 | if (ret) |
2613 | return ret; | |
2614 | } else { | |
2615 | sdhci_disable_irq_wakeups(host); | |
2616 | disable_irq_wake(host->irq); | |
2617 | } | |
d129bceb | 2618 | |
6308d290 AH |
2619 | if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && |
2620 | (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { | |
2621 | /* Card keeps power but host controller does not */ | |
2622 | sdhci_init(host, 0); | |
2623 | host->pwr = 0; | |
2624 | host->clock = 0; | |
2625 | sdhci_do_set_ios(host, &host->mmc->ios); | |
2626 | } else { | |
2627 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); | |
2628 | mmiowb(); | |
2629 | } | |
b8c86fc5 | 2630 | |
7260cf5e AV |
2631 | sdhci_enable_card_detection(host); |
2632 | ||
a1b13b4e CB |
2633 | if (host->ops->platform_resume) |
2634 | host->ops->platform_resume(host); | |
2635 | ||
cf2b5eea | 2636 | /* Set the re-tuning expiration flag */ |
973905fe | 2637 | if (host->flags & SDHCI_USING_RETUNING_TIMER) |
cf2b5eea AN |
2638 | host->flags |= SDHCI_NEEDS_RETUNING; |
2639 | ||
2f4cbb3d | 2640 | return ret; |
d129bceb PO |
2641 | } |
2642 | ||
b8c86fc5 | 2643 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
d129bceb PO |
2644 | #endif /* CONFIG_PM */ |
2645 | ||
66fd8ad5 AH |
2646 | #ifdef CONFIG_PM_RUNTIME |
2647 | ||
2648 | static int sdhci_runtime_pm_get(struct sdhci_host *host) | |
2649 | { | |
2650 | return pm_runtime_get_sync(host->mmc->parent); | |
2651 | } | |
2652 | ||
2653 | static int sdhci_runtime_pm_put(struct sdhci_host *host) | |
2654 | { | |
2655 | pm_runtime_mark_last_busy(host->mmc->parent); | |
2656 | return pm_runtime_put_autosuspend(host->mmc->parent); | |
2657 | } | |
2658 | ||
f0710a55 AH |
2659 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
2660 | { | |
2661 | if (host->runtime_suspended || host->bus_on) | |
2662 | return; | |
2663 | host->bus_on = true; | |
2664 | pm_runtime_get_noresume(host->mmc->parent); | |
2665 | } | |
2666 | ||
2667 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) | |
2668 | { | |
2669 | if (host->runtime_suspended || !host->bus_on) | |
2670 | return; | |
2671 | host->bus_on = false; | |
2672 | pm_runtime_put_noidle(host->mmc->parent); | |
2673 | } | |
2674 | ||
66fd8ad5 AH |
2675 | int sdhci_runtime_suspend_host(struct sdhci_host *host) |
2676 | { | |
2677 | unsigned long flags; | |
2678 | int ret = 0; | |
2679 | ||
2680 | /* Disable tuning since we are suspending */ | |
973905fe | 2681 | if (host->flags & SDHCI_USING_RETUNING_TIMER) { |
66fd8ad5 AH |
2682 | del_timer_sync(&host->tuning_timer); |
2683 | host->flags &= ~SDHCI_NEEDS_RETUNING; | |
2684 | } | |
2685 | ||
2686 | spin_lock_irqsave(&host->lock, flags); | |
b537f94c RK |
2687 | host->ier &= SDHCI_INT_CARD_INT; |
2688 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
2689 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
66fd8ad5 AH |
2690 | spin_unlock_irqrestore(&host->lock, flags); |
2691 | ||
781e989c | 2692 | synchronize_hardirq(host->irq); |
66fd8ad5 AH |
2693 | |
2694 | spin_lock_irqsave(&host->lock, flags); | |
2695 | host->runtime_suspended = true; | |
2696 | spin_unlock_irqrestore(&host->lock, flags); | |
2697 | ||
2698 | return ret; | |
2699 | } | |
2700 | EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); | |
2701 | ||
2702 | int sdhci_runtime_resume_host(struct sdhci_host *host) | |
2703 | { | |
2704 | unsigned long flags; | |
2705 | int ret = 0, host_flags = host->flags; | |
2706 | ||
2707 | if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { | |
2708 | if (host->ops->enable_dma) | |
2709 | host->ops->enable_dma(host); | |
2710 | } | |
2711 | ||
2712 | sdhci_init(host, 0); | |
2713 | ||
2714 | /* Force clock and power re-program */ | |
2715 | host->pwr = 0; | |
2716 | host->clock = 0; | |
2717 | sdhci_do_set_ios(host, &host->mmc->ios); | |
2718 | ||
2719 | sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); | |
52983382 KL |
2720 | if ((host_flags & SDHCI_PV_ENABLED) && |
2721 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { | |
2722 | spin_lock_irqsave(&host->lock, flags); | |
2723 | sdhci_enable_preset_value(host, true); | |
2724 | spin_unlock_irqrestore(&host->lock, flags); | |
2725 | } | |
66fd8ad5 AH |
2726 | |
2727 | /* Set the re-tuning expiration flag */ | |
973905fe | 2728 | if (host->flags & SDHCI_USING_RETUNING_TIMER) |
66fd8ad5 AH |
2729 | host->flags |= SDHCI_NEEDS_RETUNING; |
2730 | ||
2731 | spin_lock_irqsave(&host->lock, flags); | |
2732 | ||
2733 | host->runtime_suspended = false; | |
2734 | ||
2735 | /* Enable SDIO IRQ */ | |
ef104333 | 2736 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) |
66fd8ad5 AH |
2737 | sdhci_enable_sdio_irq_nolock(host, true); |
2738 | ||
2739 | /* Enable Card Detection */ | |
2740 | sdhci_enable_card_detection(host); | |
2741 | ||
2742 | spin_unlock_irqrestore(&host->lock, flags); | |
2743 | ||
2744 | return ret; | |
2745 | } | |
2746 | EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); | |
2747 | ||
2748 | #endif | |
2749 | ||
d129bceb PO |
2750 | /*****************************************************************************\ |
2751 | * * | |
b8c86fc5 | 2752 | * Device allocation/registration * |
d129bceb PO |
2753 | * * |
2754 | \*****************************************************************************/ | |
2755 | ||
b8c86fc5 PO |
2756 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
2757 | size_t priv_size) | |
d129bceb | 2758 | { |
d129bceb PO |
2759 | struct mmc_host *mmc; |
2760 | struct sdhci_host *host; | |
2761 | ||
b8c86fc5 | 2762 | WARN_ON(dev == NULL); |
d129bceb | 2763 | |
b8c86fc5 | 2764 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
d129bceb | 2765 | if (!mmc) |
b8c86fc5 | 2766 | return ERR_PTR(-ENOMEM); |
d129bceb PO |
2767 | |
2768 | host = mmc_priv(mmc); | |
2769 | host->mmc = mmc; | |
2770 | ||
b8c86fc5 PO |
2771 | return host; |
2772 | } | |
8a4da143 | 2773 | |
b8c86fc5 | 2774 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
d129bceb | 2775 | |
b8c86fc5 PO |
2776 | int sdhci_add_host(struct sdhci_host *host) |
2777 | { | |
2778 | struct mmc_host *mmc; | |
bd6a8c30 | 2779 | u32 caps[2] = {0, 0}; |
f2119df6 AN |
2780 | u32 max_current_caps; |
2781 | unsigned int ocr_avail; | |
b8c86fc5 | 2782 | int ret; |
d129bceb | 2783 | |
b8c86fc5 PO |
2784 | WARN_ON(host == NULL); |
2785 | if (host == NULL) | |
2786 | return -EINVAL; | |
d129bceb | 2787 | |
b8c86fc5 | 2788 | mmc = host->mmc; |
d129bceb | 2789 | |
b8c86fc5 PO |
2790 | if (debug_quirks) |
2791 | host->quirks = debug_quirks; | |
66fd8ad5 AH |
2792 | if (debug_quirks2) |
2793 | host->quirks2 = debug_quirks2; | |
d129bceb | 2794 | |
d96649ed PO |
2795 | sdhci_reset(host, SDHCI_RESET_ALL); |
2796 | ||
4e4141a5 | 2797 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
2134a922 PO |
2798 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
2799 | >> SDHCI_SPEC_VER_SHIFT; | |
85105c53 | 2800 | if (host->version > SDHCI_SPEC_300) { |
a3c76eb9 | 2801 | pr_err("%s: Unknown controller version (%d). " |
b69c9058 | 2802 | "You may experience problems.\n", mmc_hostname(mmc), |
2134a922 | 2803 | host->version); |
4a965505 PO |
2804 | } |
2805 | ||
f2119df6 | 2806 | caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : |
ccc92c23 | 2807 | sdhci_readl(host, SDHCI_CAPABILITIES); |
d129bceb | 2808 | |
bd6a8c30 PR |
2809 | if (host->version >= SDHCI_SPEC_300) |
2810 | caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? | |
2811 | host->caps1 : | |
2812 | sdhci_readl(host, SDHCI_CAPABILITIES_1); | |
f2119df6 | 2813 | |
b8c86fc5 | 2814 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
a13abc7b | 2815 | host->flags |= SDHCI_USE_SDMA; |
f2119df6 | 2816 | else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) |
a13abc7b | 2817 | DBG("Controller doesn't have SDMA capability\n"); |
67435274 | 2818 | else |
a13abc7b | 2819 | host->flags |= SDHCI_USE_SDMA; |
d129bceb | 2820 | |
b8c86fc5 | 2821 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
a13abc7b | 2822 | (host->flags & SDHCI_USE_SDMA)) { |
cee687ce | 2823 | DBG("Disabling DMA as it is marked broken\n"); |
a13abc7b | 2824 | host->flags &= ~SDHCI_USE_SDMA; |
7c168e3d FT |
2825 | } |
2826 | ||
f2119df6 AN |
2827 | if ((host->version >= SDHCI_SPEC_200) && |
2828 | (caps[0] & SDHCI_CAN_DO_ADMA2)) | |
a13abc7b | 2829 | host->flags |= SDHCI_USE_ADMA; |
2134a922 PO |
2830 | |
2831 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && | |
2832 | (host->flags & SDHCI_USE_ADMA)) { | |
2833 | DBG("Disabling ADMA as it is marked broken\n"); | |
2834 | host->flags &= ~SDHCI_USE_ADMA; | |
2835 | } | |
2836 | ||
a13abc7b | 2837 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
2838 | if (host->ops->enable_dma) { |
2839 | if (host->ops->enable_dma(host)) { | |
a3c76eb9 | 2840 | pr_warning("%s: No suitable DMA " |
b8c86fc5 PO |
2841 | "available. Falling back to PIO.\n", |
2842 | mmc_hostname(mmc)); | |
a13abc7b RR |
2843 | host->flags &= |
2844 | ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); | |
b8c86fc5 | 2845 | } |
d129bceb PO |
2846 | } |
2847 | } | |
2848 | ||
2134a922 PO |
2849 | if (host->flags & SDHCI_USE_ADMA) { |
2850 | /* | |
2851 | * We need to allocate descriptors for all sg entries | |
2852 | * (128) and potentially one alignment transfer for | |
2853 | * each of those entries. | |
2854 | */ | |
2855 | host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); | |
2856 | host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); | |
2857 | if (!host->adma_desc || !host->align_buffer) { | |
2858 | kfree(host->adma_desc); | |
2859 | kfree(host->align_buffer); | |
a3c76eb9 | 2860 | pr_warning("%s: Unable to allocate ADMA " |
2134a922 PO |
2861 | "buffers. Falling back to standard DMA.\n", |
2862 | mmc_hostname(mmc)); | |
2863 | host->flags &= ~SDHCI_USE_ADMA; | |
2864 | } | |
2865 | } | |
2866 | ||
7659150c PO |
2867 | /* |
2868 | * If we use DMA, then it's up to the caller to set the DMA | |
2869 | * mask, but PIO does not need the hw shim so we set a new | |
2870 | * mask here in that case. | |
2871 | */ | |
a13abc7b | 2872 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
7659150c PO |
2873 | host->dma_mask = DMA_BIT_MASK(64); |
2874 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; | |
2875 | } | |
d129bceb | 2876 | |
c4687d5f | 2877 | if (host->version >= SDHCI_SPEC_300) |
f2119df6 | 2878 | host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) |
c4687d5f ZG |
2879 | >> SDHCI_CLOCK_BASE_SHIFT; |
2880 | else | |
f2119df6 | 2881 | host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) |
c4687d5f ZG |
2882 | >> SDHCI_CLOCK_BASE_SHIFT; |
2883 | ||
4240ff0a | 2884 | host->max_clk *= 1000000; |
f27f47ef AV |
2885 | if (host->max_clk == 0 || host->quirks & |
2886 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { | |
4240ff0a | 2887 | if (!host->ops->get_max_clock) { |
a3c76eb9 | 2888 | pr_err("%s: Hardware doesn't specify base clock " |
4240ff0a BD |
2889 | "frequency.\n", mmc_hostname(mmc)); |
2890 | return -ENODEV; | |
2891 | } | |
2892 | host->max_clk = host->ops->get_max_clock(host); | |
8ef1a143 | 2893 | } |
d129bceb | 2894 | |
c3ed3877 AN |
2895 | /* |
2896 | * In case of Host Controller v3.00, find out whether clock | |
2897 | * multiplier is supported. | |
2898 | */ | |
2899 | host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> | |
2900 | SDHCI_CLOCK_MUL_SHIFT; | |
2901 | ||
2902 | /* | |
2903 | * In case the value in Clock Multiplier is 0, then programmable | |
2904 | * clock mode is not supported, otherwise the actual clock | |
2905 | * multiplier is one more than the value of Clock Multiplier | |
2906 | * in the Capabilities Register. | |
2907 | */ | |
2908 | if (host->clk_mul) | |
2909 | host->clk_mul += 1; | |
2910 | ||
d129bceb PO |
2911 | /* |
2912 | * Set host parameters. | |
2913 | */ | |
2914 | mmc->ops = &sdhci_ops; | |
c3ed3877 | 2915 | mmc->f_max = host->max_clk; |
ce5f036b | 2916 | if (host->ops->get_min_clock) |
a9e58f25 | 2917 | mmc->f_min = host->ops->get_min_clock(host); |
c3ed3877 AN |
2918 | else if (host->version >= SDHCI_SPEC_300) { |
2919 | if (host->clk_mul) { | |
2920 | mmc->f_min = (host->max_clk * host->clk_mul) / 1024; | |
2921 | mmc->f_max = host->max_clk * host->clk_mul; | |
2922 | } else | |
2923 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; | |
2924 | } else | |
0397526d | 2925 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
15ec4461 | 2926 | |
272308ca AS |
2927 | host->timeout_clk = |
2928 | (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
2929 | if (host->timeout_clk == 0) { | |
2930 | if (host->ops->get_timeout_clock) { | |
2931 | host->timeout_clk = host->ops->get_timeout_clock(host); | |
2932 | } else if (!(host->quirks & | |
2933 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { | |
a3c76eb9 | 2934 | pr_err("%s: Hardware doesn't specify timeout clock " |
272308ca AS |
2935 | "frequency.\n", mmc_hostname(mmc)); |
2936 | return -ENODEV; | |
2937 | } | |
2938 | } | |
2939 | if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) | |
2940 | host->timeout_clk *= 1000; | |
2941 | ||
2942 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) | |
65be3fef | 2943 | host->timeout_clk = mmc->f_max / 1000; |
272308ca | 2944 | |
68eb80e0 | 2945 | mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; |
58d1246d | 2946 | |
e89d456f | 2947 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; |
781e989c | 2948 | mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; |
e89d456f AW |
2949 | |
2950 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) | |
2951 | host->flags |= SDHCI_AUTO_CMD12; | |
5fe23c7f | 2952 | |
8edf6371 | 2953 | /* Auto-CMD23 stuff only works in ADMA or PIO. */ |
4f3d3e9b | 2954 | if ((host->version >= SDHCI_SPEC_300) && |
8edf6371 | 2955 | ((host->flags & SDHCI_USE_ADMA) || |
4f3d3e9b | 2956 | !(host->flags & SDHCI_USE_SDMA))) { |
8edf6371 AW |
2957 | host->flags |= SDHCI_AUTO_CMD23; |
2958 | DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); | |
2959 | } else { | |
2960 | DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); | |
2961 | } | |
2962 | ||
15ec4461 PR |
2963 | /* |
2964 | * A controller may support 8-bit width, but the board itself | |
2965 | * might not have the pins brought out. Boards that support | |
2966 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in | |
2967 | * their platform code before calling sdhci_add_host(), and we | |
2968 | * won't assume 8-bit width for hosts without that CAP. | |
2969 | */ | |
5fe23c7f | 2970 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
15ec4461 | 2971 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
d129bceb | 2972 | |
63ef5d8c JH |
2973 | if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) |
2974 | mmc->caps &= ~MMC_CAP_CMD23; | |
2975 | ||
f2119df6 | 2976 | if (caps[0] & SDHCI_CAN_DO_HISPD) |
a29e7e18 | 2977 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
cd9277c0 | 2978 | |
176d1ed4 | 2979 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
eb6d5ae1 | 2980 | !(host->mmc->caps & MMC_CAP_NONREMOVABLE)) |
68d1fb7e AV |
2981 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
2982 | ||
6231f3de | 2983 | /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ |
462849aa | 2984 | host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc"); |
657d5982 KL |
2985 | if (IS_ERR_OR_NULL(host->vqmmc)) { |
2986 | if (PTR_ERR(host->vqmmc) < 0) { | |
2987 | pr_info("%s: no vqmmc regulator found\n", | |
2988 | mmc_hostname(mmc)); | |
2989 | host->vqmmc = NULL; | |
2990 | } | |
8363c374 | 2991 | } else { |
a3361aba | 2992 | ret = regulator_enable(host->vqmmc); |
cec2e216 KL |
2993 | if (!regulator_is_supported_voltage(host->vqmmc, 1700000, |
2994 | 1950000)) | |
8363c374 KL |
2995 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | |
2996 | SDHCI_SUPPORT_SDR50 | | |
2997 | SDHCI_SUPPORT_DDR50); | |
a3361aba CB |
2998 | if (ret) { |
2999 | pr_warn("%s: Failed to enable vqmmc regulator: %d\n", | |
3000 | mmc_hostname(mmc), ret); | |
3001 | host->vqmmc = NULL; | |
3002 | } | |
8363c374 | 3003 | } |
6231f3de | 3004 | |
6a66180a DD |
3005 | if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) |
3006 | caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | | |
3007 | SDHCI_SUPPORT_DDR50); | |
3008 | ||
4188bba0 AC |
3009 | /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ |
3010 | if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | | |
3011 | SDHCI_SUPPORT_DDR50)) | |
f2119df6 AN |
3012 | mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; |
3013 | ||
3014 | /* SDR104 supports also implies SDR50 support */ | |
156e14b1 | 3015 | if (caps[1] & SDHCI_SUPPORT_SDR104) { |
f2119df6 | 3016 | mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; |
156e14b1 GC |
3017 | /* SD3.0: SDR104 is supported so (for eMMC) the caps2 |
3018 | * field can be promoted to support HS200. | |
3019 | */ | |
13868bf2 DC |
3020 | if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) |
3021 | mmc->caps2 |= MMC_CAP2_HS200; | |
156e14b1 | 3022 | } else if (caps[1] & SDHCI_SUPPORT_SDR50) |
f2119df6 AN |
3023 | mmc->caps |= MMC_CAP_UHS_SDR50; |
3024 | ||
9107ebbf MC |
3025 | if ((caps[1] & SDHCI_SUPPORT_DDR50) && |
3026 | !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) | |
f2119df6 AN |
3027 | mmc->caps |= MMC_CAP_UHS_DDR50; |
3028 | ||
069c9f14 | 3029 | /* Does the host need tuning for SDR50? */ |
b513ea25 AN |
3030 | if (caps[1] & SDHCI_USE_SDR50_TUNING) |
3031 | host->flags |= SDHCI_SDR50_NEEDS_TUNING; | |
3032 | ||
156e14b1 | 3033 | /* Does the host need tuning for SDR104 / HS200? */ |
069c9f14 | 3034 | if (mmc->caps2 & MMC_CAP2_HS200) |
156e14b1 | 3035 | host->flags |= SDHCI_SDR104_NEEDS_TUNING; |
069c9f14 | 3036 | |
d6d50a15 AN |
3037 | /* Driver Type(s) (A, C, D) supported by the host */ |
3038 | if (caps[1] & SDHCI_DRIVER_TYPE_A) | |
3039 | mmc->caps |= MMC_CAP_DRIVER_TYPE_A; | |
3040 | if (caps[1] & SDHCI_DRIVER_TYPE_C) | |
3041 | mmc->caps |= MMC_CAP_DRIVER_TYPE_C; | |
3042 | if (caps[1] & SDHCI_DRIVER_TYPE_D) | |
3043 | mmc->caps |= MMC_CAP_DRIVER_TYPE_D; | |
3044 | ||
cf2b5eea AN |
3045 | /* Initial value for re-tuning timer count */ |
3046 | host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> | |
3047 | SDHCI_RETUNING_TIMER_COUNT_SHIFT; | |
3048 | ||
3049 | /* | |
3050 | * In case Re-tuning Timer is not disabled, the actual value of | |
3051 | * re-tuning timer will be 2 ^ (n - 1). | |
3052 | */ | |
3053 | if (host->tuning_count) | |
3054 | host->tuning_count = 1 << (host->tuning_count - 1); | |
3055 | ||
3056 | /* Re-tuning mode supported by the Host Controller */ | |
3057 | host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> | |
3058 | SDHCI_RETUNING_MODE_SHIFT; | |
3059 | ||
8f230f45 | 3060 | ocr_avail = 0; |
bad37e1a | 3061 | |
462849aa | 3062 | host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc"); |
657d5982 KL |
3063 | if (IS_ERR_OR_NULL(host->vmmc)) { |
3064 | if (PTR_ERR(host->vmmc) < 0) { | |
3065 | pr_info("%s: no vmmc regulator found\n", | |
3066 | mmc_hostname(mmc)); | |
3067 | host->vmmc = NULL; | |
3068 | } | |
8363c374 | 3069 | } |
bad37e1a | 3070 | |
68737043 | 3071 | #ifdef CONFIG_REGULATOR |
a4f8f257 MS |
3072 | /* |
3073 | * Voltage range check makes sense only if regulator reports | |
3074 | * any voltage value. | |
3075 | */ | |
3076 | if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) { | |
cec2e216 KL |
3077 | ret = regulator_is_supported_voltage(host->vmmc, 2700000, |
3078 | 3600000); | |
68737043 PR |
3079 | if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330))) |
3080 | caps[0] &= ~SDHCI_CAN_VDD_330; | |
68737043 PR |
3081 | if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300))) |
3082 | caps[0] &= ~SDHCI_CAN_VDD_300; | |
cec2e216 KL |
3083 | ret = regulator_is_supported_voltage(host->vmmc, 1700000, |
3084 | 1950000); | |
68737043 PR |
3085 | if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180))) |
3086 | caps[0] &= ~SDHCI_CAN_VDD_180; | |
3087 | } | |
3088 | #endif /* CONFIG_REGULATOR */ | |
3089 | ||
f2119df6 AN |
3090 | /* |
3091 | * According to SD Host Controller spec v3.00, if the Host System | |
3092 | * can afford more than 150mA, Host Driver should set XPC to 1. Also | |
3093 | * the value is meaningful only if Voltage Support in the Capabilities | |
3094 | * register is set. The actual current value is 4 times the register | |
3095 | * value. | |
3096 | */ | |
3097 | max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); | |
bad37e1a PR |
3098 | if (!max_current_caps && host->vmmc) { |
3099 | u32 curr = regulator_get_current_limit(host->vmmc); | |
3100 | if (curr > 0) { | |
3101 | ||
3102 | /* convert to SDHCI_MAX_CURRENT format */ | |
3103 | curr = curr/1000; /* convert to mA */ | |
3104 | curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; | |
3105 | ||
3106 | curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); | |
3107 | max_current_caps = | |
3108 | (curr << SDHCI_MAX_CURRENT_330_SHIFT) | | |
3109 | (curr << SDHCI_MAX_CURRENT_300_SHIFT) | | |
3110 | (curr << SDHCI_MAX_CURRENT_180_SHIFT); | |
3111 | } | |
3112 | } | |
f2119df6 AN |
3113 | |
3114 | if (caps[0] & SDHCI_CAN_VDD_330) { | |
8f230f45 | 3115 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
f2119df6 | 3116 | |
55c4665e | 3117 | mmc->max_current_330 = ((max_current_caps & |
f2119df6 AN |
3118 | SDHCI_MAX_CURRENT_330_MASK) >> |
3119 | SDHCI_MAX_CURRENT_330_SHIFT) * | |
3120 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3121 | } |
3122 | if (caps[0] & SDHCI_CAN_VDD_300) { | |
8f230f45 | 3123 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
f2119df6 | 3124 | |
55c4665e | 3125 | mmc->max_current_300 = ((max_current_caps & |
f2119df6 AN |
3126 | SDHCI_MAX_CURRENT_300_MASK) >> |
3127 | SDHCI_MAX_CURRENT_300_SHIFT) * | |
3128 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3129 | } |
3130 | if (caps[0] & SDHCI_CAN_VDD_180) { | |
8f230f45 TI |
3131 | ocr_avail |= MMC_VDD_165_195; |
3132 | ||
55c4665e | 3133 | mmc->max_current_180 = ((max_current_caps & |
f2119df6 AN |
3134 | SDHCI_MAX_CURRENT_180_MASK) >> |
3135 | SDHCI_MAX_CURRENT_180_SHIFT) * | |
3136 | SDHCI_MAX_CURRENT_MULTIPLIER; | |
f2119df6 AN |
3137 | } |
3138 | ||
c0b887b6 HZ |
3139 | if (host->ocr_mask) |
3140 | ocr_avail = host->ocr_mask; | |
3141 | ||
8f230f45 TI |
3142 | mmc->ocr_avail = ocr_avail; |
3143 | mmc->ocr_avail_sdio = ocr_avail; | |
3144 | if (host->ocr_avail_sdio) | |
3145 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; | |
3146 | mmc->ocr_avail_sd = ocr_avail; | |
3147 | if (host->ocr_avail_sd) | |
3148 | mmc->ocr_avail_sd &= host->ocr_avail_sd; | |
3149 | else /* normal SD controllers don't support 1.8V */ | |
3150 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; | |
3151 | mmc->ocr_avail_mmc = ocr_avail; | |
3152 | if (host->ocr_avail_mmc) | |
3153 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; | |
146ad66e PO |
3154 | |
3155 | if (mmc->ocr_avail == 0) { | |
a3c76eb9 | 3156 | pr_err("%s: Hardware doesn't report any " |
b69c9058 | 3157 | "support voltages.\n", mmc_hostname(mmc)); |
b8c86fc5 | 3158 | return -ENODEV; |
146ad66e PO |
3159 | } |
3160 | ||
d129bceb PO |
3161 | spin_lock_init(&host->lock); |
3162 | ||
3163 | /* | |
2134a922 PO |
3164 | * Maximum number of segments. Depends on if the hardware |
3165 | * can do scatter/gather or not. | |
d129bceb | 3166 | */ |
2134a922 | 3167 | if (host->flags & SDHCI_USE_ADMA) |
a36274e0 | 3168 | mmc->max_segs = 128; |
a13abc7b | 3169 | else if (host->flags & SDHCI_USE_SDMA) |
a36274e0 | 3170 | mmc->max_segs = 1; |
2134a922 | 3171 | else /* PIO */ |
a36274e0 | 3172 | mmc->max_segs = 128; |
d129bceb PO |
3173 | |
3174 | /* | |
bab76961 | 3175 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 3176 | * size (512KiB). |
d129bceb | 3177 | */ |
55db890a | 3178 | mmc->max_req_size = 524288; |
d129bceb PO |
3179 | |
3180 | /* | |
3181 | * Maximum segment size. Could be one segment with the maximum number | |
2134a922 PO |
3182 | * of bytes. When doing hardware scatter/gather, each entry cannot |
3183 | * be larger than 64 KiB though. | |
d129bceb | 3184 | */ |
30652aa3 OJ |
3185 | if (host->flags & SDHCI_USE_ADMA) { |
3186 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) | |
3187 | mmc->max_seg_size = 65535; | |
3188 | else | |
3189 | mmc->max_seg_size = 65536; | |
3190 | } else { | |
2134a922 | 3191 | mmc->max_seg_size = mmc->max_req_size; |
30652aa3 | 3192 | } |
d129bceb | 3193 | |
fe4a3c7a PO |
3194 | /* |
3195 | * Maximum block size. This varies from controller to controller and | |
3196 | * is specified in the capabilities register. | |
3197 | */ | |
0633f654 AV |
3198 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
3199 | mmc->max_blk_size = 2; | |
3200 | } else { | |
f2119df6 | 3201 | mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> |
0633f654 AV |
3202 | SDHCI_MAX_BLOCK_SHIFT; |
3203 | if (mmc->max_blk_size >= 3) { | |
a3c76eb9 | 3204 | pr_warning("%s: Invalid maximum block size, " |
0633f654 AV |
3205 | "assuming 512 bytes\n", mmc_hostname(mmc)); |
3206 | mmc->max_blk_size = 0; | |
3207 | } | |
3208 | } | |
3209 | ||
3210 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 3211 | |
55db890a PO |
3212 | /* |
3213 | * Maximum block count. | |
3214 | */ | |
1388eefd | 3215 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
55db890a | 3216 | |
d129bceb PO |
3217 | /* |
3218 | * Init tasklets. | |
3219 | */ | |
d129bceb PO |
3220 | tasklet_init(&host->finish_tasklet, |
3221 | sdhci_tasklet_finish, (unsigned long)host); | |
3222 | ||
e4cad1b5 | 3223 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 3224 | |
cf2b5eea | 3225 | if (host->version >= SDHCI_SPEC_300) { |
b513ea25 AN |
3226 | init_waitqueue_head(&host->buf_ready_int); |
3227 | ||
cf2b5eea AN |
3228 | /* Initialize re-tuning timer */ |
3229 | init_timer(&host->tuning_timer); | |
3230 | host->tuning_timer.data = (unsigned long)host; | |
3231 | host->tuning_timer.function = sdhci_tuning_timer; | |
3232 | } | |
3233 | ||
2af502ca SG |
3234 | sdhci_init(host, 0); |
3235 | ||
781e989c RK |
3236 | ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, |
3237 | IRQF_SHARED, mmc_hostname(mmc), host); | |
0fc81ee3 MB |
3238 | if (ret) { |
3239 | pr_err("%s: Failed to request IRQ %d: %d\n", | |
3240 | mmc_hostname(mmc), host->irq, ret); | |
8ef1a143 | 3241 | goto untasklet; |
0fc81ee3 | 3242 | } |
d129bceb | 3243 | |
d129bceb PO |
3244 | #ifdef CONFIG_MMC_DEBUG |
3245 | sdhci_dumpregs(host); | |
3246 | #endif | |
3247 | ||
f9134319 | 3248 | #ifdef SDHCI_USE_LEDS_CLASS |
5dbace0c HS |
3249 | snprintf(host->led_name, sizeof(host->led_name), |
3250 | "%s::", mmc_hostname(mmc)); | |
3251 | host->led.name = host->led_name; | |
2f730fec PO |
3252 | host->led.brightness = LED_OFF; |
3253 | host->led.default_trigger = mmc_hostname(mmc); | |
3254 | host->led.brightness_set = sdhci_led_control; | |
3255 | ||
b8c86fc5 | 3256 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
0fc81ee3 MB |
3257 | if (ret) { |
3258 | pr_err("%s: Failed to register LED device: %d\n", | |
3259 | mmc_hostname(mmc), ret); | |
2f730fec | 3260 | goto reset; |
0fc81ee3 | 3261 | } |
2f730fec PO |
3262 | #endif |
3263 | ||
5f25a66f PO |
3264 | mmiowb(); |
3265 | ||
d129bceb PO |
3266 | mmc_add_host(mmc); |
3267 | ||
a3c76eb9 | 3268 | pr_info("%s: SDHCI controller on %s [%s] using %s\n", |
d1b26863 | 3269 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
a13abc7b RR |
3270 | (host->flags & SDHCI_USE_ADMA) ? "ADMA" : |
3271 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); | |
d129bceb | 3272 | |
7260cf5e AV |
3273 | sdhci_enable_card_detection(host); |
3274 | ||
d129bceb PO |
3275 | return 0; |
3276 | ||
f9134319 | 3277 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
3278 | reset: |
3279 | sdhci_reset(host, SDHCI_RESET_ALL); | |
b537f94c RK |
3280 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
3281 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
2f730fec PO |
3282 | free_irq(host->irq, host); |
3283 | #endif | |
8ef1a143 | 3284 | untasklet: |
d129bceb | 3285 | tasklet_kill(&host->finish_tasklet); |
d129bceb PO |
3286 | |
3287 | return ret; | |
3288 | } | |
3289 | ||
b8c86fc5 | 3290 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
d129bceb | 3291 | |
1e72859e | 3292 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
b8c86fc5 | 3293 | { |
1e72859e PO |
3294 | unsigned long flags; |
3295 | ||
3296 | if (dead) { | |
3297 | spin_lock_irqsave(&host->lock, flags); | |
3298 | ||
3299 | host->flags |= SDHCI_DEVICE_DEAD; | |
3300 | ||
3301 | if (host->mrq) { | |
a3c76eb9 | 3302 | pr_err("%s: Controller removed during " |
1e72859e PO |
3303 | " transfer!\n", mmc_hostname(host->mmc)); |
3304 | ||
3305 | host->mrq->cmd->error = -ENOMEDIUM; | |
3306 | tasklet_schedule(&host->finish_tasklet); | |
3307 | } | |
3308 | ||
3309 | spin_unlock_irqrestore(&host->lock, flags); | |
3310 | } | |
3311 | ||
7260cf5e AV |
3312 | sdhci_disable_card_detection(host); |
3313 | ||
b8c86fc5 | 3314 | mmc_remove_host(host->mmc); |
d129bceb | 3315 | |
f9134319 | 3316 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
3317 | led_classdev_unregister(&host->led); |
3318 | #endif | |
3319 | ||
1e72859e PO |
3320 | if (!dead) |
3321 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb | 3322 | |
b537f94c RK |
3323 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
3324 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); | |
d129bceb PO |
3325 | free_irq(host->irq, host); |
3326 | ||
3327 | del_timer_sync(&host->timer); | |
3328 | ||
d129bceb | 3329 | tasklet_kill(&host->finish_tasklet); |
2134a922 | 3330 | |
77dcb3f4 PR |
3331 | if (host->vmmc) { |
3332 | regulator_disable(host->vmmc); | |
9bea3c85 | 3333 | regulator_put(host->vmmc); |
77dcb3f4 | 3334 | } |
9bea3c85 | 3335 | |
6231f3de PR |
3336 | if (host->vqmmc) { |
3337 | regulator_disable(host->vqmmc); | |
3338 | regulator_put(host->vqmmc); | |
3339 | } | |
3340 | ||
2134a922 PO |
3341 | kfree(host->adma_desc); |
3342 | kfree(host->align_buffer); | |
3343 | ||
3344 | host->adma_desc = NULL; | |
3345 | host->align_buffer = NULL; | |
d129bceb PO |
3346 | } |
3347 | ||
b8c86fc5 | 3348 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
d129bceb | 3349 | |
b8c86fc5 | 3350 | void sdhci_free_host(struct sdhci_host *host) |
d129bceb | 3351 | { |
b8c86fc5 | 3352 | mmc_free_host(host->mmc); |
d129bceb PO |
3353 | } |
3354 | ||
b8c86fc5 | 3355 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
d129bceb PO |
3356 | |
3357 | /*****************************************************************************\ | |
3358 | * * | |
3359 | * Driver init/exit * | |
3360 | * * | |
3361 | \*****************************************************************************/ | |
3362 | ||
3363 | static int __init sdhci_drv_init(void) | |
3364 | { | |
a3c76eb9 | 3365 | pr_info(DRIVER_NAME |
52fbf9c9 | 3366 | ": Secure Digital Host Controller Interface driver\n"); |
a3c76eb9 | 3367 | pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
d129bceb | 3368 | |
b8c86fc5 | 3369 | return 0; |
d129bceb PO |
3370 | } |
3371 | ||
3372 | static void __exit sdhci_drv_exit(void) | |
3373 | { | |
d129bceb PO |
3374 | } |
3375 | ||
3376 | module_init(sdhci_drv_init); | |
3377 | module_exit(sdhci_drv_exit); | |
3378 | ||
df673b22 | 3379 | module_param(debug_quirks, uint, 0444); |
66fd8ad5 | 3380 | module_param(debug_quirks2, uint, 0444); |
67435274 | 3381 | |
32710e8f | 3382 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 | 3383 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
d129bceb | 3384 | MODULE_LICENSE("GPL"); |
67435274 | 3385 | |
df673b22 | 3386 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |
66fd8ad5 | 3387 | MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); |