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sdhci: Add support for bus-specific IO memory accessors
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
11763609 20#include <linux/scatterlist.h>
d129bceb 21
2f730fec
PO		 22#include <linux/leds.h>
23
d129bceb 24#include <linux/mmc/host.h>
d129bceb 25
d129bceb
PO		 26#include "sdhci.h"
27
28#define DRIVER_NAME "sdhci"
d129bceb 29
d129bceb 30#define DBG(f, x...) \
c6563178 31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 32
f9134319
PO		 33#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
34 defined(CONFIG_MMC_SDHCI_MODULE))
35#define SDHCI_USE_LEDS_CLASS
36#endif
37
df673b22 38static unsigned int debug_quirks = 0;
67435274 39
d129bceb
PO		 40static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
41static void sdhci_finish_data(struct sdhci_host *);
42
43static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
44static void sdhci_finish_command(struct sdhci_host *);
45
46static void sdhci_dumpregs(struct sdhci_host *host)
47{
48 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
49
50 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 51 sdhci_readl(host, SDHCI_DMA_ADDRESS),
52 sdhci_readw(host, SDHCI_HOST_VERSION));
d129bceb 53 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 54 sdhci_readw(host, SDHCI_BLOCK_SIZE),
55 sdhci_readw(host, SDHCI_BLOCK_COUNT));
d129bceb 56 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 57 sdhci_readl(host, SDHCI_ARGUMENT),
58 sdhci_readw(host, SDHCI_TRANSFER_MODE));
d129bceb 59 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 60 sdhci_readl(host, SDHCI_PRESENT_STATE),
61 sdhci_readb(host, SDHCI_HOST_CONTROL));
d129bceb 62 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 63 sdhci_readb(host, SDHCI_POWER_CONTROL),
64 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
d129bceb 65 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 66 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
67 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
d129bceb 68 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 69 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
70 sdhci_readl(host, SDHCI_INT_STATUS));
d129bceb 71 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 72 sdhci_readl(host, SDHCI_INT_ENABLE),
73 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
d129bceb 74 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 75 sdhci_readw(host, SDHCI_ACMD12_ERR),
76 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
d129bceb 77 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
4e4141a5
AV		 78 sdhci_readl(host, SDHCI_CAPABILITIES),
79 sdhci_readl(host, SDHCI_MAX_CURRENT));
d129bceb
PO		 80
81 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
82}
83
84/*****************************************************************************\
85 * *
86 * Low level functions *
87 * *
88\*****************************************************************************/
89
90static void sdhci_reset(struct sdhci_host *host, u8 mask)
91{
e16514d8
PO		 92 unsigned long timeout;
93
b8c86fc5 94 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 95 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 96 SDHCI_CARD_PRESENT))
97 return;
98 }
99
4e4141a5 100 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 101
e16514d8 102 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 103 host->clock = 0;
104
e16514d8
PO		 105 /* Wait max 100 ms */
106 timeout = 100;
107
108 /* hw clears the bit when it's done */
4e4141a5 109 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 110 if (timeout == 0) {
acf1da45 111 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 112 mmc_hostname(host->mmc), (int)mask);
113 sdhci_dumpregs(host);
114 return;
115 }
116 timeout--;
117 mdelay(1);
d129bceb
PO		 118 }
119}
120
121static void sdhci_init(struct sdhci_host *host)
122{
123 u32 intmask;
124
125 sdhci_reset(host, SDHCI_RESET_ALL);
126
3192a28f
PO		 127 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
128 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
129 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
130 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 131 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
2134a922
PO		 132 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
133 SDHCI_INT_ADMA_ERROR;
d129bceb 134
4e4141a5
AV		 135 sdhci_writel(host, intmask, SDHCI_INT_ENABLE);
136 sdhci_writel(host, intmask, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 137}
138
139static void sdhci_activate_led(struct sdhci_host *host)
140{
141 u8 ctrl;
142
4e4141a5 143 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 144 ctrl |= SDHCI_CTRL_LED;
4e4141a5 145 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 146}
147
148static void sdhci_deactivate_led(struct sdhci_host *host)
149{
150 u8 ctrl;
151
4e4141a5 152 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 153 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 154 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 155}
156
f9134319 157#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 158static void sdhci_led_control(struct led_classdev *led,
159 enum led_brightness brightness)
160{
161 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
162 unsigned long flags;
163
164 spin_lock_irqsave(&host->lock, flags);
165
166 if (brightness == LED_OFF)
167 sdhci_deactivate_led(host);
168 else
169 sdhci_activate_led(host);
170
171 spin_unlock_irqrestore(&host->lock, flags);
172}
173#endif
174
d129bceb
PO		 175/*****************************************************************************\
176 * *
177 * Core functions *
178 * *
179\*****************************************************************************/
180
a406f5a3 181static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 182{
7659150c
PO		 183 unsigned long flags;
184 size_t blksize, len, chunk;
7244b85b 185 u32 uninitialized_var(scratch);
7659150c 186 u8 *buf;
d129bceb 187
a406f5a3 188 DBG("PIO reading\n");
d129bceb 189
a406f5a3 190 blksize = host->data->blksz;
7659150c 191 chunk = 0;
d129bceb 192
7659150c 193 local_irq_save(flags);
d129bceb 194
a406f5a3 195 while (blksize) {
7659150c
PO		 196 if (!sg_miter_next(&host->sg_miter))
197 BUG();
d129bceb 198
7659150c 199 len = min(host->sg_miter.length, blksize);
d129bceb 200
7659150c
PO		 201 blksize -= len;
202 host->sg_miter.consumed = len;
14d836e7 203
7659150c 204 buf = host->sg_miter.addr;
d129bceb 205
7659150c
PO		 206 while (len) {
207 if (chunk == 0) {
4e4141a5 208 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 209 chunk = 4;
a406f5a3 210 }
7659150c
PO		 211
212 *buf = scratch & 0xFF;
213
214 buf++;
215 scratch >>= 8;
216 chunk--;
217 len--;
d129bceb 218 }
a406f5a3 219 }
7659150c
PO		 220
221 sg_miter_stop(&host->sg_miter);
222
223 local_irq_restore(flags);
a406f5a3 224}
d129bceb 225
a406f5a3
PO		 226static void sdhci_write_block_pio(struct sdhci_host *host)
227{
7659150c
PO		 228 unsigned long flags;
229 size_t blksize, len, chunk;
230 u32 scratch;
231 u8 *buf;
d129bceb 232
a406f5a3
PO		 233 DBG("PIO writing\n");
234
235 blksize = host->data->blksz;
7659150c
PO		 236 chunk = 0;
237 scratch = 0;
d129bceb 238
7659150c 239 local_irq_save(flags);
d129bceb 240
a406f5a3 241 while (blksize) {
7659150c
PO		 242 if (!sg_miter_next(&host->sg_miter))
243 BUG();
a406f5a3 244
7659150c
PO		 245 len = min(host->sg_miter.length, blksize);
246
247 blksize -= len;
248 host->sg_miter.consumed = len;
249
250 buf = host->sg_miter.addr;
d129bceb 251
7659150c
PO		 252 while (len) {
253 scratch |= (u32)*buf << (chunk * 8);
254
255 buf++;
256 chunk++;
257 len--;
258
259 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 260 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 261 chunk = 0;
262 scratch = 0;
d129bceb 263 }
d129bceb
PO		 264 }
265 }
7659150c
PO		 266
267 sg_miter_stop(&host->sg_miter);
268
269 local_irq_restore(flags);
a406f5a3
PO		 270}
271
272static void sdhci_transfer_pio(struct sdhci_host *host)
273{
274 u32 mask;
275
276 BUG_ON(!host->data);
277
7659150c 278 if (host->blocks == 0)
a406f5a3
PO		 279 return;
280
281 if (host->data->flags & MMC_DATA_READ)
282 mask = SDHCI_DATA_AVAILABLE;
283 else
284 mask = SDHCI_SPACE_AVAILABLE;
285
4a3cba32
PO		 286 /*
287 * Some controllers (JMicron JMB38x) mess up the buffer bits
288 * for transfers < 4 bytes. As long as it is just one block,
289 * we can ignore the bits.
290 */
291 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
292 (host->data->blocks == 1))
293 mask = ~0;
294
4e4141a5 295 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
a406f5a3
PO		 296 if (host->data->flags & MMC_DATA_READ)
297 sdhci_read_block_pio(host);
298 else
299 sdhci_write_block_pio(host);
d129bceb 300
7659150c
PO		 301 host->blocks--;
302 if (host->blocks == 0)
a406f5a3 303 break;
a406f5a3 304 }
d129bceb 305
a406f5a3 306 DBG("PIO transfer complete.\n");
d129bceb
PO		 307}
308
2134a922
PO		 309static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
310{
311 local_irq_save(*flags);
312 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
313}
314
315static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
316{
317 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
318 local_irq_restore(*flags);
319}
320
8f1934ce 321static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 322 struct mmc_data *data)
323{
324 int direction;
325
326 u8 *desc;
327 u8 *align;
328 dma_addr_t addr;
329 dma_addr_t align_addr;
330 int len, offset;
331
332 struct scatterlist *sg;
333 int i;
334 char *buffer;
335 unsigned long flags;
336
337 /*
338 * The spec does not specify endianness of descriptor table.
339 * We currently guess that it is LE.
340 */
341
342 if (data->flags & MMC_DATA_READ)
343 direction = DMA_FROM_DEVICE;
344 else
345 direction = DMA_TO_DEVICE;
346
347 /*
348 * The ADMA descriptor table is mapped further down as we
349 * need to fill it with data first.
350 */
351
352 host->align_addr = dma_map_single(mmc_dev(host->mmc),
353 host->align_buffer, 128 * 4, direction);
8d8bb39b 354 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 355 goto fail;
2134a922
PO		 356 BUG_ON(host->align_addr & 0x3);
357
358 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
359 data->sg, data->sg_len, direction);
8f1934ce
PO		 360 if (host->sg_count == 0)
361 goto unmap_align;
2134a922
PO		 362
363 desc = host->adma_desc;
364 align = host->align_buffer;
365
366 align_addr = host->align_addr;
367
368 for_each_sg(data->sg, sg, host->sg_count, i) {
369 addr = sg_dma_address(sg);
370 len = sg_dma_len(sg);
371
372 /*
373 * The SDHCI specification states that ADMA
374 * addresses must be 32-bit aligned. If they
375 * aren't, then we use a bounce buffer for
376 * the (up to three) bytes that screw up the
377 * alignment.
378 */
379 offset = (4 - (addr & 0x3)) & 0x3;
380 if (offset) {
381 if (data->flags & MMC_DATA_WRITE) {
382 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 383 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 384 memcpy(align, buffer, offset);
385 sdhci_kunmap_atomic(buffer, &flags);
386 }
387
388 desc[7] = (align_addr >> 24) & 0xff;
389 desc[6] = (align_addr >> 16) & 0xff;
390 desc[5] = (align_addr >> 8) & 0xff;
391 desc[4] = (align_addr >> 0) & 0xff;
392
393 BUG_ON(offset > 65536);
394
395 desc[3] = (offset >> 8) & 0xff;
396 desc[2] = (offset >> 0) & 0xff;
397
398 desc[1] = 0x00;
399 desc[0] = 0x21; /* tran, valid */
400
401 align += 4;
402 align_addr += 4;
403
404 desc += 8;
405
406 addr += offset;
407 len -= offset;
408 }
409
410 desc[7] = (addr >> 24) & 0xff;
411 desc[6] = (addr >> 16) & 0xff;
412 desc[5] = (addr >> 8) & 0xff;
413 desc[4] = (addr >> 0) & 0xff;
414
415 BUG_ON(len > 65536);
416
417 desc[3] = (len >> 8) & 0xff;
418 desc[2] = (len >> 0) & 0xff;
419
420 desc[1] = 0x00;
421 desc[0] = 0x21; /* tran, valid */
422
423 desc += 8;
424
425 /*
426 * If this triggers then we have a calculation bug
427 * somewhere. :/
428 */
429 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
430 }
431
432 /*
433 * Add a terminating entry.
434 */
435 desc[7] = 0;
436 desc[6] = 0;
437 desc[5] = 0;
438 desc[4] = 0;
439
440 desc[3] = 0;
441 desc[2] = 0;
442
443 desc[1] = 0x00;
444 desc[0] = 0x03; /* nop, end, valid */
445
446 /*
447 * Resync align buffer as we might have changed it.
448 */
449 if (data->flags & MMC_DATA_WRITE) {
450 dma_sync_single_for_device(mmc_dev(host->mmc),
451 host->align_addr, 128 * 4, direction);
452 }
453
454 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
455 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 456 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 457 goto unmap_entries;
2134a922 458 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 459
460 return 0;
461
462unmap_entries:
463 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
464 data->sg_len, direction);
465unmap_align:
466 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
467 128 * 4, direction);
468fail:
469 return -EINVAL;
2134a922
PO		 470}
471
472static void sdhci_adma_table_post(struct sdhci_host *host,
473 struct mmc_data *data)
474{
475 int direction;
476
477 struct scatterlist *sg;
478 int i, size;
479 u8 *align;
480 char *buffer;
481 unsigned long flags;
482
483 if (data->flags & MMC_DATA_READ)
484 direction = DMA_FROM_DEVICE;
485 else
486 direction = DMA_TO_DEVICE;
487
488 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
489 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
490
491 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
492 128 * 4, direction);
493
494 if (data->flags & MMC_DATA_READ) {
495 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
496 data->sg_len, direction);
497
498 align = host->align_buffer;
499
500 for_each_sg(data->sg, sg, host->sg_count, i) {
501 if (sg_dma_address(sg) & 0x3) {
502 size = 4 - (sg_dma_address(sg) & 0x3);
503
504 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 505 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 506 memcpy(buffer, align, size);
507 sdhci_kunmap_atomic(buffer, &flags);
508
509 align += 4;
510 }
511 }
512 }
513
514 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
515 data->sg_len, direction);
516}
517
ee53ab5d 518static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
d129bceb 519{
1c8cde92
PO		 520 u8 count;
521 unsigned target_timeout, current_timeout;
d129bceb 522
ee53ab5d
PO		 523 /*
524 * If the host controller provides us with an incorrect timeout
525 * value, just skip the check and use 0xE. The hardware may take
526 * longer to time out, but that's much better than having a too-short
527 * timeout value.
528 */
529 if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL))
530 return 0xE;
e538fbe8 531
1c8cde92
PO		 532 /* timeout in us */
533 target_timeout = data->timeout_ns / 1000 +
534 data->timeout_clks / host->clock;
d129bceb 535
1c8cde92
PO		 536 /*
537 * Figure out needed cycles.
538 * We do this in steps in order to fit inside a 32 bit int.
539 * The first step is the minimum timeout, which will have a
540 * minimum resolution of 6 bits:
541 * (1) 2^13*1000 > 2^22,
542 * (2) host->timeout_clk < 2^16
543 * =>
544 * (1) / (2) > 2^6
545 */
546 count = 0;
547 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
548 while (current_timeout < target_timeout) {
549 count++;
550 current_timeout <<= 1;
551 if (count >= 0xF)
552 break;
553 }
554
555 if (count >= 0xF) {
556 printk(KERN_WARNING "%s: Too large timeout requested!\n",
557 mmc_hostname(host->mmc));
558 count = 0xE;
559 }
560
ee53ab5d
PO		 561 return count;
562}
563
564static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
565{
566 u8 count;
2134a922 567 u8 ctrl;
8f1934ce 568 int ret;
ee53ab5d
PO		 569
570 WARN_ON(host->data);
571
572 if (data == NULL)
573 return;
574
575 /* Sanity checks */
576 BUG_ON(data->blksz * data->blocks > 524288);
577 BUG_ON(data->blksz > host->mmc->max_blk_size);
578 BUG_ON(data->blocks > 65535);
579
580 host->data = data;
581 host->data_early = 0;
582
583 count = sdhci_calc_timeout(host, data);
4e4141a5 584 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
d129bceb 585
c9fddbc4
PO		 586 if (host->flags & SDHCI_USE_DMA)
587 host->flags |= SDHCI_REQ_USE_DMA;
588
2134a922
PO		 589 /*
590 * FIXME: This doesn't account for merging when mapping the
591 * scatterlist.
592 */
593 if (host->flags & SDHCI_REQ_USE_DMA) {
594 int broken, i;
595 struct scatterlist *sg;
596
597 broken = 0;
598 if (host->flags & SDHCI_USE_ADMA) {
599 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
600 broken = 1;
601 } else {
602 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
603 broken = 1;
604 }
605
606 if (unlikely(broken)) {
607 for_each_sg(data->sg, sg, data->sg_len, i) {
608 if (sg->length & 0x3) {
609 DBG("Reverting to PIO because of "
610 "transfer size (%d)\n",
611 sg->length);
612 host->flags &= ~SDHCI_REQ_USE_DMA;
613 break;
614 }
615 }
616 }
c9fddbc4
PO		 617 }
618
619 /*
620 * The assumption here being that alignment is the same after
621 * translation to device address space.
622 */
2134a922
PO		 623 if (host->flags & SDHCI_REQ_USE_DMA) {
624 int broken, i;
625 struct scatterlist *sg;
626
627 broken = 0;
628 if (host->flags & SDHCI_USE_ADMA) {
629 /*
630 * As we use 3 byte chunks to work around
631 * alignment problems, we need to check this
632 * quirk.
633 */
634 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
635 broken = 1;
636 } else {
637 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
638 broken = 1;
639 }
640
641 if (unlikely(broken)) {
642 for_each_sg(data->sg, sg, data->sg_len, i) {
643 if (sg->offset & 0x3) {
644 DBG("Reverting to PIO because of "
645 "bad alignment\n");
646 host->flags &= ~SDHCI_REQ_USE_DMA;
647 break;
648 }
649 }
650 }
651 }
652
8f1934ce
PO		 653 if (host->flags & SDHCI_REQ_USE_DMA) {
654 if (host->flags & SDHCI_USE_ADMA) {
655 ret = sdhci_adma_table_pre(host, data);
656 if (ret) {
657 /*
658 * This only happens when someone fed
659 * us an invalid request.
660 */
661 WARN_ON(1);
ebd6d357 662 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 663 } else {
4e4141a5
AV		 664 sdhci_writel(host, host->adma_addr,
665 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 666 }
667 } else {
c8b3e02e 668 int sg_cnt;
8f1934ce 669
c8b3e02e 670 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 671 data->sg, data->sg_len,
672 (data->flags & MMC_DATA_READ) ?
673 DMA_FROM_DEVICE :
674 DMA_TO_DEVICE);
c8b3e02e 675 if (sg_cnt == 0) {
8f1934ce
PO		 676 /*
677 * This only happens when someone fed
678 * us an invalid request.
679 */
680 WARN_ON(1);
ebd6d357 681 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 682 } else {
719a61b4 683 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 684 sdhci_writel(host, sg_dma_address(data->sg),
685 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 686 }
687 }
688 }
689
2134a922
PO		 690 /*
691 * Always adjust the DMA selection as some controllers
692 * (e.g. JMicron) can't do PIO properly when the selection
693 * is ADMA.
694 */
695 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 696 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 697 ctrl &= ~SDHCI_CTRL_DMA_MASK;
698 if ((host->flags & SDHCI_REQ_USE_DMA) &&
699 (host->flags & SDHCI_USE_ADMA))
700 ctrl |= SDHCI_CTRL_ADMA32;
701 else
702 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 703 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 704 }
705
8f1934ce 706 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
7659150c
PO		 707 sg_miter_start(&host->sg_miter,
708 data->sg, data->sg_len, SG_MITER_ATOMIC);
709 host->blocks = data->blocks;
d129bceb 710 }
c7fa9963 711
bab76961 712 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
4e4141a5
AV		 713 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
714 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 715}
716
717static void sdhci_set_transfer_mode(struct sdhci_host *host,
718 struct mmc_data *data)
719{
720 u16 mode;
721
c7fa9963
PO		 722 if (data == NULL)
723 return;
724
e538fbe8
PO		 725 WARN_ON(!host->data);
726
c7fa9963
PO		 727 mode = SDHCI_TRNS_BLK_CNT_EN;
728 if (data->blocks > 1)
729 mode |= SDHCI_TRNS_MULTI;
730 if (data->flags & MMC_DATA_READ)
731 mode |= SDHCI_TRNS_READ;
c9fddbc4 732 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 733 mode |= SDHCI_TRNS_DMA;
734
4e4141a5 735 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 736}
737
738static void sdhci_finish_data(struct sdhci_host *host)
739{
740 struct mmc_data *data;
d129bceb
PO		 741
742 BUG_ON(!host->data);
743
744 data = host->data;
745 host->data = NULL;
746
c9fddbc4 747 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 748 if (host->flags & SDHCI_USE_ADMA)
749 sdhci_adma_table_post(host, data);
750 else {
751 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
752 data->sg_len, (data->flags & MMC_DATA_READ) ?
753 DMA_FROM_DEVICE : DMA_TO_DEVICE);
754 }
d129bceb
PO		 755 }
756
757 /*
c9b74c5b
PO		 758 * The specification states that the block count register must
759 * be updated, but it does not specify at what point in the
760 * data flow. That makes the register entirely useless to read
761 * back so we have to assume that nothing made it to the card
762 * in the event of an error.
d129bceb 763 */
c9b74c5b
PO		 764 if (data->error)
765 data->bytes_xfered = 0;
d129bceb 766 else
c9b74c5b 767 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 768
d129bceb
PO		 769 if (data->stop) {
770 /*
771 * The controller needs a reset of internal state machines
772 * upon error conditions.
773 */
17b0429d 774 if (data->error) {
d129bceb
PO		 775 sdhci_reset(host, SDHCI_RESET_CMD);
776 sdhci_reset(host, SDHCI_RESET_DATA);
777 }
778
779 sdhci_send_command(host, data->stop);
780 } else
781 tasklet_schedule(&host->finish_tasklet);
782}
783
784static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
785{
786 int flags;
fd2208d7 787 u32 mask;
7cb2c76f 788 unsigned long timeout;
d129bceb
PO		 789
790 WARN_ON(host->cmd);
791
d129bceb 792 /* Wait max 10 ms */
7cb2c76f 793 timeout = 10;
fd2208d7
PO		 794
795 mask = SDHCI_CMD_INHIBIT;
796 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
797 mask |= SDHCI_DATA_INHIBIT;
798
799 /* We shouldn't wait for data inihibit for stop commands, even
800 though they might use busy signaling */
801 if (host->mrq->data && (cmd == host->mrq->data->stop))
802 mask &= ~SDHCI_DATA_INHIBIT;
803
4e4141a5 804 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 805 if (timeout == 0) {
d129bceb 806 printk(KERN_ERR "%s: Controller never released "
acf1da45 807 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 808 sdhci_dumpregs(host);
17b0429d 809 cmd->error = -EIO;
d129bceb
PO		 810 tasklet_schedule(&host->finish_tasklet);
811 return;
812 }
7cb2c76f
PO		 813 timeout--;
814 mdelay(1);
815 }
d129bceb
PO		 816
817 mod_timer(&host->timer, jiffies + 10 * HZ);
818
819 host->cmd = cmd;
820
821 sdhci_prepare_data(host, cmd->data);
822
4e4141a5 823 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 824
c7fa9963
PO		 825 sdhci_set_transfer_mode(host, cmd->data);
826
d129bceb 827 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 828 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 829 mmc_hostname(host->mmc));
17b0429d 830 cmd->error = -EINVAL;
d129bceb
PO		 831 tasklet_schedule(&host->finish_tasklet);
832 return;
833 }
834
835 if (!(cmd->flags & MMC_RSP_PRESENT))
836 flags = SDHCI_CMD_RESP_NONE;
837 else if (cmd->flags & MMC_RSP_136)
838 flags = SDHCI_CMD_RESP_LONG;
839 else if (cmd->flags & MMC_RSP_BUSY)
840 flags = SDHCI_CMD_RESP_SHORT_BUSY;
841 else
842 flags = SDHCI_CMD_RESP_SHORT;
843
844 if (cmd->flags & MMC_RSP_CRC)
845 flags |= SDHCI_CMD_CRC;
846 if (cmd->flags & MMC_RSP_OPCODE)
847 flags |= SDHCI_CMD_INDEX;
848 if (cmd->data)
849 flags |= SDHCI_CMD_DATA;
850
4e4141a5 851 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 852}
853
854static void sdhci_finish_command(struct sdhci_host *host)
855{
856 int i;
857
858 BUG_ON(host->cmd == NULL);
859
860 if (host->cmd->flags & MMC_RSP_PRESENT) {
861 if (host->cmd->flags & MMC_RSP_136) {
862 /* CRC is stripped so we need to do some shifting. */
863 for (i = 0;i < 4;i++) {
4e4141a5 864 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 865 SDHCI_RESPONSE + (3-i)*4) << 8;
866 if (i != 3)
867 host->cmd->resp[i] |=
4e4141a5 868 sdhci_readb(host,
d129bceb
PO		 869 SDHCI_RESPONSE + (3-i)*4-1);
870 }
871 } else {
4e4141a5 872 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 873 }
874 }
875
17b0429d 876 host->cmd->error = 0;
d129bceb 877
e538fbe8
PO		 878 if (host->data && host->data_early)
879 sdhci_finish_data(host);
880
881 if (!host->cmd->data)
d129bceb
PO		 882 tasklet_schedule(&host->finish_tasklet);
883
884 host->cmd = NULL;
885}
886
887static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
888{
889 int div;
890 u16 clk;
7cb2c76f 891 unsigned long timeout;
d129bceb
PO		 892
893 if (clock == host->clock)
894 return;
895
4e4141a5 896 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 897
898 if (clock == 0)
899 goto out;
900
901 for (div = 1;div < 256;div *= 2) {
902 if ((host->max_clk / div) <= clock)
903 break;
904 }
905 div >>= 1;
906
907 clk = div << SDHCI_DIVIDER_SHIFT;
908 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 909 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 910
911 /* Wait max 10 ms */
7cb2c76f 912 timeout = 10;
4e4141a5 913 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 914 & SDHCI_CLOCK_INT_STABLE)) {
915 if (timeout == 0) {
acf1da45
PO		 916 printk(KERN_ERR "%s: Internal clock never "
917 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 918 sdhci_dumpregs(host);
919 return;
920 }
7cb2c76f
PO		 921 timeout--;
922 mdelay(1);
923 }
d129bceb
PO		 924
925 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 926 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 927
928out:
929 host->clock = clock;
930}
931
146ad66e
PO		 932static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
933{
934 u8 pwr;
935
936 if (host->power == power)
937 return;
938
9e9dc5f2 939 if (power == (unsigned short)-1) {
4e4141a5 940 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 941 goto out;
9e9dc5f2
DS		 942 }
943
944 /*
945 * Spec says that we should clear the power reg before setting
946 * a new value. Some controllers don't seem to like this though.
947 */
b8c86fc5 948 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 949 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e
PO		 950
951 pwr = SDHCI_POWER_ON;
952
4be34c99 953 switch (1 << power) {
55556da0 954 case MMC_VDD_165_195:
146ad66e
PO		 955 pwr |= SDHCI_POWER_180;
956 break;
4be34c99
PL		 957 case MMC_VDD_29_30:
958 case MMC_VDD_30_31:
146ad66e
PO		 959 pwr |= SDHCI_POWER_300;
960 break;
4be34c99
PL		 961 case MMC_VDD_32_33:
962 case MMC_VDD_33_34:
146ad66e
PO		 963 pwr |= SDHCI_POWER_330;
964 break;
965 default:
966 BUG();
967 }
968
e08c1694 969 /*
c71f6512 970 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 971 * and set turn on power at the same time, so set the voltage first.
972 */
b8c86fc5 973 if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
4e4141a5 974 sdhci_writeb(host, pwr & ~SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
e08c1694 975
4e4141a5 976 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
146ad66e
PO		 977
978out:
979 host->power = power;
980}
981
d129bceb
PO		 982/*****************************************************************************\
983 * *
984 * MMC callbacks *
985 * *
986\*****************************************************************************/
987
988static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
989{
990 struct sdhci_host *host;
991 unsigned long flags;
992
993 host = mmc_priv(mmc);
994
995 spin_lock_irqsave(&host->lock, flags);
996
997 WARN_ON(host->mrq != NULL);
998
f9134319 999#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1000 sdhci_activate_led(host);
2f730fec 1001#endif
d129bceb
PO		 1002
1003 host->mrq = mrq;
1004
4e4141a5 1005 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
1e72859e 1006 || (host->flags & SDHCI_DEVICE_DEAD)) {
17b0429d 1007 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1008 tasklet_schedule(&host->finish_tasklet);
1009 } else
1010 sdhci_send_command(host, mrq->cmd);
1011
5f25a66f 1012 mmiowb();
d129bceb
PO		 1013 spin_unlock_irqrestore(&host->lock, flags);
1014}
1015
1016static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1017{
1018 struct sdhci_host *host;
1019 unsigned long flags;
1020 u8 ctrl;
1021
1022 host = mmc_priv(mmc);
1023
1024 spin_lock_irqsave(&host->lock, flags);
1025
1e72859e
PO		 1026 if (host->flags & SDHCI_DEVICE_DEAD)
1027 goto out;
1028
d129bceb
PO		 1029 /*
1030 * Reset the chip on each power off.
1031 * Should clear out any weird states.
1032 */
1033 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1034 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb 1035 sdhci_init(host);
d129bceb
PO		 1036 }
1037
1038 sdhci_set_clock(host, ios->clock);
1039
1040 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1041 sdhci_set_power(host, -1);
d129bceb 1042 else
146ad66e 1043 sdhci_set_power(host, ios->vdd);
d129bceb 1044
4e4141a5 1045 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1046
d129bceb
PO		 1047 if (ios->bus_width == MMC_BUS_WIDTH_4)
1048 ctrl |= SDHCI_CTRL_4BITBUS;
1049 else
1050 ctrl &= ~SDHCI_CTRL_4BITBUS;
cd9277c0
PO		 1051
1052 if (ios->timing == MMC_TIMING_SD_HS)
1053 ctrl |= SDHCI_CTRL_HISPD;
1054 else
1055 ctrl &= ~SDHCI_CTRL_HISPD;
1056
4e4141a5 1057 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb 1058
b8352260
LD		 1059 /*
1060 * Some (ENE) controllers go apeshit on some ios operation,
1061 * signalling timeout and CRC errors even on CMD0. Resetting
1062 * it on each ios seems to solve the problem.
1063 */
b8c86fc5 1064 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1065 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1066
1e72859e 1067out:
5f25a66f 1068 mmiowb();
d129bceb
PO		 1069 spin_unlock_irqrestore(&host->lock, flags);
1070}
1071
1072static int sdhci_get_ro(struct mmc_host *mmc)
1073{
1074 struct sdhci_host *host;
1075 unsigned long flags;
1076 int present;
1077
1078 host = mmc_priv(mmc);
1079
1080 spin_lock_irqsave(&host->lock, flags);
1081
1e72859e
PO		 1082 if (host->flags & SDHCI_DEVICE_DEAD)
1083 present = 0;
1084 else
4e4141a5 1085 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
d129bceb
PO		 1086
1087 spin_unlock_irqrestore(&host->lock, flags);
1088
1089 return !(present & SDHCI_WRITE_PROTECT);
1090}
1091
f75979b7
PO		 1092static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1093{
1094 struct sdhci_host *host;
1095 unsigned long flags;
1096 u32 ier;
1097
1098 host = mmc_priv(mmc);
1099
1100 spin_lock_irqsave(&host->lock, flags);
1101
1e72859e
PO		 1102 if (host->flags & SDHCI_DEVICE_DEAD)
1103 goto out;
1104
4e4141a5 1105 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
f75979b7
PO		 1106
1107 ier &= ~SDHCI_INT_CARD_INT;
1108 if (enable)
1109 ier |= SDHCI_INT_CARD_INT;
1110
4e4141a5
AV		 1111 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
1112 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
f75979b7 1113
1e72859e 1114out:
f75979b7
PO		 1115 mmiowb();
1116
1117 spin_unlock_irqrestore(&host->lock, flags);
1118}
1119
ab7aefd0 1120static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1121 .request = sdhci_request,
1122 .set_ios = sdhci_set_ios,
1123 .get_ro = sdhci_get_ro,
f75979b7 1124 .enable_sdio_irq = sdhci_enable_sdio_irq,
d129bceb
PO		 1125};
1126
1127/*****************************************************************************\
1128 * *
1129 * Tasklets *
1130 * *
1131\*****************************************************************************/
1132
1133static void sdhci_tasklet_card(unsigned long param)
1134{
1135 struct sdhci_host *host;
1136 unsigned long flags;
1137
1138 host = (struct sdhci_host*)param;
1139
1140 spin_lock_irqsave(&host->lock, flags);
1141
4e4141a5 1142 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
d129bceb
PO		 1143 if (host->mrq) {
1144 printk(KERN_ERR "%s: Card removed during transfer!\n",
1145 mmc_hostname(host->mmc));
1146 printk(KERN_ERR "%s: Resetting controller.\n",
1147 mmc_hostname(host->mmc));
1148
1149 sdhci_reset(host, SDHCI_RESET_CMD);
1150 sdhci_reset(host, SDHCI_RESET_DATA);
1151
17b0429d 1152 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1153 tasklet_schedule(&host->finish_tasklet);
1154 }
1155 }
1156
1157 spin_unlock_irqrestore(&host->lock, flags);
1158
04cf585d 1159 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1160}
1161
1162static void sdhci_tasklet_finish(unsigned long param)
1163{
1164 struct sdhci_host *host;
1165 unsigned long flags;
1166 struct mmc_request *mrq;
1167
1168 host = (struct sdhci_host*)param;
1169
1170 spin_lock_irqsave(&host->lock, flags);
1171
1172 del_timer(&host->timer);
1173
1174 mrq = host->mrq;
1175
d129bceb
PO		 1176 /*
1177 * The controller needs a reset of internal state machines
1178 * upon error conditions.
1179 */
1e72859e
PO		 1180 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1181 (mrq->cmd->error ||
1182 (mrq->data && (mrq->data->error ||
1183 (mrq->data->stop && mrq->data->stop->error))) ||
1184 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1185
1186 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1187 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1188 unsigned int clock;
1189
1190 /* This is to force an update */
1191 clock = host->clock;
1192 host->clock = 0;
1193 sdhci_set_clock(host, clock);
1194 }
1195
1196 /* Spec says we should do both at the same time, but Ricoh
1197 controllers do not like that. */
d129bceb
PO		 1198 sdhci_reset(host, SDHCI_RESET_CMD);
1199 sdhci_reset(host, SDHCI_RESET_DATA);
1200 }
1201
1202 host->mrq = NULL;
1203 host->cmd = NULL;
1204 host->data = NULL;
1205
f9134319 1206#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1207 sdhci_deactivate_led(host);
2f730fec 1208#endif
d129bceb 1209
5f25a66f 1210 mmiowb();
d129bceb
PO		 1211 spin_unlock_irqrestore(&host->lock, flags);
1212
1213 mmc_request_done(host->mmc, mrq);
1214}
1215
1216static void sdhci_timeout_timer(unsigned long data)
1217{
1218 struct sdhci_host *host;
1219 unsigned long flags;
1220
1221 host = (struct sdhci_host*)data;
1222
1223 spin_lock_irqsave(&host->lock, flags);
1224
1225 if (host->mrq) {
acf1da45
PO		 1226 printk(KERN_ERR "%s: Timeout waiting for hardware "
1227 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1228 sdhci_dumpregs(host);
1229
1230 if (host->data) {
17b0429d 1231 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1232 sdhci_finish_data(host);
1233 } else {
1234 if (host->cmd)
17b0429d 1235 host->cmd->error = -ETIMEDOUT;
d129bceb 1236 else
17b0429d 1237 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1238
1239 tasklet_schedule(&host->finish_tasklet);
1240 }
1241 }
1242
5f25a66f 1243 mmiowb();
d129bceb
PO		 1244 spin_unlock_irqrestore(&host->lock, flags);
1245}
1246
1247/*****************************************************************************\
1248 * *
1249 * Interrupt handling *
1250 * *
1251\*****************************************************************************/
1252
1253static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1254{
1255 BUG_ON(intmask == 0);
1256
1257 if (!host->cmd) {
b67ac3f3
PO		 1258 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1259 "though no command operation was in progress.\n",
1260 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1261 sdhci_dumpregs(host);
1262 return;
1263 }
1264
43b58b36 1265 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1266 host->cmd->error = -ETIMEDOUT;
1267 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1268 SDHCI_INT_INDEX))
1269 host->cmd->error = -EILSEQ;
43b58b36 1270
e809517f 1271 if (host->cmd->error) {
d129bceb 1272 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 1273 return;
1274 }
1275
1276 /*
1277 * The host can send and interrupt when the busy state has
1278 * ended, allowing us to wait without wasting CPU cycles.
1279 * Unfortunately this is overloaded on the "data complete"
1280 * interrupt, so we need to take some care when handling
1281 * it.
1282 *
1283 * Note: The 1.0 specification is a bit ambiguous about this
1284 * feature so there might be some problems with older
1285 * controllers.
1286 */
1287 if (host->cmd->flags & MMC_RSP_BUSY) {
1288 if (host->cmd->data)
1289 DBG("Cannot wait for busy signal when also "
1290 "doing a data transfer");
f945405c 1291 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 1292 return;
f945405c
BD		 1293
1294 /* The controller does not support the end-of-busy IRQ,
1295 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 1296 }
1297
1298 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 1299 sdhci_finish_command(host);
d129bceb
PO		 1300}
1301
1302static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1303{
1304 BUG_ON(intmask == 0);
1305
1306 if (!host->data) {
1307 /*
e809517f
PO		 1308 * The "data complete" interrupt is also used to
1309 * indicate that a busy state has ended. See comment
1310 * above in sdhci_cmd_irq().
d129bceb 1311 */
e809517f
PO		 1312 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1313 if (intmask & SDHCI_INT_DATA_END) {
1314 sdhci_finish_command(host);
1315 return;
1316 }
1317 }
d129bceb 1318
b67ac3f3
PO		 1319 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1320 "though no data operation was in progress.\n",
1321 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1322 sdhci_dumpregs(host);
1323
1324 return;
1325 }
1326
1327 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d
PO		 1328 host->data->error = -ETIMEDOUT;
1329 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1330 host->data->error = -EILSEQ;
2134a922
PO		 1331 else if (intmask & SDHCI_INT_ADMA_ERROR)
1332 host->data->error = -EIO;
d129bceb 1333
17b0429d 1334 if (host->data->error)
d129bceb
PO		 1335 sdhci_finish_data(host);
1336 else {
a406f5a3 1337 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1338 sdhci_transfer_pio(host);
1339
6ba736a1
PO		 1340 /*
1341 * We currently don't do anything fancy with DMA
1342 * boundaries, but as we can't disable the feature
1343 * we need to at least restart the transfer.
1344 */
1345 if (intmask & SDHCI_INT_DMA_END)
4e4141a5
AV		 1346 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1347 SDHCI_DMA_ADDRESS);
6ba736a1 1348
e538fbe8
PO		 1349 if (intmask & SDHCI_INT_DATA_END) {
1350 if (host->cmd) {
1351 /*
1352 * Data managed to finish before the
1353 * command completed. Make sure we do
1354 * things in the proper order.
1355 */
1356 host->data_early = 1;
1357 } else {
1358 sdhci_finish_data(host);
1359 }
1360 }
d129bceb
PO		 1361 }
1362}
1363
7d12e780 1364static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1365{
1366 irqreturn_t result;
1367 struct sdhci_host* host = dev_id;
1368 u32 intmask;
f75979b7 1369 int cardint = 0;
d129bceb
PO		 1370
1371 spin_lock(&host->lock);
1372
4e4141a5 1373 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 1374
62df67a5 1375 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1376 result = IRQ_NONE;
1377 goto out;
1378 }
1379
b69c9058
PO		 1380 DBG("*** %s got interrupt: 0x%08x\n",
1381 mmc_hostname(host->mmc), intmask);
d129bceb 1382
3192a28f 1383 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
4e4141a5
AV		 1384 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1385 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
d129bceb 1386 tasklet_schedule(&host->card_tasklet);
3192a28f 1387 }
d129bceb 1388
3192a28f 1389 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1390
3192a28f 1391 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 1392 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1393 SDHCI_INT_STATUS);
3192a28f 1394 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1395 }
1396
1397 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 1398 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1399 SDHCI_INT_STATUS);
3192a28f 1400 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1401 }
1402
1403 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1404
964f9ce2
PO		 1405 intmask &= ~SDHCI_INT_ERROR;
1406
d129bceb 1407 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1408 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1409 mmc_hostname(host->mmc));
4e4141a5 1410 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 1411 }
1412
9d26a5d3 1413 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 1414
f75979b7
PO		 1415 if (intmask & SDHCI_INT_CARD_INT)
1416 cardint = 1;
1417
1418 intmask &= ~SDHCI_INT_CARD_INT;
1419
3192a28f 1420 if (intmask) {
acf1da45 1421 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1422 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1423 sdhci_dumpregs(host);
1424
4e4141a5 1425 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 1426 }
d129bceb
PO		 1427
1428 result = IRQ_HANDLED;
1429
5f25a66f 1430 mmiowb();
d129bceb
PO		 1431out:
1432 spin_unlock(&host->lock);
1433
f75979b7
PO		 1434 /*
1435 * We have to delay this as it calls back into the driver.
1436 */
1437 if (cardint)
1438 mmc_signal_sdio_irq(host->mmc);
1439
d129bceb
PO		 1440 return result;
1441}
1442
1443/*****************************************************************************\
1444 * *
1445 * Suspend/resume *
1446 * *
1447\*****************************************************************************/
1448
1449#ifdef CONFIG_PM
1450
b8c86fc5 1451int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 1452{
b8c86fc5 1453 int ret;
a715dfc7 1454
b8c86fc5
PO		 1455 ret = mmc_suspend_host(host->mmc, state);
1456 if (ret)
1457 return ret;
a715dfc7 1458
b8c86fc5 1459 free_irq(host->irq, host);
d129bceb
PO		 1460
1461 return 0;
1462}
1463
b8c86fc5 1464EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 1465
b8c86fc5
PO		 1466int sdhci_resume_host(struct sdhci_host *host)
1467{
1468 int ret;
d129bceb 1469
b8c86fc5
PO		 1470 if (host->flags & SDHCI_USE_DMA) {
1471 if (host->ops->enable_dma)
1472 host->ops->enable_dma(host);
1473 }
d129bceb 1474
b8c86fc5
PO		 1475 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1476 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 1477 if (ret)
1478 return ret;
d129bceb 1479
b8c86fc5
PO		 1480 sdhci_init(host);
1481 mmiowb();
1482
1483 ret = mmc_resume_host(host->mmc);
1484 if (ret)
1485 return ret;
d129bceb
PO		 1486
1487 return 0;
1488}
1489
b8c86fc5 1490EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 1491
1492#endif /* CONFIG_PM */
1493
1494/*****************************************************************************\
1495 * *
b8c86fc5 1496 * Device allocation/registration *
d129bceb
PO		 1497 * *
1498\*****************************************************************************/
1499
b8c86fc5
PO		 1500struct sdhci_host *sdhci_alloc_host(struct device *dev,
1501 size_t priv_size)
d129bceb 1502{
d129bceb
PO		 1503 struct mmc_host *mmc;
1504 struct sdhci_host *host;
1505
b8c86fc5 1506 WARN_ON(dev == NULL);
d129bceb 1507
b8c86fc5 1508 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 1509 if (!mmc)
b8c86fc5 1510 return ERR_PTR(-ENOMEM);
d129bceb
PO		 1511
1512 host = mmc_priv(mmc);
1513 host->mmc = mmc;
1514
b8c86fc5
PO		 1515 return host;
1516}
8a4da143 1517
b8c86fc5 1518EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 1519
b8c86fc5
PO		 1520int sdhci_add_host(struct sdhci_host *host)
1521{
1522 struct mmc_host *mmc;
1523 unsigned int caps;
b8c86fc5 1524 int ret;
d129bceb 1525
b8c86fc5
PO		 1526 WARN_ON(host == NULL);
1527 if (host == NULL)
1528 return -EINVAL;
d129bceb 1529
b8c86fc5 1530 mmc = host->mmc;
d129bceb 1531
b8c86fc5
PO		 1532 if (debug_quirks)
1533 host->quirks = debug_quirks;
d129bceb 1534
d96649ed
PO		 1535 sdhci_reset(host, SDHCI_RESET_ALL);
1536
4e4141a5 1537 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 1538 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1539 >> SDHCI_SPEC_VER_SHIFT;
1540 if (host->version > SDHCI_SPEC_200) {
4a965505 1541 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 1542 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 1543 host->version);
4a965505
PO		 1544 }
1545
4e4141a5 1546 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 1547
b8c86fc5 1548 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
98608076 1549 host->flags |= SDHCI_USE_DMA;
67435274
PO		 1550 else if (!(caps & SDHCI_CAN_DO_DMA))
1551 DBG("Controller doesn't have DMA capability\n");
1552 else
d129bceb
PO		 1553 host->flags |= SDHCI_USE_DMA;
1554
b8c86fc5 1555 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
7c168e3d 1556 (host->flags & SDHCI_USE_DMA)) {
cee687ce 1557 DBG("Disabling DMA as it is marked broken\n");
7c168e3d
FT		 1558 host->flags &= ~SDHCI_USE_DMA;
1559 }
1560
2134a922
PO		 1561 if (host->flags & SDHCI_USE_DMA) {
1562 if ((host->version >= SDHCI_SPEC_200) &&
1563 (caps & SDHCI_CAN_DO_ADMA2))
1564 host->flags |= SDHCI_USE_ADMA;
1565 }
1566
1567 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1568 (host->flags & SDHCI_USE_ADMA)) {
1569 DBG("Disabling ADMA as it is marked broken\n");
1570 host->flags &= ~SDHCI_USE_ADMA;
1571 }
1572
d129bceb 1573 if (host->flags & SDHCI_USE_DMA) {
b8c86fc5
PO		 1574 if (host->ops->enable_dma) {
1575 if (host->ops->enable_dma(host)) {
1576 printk(KERN_WARNING "%s: No suitable DMA "
1577 "available. Falling back to PIO.\n",
1578 mmc_hostname(mmc));
2134a922 1579 host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA);
b8c86fc5 1580 }
d129bceb
PO		 1581 }
1582 }
1583
2134a922
PO		 1584 if (host->flags & SDHCI_USE_ADMA) {
1585 /*
1586 * We need to allocate descriptors for all sg entries
1587 * (128) and potentially one alignment transfer for
1588 * each of those entries.
1589 */
1590 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1591 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1592 if (!host->adma_desc || !host->align_buffer) {
1593 kfree(host->adma_desc);
1594 kfree(host->align_buffer);
1595 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1596 "buffers. Falling back to standard DMA.\n",
1597 mmc_hostname(mmc));
1598 host->flags &= ~SDHCI_USE_ADMA;
1599 }
1600 }
1601
7659150c
PO		 1602 /*
1603 * If we use DMA, then it's up to the caller to set the DMA
1604 * mask, but PIO does not need the hw shim so we set a new
1605 * mask here in that case.
1606 */
1607 if (!(host->flags & SDHCI_USE_DMA)) {
1608 host->dma_mask = DMA_BIT_MASK(64);
1609 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1610 }
d129bceb 1611
8ef1a143
PO		 1612 host->max_clk =
1613 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1614 if (host->max_clk == 0) {
1615 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
b69c9058 1616 "frequency.\n", mmc_hostname(mmc));
b8c86fc5 1617 return -ENODEV;
8ef1a143 1618 }
d129bceb
PO		 1619 host->max_clk *= 1000000;
1620
1c8cde92
PO		 1621 host->timeout_clk =
1622 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1623 if (host->timeout_clk == 0) {
1624 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
b69c9058 1625 "frequency.\n", mmc_hostname(mmc));
b8c86fc5 1626 return -ENODEV;
1c8cde92
PO		 1627 }
1628 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1629 host->timeout_clk *= 1000;
d129bceb
PO		 1630
1631 /*
1632 * Set host parameters.
1633 */
1634 mmc->ops = &sdhci_ops;
1635 mmc->f_min = host->max_clk / 256;
1636 mmc->f_max = host->max_clk;
c9b74c5b 1637 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
d129bceb 1638
86a6a874 1639 if (caps & SDHCI_CAN_DO_HISPD)
cd9277c0
PO		 1640 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1641
146ad66e
PO		 1642 mmc->ocr_avail = 0;
1643 if (caps & SDHCI_CAN_VDD_330)
1644 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1645 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1646 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1647 if (caps & SDHCI_CAN_VDD_180)
55556da0 1648 mmc->ocr_avail |= MMC_VDD_165_195;
146ad66e
PO		 1649
1650 if (mmc->ocr_avail == 0) {
1651 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 1652 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 1653 return -ENODEV;
146ad66e
PO		 1654 }
1655
d129bceb
PO		 1656 spin_lock_init(&host->lock);
1657
1658 /*
2134a922
PO		 1659 * Maximum number of segments. Depends on if the hardware
1660 * can do scatter/gather or not.
d129bceb 1661 */
2134a922
PO		 1662 if (host->flags & SDHCI_USE_ADMA)
1663 mmc->max_hw_segs = 128;
1664 else if (host->flags & SDHCI_USE_DMA)
d129bceb 1665 mmc->max_hw_segs = 1;
2134a922
PO		 1666 else /* PIO */
1667 mmc->max_hw_segs = 128;
1668 mmc->max_phys_segs = 128;
d129bceb
PO		 1669
1670 /*
bab76961 1671 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1672 * size (512KiB).
d129bceb 1673 */
55db890a 1674 mmc->max_req_size = 524288;
d129bceb
PO		 1675
1676 /*
1677 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 1678 * of bytes. When doing hardware scatter/gather, each entry cannot
1679 * be larger than 64 KiB though.
d129bceb 1680 */
2134a922
PO		 1681 if (host->flags & SDHCI_USE_ADMA)
1682 mmc->max_seg_size = 65536;
1683 else
1684 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1685
fe4a3c7a
PO		 1686 /*
1687 * Maximum block size. This varies from controller to controller and
1688 * is specified in the capabilities register.
1689 */
1690 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1691 if (mmc->max_blk_size >= 3) {
b69c9058
PO		 1692 printk(KERN_WARNING "%s: Invalid maximum block size, "
1693 "assuming 512 bytes\n", mmc_hostname(mmc));
03f8590d
DV		 1694 mmc->max_blk_size = 512;
1695 } else
1696 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 1697
55db890a
PO		 1698 /*
1699 * Maximum block count.
1700 */
1701 mmc->max_blk_count = 65535;
1702
d129bceb
PO		 1703 /*
1704 * Init tasklets.
1705 */
1706 tasklet_init(&host->card_tasklet,
1707 sdhci_tasklet_card, (unsigned long)host);
1708 tasklet_init(&host->finish_tasklet,
1709 sdhci_tasklet_finish, (unsigned long)host);
1710
e4cad1b5 1711 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1712
dace1453 1713 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 1714 mmc_hostname(mmc), host);
d129bceb 1715 if (ret)
8ef1a143 1716 goto untasklet;
d129bceb
PO		 1717
1718 sdhci_init(host);
1719
1720#ifdef CONFIG_MMC_DEBUG
1721 sdhci_dumpregs(host);
1722#endif
1723
f9134319 1724#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 1725 snprintf(host->led_name, sizeof(host->led_name),
1726 "%s::", mmc_hostname(mmc));
1727 host->led.name = host->led_name;
2f730fec
PO		 1728 host->led.brightness = LED_OFF;
1729 host->led.default_trigger = mmc_hostname(mmc);
1730 host->led.brightness_set = sdhci_led_control;
1731
b8c86fc5 1732 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 1733 if (ret)
1734 goto reset;
1735#endif
1736
5f25a66f
PO		 1737 mmiowb();
1738
d129bceb
PO		 1739 mmc_add_host(mmc);
1740
2134a922 1741 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n",
d1b26863 1742 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2134a922 1743 (host->flags & SDHCI_USE_ADMA)?"A":"",
d129bceb
PO		 1744 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1745
1746 return 0;
1747
f9134319 1748#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 1749reset:
1750 sdhci_reset(host, SDHCI_RESET_ALL);
1751 free_irq(host->irq, host);
1752#endif
8ef1a143 1753untasklet:
d129bceb
PO		 1754 tasklet_kill(&host->card_tasklet);
1755 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 1756
1757 return ret;
1758}
1759
b8c86fc5 1760EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 1761
1e72859e 1762void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 1763{
1e72859e
PO		 1764 unsigned long flags;
1765
1766 if (dead) {
1767 spin_lock_irqsave(&host->lock, flags);
1768
1769 host->flags |= SDHCI_DEVICE_DEAD;
1770
1771 if (host->mrq) {
1772 printk(KERN_ERR "%s: Controller removed during "
1773 " transfer!\n", mmc_hostname(host->mmc));
1774
1775 host->mrq->cmd->error = -ENOMEDIUM;
1776 tasklet_schedule(&host->finish_tasklet);
1777 }
1778
1779 spin_unlock_irqrestore(&host->lock, flags);
1780 }
1781
b8c86fc5 1782 mmc_remove_host(host->mmc);
d129bceb 1783
f9134319 1784#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 1785 led_classdev_unregister(&host->led);
1786#endif
1787
1e72859e
PO		 1788 if (!dead)
1789 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 1790
1791 free_irq(host->irq, host);
1792
1793 del_timer_sync(&host->timer);
1794
1795 tasklet_kill(&host->card_tasklet);
1796 tasklet_kill(&host->finish_tasklet);
2134a922
PO		 1797
1798 kfree(host->adma_desc);
1799 kfree(host->align_buffer);
1800
1801 host->adma_desc = NULL;
1802 host->align_buffer = NULL;
d129bceb
PO		 1803}
1804
b8c86fc5 1805EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 1806
b8c86fc5 1807void sdhci_free_host(struct sdhci_host *host)
d129bceb 1808{
b8c86fc5 1809 mmc_free_host(host->mmc);
d129bceb
PO		 1810}
1811
b8c86fc5 1812EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 1813
1814/*****************************************************************************\
1815 * *
1816 * Driver init/exit *
1817 * *
1818\*****************************************************************************/
1819
1820static int __init sdhci_drv_init(void)
1821{
1822 printk(KERN_INFO DRIVER_NAME
52fbf9c9 1823 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 1824 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1825
b8c86fc5 1826 return 0;
d129bceb
PO		 1827}
1828
1829static void __exit sdhci_drv_exit(void)
1830{
d129bceb
PO		 1831}
1832
1833module_init(sdhci_drv_init);
1834module_exit(sdhci_drv_exit);
1835
df673b22 1836module_param(debug_quirks, uint, 0444);
67435274 1837
d129bceb 1838MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
b8c86fc5 1839MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 1840MODULE_LICENSE("GPL");
67435274 1841
df673b22 1842MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux 6.x block layer and io_uring tree(s)