Commit | Line | Data |
---|---|---|
d129bceb | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
d129bceb | 3 | * |
b69c9058 | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
d129bceb PO |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
643f720c PO |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation; either version 2 of the License, or (at | |
9 | * your option) any later version. | |
84c46a53 PO |
10 | * |
11 | * Thanks to the following companies for their support: | |
12 | * | |
13 | * - JMicron (hardware and technical support) | |
d129bceb PO |
14 | */ |
15 | ||
d129bceb PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
b8c86fc5 | 18 | #include <linux/io.h> |
d129bceb | 19 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
11763609 | 21 | #include <linux/scatterlist.h> |
9bea3c85 | 22 | #include <linux/regulator/consumer.h> |
d129bceb | 23 | |
2f730fec PO |
24 | #include <linux/leds.h> |
25 | ||
22113efd | 26 | #include <linux/mmc/mmc.h> |
d129bceb | 27 | #include <linux/mmc/host.h> |
d129bceb | 28 | |
d129bceb PO |
29 | #include "sdhci.h" |
30 | ||
31 | #define DRIVER_NAME "sdhci" | |
d129bceb | 32 | |
d129bceb | 33 | #define DBG(f, x...) \ |
c6563178 | 34 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
d129bceb | 35 | |
f9134319 PO |
36 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
37 | defined(CONFIG_MMC_SDHCI_MODULE)) | |
38 | #define SDHCI_USE_LEDS_CLASS | |
39 | #endif | |
40 | ||
df673b22 | 41 | static unsigned int debug_quirks = 0; |
67435274 | 42 | |
d129bceb PO |
43 | static void sdhci_finish_data(struct sdhci_host *); |
44 | ||
45 | static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); | |
46 | static void sdhci_finish_command(struct sdhci_host *); | |
47 | ||
48 | static void sdhci_dumpregs(struct sdhci_host *host) | |
49 | { | |
412ab659 PR |
50 | printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", |
51 | mmc_hostname(host->mmc)); | |
d129bceb PO |
52 | |
53 | printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", | |
4e4141a5 AV |
54 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
55 | sdhci_readw(host, SDHCI_HOST_VERSION)); | |
d129bceb | 56 | printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
4e4141a5 AV |
57 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
58 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); | |
d129bceb | 59 | printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
4e4141a5 AV |
60 | sdhci_readl(host, SDHCI_ARGUMENT), |
61 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); | |
d129bceb | 62 | printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
4e4141a5 AV |
63 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
64 | sdhci_readb(host, SDHCI_HOST_CONTROL)); | |
d129bceb | 65 | printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
4e4141a5 AV |
66 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
67 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); | |
d129bceb | 68 | printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
4e4141a5 AV |
69 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
70 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); | |
d129bceb | 71 | printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
4e4141a5 AV |
72 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
73 | sdhci_readl(host, SDHCI_INT_STATUS)); | |
d129bceb | 74 | printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
4e4141a5 AV |
75 | sdhci_readl(host, SDHCI_INT_ENABLE), |
76 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); | |
d129bceb | 77 | printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
4e4141a5 AV |
78 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
79 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); | |
e8120ad1 | 80 | printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", |
4e4141a5 | 81 | sdhci_readl(host, SDHCI_CAPABILITIES), |
e8120ad1 PR |
82 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
83 | printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", | |
84 | sdhci_readw(host, SDHCI_COMMAND), | |
4e4141a5 | 85 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
d129bceb | 86 | |
be3f4ae0 BD |
87 | if (host->flags & SDHCI_USE_ADMA) |
88 | printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", | |
89 | readl(host->ioaddr + SDHCI_ADMA_ERROR), | |
90 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); | |
91 | ||
d129bceb PO |
92 | printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n"); |
93 | } | |
94 | ||
95 | /*****************************************************************************\ | |
96 | * * | |
97 | * Low level functions * | |
98 | * * | |
99 | \*****************************************************************************/ | |
100 | ||
7260cf5e AV |
101 | static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) |
102 | { | |
103 | u32 ier; | |
104 | ||
105 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
106 | ier &= ~clear; | |
107 | ier |= set; | |
108 | sdhci_writel(host, ier, SDHCI_INT_ENABLE); | |
109 | sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); | |
110 | } | |
111 | ||
112 | static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) | |
113 | { | |
114 | sdhci_clear_set_irqs(host, 0, irqs); | |
115 | } | |
116 | ||
117 | static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) | |
118 | { | |
119 | sdhci_clear_set_irqs(host, irqs, 0); | |
120 | } | |
121 | ||
122 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) | |
123 | { | |
124 | u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; | |
125 | ||
68d1fb7e AV |
126 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
127 | return; | |
128 | ||
7260cf5e AV |
129 | if (enable) |
130 | sdhci_unmask_irqs(host, irqs); | |
131 | else | |
132 | sdhci_mask_irqs(host, irqs); | |
133 | } | |
134 | ||
135 | static void sdhci_enable_card_detection(struct sdhci_host *host) | |
136 | { | |
137 | sdhci_set_card_detection(host, true); | |
138 | } | |
139 | ||
140 | static void sdhci_disable_card_detection(struct sdhci_host *host) | |
141 | { | |
142 | sdhci_set_card_detection(host, false); | |
143 | } | |
144 | ||
d129bceb PO |
145 | static void sdhci_reset(struct sdhci_host *host, u8 mask) |
146 | { | |
e16514d8 | 147 | unsigned long timeout; |
063a9dbb | 148 | u32 uninitialized_var(ier); |
e16514d8 | 149 | |
b8c86fc5 | 150 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
4e4141a5 | 151 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & |
8a4da143 PO |
152 | SDHCI_CARD_PRESENT)) |
153 | return; | |
154 | } | |
155 | ||
063a9dbb AV |
156 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) |
157 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); | |
158 | ||
393c1a34 PR |
159 | if (host->ops->platform_reset_enter) |
160 | host->ops->platform_reset_enter(host, mask); | |
161 | ||
4e4141a5 | 162 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
d129bceb | 163 | |
e16514d8 | 164 | if (mask & SDHCI_RESET_ALL) |
d129bceb PO |
165 | host->clock = 0; |
166 | ||
e16514d8 PO |
167 | /* Wait max 100 ms */ |
168 | timeout = 100; | |
169 | ||
170 | /* hw clears the bit when it's done */ | |
4e4141a5 | 171 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
e16514d8 | 172 | if (timeout == 0) { |
acf1da45 | 173 | printk(KERN_ERR "%s: Reset 0x%x never completed.\n", |
e16514d8 PO |
174 | mmc_hostname(host->mmc), (int)mask); |
175 | sdhci_dumpregs(host); | |
176 | return; | |
177 | } | |
178 | timeout--; | |
179 | mdelay(1); | |
d129bceb | 180 | } |
063a9dbb | 181 | |
393c1a34 PR |
182 | if (host->ops->platform_reset_exit) |
183 | host->ops->platform_reset_exit(host, mask); | |
184 | ||
063a9dbb AV |
185 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) |
186 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); | |
d129bceb PO |
187 | } |
188 | ||
2f4cbb3d NP |
189 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
190 | ||
191 | static void sdhci_init(struct sdhci_host *host, int soft) | |
d129bceb | 192 | { |
2f4cbb3d NP |
193 | if (soft) |
194 | sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); | |
195 | else | |
196 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb | 197 | |
7260cf5e AV |
198 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, |
199 | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | | |
3192a28f PO |
200 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | |
201 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | | |
6aa943ab | 202 | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); |
2f4cbb3d NP |
203 | |
204 | if (soft) { | |
205 | /* force clock reconfiguration */ | |
206 | host->clock = 0; | |
207 | sdhci_set_ios(host->mmc, &host->mmc->ios); | |
208 | } | |
7260cf5e | 209 | } |
d129bceb | 210 | |
7260cf5e AV |
211 | static void sdhci_reinit(struct sdhci_host *host) |
212 | { | |
2f4cbb3d | 213 | sdhci_init(host, 0); |
7260cf5e | 214 | sdhci_enable_card_detection(host); |
d129bceb PO |
215 | } |
216 | ||
217 | static void sdhci_activate_led(struct sdhci_host *host) | |
218 | { | |
219 | u8 ctrl; | |
220 | ||
4e4141a5 | 221 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 222 | ctrl |= SDHCI_CTRL_LED; |
4e4141a5 | 223 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
224 | } |
225 | ||
226 | static void sdhci_deactivate_led(struct sdhci_host *host) | |
227 | { | |
228 | u8 ctrl; | |
229 | ||
4e4141a5 | 230 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
d129bceb | 231 | ctrl &= ~SDHCI_CTRL_LED; |
4e4141a5 | 232 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb PO |
233 | } |
234 | ||
f9134319 | 235 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
236 | static void sdhci_led_control(struct led_classdev *led, |
237 | enum led_brightness brightness) | |
238 | { | |
239 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); | |
240 | unsigned long flags; | |
241 | ||
242 | spin_lock_irqsave(&host->lock, flags); | |
243 | ||
244 | if (brightness == LED_OFF) | |
245 | sdhci_deactivate_led(host); | |
246 | else | |
247 | sdhci_activate_led(host); | |
248 | ||
249 | spin_unlock_irqrestore(&host->lock, flags); | |
250 | } | |
251 | #endif | |
252 | ||
d129bceb PO |
253 | /*****************************************************************************\ |
254 | * * | |
255 | * Core functions * | |
256 | * * | |
257 | \*****************************************************************************/ | |
258 | ||
a406f5a3 | 259 | static void sdhci_read_block_pio(struct sdhci_host *host) |
d129bceb | 260 | { |
7659150c PO |
261 | unsigned long flags; |
262 | size_t blksize, len, chunk; | |
7244b85b | 263 | u32 uninitialized_var(scratch); |
7659150c | 264 | u8 *buf; |
d129bceb | 265 | |
a406f5a3 | 266 | DBG("PIO reading\n"); |
d129bceb | 267 | |
a406f5a3 | 268 | blksize = host->data->blksz; |
7659150c | 269 | chunk = 0; |
d129bceb | 270 | |
7659150c | 271 | local_irq_save(flags); |
d129bceb | 272 | |
a406f5a3 | 273 | while (blksize) { |
7659150c PO |
274 | if (!sg_miter_next(&host->sg_miter)) |
275 | BUG(); | |
d129bceb | 276 | |
7659150c | 277 | len = min(host->sg_miter.length, blksize); |
d129bceb | 278 | |
7659150c PO |
279 | blksize -= len; |
280 | host->sg_miter.consumed = len; | |
14d836e7 | 281 | |
7659150c | 282 | buf = host->sg_miter.addr; |
d129bceb | 283 | |
7659150c PO |
284 | while (len) { |
285 | if (chunk == 0) { | |
4e4141a5 | 286 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
7659150c | 287 | chunk = 4; |
a406f5a3 | 288 | } |
7659150c PO |
289 | |
290 | *buf = scratch & 0xFF; | |
291 | ||
292 | buf++; | |
293 | scratch >>= 8; | |
294 | chunk--; | |
295 | len--; | |
d129bceb | 296 | } |
a406f5a3 | 297 | } |
7659150c PO |
298 | |
299 | sg_miter_stop(&host->sg_miter); | |
300 | ||
301 | local_irq_restore(flags); | |
a406f5a3 | 302 | } |
d129bceb | 303 | |
a406f5a3 PO |
304 | static void sdhci_write_block_pio(struct sdhci_host *host) |
305 | { | |
7659150c PO |
306 | unsigned long flags; |
307 | size_t blksize, len, chunk; | |
308 | u32 scratch; | |
309 | u8 *buf; | |
d129bceb | 310 | |
a406f5a3 PO |
311 | DBG("PIO writing\n"); |
312 | ||
313 | blksize = host->data->blksz; | |
7659150c PO |
314 | chunk = 0; |
315 | scratch = 0; | |
d129bceb | 316 | |
7659150c | 317 | local_irq_save(flags); |
d129bceb | 318 | |
a406f5a3 | 319 | while (blksize) { |
7659150c PO |
320 | if (!sg_miter_next(&host->sg_miter)) |
321 | BUG(); | |
a406f5a3 | 322 | |
7659150c PO |
323 | len = min(host->sg_miter.length, blksize); |
324 | ||
325 | blksize -= len; | |
326 | host->sg_miter.consumed = len; | |
327 | ||
328 | buf = host->sg_miter.addr; | |
d129bceb | 329 | |
7659150c PO |
330 | while (len) { |
331 | scratch |= (u32)*buf << (chunk * 8); | |
332 | ||
333 | buf++; | |
334 | chunk++; | |
335 | len--; | |
336 | ||
337 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { | |
4e4141a5 | 338 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
7659150c PO |
339 | chunk = 0; |
340 | scratch = 0; | |
d129bceb | 341 | } |
d129bceb PO |
342 | } |
343 | } | |
7659150c PO |
344 | |
345 | sg_miter_stop(&host->sg_miter); | |
346 | ||
347 | local_irq_restore(flags); | |
a406f5a3 PO |
348 | } |
349 | ||
350 | static void sdhci_transfer_pio(struct sdhci_host *host) | |
351 | { | |
352 | u32 mask; | |
353 | ||
354 | BUG_ON(!host->data); | |
355 | ||
7659150c | 356 | if (host->blocks == 0) |
a406f5a3 PO |
357 | return; |
358 | ||
359 | if (host->data->flags & MMC_DATA_READ) | |
360 | mask = SDHCI_DATA_AVAILABLE; | |
361 | else | |
362 | mask = SDHCI_SPACE_AVAILABLE; | |
363 | ||
4a3cba32 PO |
364 | /* |
365 | * Some controllers (JMicron JMB38x) mess up the buffer bits | |
366 | * for transfers < 4 bytes. As long as it is just one block, | |
367 | * we can ignore the bits. | |
368 | */ | |
369 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && | |
370 | (host->data->blocks == 1)) | |
371 | mask = ~0; | |
372 | ||
4e4141a5 | 373 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
3e3bf207 AV |
374 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
375 | udelay(100); | |
376 | ||
a406f5a3 PO |
377 | if (host->data->flags & MMC_DATA_READ) |
378 | sdhci_read_block_pio(host); | |
379 | else | |
380 | sdhci_write_block_pio(host); | |
d129bceb | 381 | |
7659150c PO |
382 | host->blocks--; |
383 | if (host->blocks == 0) | |
a406f5a3 | 384 | break; |
a406f5a3 | 385 | } |
d129bceb | 386 | |
a406f5a3 | 387 | DBG("PIO transfer complete.\n"); |
d129bceb PO |
388 | } |
389 | ||
2134a922 PO |
390 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
391 | { | |
392 | local_irq_save(*flags); | |
393 | return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; | |
394 | } | |
395 | ||
396 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) | |
397 | { | |
398 | kunmap_atomic(buffer, KM_BIO_SRC_IRQ); | |
399 | local_irq_restore(*flags); | |
400 | } | |
401 | ||
118cd17d BD |
402 | static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) |
403 | { | |
9e506f35 BD |
404 | __le32 *dataddr = (__le32 __force *)(desc + 4); |
405 | __le16 *cmdlen = (__le16 __force *)desc; | |
118cd17d | 406 | |
9e506f35 BD |
407 | /* SDHCI specification says ADMA descriptors should be 4 byte |
408 | * aligned, so using 16 or 32bit operations should be safe. */ | |
118cd17d | 409 | |
9e506f35 BD |
410 | cmdlen[0] = cpu_to_le16(cmd); |
411 | cmdlen[1] = cpu_to_le16(len); | |
412 | ||
413 | dataddr[0] = cpu_to_le32(addr); | |
118cd17d BD |
414 | } |
415 | ||
8f1934ce | 416 | static int sdhci_adma_table_pre(struct sdhci_host *host, |
2134a922 PO |
417 | struct mmc_data *data) |
418 | { | |
419 | int direction; | |
420 | ||
421 | u8 *desc; | |
422 | u8 *align; | |
423 | dma_addr_t addr; | |
424 | dma_addr_t align_addr; | |
425 | int len, offset; | |
426 | ||
427 | struct scatterlist *sg; | |
428 | int i; | |
429 | char *buffer; | |
430 | unsigned long flags; | |
431 | ||
432 | /* | |
433 | * The spec does not specify endianness of descriptor table. | |
434 | * We currently guess that it is LE. | |
435 | */ | |
436 | ||
437 | if (data->flags & MMC_DATA_READ) | |
438 | direction = DMA_FROM_DEVICE; | |
439 | else | |
440 | direction = DMA_TO_DEVICE; | |
441 | ||
442 | /* | |
443 | * The ADMA descriptor table is mapped further down as we | |
444 | * need to fill it with data first. | |
445 | */ | |
446 | ||
447 | host->align_addr = dma_map_single(mmc_dev(host->mmc), | |
448 | host->align_buffer, 128 * 4, direction); | |
8d8bb39b | 449 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) |
8f1934ce | 450 | goto fail; |
2134a922 PO |
451 | BUG_ON(host->align_addr & 0x3); |
452 | ||
453 | host->sg_count = dma_map_sg(mmc_dev(host->mmc), | |
454 | data->sg, data->sg_len, direction); | |
8f1934ce PO |
455 | if (host->sg_count == 0) |
456 | goto unmap_align; | |
2134a922 PO |
457 | |
458 | desc = host->adma_desc; | |
459 | align = host->align_buffer; | |
460 | ||
461 | align_addr = host->align_addr; | |
462 | ||
463 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
464 | addr = sg_dma_address(sg); | |
465 | len = sg_dma_len(sg); | |
466 | ||
467 | /* | |
468 | * The SDHCI specification states that ADMA | |
469 | * addresses must be 32-bit aligned. If they | |
470 | * aren't, then we use a bounce buffer for | |
471 | * the (up to three) bytes that screw up the | |
472 | * alignment. | |
473 | */ | |
474 | offset = (4 - (addr & 0x3)) & 0x3; | |
475 | if (offset) { | |
476 | if (data->flags & MMC_DATA_WRITE) { | |
477 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 478 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
479 | memcpy(align, buffer, offset); |
480 | sdhci_kunmap_atomic(buffer, &flags); | |
481 | } | |
482 | ||
118cd17d BD |
483 | /* tran, valid */ |
484 | sdhci_set_adma_desc(desc, align_addr, offset, 0x21); | |
2134a922 PO |
485 | |
486 | BUG_ON(offset > 65536); | |
487 | ||
2134a922 PO |
488 | align += 4; |
489 | align_addr += 4; | |
490 | ||
491 | desc += 8; | |
492 | ||
493 | addr += offset; | |
494 | len -= offset; | |
495 | } | |
496 | ||
2134a922 PO |
497 | BUG_ON(len > 65536); |
498 | ||
118cd17d BD |
499 | /* tran, valid */ |
500 | sdhci_set_adma_desc(desc, addr, len, 0x21); | |
2134a922 PO |
501 | desc += 8; |
502 | ||
503 | /* | |
504 | * If this triggers then we have a calculation bug | |
505 | * somewhere. :/ | |
506 | */ | |
507 | WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); | |
508 | } | |
509 | ||
70764a90 TA |
510 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
511 | /* | |
512 | * Mark the last descriptor as the terminating descriptor | |
513 | */ | |
514 | if (desc != host->adma_desc) { | |
515 | desc -= 8; | |
516 | desc[0] |= 0x2; /* end */ | |
517 | } | |
518 | } else { | |
519 | /* | |
520 | * Add a terminating entry. | |
521 | */ | |
2134a922 | 522 | |
70764a90 TA |
523 | /* nop, end, valid */ |
524 | sdhci_set_adma_desc(desc, 0, 0, 0x3); | |
525 | } | |
2134a922 PO |
526 | |
527 | /* | |
528 | * Resync align buffer as we might have changed it. | |
529 | */ | |
530 | if (data->flags & MMC_DATA_WRITE) { | |
531 | dma_sync_single_for_device(mmc_dev(host->mmc), | |
532 | host->align_addr, 128 * 4, direction); | |
533 | } | |
534 | ||
535 | host->adma_addr = dma_map_single(mmc_dev(host->mmc), | |
536 | host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
980167b7 | 537 | if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) |
8f1934ce | 538 | goto unmap_entries; |
2134a922 | 539 | BUG_ON(host->adma_addr & 0x3); |
8f1934ce PO |
540 | |
541 | return 0; | |
542 | ||
543 | unmap_entries: | |
544 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
545 | data->sg_len, direction); | |
546 | unmap_align: | |
547 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
548 | 128 * 4, direction); | |
549 | fail: | |
550 | return -EINVAL; | |
2134a922 PO |
551 | } |
552 | ||
553 | static void sdhci_adma_table_post(struct sdhci_host *host, | |
554 | struct mmc_data *data) | |
555 | { | |
556 | int direction; | |
557 | ||
558 | struct scatterlist *sg; | |
559 | int i, size; | |
560 | u8 *align; | |
561 | char *buffer; | |
562 | unsigned long flags; | |
563 | ||
564 | if (data->flags & MMC_DATA_READ) | |
565 | direction = DMA_FROM_DEVICE; | |
566 | else | |
567 | direction = DMA_TO_DEVICE; | |
568 | ||
569 | dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, | |
570 | (128 * 2 + 1) * 4, DMA_TO_DEVICE); | |
571 | ||
572 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, | |
573 | 128 * 4, direction); | |
574 | ||
575 | if (data->flags & MMC_DATA_READ) { | |
576 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, | |
577 | data->sg_len, direction); | |
578 | ||
579 | align = host->align_buffer; | |
580 | ||
581 | for_each_sg(data->sg, sg, host->sg_count, i) { | |
582 | if (sg_dma_address(sg) & 0x3) { | |
583 | size = 4 - (sg_dma_address(sg) & 0x3); | |
584 | ||
585 | buffer = sdhci_kmap_atomic(sg, &flags); | |
6cefd05f | 586 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
2134a922 PO |
587 | memcpy(buffer, align, size); |
588 | sdhci_kunmap_atomic(buffer, &flags); | |
589 | ||
590 | align += 4; | |
591 | } | |
592 | } | |
593 | } | |
594 | ||
595 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
596 | data->sg_len, direction); | |
597 | } | |
598 | ||
a3c7778f | 599 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
d129bceb | 600 | { |
1c8cde92 | 601 | u8 count; |
a3c7778f | 602 | struct mmc_data *data = cmd->data; |
1c8cde92 | 603 | unsigned target_timeout, current_timeout; |
d129bceb | 604 | |
ee53ab5d PO |
605 | /* |
606 | * If the host controller provides us with an incorrect timeout | |
607 | * value, just skip the check and use 0xE. The hardware may take | |
608 | * longer to time out, but that's much better than having a too-short | |
609 | * timeout value. | |
610 | */ | |
11a2f1b7 | 611 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
ee53ab5d | 612 | return 0xE; |
e538fbe8 | 613 | |
a3c7778f AW |
614 | /* Unspecified timeout, assume max */ |
615 | if (!data && !cmd->cmd_timeout_ms) | |
616 | return 0xE; | |
d129bceb | 617 | |
a3c7778f AW |
618 | /* timeout in us */ |
619 | if (!data) | |
620 | target_timeout = cmd->cmd_timeout_ms * 1000; | |
621 | else | |
622 | target_timeout = data->timeout_ns / 1000 + | |
623 | data->timeout_clks / host->clock; | |
81b39802 | 624 | |
4b01681c MB |
625 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) |
626 | host->timeout_clk = host->clock / 1000; | |
627 | ||
1c8cde92 PO |
628 | /* |
629 | * Figure out needed cycles. | |
630 | * We do this in steps in order to fit inside a 32 bit int. | |
631 | * The first step is the minimum timeout, which will have a | |
632 | * minimum resolution of 6 bits: | |
633 | * (1) 2^13*1000 > 2^22, | |
634 | * (2) host->timeout_clk < 2^16 | |
635 | * => | |
636 | * (1) / (2) > 2^6 | |
637 | */ | |
4b01681c | 638 | BUG_ON(!host->timeout_clk); |
1c8cde92 PO |
639 | count = 0; |
640 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; | |
641 | while (current_timeout < target_timeout) { | |
642 | count++; | |
643 | current_timeout <<= 1; | |
644 | if (count >= 0xF) | |
645 | break; | |
646 | } | |
647 | ||
648 | if (count >= 0xF) { | |
a3c7778f AW |
649 | printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n", |
650 | mmc_hostname(host->mmc), cmd->opcode); | |
1c8cde92 PO |
651 | count = 0xE; |
652 | } | |
653 | ||
ee53ab5d PO |
654 | return count; |
655 | } | |
656 | ||
6aa943ab AV |
657 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
658 | { | |
659 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; | |
660 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; | |
661 | ||
662 | if (host->flags & SDHCI_REQ_USE_DMA) | |
663 | sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); | |
664 | else | |
665 | sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); | |
666 | } | |
667 | ||
a3c7778f | 668 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) |
ee53ab5d PO |
669 | { |
670 | u8 count; | |
2134a922 | 671 | u8 ctrl; |
a3c7778f | 672 | struct mmc_data *data = cmd->data; |
8f1934ce | 673 | int ret; |
ee53ab5d PO |
674 | |
675 | WARN_ON(host->data); | |
676 | ||
a3c7778f AW |
677 | if (data || (cmd->flags & MMC_RSP_BUSY)) { |
678 | count = sdhci_calc_timeout(host, cmd); | |
679 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); | |
680 | } | |
681 | ||
682 | if (!data) | |
ee53ab5d PO |
683 | return; |
684 | ||
685 | /* Sanity checks */ | |
686 | BUG_ON(data->blksz * data->blocks > 524288); | |
687 | BUG_ON(data->blksz > host->mmc->max_blk_size); | |
688 | BUG_ON(data->blocks > 65535); | |
689 | ||
690 | host->data = data; | |
691 | host->data_early = 0; | |
f6a03cbf | 692 | host->data->bytes_xfered = 0; |
ee53ab5d | 693 | |
a13abc7b | 694 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) |
c9fddbc4 PO |
695 | host->flags |= SDHCI_REQ_USE_DMA; |
696 | ||
2134a922 PO |
697 | /* |
698 | * FIXME: This doesn't account for merging when mapping the | |
699 | * scatterlist. | |
700 | */ | |
701 | if (host->flags & SDHCI_REQ_USE_DMA) { | |
702 | int broken, i; | |
703 | struct scatterlist *sg; | |
704 | ||
705 | broken = 0; | |
706 | if (host->flags & SDHCI_USE_ADMA) { | |
707 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
708 | broken = 1; | |
709 | } else { | |
710 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) | |
711 | broken = 1; | |
712 | } | |
713 | ||
714 | if (unlikely(broken)) { | |
715 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
716 | if (sg->length & 0x3) { | |
717 | DBG("Reverting to PIO because of " | |
718 | "transfer size (%d)\n", | |
719 | sg->length); | |
720 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
721 | break; | |
722 | } | |
723 | } | |
724 | } | |
c9fddbc4 PO |
725 | } |
726 | ||
727 | /* | |
728 | * The assumption here being that alignment is the same after | |
729 | * translation to device address space. | |
730 | */ | |
2134a922 PO |
731 | if (host->flags & SDHCI_REQ_USE_DMA) { |
732 | int broken, i; | |
733 | struct scatterlist *sg; | |
734 | ||
735 | broken = 0; | |
736 | if (host->flags & SDHCI_USE_ADMA) { | |
737 | /* | |
738 | * As we use 3 byte chunks to work around | |
739 | * alignment problems, we need to check this | |
740 | * quirk. | |
741 | */ | |
742 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) | |
743 | broken = 1; | |
744 | } else { | |
745 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) | |
746 | broken = 1; | |
747 | } | |
748 | ||
749 | if (unlikely(broken)) { | |
750 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
751 | if (sg->offset & 0x3) { | |
752 | DBG("Reverting to PIO because of " | |
753 | "bad alignment\n"); | |
754 | host->flags &= ~SDHCI_REQ_USE_DMA; | |
755 | break; | |
756 | } | |
757 | } | |
758 | } | |
759 | } | |
760 | ||
8f1934ce PO |
761 | if (host->flags & SDHCI_REQ_USE_DMA) { |
762 | if (host->flags & SDHCI_USE_ADMA) { | |
763 | ret = sdhci_adma_table_pre(host, data); | |
764 | if (ret) { | |
765 | /* | |
766 | * This only happens when someone fed | |
767 | * us an invalid request. | |
768 | */ | |
769 | WARN_ON(1); | |
ebd6d357 | 770 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 771 | } else { |
4e4141a5 AV |
772 | sdhci_writel(host, host->adma_addr, |
773 | SDHCI_ADMA_ADDRESS); | |
8f1934ce PO |
774 | } |
775 | } else { | |
c8b3e02e | 776 | int sg_cnt; |
8f1934ce | 777 | |
c8b3e02e | 778 | sg_cnt = dma_map_sg(mmc_dev(host->mmc), |
8f1934ce PO |
779 | data->sg, data->sg_len, |
780 | (data->flags & MMC_DATA_READ) ? | |
781 | DMA_FROM_DEVICE : | |
782 | DMA_TO_DEVICE); | |
c8b3e02e | 783 | if (sg_cnt == 0) { |
8f1934ce PO |
784 | /* |
785 | * This only happens when someone fed | |
786 | * us an invalid request. | |
787 | */ | |
788 | WARN_ON(1); | |
ebd6d357 | 789 | host->flags &= ~SDHCI_REQ_USE_DMA; |
8f1934ce | 790 | } else { |
719a61b4 | 791 | WARN_ON(sg_cnt != 1); |
4e4141a5 AV |
792 | sdhci_writel(host, sg_dma_address(data->sg), |
793 | SDHCI_DMA_ADDRESS); | |
8f1934ce PO |
794 | } |
795 | } | |
796 | } | |
797 | ||
2134a922 PO |
798 | /* |
799 | * Always adjust the DMA selection as some controllers | |
800 | * (e.g. JMicron) can't do PIO properly when the selection | |
801 | * is ADMA. | |
802 | */ | |
803 | if (host->version >= SDHCI_SPEC_200) { | |
4e4141a5 | 804 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
2134a922 PO |
805 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
806 | if ((host->flags & SDHCI_REQ_USE_DMA) && | |
807 | (host->flags & SDHCI_USE_ADMA)) | |
808 | ctrl |= SDHCI_CTRL_ADMA32; | |
809 | else | |
810 | ctrl |= SDHCI_CTRL_SDMA; | |
4e4141a5 | 811 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
c9fddbc4 PO |
812 | } |
813 | ||
8f1934ce | 814 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
da60a91d SAS |
815 | int flags; |
816 | ||
817 | flags = SG_MITER_ATOMIC; | |
818 | if (host->data->flags & MMC_DATA_READ) | |
819 | flags |= SG_MITER_TO_SG; | |
820 | else | |
821 | flags |= SG_MITER_FROM_SG; | |
822 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
7659150c | 823 | host->blocks = data->blocks; |
d129bceb | 824 | } |
c7fa9963 | 825 | |
6aa943ab AV |
826 | sdhci_set_transfer_irqs(host); |
827 | ||
f6a03cbf MV |
828 | /* Set the DMA boundary value and block size */ |
829 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, | |
830 | data->blksz), SDHCI_BLOCK_SIZE); | |
4e4141a5 | 831 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
c7fa9963 PO |
832 | } |
833 | ||
834 | static void sdhci_set_transfer_mode(struct sdhci_host *host, | |
835 | struct mmc_data *data) | |
836 | { | |
837 | u16 mode; | |
838 | ||
c7fa9963 PO |
839 | if (data == NULL) |
840 | return; | |
841 | ||
e538fbe8 PO |
842 | WARN_ON(!host->data); |
843 | ||
c7fa9963 | 844 | mode = SDHCI_TRNS_BLK_CNT_EN; |
c4512f79 JH |
845 | if (data->blocks > 1) { |
846 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) | |
847 | mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12; | |
848 | else | |
849 | mode |= SDHCI_TRNS_MULTI; | |
850 | } | |
c7fa9963 PO |
851 | if (data->flags & MMC_DATA_READ) |
852 | mode |= SDHCI_TRNS_READ; | |
c9fddbc4 | 853 | if (host->flags & SDHCI_REQ_USE_DMA) |
c7fa9963 PO |
854 | mode |= SDHCI_TRNS_DMA; |
855 | ||
4e4141a5 | 856 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
d129bceb PO |
857 | } |
858 | ||
859 | static void sdhci_finish_data(struct sdhci_host *host) | |
860 | { | |
861 | struct mmc_data *data; | |
d129bceb PO |
862 | |
863 | BUG_ON(!host->data); | |
864 | ||
865 | data = host->data; | |
866 | host->data = NULL; | |
867 | ||
c9fddbc4 | 868 | if (host->flags & SDHCI_REQ_USE_DMA) { |
2134a922 PO |
869 | if (host->flags & SDHCI_USE_ADMA) |
870 | sdhci_adma_table_post(host, data); | |
871 | else { | |
872 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, | |
873 | data->sg_len, (data->flags & MMC_DATA_READ) ? | |
874 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
875 | } | |
d129bceb PO |
876 | } |
877 | ||
878 | /* | |
c9b74c5b PO |
879 | * The specification states that the block count register must |
880 | * be updated, but it does not specify at what point in the | |
881 | * data flow. That makes the register entirely useless to read | |
882 | * back so we have to assume that nothing made it to the card | |
883 | * in the event of an error. | |
d129bceb | 884 | */ |
c9b74c5b PO |
885 | if (data->error) |
886 | data->bytes_xfered = 0; | |
d129bceb | 887 | else |
c9b74c5b | 888 | data->bytes_xfered = data->blksz * data->blocks; |
d129bceb | 889 | |
d129bceb PO |
890 | if (data->stop) { |
891 | /* | |
892 | * The controller needs a reset of internal state machines | |
893 | * upon error conditions. | |
894 | */ | |
17b0429d | 895 | if (data->error) { |
d129bceb PO |
896 | sdhci_reset(host, SDHCI_RESET_CMD); |
897 | sdhci_reset(host, SDHCI_RESET_DATA); | |
898 | } | |
899 | ||
900 | sdhci_send_command(host, data->stop); | |
901 | } else | |
902 | tasklet_schedule(&host->finish_tasklet); | |
903 | } | |
904 | ||
905 | static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) | |
906 | { | |
907 | int flags; | |
fd2208d7 | 908 | u32 mask; |
7cb2c76f | 909 | unsigned long timeout; |
d129bceb PO |
910 | |
911 | WARN_ON(host->cmd); | |
912 | ||
d129bceb | 913 | /* Wait max 10 ms */ |
7cb2c76f | 914 | timeout = 10; |
fd2208d7 PO |
915 | |
916 | mask = SDHCI_CMD_INHIBIT; | |
917 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) | |
918 | mask |= SDHCI_DATA_INHIBIT; | |
919 | ||
920 | /* We shouldn't wait for data inihibit for stop commands, even | |
921 | though they might use busy signaling */ | |
922 | if (host->mrq->data && (cmd == host->mrq->data->stop)) | |
923 | mask &= ~SDHCI_DATA_INHIBIT; | |
924 | ||
4e4141a5 | 925 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
7cb2c76f | 926 | if (timeout == 0) { |
d129bceb | 927 | printk(KERN_ERR "%s: Controller never released " |
acf1da45 | 928 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
d129bceb | 929 | sdhci_dumpregs(host); |
17b0429d | 930 | cmd->error = -EIO; |
d129bceb PO |
931 | tasklet_schedule(&host->finish_tasklet); |
932 | return; | |
933 | } | |
7cb2c76f PO |
934 | timeout--; |
935 | mdelay(1); | |
936 | } | |
d129bceb PO |
937 | |
938 | mod_timer(&host->timer, jiffies + 10 * HZ); | |
939 | ||
940 | host->cmd = cmd; | |
941 | ||
a3c7778f | 942 | sdhci_prepare_data(host, cmd); |
d129bceb | 943 | |
4e4141a5 | 944 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
d129bceb | 945 | |
c7fa9963 PO |
946 | sdhci_set_transfer_mode(host, cmd->data); |
947 | ||
d129bceb | 948 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
acf1da45 | 949 | printk(KERN_ERR "%s: Unsupported response type!\n", |
d129bceb | 950 | mmc_hostname(host->mmc)); |
17b0429d | 951 | cmd->error = -EINVAL; |
d129bceb PO |
952 | tasklet_schedule(&host->finish_tasklet); |
953 | return; | |
954 | } | |
955 | ||
956 | if (!(cmd->flags & MMC_RSP_PRESENT)) | |
957 | flags = SDHCI_CMD_RESP_NONE; | |
958 | else if (cmd->flags & MMC_RSP_136) | |
959 | flags = SDHCI_CMD_RESP_LONG; | |
960 | else if (cmd->flags & MMC_RSP_BUSY) | |
961 | flags = SDHCI_CMD_RESP_SHORT_BUSY; | |
962 | else | |
963 | flags = SDHCI_CMD_RESP_SHORT; | |
964 | ||
965 | if (cmd->flags & MMC_RSP_CRC) | |
966 | flags |= SDHCI_CMD_CRC; | |
967 | if (cmd->flags & MMC_RSP_OPCODE) | |
968 | flags |= SDHCI_CMD_INDEX; | |
969 | if (cmd->data) | |
970 | flags |= SDHCI_CMD_DATA; | |
971 | ||
4e4141a5 | 972 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
d129bceb PO |
973 | } |
974 | ||
975 | static void sdhci_finish_command(struct sdhci_host *host) | |
976 | { | |
977 | int i; | |
978 | ||
979 | BUG_ON(host->cmd == NULL); | |
980 | ||
981 | if (host->cmd->flags & MMC_RSP_PRESENT) { | |
982 | if (host->cmd->flags & MMC_RSP_136) { | |
983 | /* CRC is stripped so we need to do some shifting. */ | |
984 | for (i = 0;i < 4;i++) { | |
4e4141a5 | 985 | host->cmd->resp[i] = sdhci_readl(host, |
d129bceb PO |
986 | SDHCI_RESPONSE + (3-i)*4) << 8; |
987 | if (i != 3) | |
988 | host->cmd->resp[i] |= | |
4e4141a5 | 989 | sdhci_readb(host, |
d129bceb PO |
990 | SDHCI_RESPONSE + (3-i)*4-1); |
991 | } | |
992 | } else { | |
4e4141a5 | 993 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
d129bceb PO |
994 | } |
995 | } | |
996 | ||
17b0429d | 997 | host->cmd->error = 0; |
d129bceb | 998 | |
e538fbe8 PO |
999 | if (host->data && host->data_early) |
1000 | sdhci_finish_data(host); | |
1001 | ||
1002 | if (!host->cmd->data) | |
d129bceb PO |
1003 | tasklet_schedule(&host->finish_tasklet); |
1004 | ||
1005 | host->cmd = NULL; | |
1006 | } | |
1007 | ||
1008 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) | |
1009 | { | |
1010 | int div; | |
1011 | u16 clk; | |
7cb2c76f | 1012 | unsigned long timeout; |
d129bceb PO |
1013 | |
1014 | if (clock == host->clock) | |
1015 | return; | |
1016 | ||
8114634c AV |
1017 | if (host->ops->set_clock) { |
1018 | host->ops->set_clock(host, clock); | |
1019 | if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) | |
1020 | return; | |
1021 | } | |
1022 | ||
4e4141a5 | 1023 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1024 | |
1025 | if (clock == 0) | |
1026 | goto out; | |
1027 | ||
85105c53 ZG |
1028 | if (host->version >= SDHCI_SPEC_300) { |
1029 | /* Version 3.00 divisors must be a multiple of 2. */ | |
1030 | if (host->max_clk <= clock) | |
1031 | div = 1; | |
1032 | else { | |
0397526d | 1033 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { |
85105c53 ZG |
1034 | if ((host->max_clk / div) <= clock) |
1035 | break; | |
1036 | } | |
1037 | } | |
1038 | } else { | |
1039 | /* Version 2.00 divisors must be a power of 2. */ | |
0397526d | 1040 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
85105c53 ZG |
1041 | if ((host->max_clk / div) <= clock) |
1042 | break; | |
1043 | } | |
d129bceb PO |
1044 | } |
1045 | div >>= 1; | |
1046 | ||
85105c53 ZG |
1047 | clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
1048 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) | |
1049 | << SDHCI_DIVIDER_HI_SHIFT; | |
d129bceb | 1050 | clk |= SDHCI_CLOCK_INT_EN; |
4e4141a5 | 1051 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb | 1052 | |
27f6cb16 CB |
1053 | /* Wait max 20 ms */ |
1054 | timeout = 20; | |
4e4141a5 | 1055 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
7cb2c76f PO |
1056 | & SDHCI_CLOCK_INT_STABLE)) { |
1057 | if (timeout == 0) { | |
acf1da45 PO |
1058 | printk(KERN_ERR "%s: Internal clock never " |
1059 | "stabilised.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
1060 | sdhci_dumpregs(host); |
1061 | return; | |
1062 | } | |
7cb2c76f PO |
1063 | timeout--; |
1064 | mdelay(1); | |
1065 | } | |
d129bceb PO |
1066 | |
1067 | clk |= SDHCI_CLOCK_CARD_EN; | |
4e4141a5 | 1068 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
d129bceb PO |
1069 | |
1070 | out: | |
1071 | host->clock = clock; | |
1072 | } | |
1073 | ||
146ad66e PO |
1074 | static void sdhci_set_power(struct sdhci_host *host, unsigned short power) |
1075 | { | |
8364248a | 1076 | u8 pwr = 0; |
146ad66e | 1077 | |
8364248a | 1078 | if (power != (unsigned short)-1) { |
ae628903 PO |
1079 | switch (1 << power) { |
1080 | case MMC_VDD_165_195: | |
1081 | pwr = SDHCI_POWER_180; | |
1082 | break; | |
1083 | case MMC_VDD_29_30: | |
1084 | case MMC_VDD_30_31: | |
1085 | pwr = SDHCI_POWER_300; | |
1086 | break; | |
1087 | case MMC_VDD_32_33: | |
1088 | case MMC_VDD_33_34: | |
1089 | pwr = SDHCI_POWER_330; | |
1090 | break; | |
1091 | default: | |
1092 | BUG(); | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | if (host->pwr == pwr) | |
146ad66e PO |
1097 | return; |
1098 | ||
ae628903 PO |
1099 | host->pwr = pwr; |
1100 | ||
1101 | if (pwr == 0) { | |
4e4141a5 | 1102 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
ae628903 | 1103 | return; |
9e9dc5f2 DS |
1104 | } |
1105 | ||
1106 | /* | |
1107 | * Spec says that we should clear the power reg before setting | |
1108 | * a new value. Some controllers don't seem to like this though. | |
1109 | */ | |
b8c86fc5 | 1110 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
4e4141a5 | 1111 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
146ad66e | 1112 | |
e08c1694 | 1113 | /* |
c71f6512 | 1114 | * At least the Marvell CaFe chip gets confused if we set the voltage |
e08c1694 AS |
1115 | * and set turn on power at the same time, so set the voltage first. |
1116 | */ | |
11a2f1b7 | 1117 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) |
ae628903 | 1118 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
e08c1694 | 1119 | |
ae628903 | 1120 | pwr |= SDHCI_POWER_ON; |
146ad66e | 1121 | |
ae628903 | 1122 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
557b0697 HW |
1123 | |
1124 | /* | |
1125 | * Some controllers need an extra 10ms delay of 10ms before they | |
1126 | * can apply clock after applying power | |
1127 | */ | |
11a2f1b7 | 1128 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) |
557b0697 | 1129 | mdelay(10); |
146ad66e PO |
1130 | } |
1131 | ||
d129bceb PO |
1132 | /*****************************************************************************\ |
1133 | * * | |
1134 | * MMC callbacks * | |
1135 | * * | |
1136 | \*****************************************************************************/ | |
1137 | ||
1138 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1139 | { | |
1140 | struct sdhci_host *host; | |
68d1fb7e | 1141 | bool present; |
d129bceb PO |
1142 | unsigned long flags; |
1143 | ||
1144 | host = mmc_priv(mmc); | |
1145 | ||
1146 | spin_lock_irqsave(&host->lock, flags); | |
1147 | ||
1148 | WARN_ON(host->mrq != NULL); | |
1149 | ||
f9134319 | 1150 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1151 | sdhci_activate_led(host); |
2f730fec | 1152 | #endif |
c4512f79 JH |
1153 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) { |
1154 | if (mrq->stop) { | |
1155 | mrq->data->stop = NULL; | |
1156 | mrq->stop = NULL; | |
1157 | } | |
1158 | } | |
d129bceb PO |
1159 | |
1160 | host->mrq = mrq; | |
1161 | ||
68d1fb7e AV |
1162 | /* If polling, assume that the card is always present. */ |
1163 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) | |
1164 | present = true; | |
1165 | else | |
1166 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & | |
1167 | SDHCI_CARD_PRESENT; | |
1168 | ||
1169 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { | |
17b0429d | 1170 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1171 | tasklet_schedule(&host->finish_tasklet); |
1172 | } else | |
1173 | sdhci_send_command(host, mrq->cmd); | |
1174 | ||
5f25a66f | 1175 | mmiowb(); |
d129bceb PO |
1176 | spin_unlock_irqrestore(&host->lock, flags); |
1177 | } | |
1178 | ||
1179 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1180 | { | |
1181 | struct sdhci_host *host; | |
1182 | unsigned long flags; | |
1183 | u8 ctrl; | |
1184 | ||
1185 | host = mmc_priv(mmc); | |
1186 | ||
1187 | spin_lock_irqsave(&host->lock, flags); | |
1188 | ||
1e72859e PO |
1189 | if (host->flags & SDHCI_DEVICE_DEAD) |
1190 | goto out; | |
1191 | ||
d129bceb PO |
1192 | /* |
1193 | * Reset the chip on each power off. | |
1194 | * Should clear out any weird states. | |
1195 | */ | |
1196 | if (ios->power_mode == MMC_POWER_OFF) { | |
4e4141a5 | 1197 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
7260cf5e | 1198 | sdhci_reinit(host); |
d129bceb PO |
1199 | } |
1200 | ||
1201 | sdhci_set_clock(host, ios->clock); | |
1202 | ||
1203 | if (ios->power_mode == MMC_POWER_OFF) | |
146ad66e | 1204 | sdhci_set_power(host, -1); |
d129bceb | 1205 | else |
146ad66e | 1206 | sdhci_set_power(host, ios->vdd); |
d129bceb | 1207 | |
643a81ff PR |
1208 | if (host->ops->platform_send_init_74_clocks) |
1209 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); | |
1210 | ||
15ec4461 PR |
1211 | /* |
1212 | * If your platform has 8-bit width support but is not a v3 controller, | |
1213 | * or if it requires special setup code, you should implement that in | |
1214 | * platform_8bit_width(). | |
1215 | */ | |
1216 | if (host->ops->platform_8bit_width) | |
1217 | host->ops->platform_8bit_width(host, ios->bus_width); | |
1218 | else { | |
1219 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
1220 | if (ios->bus_width == MMC_BUS_WIDTH_8) { | |
1221 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1222 | if (host->version >= SDHCI_SPEC_300) | |
1223 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1224 | } else { | |
1225 | if (host->version >= SDHCI_SPEC_300) | |
1226 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1227 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
1228 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1229 | else | |
1230 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1231 | } | |
1232 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
1233 | } | |
ae6d6c92 | 1234 | |
15ec4461 | 1235 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
cd9277c0 | 1236 | |
3ab9c8da PR |
1237 | if ((ios->timing == MMC_TIMING_SD_HS || |
1238 | ios->timing == MMC_TIMING_MMC_HS) | |
1239 | && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) | |
cd9277c0 PO |
1240 | ctrl |= SDHCI_CTRL_HISPD; |
1241 | else | |
1242 | ctrl &= ~SDHCI_CTRL_HISPD; | |
1243 | ||
4e4141a5 | 1244 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
d129bceb | 1245 | |
b8352260 LD |
1246 | /* |
1247 | * Some (ENE) controllers go apeshit on some ios operation, | |
1248 | * signalling timeout and CRC errors even on CMD0. Resetting | |
1249 | * it on each ios seems to solve the problem. | |
1250 | */ | |
b8c86fc5 | 1251 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
b8352260 LD |
1252 | sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
1253 | ||
1e72859e | 1254 | out: |
5f25a66f | 1255 | mmiowb(); |
d129bceb PO |
1256 | spin_unlock_irqrestore(&host->lock, flags); |
1257 | } | |
1258 | ||
1259 | static int sdhci_get_ro(struct mmc_host *mmc) | |
1260 | { | |
1261 | struct sdhci_host *host; | |
1262 | unsigned long flags; | |
2dfb579c | 1263 | int is_readonly; |
d129bceb PO |
1264 | |
1265 | host = mmc_priv(mmc); | |
1266 | ||
1267 | spin_lock_irqsave(&host->lock, flags); | |
1268 | ||
1e72859e | 1269 | if (host->flags & SDHCI_DEVICE_DEAD) |
2dfb579c WS |
1270 | is_readonly = 0; |
1271 | else if (host->ops->get_ro) | |
1272 | is_readonly = host->ops->get_ro(host); | |
1e72859e | 1273 | else |
2dfb579c WS |
1274 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
1275 | & SDHCI_WRITE_PROTECT); | |
d129bceb PO |
1276 | |
1277 | spin_unlock_irqrestore(&host->lock, flags); | |
1278 | ||
2dfb579c WS |
1279 | /* This quirk needs to be replaced by a callback-function later */ |
1280 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? | |
1281 | !is_readonly : is_readonly; | |
d129bceb PO |
1282 | } |
1283 | ||
f75979b7 PO |
1284 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1285 | { | |
1286 | struct sdhci_host *host; | |
1287 | unsigned long flags; | |
f75979b7 PO |
1288 | |
1289 | host = mmc_priv(mmc); | |
1290 | ||
1291 | spin_lock_irqsave(&host->lock, flags); | |
1292 | ||
1e72859e PO |
1293 | if (host->flags & SDHCI_DEVICE_DEAD) |
1294 | goto out; | |
1295 | ||
f75979b7 | 1296 | if (enable) |
7260cf5e AV |
1297 | sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); |
1298 | else | |
1299 | sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); | |
1e72859e | 1300 | out: |
f75979b7 PO |
1301 | mmiowb(); |
1302 | ||
1303 | spin_unlock_irqrestore(&host->lock, flags); | |
1304 | } | |
1305 | ||
ab7aefd0 | 1306 | static const struct mmc_host_ops sdhci_ops = { |
d129bceb PO |
1307 | .request = sdhci_request, |
1308 | .set_ios = sdhci_set_ios, | |
1309 | .get_ro = sdhci_get_ro, | |
f75979b7 | 1310 | .enable_sdio_irq = sdhci_enable_sdio_irq, |
d129bceb PO |
1311 | }; |
1312 | ||
1313 | /*****************************************************************************\ | |
1314 | * * | |
1315 | * Tasklets * | |
1316 | * * | |
1317 | \*****************************************************************************/ | |
1318 | ||
1319 | static void sdhci_tasklet_card(unsigned long param) | |
1320 | { | |
1321 | struct sdhci_host *host; | |
1322 | unsigned long flags; | |
1323 | ||
1324 | host = (struct sdhci_host*)param; | |
1325 | ||
1326 | spin_lock_irqsave(&host->lock, flags); | |
1327 | ||
4e4141a5 | 1328 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { |
d129bceb PO |
1329 | if (host->mrq) { |
1330 | printk(KERN_ERR "%s: Card removed during transfer!\n", | |
1331 | mmc_hostname(host->mmc)); | |
1332 | printk(KERN_ERR "%s: Resetting controller.\n", | |
1333 | mmc_hostname(host->mmc)); | |
1334 | ||
1335 | sdhci_reset(host, SDHCI_RESET_CMD); | |
1336 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1337 | ||
17b0429d | 1338 | host->mrq->cmd->error = -ENOMEDIUM; |
d129bceb PO |
1339 | tasklet_schedule(&host->finish_tasklet); |
1340 | } | |
1341 | } | |
1342 | ||
1343 | spin_unlock_irqrestore(&host->lock, flags); | |
1344 | ||
04cf585d | 1345 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); |
d129bceb PO |
1346 | } |
1347 | ||
1348 | static void sdhci_tasklet_finish(unsigned long param) | |
1349 | { | |
1350 | struct sdhci_host *host; | |
1351 | unsigned long flags; | |
1352 | struct mmc_request *mrq; | |
1353 | ||
1354 | host = (struct sdhci_host*)param; | |
1355 | ||
0c9c99a7 CB |
1356 | /* |
1357 | * If this tasklet gets rescheduled while running, it will | |
1358 | * be run again afterwards but without any active request. | |
1359 | */ | |
1360 | if (!host->mrq) | |
1361 | return; | |
1362 | ||
d129bceb PO |
1363 | spin_lock_irqsave(&host->lock, flags); |
1364 | ||
1365 | del_timer(&host->timer); | |
1366 | ||
1367 | mrq = host->mrq; | |
1368 | ||
d129bceb PO |
1369 | /* |
1370 | * The controller needs a reset of internal state machines | |
1371 | * upon error conditions. | |
1372 | */ | |
1e72859e | 1373 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
b7b4d342 | 1374 | ((mrq->cmd && mrq->cmd->error) || |
1e72859e PO |
1375 | (mrq->data && (mrq->data->error || |
1376 | (mrq->data->stop && mrq->data->stop->error))) || | |
1377 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { | |
645289dc PO |
1378 | |
1379 | /* Some controllers need this kick or reset won't work here */ | |
b8c86fc5 | 1380 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { |
645289dc PO |
1381 | unsigned int clock; |
1382 | ||
1383 | /* This is to force an update */ | |
1384 | clock = host->clock; | |
1385 | host->clock = 0; | |
1386 | sdhci_set_clock(host, clock); | |
1387 | } | |
1388 | ||
1389 | /* Spec says we should do both at the same time, but Ricoh | |
1390 | controllers do not like that. */ | |
d129bceb PO |
1391 | sdhci_reset(host, SDHCI_RESET_CMD); |
1392 | sdhci_reset(host, SDHCI_RESET_DATA); | |
1393 | } | |
1394 | ||
1395 | host->mrq = NULL; | |
1396 | host->cmd = NULL; | |
1397 | host->data = NULL; | |
1398 | ||
f9134319 | 1399 | #ifndef SDHCI_USE_LEDS_CLASS |
d129bceb | 1400 | sdhci_deactivate_led(host); |
2f730fec | 1401 | #endif |
d129bceb | 1402 | |
5f25a66f | 1403 | mmiowb(); |
d129bceb PO |
1404 | spin_unlock_irqrestore(&host->lock, flags); |
1405 | ||
1406 | mmc_request_done(host->mmc, mrq); | |
1407 | } | |
1408 | ||
1409 | static void sdhci_timeout_timer(unsigned long data) | |
1410 | { | |
1411 | struct sdhci_host *host; | |
1412 | unsigned long flags; | |
1413 | ||
1414 | host = (struct sdhci_host*)data; | |
1415 | ||
1416 | spin_lock_irqsave(&host->lock, flags); | |
1417 | ||
1418 | if (host->mrq) { | |
acf1da45 PO |
1419 | printk(KERN_ERR "%s: Timeout waiting for hardware " |
1420 | "interrupt.\n", mmc_hostname(host->mmc)); | |
d129bceb PO |
1421 | sdhci_dumpregs(host); |
1422 | ||
1423 | if (host->data) { | |
17b0429d | 1424 | host->data->error = -ETIMEDOUT; |
d129bceb PO |
1425 | sdhci_finish_data(host); |
1426 | } else { | |
1427 | if (host->cmd) | |
17b0429d | 1428 | host->cmd->error = -ETIMEDOUT; |
d129bceb | 1429 | else |
17b0429d | 1430 | host->mrq->cmd->error = -ETIMEDOUT; |
d129bceb PO |
1431 | |
1432 | tasklet_schedule(&host->finish_tasklet); | |
1433 | } | |
1434 | } | |
1435 | ||
5f25a66f | 1436 | mmiowb(); |
d129bceb PO |
1437 | spin_unlock_irqrestore(&host->lock, flags); |
1438 | } | |
1439 | ||
1440 | /*****************************************************************************\ | |
1441 | * * | |
1442 | * Interrupt handling * | |
1443 | * * | |
1444 | \*****************************************************************************/ | |
1445 | ||
1446 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) | |
1447 | { | |
1448 | BUG_ON(intmask == 0); | |
1449 | ||
1450 | if (!host->cmd) { | |
b67ac3f3 PO |
1451 | printk(KERN_ERR "%s: Got command interrupt 0x%08x even " |
1452 | "though no command operation was in progress.\n", | |
1453 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1454 | sdhci_dumpregs(host); |
1455 | return; | |
1456 | } | |
1457 | ||
43b58b36 | 1458 | if (intmask & SDHCI_INT_TIMEOUT) |
17b0429d PO |
1459 | host->cmd->error = -ETIMEDOUT; |
1460 | else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | | |
1461 | SDHCI_INT_INDEX)) | |
1462 | host->cmd->error = -EILSEQ; | |
43b58b36 | 1463 | |
e809517f | 1464 | if (host->cmd->error) { |
d129bceb | 1465 | tasklet_schedule(&host->finish_tasklet); |
e809517f PO |
1466 | return; |
1467 | } | |
1468 | ||
1469 | /* | |
1470 | * The host can send and interrupt when the busy state has | |
1471 | * ended, allowing us to wait without wasting CPU cycles. | |
1472 | * Unfortunately this is overloaded on the "data complete" | |
1473 | * interrupt, so we need to take some care when handling | |
1474 | * it. | |
1475 | * | |
1476 | * Note: The 1.0 specification is a bit ambiguous about this | |
1477 | * feature so there might be some problems with older | |
1478 | * controllers. | |
1479 | */ | |
1480 | if (host->cmd->flags & MMC_RSP_BUSY) { | |
1481 | if (host->cmd->data) | |
1482 | DBG("Cannot wait for busy signal when also " | |
1483 | "doing a data transfer"); | |
f945405c | 1484 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) |
e809517f | 1485 | return; |
f945405c BD |
1486 | |
1487 | /* The controller does not support the end-of-busy IRQ, | |
1488 | * fall through and take the SDHCI_INT_RESPONSE */ | |
e809517f PO |
1489 | } |
1490 | ||
1491 | if (intmask & SDHCI_INT_RESPONSE) | |
43b58b36 | 1492 | sdhci_finish_command(host); |
d129bceb PO |
1493 | } |
1494 | ||
0957c333 | 1495 | #ifdef CONFIG_MMC_DEBUG |
6882a8c0 BD |
1496 | static void sdhci_show_adma_error(struct sdhci_host *host) |
1497 | { | |
1498 | const char *name = mmc_hostname(host->mmc); | |
1499 | u8 *desc = host->adma_desc; | |
1500 | __le32 *dma; | |
1501 | __le16 *len; | |
1502 | u8 attr; | |
1503 | ||
1504 | sdhci_dumpregs(host); | |
1505 | ||
1506 | while (true) { | |
1507 | dma = (__le32 *)(desc + 4); | |
1508 | len = (__le16 *)(desc + 2); | |
1509 | attr = *desc; | |
1510 | ||
1511 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", | |
1512 | name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); | |
1513 | ||
1514 | desc += 8; | |
1515 | ||
1516 | if (attr & 2) | |
1517 | break; | |
1518 | } | |
1519 | } | |
1520 | #else | |
1521 | static void sdhci_show_adma_error(struct sdhci_host *host) { } | |
1522 | #endif | |
1523 | ||
d129bceb PO |
1524 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
1525 | { | |
1526 | BUG_ON(intmask == 0); | |
1527 | ||
1528 | if (!host->data) { | |
1529 | /* | |
e809517f PO |
1530 | * The "data complete" interrupt is also used to |
1531 | * indicate that a busy state has ended. See comment | |
1532 | * above in sdhci_cmd_irq(). | |
d129bceb | 1533 | */ |
e809517f PO |
1534 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
1535 | if (intmask & SDHCI_INT_DATA_END) { | |
1536 | sdhci_finish_command(host); | |
1537 | return; | |
1538 | } | |
1539 | } | |
d129bceb | 1540 | |
b67ac3f3 PO |
1541 | printk(KERN_ERR "%s: Got data interrupt 0x%08x even " |
1542 | "though no data operation was in progress.\n", | |
1543 | mmc_hostname(host->mmc), (unsigned)intmask); | |
d129bceb PO |
1544 | sdhci_dumpregs(host); |
1545 | ||
1546 | return; | |
1547 | } | |
1548 | ||
1549 | if (intmask & SDHCI_INT_DATA_TIMEOUT) | |
17b0429d | 1550 | host->data->error = -ETIMEDOUT; |
22113efd AL |
1551 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
1552 | host->data->error = -EILSEQ; | |
1553 | else if ((intmask & SDHCI_INT_DATA_CRC) && | |
1554 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) | |
1555 | != MMC_BUS_TEST_R) | |
17b0429d | 1556 | host->data->error = -EILSEQ; |
6882a8c0 BD |
1557 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
1558 | printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc)); | |
1559 | sdhci_show_adma_error(host); | |
2134a922 | 1560 | host->data->error = -EIO; |
6882a8c0 | 1561 | } |
d129bceb | 1562 | |
17b0429d | 1563 | if (host->data->error) |
d129bceb PO |
1564 | sdhci_finish_data(host); |
1565 | else { | |
a406f5a3 | 1566 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
d129bceb PO |
1567 | sdhci_transfer_pio(host); |
1568 | ||
6ba736a1 PO |
1569 | /* |
1570 | * We currently don't do anything fancy with DMA | |
1571 | * boundaries, but as we can't disable the feature | |
1572 | * we need to at least restart the transfer. | |
f6a03cbf MV |
1573 | * |
1574 | * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) | |
1575 | * should return a valid address to continue from, but as | |
1576 | * some controllers are faulty, don't trust them. | |
6ba736a1 | 1577 | */ |
f6a03cbf MV |
1578 | if (intmask & SDHCI_INT_DMA_END) { |
1579 | u32 dmastart, dmanow; | |
1580 | dmastart = sg_dma_address(host->data->sg); | |
1581 | dmanow = dmastart + host->data->bytes_xfered; | |
1582 | /* | |
1583 | * Force update to the next DMA block boundary. | |
1584 | */ | |
1585 | dmanow = (dmanow & | |
1586 | ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + | |
1587 | SDHCI_DEFAULT_BOUNDARY_SIZE; | |
1588 | host->data->bytes_xfered = dmanow - dmastart; | |
1589 | DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," | |
1590 | " next 0x%08x\n", | |
1591 | mmc_hostname(host->mmc), dmastart, | |
1592 | host->data->bytes_xfered, dmanow); | |
1593 | sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); | |
1594 | } | |
6ba736a1 | 1595 | |
e538fbe8 PO |
1596 | if (intmask & SDHCI_INT_DATA_END) { |
1597 | if (host->cmd) { | |
1598 | /* | |
1599 | * Data managed to finish before the | |
1600 | * command completed. Make sure we do | |
1601 | * things in the proper order. | |
1602 | */ | |
1603 | host->data_early = 1; | |
1604 | } else { | |
1605 | sdhci_finish_data(host); | |
1606 | } | |
1607 | } | |
d129bceb PO |
1608 | } |
1609 | } | |
1610 | ||
7d12e780 | 1611 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
d129bceb PO |
1612 | { |
1613 | irqreturn_t result; | |
1614 | struct sdhci_host* host = dev_id; | |
1615 | u32 intmask; | |
f75979b7 | 1616 | int cardint = 0; |
d129bceb PO |
1617 | |
1618 | spin_lock(&host->lock); | |
1619 | ||
4e4141a5 | 1620 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
d129bceb | 1621 | |
62df67a5 | 1622 | if (!intmask || intmask == 0xffffffff) { |
d129bceb PO |
1623 | result = IRQ_NONE; |
1624 | goto out; | |
1625 | } | |
1626 | ||
b69c9058 PO |
1627 | DBG("*** %s got interrupt: 0x%08x\n", |
1628 | mmc_hostname(host->mmc), intmask); | |
d129bceb | 1629 | |
3192a28f | 1630 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
4e4141a5 AV |
1631 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | |
1632 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); | |
d129bceb | 1633 | tasklet_schedule(&host->card_tasklet); |
3192a28f | 1634 | } |
d129bceb | 1635 | |
3192a28f | 1636 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
d129bceb | 1637 | |
3192a28f | 1638 | if (intmask & SDHCI_INT_CMD_MASK) { |
4e4141a5 AV |
1639 | sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, |
1640 | SDHCI_INT_STATUS); | |
3192a28f | 1641 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
d129bceb PO |
1642 | } |
1643 | ||
1644 | if (intmask & SDHCI_INT_DATA_MASK) { | |
4e4141a5 AV |
1645 | sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, |
1646 | SDHCI_INT_STATUS); | |
3192a28f | 1647 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
d129bceb PO |
1648 | } |
1649 | ||
1650 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); | |
1651 | ||
964f9ce2 PO |
1652 | intmask &= ~SDHCI_INT_ERROR; |
1653 | ||
d129bceb | 1654 | if (intmask & SDHCI_INT_BUS_POWER) { |
3192a28f | 1655 | printk(KERN_ERR "%s: Card is consuming too much power!\n", |
d129bceb | 1656 | mmc_hostname(host->mmc)); |
4e4141a5 | 1657 | sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); |
d129bceb PO |
1658 | } |
1659 | ||
9d26a5d3 | 1660 | intmask &= ~SDHCI_INT_BUS_POWER; |
3192a28f | 1661 | |
f75979b7 PO |
1662 | if (intmask & SDHCI_INT_CARD_INT) |
1663 | cardint = 1; | |
1664 | ||
1665 | intmask &= ~SDHCI_INT_CARD_INT; | |
1666 | ||
3192a28f | 1667 | if (intmask) { |
acf1da45 | 1668 | printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n", |
3192a28f | 1669 | mmc_hostname(host->mmc), intmask); |
d129bceb PO |
1670 | sdhci_dumpregs(host); |
1671 | ||
4e4141a5 | 1672 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); |
3192a28f | 1673 | } |
d129bceb PO |
1674 | |
1675 | result = IRQ_HANDLED; | |
1676 | ||
5f25a66f | 1677 | mmiowb(); |
d129bceb PO |
1678 | out: |
1679 | spin_unlock(&host->lock); | |
1680 | ||
f75979b7 PO |
1681 | /* |
1682 | * We have to delay this as it calls back into the driver. | |
1683 | */ | |
1684 | if (cardint) | |
1685 | mmc_signal_sdio_irq(host->mmc); | |
1686 | ||
d129bceb PO |
1687 | return result; |
1688 | } | |
1689 | ||
1690 | /*****************************************************************************\ | |
1691 | * * | |
1692 | * Suspend/resume * | |
1693 | * * | |
1694 | \*****************************************************************************/ | |
1695 | ||
1696 | #ifdef CONFIG_PM | |
1697 | ||
b8c86fc5 | 1698 | int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state) |
d129bceb | 1699 | { |
b8c86fc5 | 1700 | int ret; |
a715dfc7 | 1701 | |
7260cf5e AV |
1702 | sdhci_disable_card_detection(host); |
1703 | ||
1a13f8fa | 1704 | ret = mmc_suspend_host(host->mmc); |
b8c86fc5 PO |
1705 | if (ret) |
1706 | return ret; | |
a715dfc7 | 1707 | |
b8c86fc5 | 1708 | free_irq(host->irq, host); |
d129bceb | 1709 | |
9bea3c85 MS |
1710 | if (host->vmmc) |
1711 | ret = regulator_disable(host->vmmc); | |
1712 | ||
1713 | return ret; | |
d129bceb PO |
1714 | } |
1715 | ||
b8c86fc5 | 1716 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
d129bceb | 1717 | |
b8c86fc5 PO |
1718 | int sdhci_resume_host(struct sdhci_host *host) |
1719 | { | |
1720 | int ret; | |
d129bceb | 1721 | |
9bea3c85 MS |
1722 | if (host->vmmc) { |
1723 | int ret = regulator_enable(host->vmmc); | |
1724 | if (ret) | |
1725 | return ret; | |
1726 | } | |
1727 | ||
1728 | ||
a13abc7b | 1729 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
1730 | if (host->ops->enable_dma) |
1731 | host->ops->enable_dma(host); | |
1732 | } | |
d129bceb | 1733 | |
b8c86fc5 PO |
1734 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
1735 | mmc_hostname(host->mmc), host); | |
df1c4b7b PO |
1736 | if (ret) |
1737 | return ret; | |
d129bceb | 1738 | |
2f4cbb3d | 1739 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); |
b8c86fc5 PO |
1740 | mmiowb(); |
1741 | ||
1742 | ret = mmc_resume_host(host->mmc); | |
7260cf5e AV |
1743 | sdhci_enable_card_detection(host); |
1744 | ||
2f4cbb3d | 1745 | return ret; |
d129bceb PO |
1746 | } |
1747 | ||
b8c86fc5 | 1748 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
d129bceb | 1749 | |
5f619704 DD |
1750 | void sdhci_enable_irq_wakeups(struct sdhci_host *host) |
1751 | { | |
1752 | u8 val; | |
1753 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); | |
1754 | val |= SDHCI_WAKE_ON_INT; | |
1755 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); | |
1756 | } | |
1757 | ||
1758 | EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); | |
1759 | ||
d129bceb PO |
1760 | #endif /* CONFIG_PM */ |
1761 | ||
1762 | /*****************************************************************************\ | |
1763 | * * | |
b8c86fc5 | 1764 | * Device allocation/registration * |
d129bceb PO |
1765 | * * |
1766 | \*****************************************************************************/ | |
1767 | ||
b8c86fc5 PO |
1768 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
1769 | size_t priv_size) | |
d129bceb | 1770 | { |
d129bceb PO |
1771 | struct mmc_host *mmc; |
1772 | struct sdhci_host *host; | |
1773 | ||
b8c86fc5 | 1774 | WARN_ON(dev == NULL); |
d129bceb | 1775 | |
b8c86fc5 | 1776 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
d129bceb | 1777 | if (!mmc) |
b8c86fc5 | 1778 | return ERR_PTR(-ENOMEM); |
d129bceb PO |
1779 | |
1780 | host = mmc_priv(mmc); | |
1781 | host->mmc = mmc; | |
1782 | ||
b8c86fc5 PO |
1783 | return host; |
1784 | } | |
8a4da143 | 1785 | |
b8c86fc5 | 1786 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
d129bceb | 1787 | |
b8c86fc5 PO |
1788 | int sdhci_add_host(struct sdhci_host *host) |
1789 | { | |
1790 | struct mmc_host *mmc; | |
8f230f45 | 1791 | unsigned int caps, ocr_avail; |
b8c86fc5 | 1792 | int ret; |
d129bceb | 1793 | |
b8c86fc5 PO |
1794 | WARN_ON(host == NULL); |
1795 | if (host == NULL) | |
1796 | return -EINVAL; | |
d129bceb | 1797 | |
b8c86fc5 | 1798 | mmc = host->mmc; |
d129bceb | 1799 | |
b8c86fc5 PO |
1800 | if (debug_quirks) |
1801 | host->quirks = debug_quirks; | |
d129bceb | 1802 | |
d96649ed PO |
1803 | sdhci_reset(host, SDHCI_RESET_ALL); |
1804 | ||
4e4141a5 | 1805 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
2134a922 PO |
1806 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
1807 | >> SDHCI_SPEC_VER_SHIFT; | |
85105c53 | 1808 | if (host->version > SDHCI_SPEC_300) { |
4a965505 | 1809 | printk(KERN_ERR "%s: Unknown controller version (%d). " |
b69c9058 | 1810 | "You may experience problems.\n", mmc_hostname(mmc), |
2134a922 | 1811 | host->version); |
4a965505 PO |
1812 | } |
1813 | ||
ccc92c23 ML |
1814 | caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : |
1815 | sdhci_readl(host, SDHCI_CAPABILITIES); | |
d129bceb | 1816 | |
b8c86fc5 | 1817 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
a13abc7b RR |
1818 | host->flags |= SDHCI_USE_SDMA; |
1819 | else if (!(caps & SDHCI_CAN_DO_SDMA)) | |
1820 | DBG("Controller doesn't have SDMA capability\n"); | |
67435274 | 1821 | else |
a13abc7b | 1822 | host->flags |= SDHCI_USE_SDMA; |
d129bceb | 1823 | |
b8c86fc5 | 1824 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
a13abc7b | 1825 | (host->flags & SDHCI_USE_SDMA)) { |
cee687ce | 1826 | DBG("Disabling DMA as it is marked broken\n"); |
a13abc7b | 1827 | host->flags &= ~SDHCI_USE_SDMA; |
7c168e3d FT |
1828 | } |
1829 | ||
a13abc7b RR |
1830 | if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2)) |
1831 | host->flags |= SDHCI_USE_ADMA; | |
2134a922 PO |
1832 | |
1833 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && | |
1834 | (host->flags & SDHCI_USE_ADMA)) { | |
1835 | DBG("Disabling ADMA as it is marked broken\n"); | |
1836 | host->flags &= ~SDHCI_USE_ADMA; | |
1837 | } | |
1838 | ||
a13abc7b | 1839 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
b8c86fc5 PO |
1840 | if (host->ops->enable_dma) { |
1841 | if (host->ops->enable_dma(host)) { | |
1842 | printk(KERN_WARNING "%s: No suitable DMA " | |
1843 | "available. Falling back to PIO.\n", | |
1844 | mmc_hostname(mmc)); | |
a13abc7b RR |
1845 | host->flags &= |
1846 | ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); | |
b8c86fc5 | 1847 | } |
d129bceb PO |
1848 | } |
1849 | } | |
1850 | ||
2134a922 PO |
1851 | if (host->flags & SDHCI_USE_ADMA) { |
1852 | /* | |
1853 | * We need to allocate descriptors for all sg entries | |
1854 | * (128) and potentially one alignment transfer for | |
1855 | * each of those entries. | |
1856 | */ | |
1857 | host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); | |
1858 | host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); | |
1859 | if (!host->adma_desc || !host->align_buffer) { | |
1860 | kfree(host->adma_desc); | |
1861 | kfree(host->align_buffer); | |
1862 | printk(KERN_WARNING "%s: Unable to allocate ADMA " | |
1863 | "buffers. Falling back to standard DMA.\n", | |
1864 | mmc_hostname(mmc)); | |
1865 | host->flags &= ~SDHCI_USE_ADMA; | |
1866 | } | |
1867 | } | |
1868 | ||
7659150c PO |
1869 | /* |
1870 | * If we use DMA, then it's up to the caller to set the DMA | |
1871 | * mask, but PIO does not need the hw shim so we set a new | |
1872 | * mask here in that case. | |
1873 | */ | |
a13abc7b | 1874 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
7659150c PO |
1875 | host->dma_mask = DMA_BIT_MASK(64); |
1876 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; | |
1877 | } | |
d129bceb | 1878 | |
c4687d5f ZG |
1879 | if (host->version >= SDHCI_SPEC_300) |
1880 | host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) | |
1881 | >> SDHCI_CLOCK_BASE_SHIFT; | |
1882 | else | |
1883 | host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) | |
1884 | >> SDHCI_CLOCK_BASE_SHIFT; | |
1885 | ||
4240ff0a | 1886 | host->max_clk *= 1000000; |
f27f47ef AV |
1887 | if (host->max_clk == 0 || host->quirks & |
1888 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { | |
4240ff0a BD |
1889 | if (!host->ops->get_max_clock) { |
1890 | printk(KERN_ERR | |
1891 | "%s: Hardware doesn't specify base clock " | |
1892 | "frequency.\n", mmc_hostname(mmc)); | |
1893 | return -ENODEV; | |
1894 | } | |
1895 | host->max_clk = host->ops->get_max_clock(host); | |
8ef1a143 | 1896 | } |
d129bceb | 1897 | |
1c8cde92 PO |
1898 | host->timeout_clk = |
1899 | (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; | |
1900 | if (host->timeout_clk == 0) { | |
81b39802 AV |
1901 | if (host->ops->get_timeout_clock) { |
1902 | host->timeout_clk = host->ops->get_timeout_clock(host); | |
1903 | } else if (!(host->quirks & | |
1904 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { | |
4240ff0a BD |
1905 | printk(KERN_ERR |
1906 | "%s: Hardware doesn't specify timeout clock " | |
1907 | "frequency.\n", mmc_hostname(mmc)); | |
1908 | return -ENODEV; | |
1909 | } | |
1c8cde92 PO |
1910 | } |
1911 | if (caps & SDHCI_TIMEOUT_CLK_UNIT) | |
1912 | host->timeout_clk *= 1000; | |
d129bceb PO |
1913 | |
1914 | /* | |
1915 | * Set host parameters. | |
1916 | */ | |
1917 | mmc->ops = &sdhci_ops; | |
ce5f036b | 1918 | if (host->ops->get_min_clock) |
a9e58f25 | 1919 | mmc->f_min = host->ops->get_min_clock(host); |
0397526d ZG |
1920 | else if (host->version >= SDHCI_SPEC_300) |
1921 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; | |
a9e58f25 | 1922 | else |
0397526d | 1923 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
15ec4461 | 1924 | |
d129bceb | 1925 | mmc->f_max = host->max_clk; |
a3c7778f | 1926 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE; |
5fe23c7f | 1927 | |
15ec4461 PR |
1928 | /* |
1929 | * A controller may support 8-bit width, but the board itself | |
1930 | * might not have the pins brought out. Boards that support | |
1931 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in | |
1932 | * their platform code before calling sdhci_add_host(), and we | |
1933 | * won't assume 8-bit width for hosts without that CAP. | |
1934 | */ | |
5fe23c7f | 1935 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
15ec4461 | 1936 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
d129bceb | 1937 | |
86a6a874 | 1938 | if (caps & SDHCI_CAN_DO_HISPD) |
a29e7e18 | 1939 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
cd9277c0 | 1940 | |
176d1ed4 JC |
1941 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
1942 | mmc_card_is_removable(mmc)) | |
68d1fb7e AV |
1943 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
1944 | ||
8f230f45 | 1945 | ocr_avail = 0; |
146ad66e | 1946 | if (caps & SDHCI_CAN_VDD_330) |
8f230f45 | 1947 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
c70840e8 | 1948 | if (caps & SDHCI_CAN_VDD_300) |
8f230f45 | 1949 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
c70840e8 | 1950 | if (caps & SDHCI_CAN_VDD_180) |
8f230f45 TI |
1951 | ocr_avail |= MMC_VDD_165_195; |
1952 | ||
1953 | mmc->ocr_avail = ocr_avail; | |
1954 | mmc->ocr_avail_sdio = ocr_avail; | |
1955 | if (host->ocr_avail_sdio) | |
1956 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; | |
1957 | mmc->ocr_avail_sd = ocr_avail; | |
1958 | if (host->ocr_avail_sd) | |
1959 | mmc->ocr_avail_sd &= host->ocr_avail_sd; | |
1960 | else /* normal SD controllers don't support 1.8V */ | |
1961 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; | |
1962 | mmc->ocr_avail_mmc = ocr_avail; | |
1963 | if (host->ocr_avail_mmc) | |
1964 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; | |
146ad66e PO |
1965 | |
1966 | if (mmc->ocr_avail == 0) { | |
1967 | printk(KERN_ERR "%s: Hardware doesn't report any " | |
b69c9058 | 1968 | "support voltages.\n", mmc_hostname(mmc)); |
b8c86fc5 | 1969 | return -ENODEV; |
146ad66e PO |
1970 | } |
1971 | ||
d129bceb PO |
1972 | spin_lock_init(&host->lock); |
1973 | ||
1974 | /* | |
2134a922 PO |
1975 | * Maximum number of segments. Depends on if the hardware |
1976 | * can do scatter/gather or not. | |
d129bceb | 1977 | */ |
2134a922 | 1978 | if (host->flags & SDHCI_USE_ADMA) |
a36274e0 | 1979 | mmc->max_segs = 128; |
a13abc7b | 1980 | else if (host->flags & SDHCI_USE_SDMA) |
a36274e0 | 1981 | mmc->max_segs = 1; |
2134a922 | 1982 | else /* PIO */ |
a36274e0 | 1983 | mmc->max_segs = 128; |
d129bceb PO |
1984 | |
1985 | /* | |
bab76961 | 1986 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
55db890a | 1987 | * size (512KiB). |
d129bceb | 1988 | */ |
55db890a | 1989 | mmc->max_req_size = 524288; |
d129bceb PO |
1990 | |
1991 | /* | |
1992 | * Maximum segment size. Could be one segment with the maximum number | |
2134a922 PO |
1993 | * of bytes. When doing hardware scatter/gather, each entry cannot |
1994 | * be larger than 64 KiB though. | |
d129bceb | 1995 | */ |
30652aa3 OJ |
1996 | if (host->flags & SDHCI_USE_ADMA) { |
1997 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) | |
1998 | mmc->max_seg_size = 65535; | |
1999 | else | |
2000 | mmc->max_seg_size = 65536; | |
2001 | } else { | |
2134a922 | 2002 | mmc->max_seg_size = mmc->max_req_size; |
30652aa3 | 2003 | } |
d129bceb | 2004 | |
fe4a3c7a PO |
2005 | /* |
2006 | * Maximum block size. This varies from controller to controller and | |
2007 | * is specified in the capabilities register. | |
2008 | */ | |
0633f654 AV |
2009 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
2010 | mmc->max_blk_size = 2; | |
2011 | } else { | |
2012 | mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> | |
2013 | SDHCI_MAX_BLOCK_SHIFT; | |
2014 | if (mmc->max_blk_size >= 3) { | |
2015 | printk(KERN_WARNING "%s: Invalid maximum block size, " | |
2016 | "assuming 512 bytes\n", mmc_hostname(mmc)); | |
2017 | mmc->max_blk_size = 0; | |
2018 | } | |
2019 | } | |
2020 | ||
2021 | mmc->max_blk_size = 512 << mmc->max_blk_size; | |
fe4a3c7a | 2022 | |
55db890a PO |
2023 | /* |
2024 | * Maximum block count. | |
2025 | */ | |
1388eefd | 2026 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
55db890a | 2027 | |
d129bceb PO |
2028 | /* |
2029 | * Init tasklets. | |
2030 | */ | |
2031 | tasklet_init(&host->card_tasklet, | |
2032 | sdhci_tasklet_card, (unsigned long)host); | |
2033 | tasklet_init(&host->finish_tasklet, | |
2034 | sdhci_tasklet_finish, (unsigned long)host); | |
2035 | ||
e4cad1b5 | 2036 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
d129bceb | 2037 | |
dace1453 | 2038 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
b69c9058 | 2039 | mmc_hostname(mmc), host); |
d129bceb | 2040 | if (ret) |
8ef1a143 | 2041 | goto untasklet; |
d129bceb | 2042 | |
9bea3c85 MS |
2043 | host->vmmc = regulator_get(mmc_dev(mmc), "vmmc"); |
2044 | if (IS_ERR(host->vmmc)) { | |
2045 | printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc)); | |
2046 | host->vmmc = NULL; | |
2047 | } else { | |
2048 | regulator_enable(host->vmmc); | |
2049 | } | |
2050 | ||
2f4cbb3d | 2051 | sdhci_init(host, 0); |
d129bceb PO |
2052 | |
2053 | #ifdef CONFIG_MMC_DEBUG | |
2054 | sdhci_dumpregs(host); | |
2055 | #endif | |
2056 | ||
f9134319 | 2057 | #ifdef SDHCI_USE_LEDS_CLASS |
5dbace0c HS |
2058 | snprintf(host->led_name, sizeof(host->led_name), |
2059 | "%s::", mmc_hostname(mmc)); | |
2060 | host->led.name = host->led_name; | |
2f730fec PO |
2061 | host->led.brightness = LED_OFF; |
2062 | host->led.default_trigger = mmc_hostname(mmc); | |
2063 | host->led.brightness_set = sdhci_led_control; | |
2064 | ||
b8c86fc5 | 2065 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
2f730fec PO |
2066 | if (ret) |
2067 | goto reset; | |
2068 | #endif | |
2069 | ||
5f25a66f PO |
2070 | mmiowb(); |
2071 | ||
d129bceb PO |
2072 | mmc_add_host(mmc); |
2073 | ||
a13abc7b | 2074 | printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n", |
d1b26863 | 2075 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
a13abc7b RR |
2076 | (host->flags & SDHCI_USE_ADMA) ? "ADMA" : |
2077 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); | |
d129bceb | 2078 | |
7260cf5e AV |
2079 | sdhci_enable_card_detection(host); |
2080 | ||
d129bceb PO |
2081 | return 0; |
2082 | ||
f9134319 | 2083 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
2084 | reset: |
2085 | sdhci_reset(host, SDHCI_RESET_ALL); | |
2086 | free_irq(host->irq, host); | |
2087 | #endif | |
8ef1a143 | 2088 | untasklet: |
d129bceb PO |
2089 | tasklet_kill(&host->card_tasklet); |
2090 | tasklet_kill(&host->finish_tasklet); | |
d129bceb PO |
2091 | |
2092 | return ret; | |
2093 | } | |
2094 | ||
b8c86fc5 | 2095 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
d129bceb | 2096 | |
1e72859e | 2097 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
b8c86fc5 | 2098 | { |
1e72859e PO |
2099 | unsigned long flags; |
2100 | ||
2101 | if (dead) { | |
2102 | spin_lock_irqsave(&host->lock, flags); | |
2103 | ||
2104 | host->flags |= SDHCI_DEVICE_DEAD; | |
2105 | ||
2106 | if (host->mrq) { | |
2107 | printk(KERN_ERR "%s: Controller removed during " | |
2108 | " transfer!\n", mmc_hostname(host->mmc)); | |
2109 | ||
2110 | host->mrq->cmd->error = -ENOMEDIUM; | |
2111 | tasklet_schedule(&host->finish_tasklet); | |
2112 | } | |
2113 | ||
2114 | spin_unlock_irqrestore(&host->lock, flags); | |
2115 | } | |
2116 | ||
7260cf5e AV |
2117 | sdhci_disable_card_detection(host); |
2118 | ||
b8c86fc5 | 2119 | mmc_remove_host(host->mmc); |
d129bceb | 2120 | |
f9134319 | 2121 | #ifdef SDHCI_USE_LEDS_CLASS |
2f730fec PO |
2122 | led_classdev_unregister(&host->led); |
2123 | #endif | |
2124 | ||
1e72859e PO |
2125 | if (!dead) |
2126 | sdhci_reset(host, SDHCI_RESET_ALL); | |
d129bceb PO |
2127 | |
2128 | free_irq(host->irq, host); | |
2129 | ||
2130 | del_timer_sync(&host->timer); | |
2131 | ||
2132 | tasklet_kill(&host->card_tasklet); | |
2133 | tasklet_kill(&host->finish_tasklet); | |
2134a922 | 2134 | |
9bea3c85 MS |
2135 | if (host->vmmc) { |
2136 | regulator_disable(host->vmmc); | |
2137 | regulator_put(host->vmmc); | |
2138 | } | |
2139 | ||
2134a922 PO |
2140 | kfree(host->adma_desc); |
2141 | kfree(host->align_buffer); | |
2142 | ||
2143 | host->adma_desc = NULL; | |
2144 | host->align_buffer = NULL; | |
d129bceb PO |
2145 | } |
2146 | ||
b8c86fc5 | 2147 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
d129bceb | 2148 | |
b8c86fc5 | 2149 | void sdhci_free_host(struct sdhci_host *host) |
d129bceb | 2150 | { |
b8c86fc5 | 2151 | mmc_free_host(host->mmc); |
d129bceb PO |
2152 | } |
2153 | ||
b8c86fc5 | 2154 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
d129bceb PO |
2155 | |
2156 | /*****************************************************************************\ | |
2157 | * * | |
2158 | * Driver init/exit * | |
2159 | * * | |
2160 | \*****************************************************************************/ | |
2161 | ||
2162 | static int __init sdhci_drv_init(void) | |
2163 | { | |
2164 | printk(KERN_INFO DRIVER_NAME | |
52fbf9c9 | 2165 | ": Secure Digital Host Controller Interface driver\n"); |
d129bceb PO |
2166 | printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
2167 | ||
b8c86fc5 | 2168 | return 0; |
d129bceb PO |
2169 | } |
2170 | ||
2171 | static void __exit sdhci_drv_exit(void) | |
2172 | { | |
d129bceb PO |
2173 | } |
2174 | ||
2175 | module_init(sdhci_drv_init); | |
2176 | module_exit(sdhci_drv_exit); | |
2177 | ||
df673b22 | 2178 | module_param(debug_quirks, uint, 0444); |
67435274 | 2179 | |
32710e8f | 2180 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 | 2181 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
d129bceb | 2182 | MODULE_LICENSE("GPL"); |
67435274 | 2183 | |
df673b22 | 2184 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |