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mmc: core: Add claiming of hosts during mmc_cache_ctrl
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
d129bceb 30
d129bceb
PO		 31#include "sdhci.h"
32
33#define DRIVER_NAME "sdhci"
d129bceb 34
d129bceb 35#define DBG(f, x...) \
c6563178 36 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 37
f9134319
PO		 38#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
39 defined(CONFIG_MMC_SDHCI_MODULE))
40#define SDHCI_USE_LEDS_CLASS
41#endif
42
b513ea25
AN		 43#define MAX_TUNING_LOOP 40
44
df673b22 45static unsigned int debug_quirks = 0;
66fd8ad5 46static unsigned int debug_quirks2;
67435274 47
d129bceb
PO		 48static void sdhci_finish_data(struct sdhci_host *);
49
50static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
51static void sdhci_finish_command(struct sdhci_host *);
cf2b5eea
AN		 52static int sdhci_execute_tuning(struct mmc_host *mmc);
53static void sdhci_tuning_timer(unsigned long data);
d129bceb 54
66fd8ad5
AH		 55#ifdef CONFIG_PM_RUNTIME
56static int sdhci_runtime_pm_get(struct sdhci_host *host);
57static int sdhci_runtime_pm_put(struct sdhci_host *host);
58#else
59static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
60{
61 return 0;
62}
63static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
64{
65 return 0;
66}
67#endif
68
d129bceb
PO		 69static void sdhci_dumpregs(struct sdhci_host *host)
70{
a3c76eb9 71 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 72 mmc_hostname(host->mmc));
d129bceb 73
a3c76eb9 74 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 75 sdhci_readl(host, SDHCI_DMA_ADDRESS),
76 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 77 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 78 sdhci_readw(host, SDHCI_BLOCK_SIZE),
79 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 80 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 81 sdhci_readl(host, SDHCI_ARGUMENT),
82 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 83 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 84 sdhci_readl(host, SDHCI_PRESENT_STATE),
85 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 86 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 87 sdhci_readb(host, SDHCI_POWER_CONTROL),
88 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 89 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 90 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
91 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 92 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 93 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
94 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 95 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 96 sdhci_readl(host, SDHCI_INT_ENABLE),
97 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 98 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 99 sdhci_readw(host, SDHCI_ACMD12_ERR),
100 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 101 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 102 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 103 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 104 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 105 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 106 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 107 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 108 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 109
be3f4ae0 110 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 111 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 112 readl(host->ioaddr + SDHCI_ADMA_ERROR),
113 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
114
a3c76eb9 115 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 116}
117
118/*****************************************************************************\
119 * *
120 * Low level functions *
121 * *
122\*****************************************************************************/
123
7260cf5e
AV		 124static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
125{
126 u32 ier;
127
128 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
129 ier &= ~clear;
130 ier |= set;
131 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
132 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
133}
134
135static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
136{
137 sdhci_clear_set_irqs(host, 0, irqs);
138}
139
140static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
141{
142 sdhci_clear_set_irqs(host, irqs, 0);
143}
144
145static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
146{
d25928d1 147 u32 present, irqs;
7260cf5e 148
68d1fb7e
AV		 149 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
150 return;
151
66fd8ad5
AH		 152 if (host->quirks2 & SDHCI_QUIRK2_OWN_CARD_DETECTION)
153 return;
154
d25928d1
SG		 155 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
156 SDHCI_CARD_PRESENT;
157 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
158
7260cf5e
AV		 159 if (enable)
160 sdhci_unmask_irqs(host, irqs);
161 else
162 sdhci_mask_irqs(host, irqs);
163}
164
165static void sdhci_enable_card_detection(struct sdhci_host *host)
166{
167 sdhci_set_card_detection(host, true);
168}
169
170static void sdhci_disable_card_detection(struct sdhci_host *host)
171{
172 sdhci_set_card_detection(host, false);
173}
174
d129bceb
PO		 175static void sdhci_reset(struct sdhci_host *host, u8 mask)
176{
e16514d8 177 unsigned long timeout;
063a9dbb 178 u32 uninitialized_var(ier);
e16514d8 179
b8c86fc5 180 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 181 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 182 SDHCI_CARD_PRESENT))
183 return;
184 }
185
063a9dbb
AV		 186 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
187 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
188
393c1a34
PR		 189 if (host->ops->platform_reset_enter)
190 host->ops->platform_reset_enter(host, mask);
191
4e4141a5 192 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 193
e16514d8 194 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 195 host->clock = 0;
196
e16514d8
PO		 197 /* Wait max 100 ms */
198 timeout = 100;
199
200 /* hw clears the bit when it's done */
4e4141a5 201 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 202 if (timeout == 0) {
a3c76eb9 203 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 204 mmc_hostname(host->mmc), (int)mask);
205 sdhci_dumpregs(host);
206 return;
207 }
208 timeout--;
209 mdelay(1);
d129bceb 210 }
063a9dbb 211
393c1a34
PR		 212 if (host->ops->platform_reset_exit)
213 host->ops->platform_reset_exit(host, mask);
214
063a9dbb
AV		 215 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
216 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 217}
218
2f4cbb3d
NP		 219static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
220
221static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 222{
2f4cbb3d
NP		 223 if (soft)
224 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
225 else
226 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 227
7260cf5e
AV		 228 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
229 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 230 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
231 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 232 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 233
234 if (soft) {
235 /* force clock reconfiguration */
236 host->clock = 0;
237 sdhci_set_ios(host->mmc, &host->mmc->ios);
238 }
7260cf5e 239}
d129bceb 240
7260cf5e
AV		 241static void sdhci_reinit(struct sdhci_host *host)
242{
2f4cbb3d 243 sdhci_init(host, 0);
7260cf5e 244 sdhci_enable_card_detection(host);
d129bceb
PO		 245}
246
247static void sdhci_activate_led(struct sdhci_host *host)
248{
249 u8 ctrl;
250
4e4141a5 251 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 252 ctrl |= SDHCI_CTRL_LED;
4e4141a5 253 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 254}
255
256static void sdhci_deactivate_led(struct sdhci_host *host)
257{
258 u8 ctrl;
259
4e4141a5 260 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 261 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 262 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 263}
264
f9134319 265#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 266static void sdhci_led_control(struct led_classdev *led,
267 enum led_brightness brightness)
268{
269 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
270 unsigned long flags;
271
272 spin_lock_irqsave(&host->lock, flags);
273
66fd8ad5
AH		 274 if (host->runtime_suspended)
275 goto out;
276
2f730fec
PO		 277 if (brightness == LED_OFF)
278 sdhci_deactivate_led(host);
279 else
280 sdhci_activate_led(host);
66fd8ad5 281out:
2f730fec
PO		 282 spin_unlock_irqrestore(&host->lock, flags);
283}
284#endif
285
d129bceb
PO		 286/*****************************************************************************\
287 * *
288 * Core functions *
289 * *
290\*****************************************************************************/
291
a406f5a3 292static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 293{
7659150c
PO		 294 unsigned long flags;
295 size_t blksize, len, chunk;
7244b85b 296 u32 uninitialized_var(scratch);
7659150c 297 u8 *buf;
d129bceb 298
a406f5a3 299 DBG("PIO reading\n");
d129bceb 300
a406f5a3 301 blksize = host->data->blksz;
7659150c 302 chunk = 0;
d129bceb 303
7659150c 304 local_irq_save(flags);
d129bceb 305
a406f5a3 306 while (blksize) {
7659150c
PO		 307 if (!sg_miter_next(&host->sg_miter))
308 BUG();
d129bceb 309
7659150c 310 len = min(host->sg_miter.length, blksize);
d129bceb 311
7659150c
PO		 312 blksize -= len;
313 host->sg_miter.consumed = len;
14d836e7 314
7659150c 315 buf = host->sg_miter.addr;
d129bceb 316
7659150c
PO		 317 while (len) {
318 if (chunk == 0) {
4e4141a5 319 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 320 chunk = 4;
a406f5a3 321 }
7659150c
PO		 322
323 *buf = scratch & 0xFF;
324
325 buf++;
326 scratch >>= 8;
327 chunk--;
328 len--;
d129bceb 329 }
a406f5a3 330 }
7659150c
PO		 331
332 sg_miter_stop(&host->sg_miter);
333
334 local_irq_restore(flags);
a406f5a3 335}
d129bceb 336
a406f5a3
PO		 337static void sdhci_write_block_pio(struct sdhci_host *host)
338{
7659150c
PO		 339 unsigned long flags;
340 size_t blksize, len, chunk;
341 u32 scratch;
342 u8 *buf;
d129bceb 343
a406f5a3
PO		 344 DBG("PIO writing\n");
345
346 blksize = host->data->blksz;
7659150c
PO		 347 chunk = 0;
348 scratch = 0;
d129bceb 349
7659150c 350 local_irq_save(flags);
d129bceb 351
a406f5a3 352 while (blksize) {
7659150c
PO		 353 if (!sg_miter_next(&host->sg_miter))
354 BUG();
a406f5a3 355
7659150c
PO		 356 len = min(host->sg_miter.length, blksize);
357
358 blksize -= len;
359 host->sg_miter.consumed = len;
360
361 buf = host->sg_miter.addr;
d129bceb 362
7659150c
PO		 363 while (len) {
364 scratch |= (u32)*buf << (chunk * 8);
365
366 buf++;
367 chunk++;
368 len--;
369
370 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 371 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 372 chunk = 0;
373 scratch = 0;
d129bceb 374 }
d129bceb
PO		 375 }
376 }
7659150c
PO		 377
378 sg_miter_stop(&host->sg_miter);
379
380 local_irq_restore(flags);
a406f5a3
PO		 381}
382
383static void sdhci_transfer_pio(struct sdhci_host *host)
384{
385 u32 mask;
386
387 BUG_ON(!host->data);
388
7659150c 389 if (host->blocks == 0)
a406f5a3
PO		 390 return;
391
392 if (host->data->flags & MMC_DATA_READ)
393 mask = SDHCI_DATA_AVAILABLE;
394 else
395 mask = SDHCI_SPACE_AVAILABLE;
396
4a3cba32
PO		 397 /*
398 * Some controllers (JMicron JMB38x) mess up the buffer bits
399 * for transfers < 4 bytes. As long as it is just one block,
400 * we can ignore the bits.
401 */
402 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
403 (host->data->blocks == 1))
404 mask = ~0;
405
4e4141a5 406 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 407 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
408 udelay(100);
409
a406f5a3
PO		 410 if (host->data->flags & MMC_DATA_READ)
411 sdhci_read_block_pio(host);
412 else
413 sdhci_write_block_pio(host);
d129bceb 414
7659150c
PO		 415 host->blocks--;
416 if (host->blocks == 0)
a406f5a3 417 break;
a406f5a3 418 }
d129bceb 419
a406f5a3 420 DBG("PIO transfer complete.\n");
d129bceb
PO		 421}
422
2134a922
PO		 423static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
424{
425 local_irq_save(*flags);
482fce99 426 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 427}
428
429static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
430{
482fce99 431 kunmap_atomic(buffer);
2134a922
PO		 432 local_irq_restore(*flags);
433}
434
118cd17d
BD		 435static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
436{
9e506f35
BD		 437 __le32 *dataddr = (__le32 __force *)(desc + 4);
438 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 439
9e506f35
BD		 440 /* SDHCI specification says ADMA descriptors should be 4 byte
441 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 442
9e506f35
BD		 443 cmdlen[0] = cpu_to_le16(cmd);
444 cmdlen[1] = cpu_to_le16(len);
445
446 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 447}
448
8f1934ce 449static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 450 struct mmc_data *data)
451{
452 int direction;
453
454 u8 *desc;
455 u8 *align;
456 dma_addr_t addr;
457 dma_addr_t align_addr;
458 int len, offset;
459
460 struct scatterlist *sg;
461 int i;
462 char *buffer;
463 unsigned long flags;
464
465 /*
466 * The spec does not specify endianness of descriptor table.
467 * We currently guess that it is LE.
468 */
469
470 if (data->flags & MMC_DATA_READ)
471 direction = DMA_FROM_DEVICE;
472 else
473 direction = DMA_TO_DEVICE;
474
475 /*
476 * The ADMA descriptor table is mapped further down as we
477 * need to fill it with data first.
478 */
479
480 host->align_addr = dma_map_single(mmc_dev(host->mmc),
481 host->align_buffer, 128 * 4, direction);
8d8bb39b 482 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 483 goto fail;
2134a922
PO		 484 BUG_ON(host->align_addr & 0x3);
485
486 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
487 data->sg, data->sg_len, direction);
8f1934ce
PO		 488 if (host->sg_count == 0)
489 goto unmap_align;
2134a922
PO		 490
491 desc = host->adma_desc;
492 align = host->align_buffer;
493
494 align_addr = host->align_addr;
495
496 for_each_sg(data->sg, sg, host->sg_count, i) {
497 addr = sg_dma_address(sg);
498 len = sg_dma_len(sg);
499
500 /*
501 * The SDHCI specification states that ADMA
502 * addresses must be 32-bit aligned. If they
503 * aren't, then we use a bounce buffer for
504 * the (up to three) bytes that screw up the
505 * alignment.
506 */
507 offset = (4 - (addr & 0x3)) & 0x3;
508 if (offset) {
509 if (data->flags & MMC_DATA_WRITE) {
510 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 511 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 512 memcpy(align, buffer, offset);
513 sdhci_kunmap_atomic(buffer, &flags);
514 }
515
118cd17d
BD		 516 /* tran, valid */
517 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 518
519 BUG_ON(offset > 65536);
520
2134a922
PO		 521 align += 4;
522 align_addr += 4;
523
524 desc += 8;
525
526 addr += offset;
527 len -= offset;
528 }
529
2134a922
PO		 530 BUG_ON(len > 65536);
531
118cd17d
BD		 532 /* tran, valid */
533 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 534 desc += 8;
535
536 /*
537 * If this triggers then we have a calculation bug
538 * somewhere. :/
539 */
540 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
541 }
542
70764a90
TA		 543 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
544 /*
545 * Mark the last descriptor as the terminating descriptor
546 */
547 if (desc != host->adma_desc) {
548 desc -= 8;
549 desc[0] |= 0x2; /* end */
550 }
551 } else {
552 /*
553 * Add a terminating entry.
554 */
2134a922 555
70764a90
TA		 556 /* nop, end, valid */
557 sdhci_set_adma_desc(desc, 0, 0, 0x3);
558 }
2134a922
PO		 559
560 /*
561 * Resync align buffer as we might have changed it.
562 */
563 if (data->flags & MMC_DATA_WRITE) {
564 dma_sync_single_for_device(mmc_dev(host->mmc),
565 host->align_addr, 128 * 4, direction);
566 }
567
568 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
569 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 570 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 571 goto unmap_entries;
2134a922 572 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 573
574 return 0;
575
576unmap_entries:
577 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
578 data->sg_len, direction);
579unmap_align:
580 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
581 128 * 4, direction);
582fail:
583 return -EINVAL;
2134a922
PO		 584}
585
586static void sdhci_adma_table_post(struct sdhci_host *host,
587 struct mmc_data *data)
588{
589 int direction;
590
591 struct scatterlist *sg;
592 int i, size;
593 u8 *align;
594 char *buffer;
595 unsigned long flags;
596
597 if (data->flags & MMC_DATA_READ)
598 direction = DMA_FROM_DEVICE;
599 else
600 direction = DMA_TO_DEVICE;
601
602 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
603 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
604
605 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
606 128 * 4, direction);
607
608 if (data->flags & MMC_DATA_READ) {
609 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
610 data->sg_len, direction);
611
612 align = host->align_buffer;
613
614 for_each_sg(data->sg, sg, host->sg_count, i) {
615 if (sg_dma_address(sg) & 0x3) {
616 size = 4 - (sg_dma_address(sg) & 0x3);
617
618 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 619 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 620 memcpy(buffer, align, size);
621 sdhci_kunmap_atomic(buffer, &flags);
622
623 align += 4;
624 }
625 }
626 }
627
628 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
629 data->sg_len, direction);
630}
631
a3c7778f 632static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 633{
1c8cde92 634 u8 count;
a3c7778f 635 struct mmc_data *data = cmd->data;
1c8cde92 636 unsigned target_timeout, current_timeout;
d129bceb 637
ee53ab5d
PO		 638 /*
639 * If the host controller provides us with an incorrect timeout
640 * value, just skip the check and use 0xE. The hardware may take
641 * longer to time out, but that's much better than having a too-short
642 * timeout value.
643 */
11a2f1b7 644 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 645 return 0xE;
e538fbe8 646
a3c7778f
AW		 647 /* Unspecified timeout, assume max */
648 if (!data && !cmd->cmd_timeout_ms)
649 return 0xE;
d129bceb 650
a3c7778f
AW		 651 /* timeout in us */
652 if (!data)
653 target_timeout = cmd->cmd_timeout_ms * 1000;
78a2ca27
AS		 654 else {
655 target_timeout = data->timeout_ns / 1000;
656 if (host->clock)
657 target_timeout += data->timeout_clks / host->clock;
658 }
81b39802 659
1c8cde92
PO		 660 /*
661 * Figure out needed cycles.
662 * We do this in steps in order to fit inside a 32 bit int.
663 * The first step is the minimum timeout, which will have a
664 * minimum resolution of 6 bits:
665 * (1) 2^13*1000 > 2^22,
666 * (2) host->timeout_clk < 2^16
667 * =>
668 * (1) / (2) > 2^6
669 */
670 count = 0;
671 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
672 while (current_timeout < target_timeout) {
673 count++;
674 current_timeout <<= 1;
675 if (count >= 0xF)
676 break;
677 }
678
679 if (count >= 0xF) {
a3c76eb9 680 pr_warning("%s: Too large timeout requested for CMD%d!\n",
a3c7778f 681 mmc_hostname(host->mmc), cmd->opcode);
1c8cde92
PO		 682 count = 0xE;
683 }
684
ee53ab5d
PO		 685 return count;
686}
687
6aa943ab
AV		 688static void sdhci_set_transfer_irqs(struct sdhci_host *host)
689{
690 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
691 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
692
693 if (host->flags & SDHCI_REQ_USE_DMA)
694 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
695 else
696 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
697}
698
a3c7778f 699static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 700{
701 u8 count;
2134a922 702 u8 ctrl;
a3c7778f 703 struct mmc_data *data = cmd->data;
8f1934ce 704 int ret;
ee53ab5d
PO		 705
706 WARN_ON(host->data);
707
a3c7778f
AW		 708 if (data || (cmd->flags & MMC_RSP_BUSY)) {
709 count = sdhci_calc_timeout(host, cmd);
710 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
711 }
712
713 if (!data)
ee53ab5d
PO		 714 return;
715
716 /* Sanity checks */
717 BUG_ON(data->blksz * data->blocks > 524288);
718 BUG_ON(data->blksz > host->mmc->max_blk_size);
719 BUG_ON(data->blocks > 65535);
720
721 host->data = data;
722 host->data_early = 0;
f6a03cbf 723 host->data->bytes_xfered = 0;
ee53ab5d 724
a13abc7b 725 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 726 host->flags |= SDHCI_REQ_USE_DMA;
727
2134a922
PO		 728 /*
729 * FIXME: This doesn't account for merging when mapping the
730 * scatterlist.
731 */
732 if (host->flags & SDHCI_REQ_USE_DMA) {
733 int broken, i;
734 struct scatterlist *sg;
735
736 broken = 0;
737 if (host->flags & SDHCI_USE_ADMA) {
738 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
739 broken = 1;
740 } else {
741 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
742 broken = 1;
743 }
744
745 if (unlikely(broken)) {
746 for_each_sg(data->sg, sg, data->sg_len, i) {
747 if (sg->length & 0x3) {
748 DBG("Reverting to PIO because of "
749 "transfer size (%d)\n",
750 sg->length);
751 host->flags &= ~SDHCI_REQ_USE_DMA;
752 break;
753 }
754 }
755 }
c9fddbc4
PO		 756 }
757
758 /*
759 * The assumption here being that alignment is the same after
760 * translation to device address space.
761 */
2134a922
PO		 762 if (host->flags & SDHCI_REQ_USE_DMA) {
763 int broken, i;
764 struct scatterlist *sg;
765
766 broken = 0;
767 if (host->flags & SDHCI_USE_ADMA) {
768 /*
769 * As we use 3 byte chunks to work around
770 * alignment problems, we need to check this
771 * quirk.
772 */
773 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
774 broken = 1;
775 } else {
776 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
777 broken = 1;
778 }
779
780 if (unlikely(broken)) {
781 for_each_sg(data->sg, sg, data->sg_len, i) {
782 if (sg->offset & 0x3) {
783 DBG("Reverting to PIO because of "
784 "bad alignment\n");
785 host->flags &= ~SDHCI_REQ_USE_DMA;
786 break;
787 }
788 }
789 }
790 }
791
8f1934ce
PO		 792 if (host->flags & SDHCI_REQ_USE_DMA) {
793 if (host->flags & SDHCI_USE_ADMA) {
794 ret = sdhci_adma_table_pre(host, data);
795 if (ret) {
796 /*
797 * This only happens when someone fed
798 * us an invalid request.
799 */
800 WARN_ON(1);
ebd6d357 801 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 802 } else {
4e4141a5
AV		 803 sdhci_writel(host, host->adma_addr,
804 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 805 }
806 } else {
c8b3e02e 807 int sg_cnt;
8f1934ce 808
c8b3e02e 809 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 810 data->sg, data->sg_len,
811 (data->flags & MMC_DATA_READ) ?
812 DMA_FROM_DEVICE :
813 DMA_TO_DEVICE);
c8b3e02e 814 if (sg_cnt == 0) {
8f1934ce
PO		 815 /*
816 * This only happens when someone fed
817 * us an invalid request.
818 */
819 WARN_ON(1);
ebd6d357 820 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 821 } else {
719a61b4 822 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 823 sdhci_writel(host, sg_dma_address(data->sg),
824 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 825 }
826 }
827 }
828
2134a922
PO		 829 /*
830 * Always adjust the DMA selection as some controllers
831 * (e.g. JMicron) can't do PIO properly when the selection
832 * is ADMA.
833 */
834 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 835 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 836 ctrl &= ~SDHCI_CTRL_DMA_MASK;
837 if ((host->flags & SDHCI_REQ_USE_DMA) &&
838 (host->flags & SDHCI_USE_ADMA))
839 ctrl |= SDHCI_CTRL_ADMA32;
840 else
841 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 842 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 843 }
844
8f1934ce 845 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 846 int flags;
847
848 flags = SG_MITER_ATOMIC;
849 if (host->data->flags & MMC_DATA_READ)
850 flags |= SG_MITER_TO_SG;
851 else
852 flags |= SG_MITER_FROM_SG;
853 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 854 host->blocks = data->blocks;
d129bceb 855 }
c7fa9963 856
6aa943ab
AV		 857 sdhci_set_transfer_irqs(host);
858
f6a03cbf
MV		 859 /* Set the DMA boundary value and block size */
860 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
861 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 862 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 863}
864
865static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 866 struct mmc_command *cmd)
c7fa9963
PO		 867{
868 u16 mode;
e89d456f 869 struct mmc_data *data = cmd->data;
c7fa9963 870
c7fa9963
PO		 871 if (data == NULL)
872 return;
873
e538fbe8
PO		 874 WARN_ON(!host->data);
875
c7fa9963 876 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 877 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
878 mode |= SDHCI_TRNS_MULTI;
879 /*
880 * If we are sending CMD23, CMD12 never gets sent
881 * on successful completion (so no Auto-CMD12).
882 */
883 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
884 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 885 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
886 mode |= SDHCI_TRNS_AUTO_CMD23;
887 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
888 }
c4512f79 889 }
8edf6371 890
c7fa9963
PO		 891 if (data->flags & MMC_DATA_READ)
892 mode |= SDHCI_TRNS_READ;
c9fddbc4 893 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 894 mode |= SDHCI_TRNS_DMA;
895
4e4141a5 896 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 897}
898
899static void sdhci_finish_data(struct sdhci_host *host)
900{
901 struct mmc_data *data;
d129bceb
PO		 902
903 BUG_ON(!host->data);
904
905 data = host->data;
906 host->data = NULL;
907
c9fddbc4 908 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 909 if (host->flags & SDHCI_USE_ADMA)
910 sdhci_adma_table_post(host, data);
911 else {
912 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
913 data->sg_len, (data->flags & MMC_DATA_READ) ?
914 DMA_FROM_DEVICE : DMA_TO_DEVICE);
915 }
d129bceb
PO		 916 }
917
918 /*
c9b74c5b
PO		 919 * The specification states that the block count register must
920 * be updated, but it does not specify at what point in the
921 * data flow. That makes the register entirely useless to read
922 * back so we have to assume that nothing made it to the card
923 * in the event of an error.
d129bceb 924 */
c9b74c5b
PO		 925 if (data->error)
926 data->bytes_xfered = 0;
d129bceb 927 else
c9b74c5b 928 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 929
e89d456f
AW		 930 /*
931 * Need to send CMD12 if -
932 * a) open-ended multiblock transfer (no CMD23)
933 * b) error in multiblock transfer
934 */
935 if (data->stop &&
936 (data->error ||
937 !host->mrq->sbc)) {
938
d129bceb
PO		 939 /*
940 * The controller needs a reset of internal state machines
941 * upon error conditions.
942 */
17b0429d 943 if (data->error) {
d129bceb
PO		 944 sdhci_reset(host, SDHCI_RESET_CMD);
945 sdhci_reset(host, SDHCI_RESET_DATA);
946 }
947
948 sdhci_send_command(host, data->stop);
949 } else
950 tasklet_schedule(&host->finish_tasklet);
951}
952
953static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
954{
955 int flags;
fd2208d7 956 u32 mask;
7cb2c76f 957 unsigned long timeout;
d129bceb
PO		 958
959 WARN_ON(host->cmd);
960
d129bceb 961 /* Wait max 10 ms */
7cb2c76f 962 timeout = 10;
fd2208d7
PO		 963
964 mask = SDHCI_CMD_INHIBIT;
965 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
966 mask |= SDHCI_DATA_INHIBIT;
967
968 /* We shouldn't wait for data inihibit for stop commands, even
969 though they might use busy signaling */
970 if (host->mrq->data && (cmd == host->mrq->data->stop))
971 mask &= ~SDHCI_DATA_INHIBIT;
972
4e4141a5 973 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 974 if (timeout == 0) {
a3c76eb9 975 pr_err("%s: Controller never released "
acf1da45 976 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 977 sdhci_dumpregs(host);
17b0429d 978 cmd->error = -EIO;
d129bceb
PO		 979 tasklet_schedule(&host->finish_tasklet);
980 return;
981 }
7cb2c76f
PO		 982 timeout--;
983 mdelay(1);
984 }
d129bceb
PO		 985
986 mod_timer(&host->timer, jiffies + 10 * HZ);
987
988 host->cmd = cmd;
989
a3c7778f 990 sdhci_prepare_data(host, cmd);
d129bceb 991
4e4141a5 992 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 993
e89d456f 994 sdhci_set_transfer_mode(host, cmd);
c7fa9963 995
d129bceb 996 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 997 pr_err("%s: Unsupported response type!\n",
d129bceb 998 mmc_hostname(host->mmc));
17b0429d 999 cmd->error = -EINVAL;
d129bceb
PO		 1000 tasklet_schedule(&host->finish_tasklet);
1001 return;
1002 }
1003
1004 if (!(cmd->flags & MMC_RSP_PRESENT))
1005 flags = SDHCI_CMD_RESP_NONE;
1006 else if (cmd->flags & MMC_RSP_136)
1007 flags = SDHCI_CMD_RESP_LONG;
1008 else if (cmd->flags & MMC_RSP_BUSY)
1009 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1010 else
1011 flags = SDHCI_CMD_RESP_SHORT;
1012
1013 if (cmd->flags & MMC_RSP_CRC)
1014 flags |= SDHCI_CMD_CRC;
1015 if (cmd->flags & MMC_RSP_OPCODE)
1016 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1017
1018 /* CMD19 is special in that the Data Present Select should be set */
1019 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
d129bceb
PO		 1020 flags |= SDHCI_CMD_DATA;
1021
4e4141a5 1022 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 1023}
1024
1025static void sdhci_finish_command(struct sdhci_host *host)
1026{
1027 int i;
1028
1029 BUG_ON(host->cmd == NULL);
1030
1031 if (host->cmd->flags & MMC_RSP_PRESENT) {
1032 if (host->cmd->flags & MMC_RSP_136) {
1033 /* CRC is stripped so we need to do some shifting. */
1034 for (i = 0;i < 4;i++) {
4e4141a5 1035 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1036 SDHCI_RESPONSE + (3-i)*4) << 8;
1037 if (i != 3)
1038 host->cmd->resp[i] |=
4e4141a5 1039 sdhci_readb(host,
d129bceb
PO		 1040 SDHCI_RESPONSE + (3-i)*4-1);
1041 }
1042 } else {
4e4141a5 1043 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1044 }
1045 }
1046
17b0429d 1047 host->cmd->error = 0;
d129bceb 1048
e89d456f
AW		 1049 /* Finished CMD23, now send actual command. */
1050 if (host->cmd == host->mrq->sbc) {
1051 host->cmd = NULL;
1052 sdhci_send_command(host, host->mrq->cmd);
1053 } else {
e538fbe8 1054
e89d456f
AW		 1055 /* Processed actual command. */
1056 if (host->data && host->data_early)
1057 sdhci_finish_data(host);
d129bceb 1058
e89d456f
AW		 1059 if (!host->cmd->data)
1060 tasklet_schedule(&host->finish_tasklet);
1061
1062 host->cmd = NULL;
1063 }
d129bceb
PO		 1064}
1065
1066static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1067{
c3ed3877 1068 int div = 0; /* Initialized for compiler warning */
df16219f 1069 int real_div = div, clk_mul = 1;
c3ed3877 1070 u16 clk = 0;
7cb2c76f 1071 unsigned long timeout;
d129bceb
PO		 1072
1073 if (clock == host->clock)
1074 return;
1075
df16219f
GC		 1076 host->mmc->actual_clock = 0;
1077
8114634c
AV		 1078 if (host->ops->set_clock) {
1079 host->ops->set_clock(host, clock);
1080 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1081 return;
1082 }
1083
4e4141a5 1084 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1085
1086 if (clock == 0)
1087 goto out;
1088
85105c53 1089 if (host->version >= SDHCI_SPEC_300) {
c3ed3877
AN		 1090 /*
1091 * Check if the Host Controller supports Programmable Clock
1092 * Mode.
1093 */
1094 if (host->clk_mul) {
1095 u16 ctrl;
1096
1097 /*
1098 * We need to figure out whether the Host Driver needs
1099 * to select Programmable Clock Mode, or the value can
1100 * be set automatically by the Host Controller based on
1101 * the Preset Value registers.
1102 */
1103 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1104 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1105 for (div = 1; div <= 1024; div++) {
1106 if (((host->max_clk * host->clk_mul) /
1107 div) <= clock)
1108 break;
1109 }
1110 /*
1111 * Set Programmable Clock Mode in the Clock
1112 * Control register.
1113 */
1114 clk = SDHCI_PROG_CLOCK_MODE;
df16219f
GC		 1115 real_div = div;
1116 clk_mul = host->clk_mul;
c3ed3877
AN		 1117 div--;
1118 }
1119 } else {
1120 /* Version 3.00 divisors must be a multiple of 2. */
1121 if (host->max_clk <= clock)
1122 div = 1;
1123 else {
1124 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1125 div += 2) {
1126 if ((host->max_clk / div) <= clock)
1127 break;
1128 }
85105c53 1129 }
df16219f 1130 real_div = div;
c3ed3877 1131 div >>= 1;
85105c53
ZG		 1132 }
1133 } else {
1134 /* Version 2.00 divisors must be a power of 2. */
0397526d 1135 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1136 if ((host->max_clk / div) <= clock)
1137 break;
1138 }
df16219f 1139 real_div = div;
c3ed3877 1140 div >>= 1;
d129bceb 1141 }
d129bceb 1142
df16219f
GC		 1143 if (real_div)
1144 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1145
c3ed3877 1146 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1147 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1148 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1149 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1150 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1151
27f6cb16
CB		 1152 /* Wait max 20 ms */
1153 timeout = 20;
4e4141a5 1154 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1155 & SDHCI_CLOCK_INT_STABLE)) {
1156 if (timeout == 0) {
a3c76eb9 1157 pr_err("%s: Internal clock never "
acf1da45 1158 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1159 sdhci_dumpregs(host);
1160 return;
1161 }
7cb2c76f
PO		 1162 timeout--;
1163 mdelay(1);
1164 }
d129bceb
PO		 1165
1166 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1167 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1168
1169out:
1170 host->clock = clock;
1171}
1172
146ad66e
PO		 1173static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1174{
8364248a 1175 u8 pwr = 0;
146ad66e 1176
8364248a 1177 if (power != (unsigned short)-1) {
ae628903
PO		 1178 switch (1 << power) {
1179 case MMC_VDD_165_195:
1180 pwr = SDHCI_POWER_180;
1181 break;
1182 case MMC_VDD_29_30:
1183 case MMC_VDD_30_31:
1184 pwr = SDHCI_POWER_300;
1185 break;
1186 case MMC_VDD_32_33:
1187 case MMC_VDD_33_34:
1188 pwr = SDHCI_POWER_330;
1189 break;
1190 default:
1191 BUG();
1192 }
1193 }
1194
1195 if (host->pwr == pwr)
146ad66e
PO		 1196 return;
1197
ae628903
PO		 1198 host->pwr = pwr;
1199
1200 if (pwr == 0) {
4e4141a5 1201 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ae628903 1202 return;
9e9dc5f2
DS		 1203 }
1204
1205 /*
1206 * Spec says that we should clear the power reg before setting
1207 * a new value. Some controllers don't seem to like this though.
1208 */
b8c86fc5 1209 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1210 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1211
e08c1694 1212 /*
c71f6512 1213 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1214 * and set turn on power at the same time, so set the voltage first.
1215 */
11a2f1b7 1216 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1217 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1218
ae628903 1219 pwr |= SDHCI_POWER_ON;
146ad66e 1220
ae628903 1221 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1222
1223 /*
1224 * Some controllers need an extra 10ms delay of 10ms before they
1225 * can apply clock after applying power
1226 */
11a2f1b7 1227 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1228 mdelay(10);
146ad66e
PO		 1229}
1230
d129bceb
PO		 1231/*****************************************************************************\
1232 * *
1233 * MMC callbacks *
1234 * *
1235\*****************************************************************************/
1236
1237static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1238{
1239 struct sdhci_host *host;
68d1fb7e 1240 bool present;
d129bceb
PO		 1241 unsigned long flags;
1242
1243 host = mmc_priv(mmc);
1244
66fd8ad5
AH		 1245 sdhci_runtime_pm_get(host);
1246
d129bceb
PO		 1247 spin_lock_irqsave(&host->lock, flags);
1248
1249 WARN_ON(host->mrq != NULL);
1250
f9134319 1251#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1252 sdhci_activate_led(host);
2f730fec 1253#endif
e89d456f
AW		 1254
1255 /*
1256 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1257 * requests if Auto-CMD12 is enabled.
1258 */
1259 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1260 if (mrq->stop) {
1261 mrq->data->stop = NULL;
1262 mrq->stop = NULL;
1263 }
1264 }
d129bceb
PO		 1265
1266 host->mrq = mrq;
1267
68d1fb7e
AV		 1268 /* If polling, assume that the card is always present. */
1269 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1270 present = true;
1271 else
1272 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1273 SDHCI_CARD_PRESENT;
1274
1275 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1276 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1277 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1278 } else {
1279 u32 present_state;
1280
1281 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1282 /*
1283 * Check if the re-tuning timer has already expired and there
1284 * is no on-going data transfer. If so, we need to execute
1285 * tuning procedure before sending command.
1286 */
1287 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1288 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1289 spin_unlock_irqrestore(&host->lock, flags);
1290 sdhci_execute_tuning(mmc);
1291 spin_lock_irqsave(&host->lock, flags);
1292
1293 /* Restore original mmc_request structure */
1294 host->mrq = mrq;
1295 }
1296
8edf6371 1297 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1298 sdhci_send_command(host, mrq->sbc);
1299 else
1300 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1301 }
d129bceb 1302
5f25a66f 1303 mmiowb();
d129bceb
PO		 1304 spin_unlock_irqrestore(&host->lock, flags);
1305}
1306
66fd8ad5 1307static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1308{
d129bceb
PO		 1309 unsigned long flags;
1310 u8 ctrl;
1311
d129bceb
PO		 1312 spin_lock_irqsave(&host->lock, flags);
1313
1e72859e
PO		 1314 if (host->flags & SDHCI_DEVICE_DEAD)
1315 goto out;
1316
d129bceb
PO		 1317 /*
1318 * Reset the chip on each power off.
1319 * Should clear out any weird states.
1320 */
1321 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1322 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1323 sdhci_reinit(host);
d129bceb
PO		 1324 }
1325
1326 sdhci_set_clock(host, ios->clock);
1327
1328 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1329 sdhci_set_power(host, -1);
d129bceb 1330 else
146ad66e 1331 sdhci_set_power(host, ios->vdd);
d129bceb 1332
643a81ff
PR		 1333 if (host->ops->platform_send_init_74_clocks)
1334 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1335
15ec4461
PR		 1336 /*
1337 * If your platform has 8-bit width support but is not a v3 controller,
1338 * or if it requires special setup code, you should implement that in
1339 * platform_8bit_width().
1340 */
1341 if (host->ops->platform_8bit_width)
1342 host->ops->platform_8bit_width(host, ios->bus_width);
1343 else {
1344 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1345 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1346 ctrl &= ~SDHCI_CTRL_4BITBUS;
1347 if (host->version >= SDHCI_SPEC_300)
1348 ctrl |= SDHCI_CTRL_8BITBUS;
1349 } else {
1350 if (host->version >= SDHCI_SPEC_300)
1351 ctrl &= ~SDHCI_CTRL_8BITBUS;
1352 if (ios->bus_width == MMC_BUS_WIDTH_4)
1353 ctrl |= SDHCI_CTRL_4BITBUS;
1354 else
1355 ctrl &= ~SDHCI_CTRL_4BITBUS;
1356 }
1357 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1358 }
ae6d6c92 1359
15ec4461 1360 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1361
3ab9c8da
PR		 1362 if ((ios->timing == MMC_TIMING_SD_HS ||
1363 ios->timing == MMC_TIMING_MMC_HS)
1364 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1365 ctrl |= SDHCI_CTRL_HISPD;
1366 else
1367 ctrl &= ~SDHCI_CTRL_HISPD;
1368
d6d50a15 1369 if (host->version >= SDHCI_SPEC_300) {
49c468fc
AN		 1370 u16 clk, ctrl_2;
1371 unsigned int clock;
1372
1373 /* In case of UHS-I modes, set High Speed Enable */
1374 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1375 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1376 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1377 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1378 (ios->timing == MMC_TIMING_UHS_SDR12))
1379 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1380
1381 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1382 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1383 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1384 /*
1385 * We only need to set Driver Strength if the
1386 * preset value enable is not set.
1387 */
1388 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1389 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1390 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1391 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1392 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1393
1394 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1395 } else {
1396 /*
1397 * According to SDHC Spec v3.00, if the Preset Value
1398 * Enable in the Host Control 2 register is set, we
1399 * need to reset SD Clock Enable before changing High
1400 * Speed Enable to avoid generating clock gliches.
1401 */
758535c4
AN		 1402
1403 /* Reset SD Clock Enable */
1404 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1405 clk &= ~SDHCI_CLOCK_CARD_EN;
1406 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1407
1408 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1409
1410 /* Re-enable SD Clock */
1411 clock = host->clock;
1412 host->clock = 0;
1413 sdhci_set_clock(host, clock);
d6d50a15 1414 }
49c468fc 1415
49c468fc
AN		 1416
1417 /* Reset SD Clock Enable */
1418 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1419 clk &= ~SDHCI_CLOCK_CARD_EN;
1420 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1421
6322cdd0
PR		 1422 if (host->ops->set_uhs_signaling)
1423 host->ops->set_uhs_signaling(host, ios->timing);
1424 else {
1425 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1426 /* Select Bus Speed Mode for host */
1427 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1428 if (ios->timing == MMC_TIMING_UHS_SDR12)
1429 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1430 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1431 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1432 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1433 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1434 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1435 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1436 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1437 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1438 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1439 }
49c468fc
AN		 1440
1441 /* Re-enable SD Clock */
1442 clock = host->clock;
1443 host->clock = 0;
1444 sdhci_set_clock(host, clock);
758535c4
AN		 1445 } else
1446 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1447
b8352260
LD		 1448 /*
1449 * Some (ENE) controllers go apeshit on some ios operation,
1450 * signalling timeout and CRC errors even on CMD0. Resetting
1451 * it on each ios seems to solve the problem.
1452 */
b8c86fc5 1453 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1454 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1455
1e72859e 1456out:
5f25a66f 1457 mmiowb();
d129bceb
PO		 1458 spin_unlock_irqrestore(&host->lock, flags);
1459}
1460
66fd8ad5
AH		 1461static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1462{
1463 struct sdhci_host *host = mmc_priv(mmc);
1464
1465 sdhci_runtime_pm_get(host);
1466 sdhci_do_set_ios(host, ios);
1467 sdhci_runtime_pm_put(host);
1468}
1469
1470static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1471{
d129bceb 1472 unsigned long flags;
2dfb579c 1473 int is_readonly;
d129bceb 1474
d129bceb
PO		 1475 spin_lock_irqsave(&host->lock, flags);
1476
1e72859e 1477 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1478 is_readonly = 0;
1479 else if (host->ops->get_ro)
1480 is_readonly = host->ops->get_ro(host);
1e72859e 1481 else
2dfb579c
WS		 1482 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1483 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1484
1485 spin_unlock_irqrestore(&host->lock, flags);
1486
2dfb579c
WS		 1487 /* This quirk needs to be replaced by a callback-function later */
1488 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1489 !is_readonly : is_readonly;
d129bceb
PO		 1490}
1491
82b0e23a
TI		 1492#define SAMPLE_COUNT 5
1493
66fd8ad5 1494static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1495{
82b0e23a
TI		 1496 int i, ro_count;
1497
82b0e23a 1498 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1499 return sdhci_check_ro(host);
82b0e23a
TI		 1500
1501 ro_count = 0;
1502 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1503 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1504 if (++ro_count > SAMPLE_COUNT / 2)
1505 return 1;
1506 }
1507 msleep(30);
1508 }
1509 return 0;
1510}
1511
20758b66
AH		 1512static void sdhci_hw_reset(struct mmc_host *mmc)
1513{
1514 struct sdhci_host *host = mmc_priv(mmc);
1515
1516 if (host->ops && host->ops->hw_reset)
1517 host->ops->hw_reset(host);
1518}
1519
66fd8ad5 1520static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1521{
66fd8ad5
AH		 1522 struct sdhci_host *host = mmc_priv(mmc);
1523 int ret;
f75979b7 1524
66fd8ad5
AH		 1525 sdhci_runtime_pm_get(host);
1526 ret = sdhci_do_get_ro(host);
1527 sdhci_runtime_pm_put(host);
1528 return ret;
1529}
f75979b7 1530
66fd8ad5
AH		 1531static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1532{
1e72859e
PO		 1533 if (host->flags & SDHCI_DEVICE_DEAD)
1534 goto out;
1535
66fd8ad5
AH		 1536 if (enable)
1537 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1538 else
1539 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1540
1541 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1542 if (host->runtime_suspended)
1543 goto out;
1544
f75979b7 1545 if (enable)
7260cf5e
AV		 1546 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1547 else
1548 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1549out:
f75979b7 1550 mmiowb();
66fd8ad5
AH		 1551}
1552
1553static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1554{
1555 struct sdhci_host *host = mmc_priv(mmc);
1556 unsigned long flags;
f75979b7 1557
66fd8ad5
AH		 1558 spin_lock_irqsave(&host->lock, flags);
1559 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1560 spin_unlock_irqrestore(&host->lock, flags);
1561}
1562
66fd8ad5
AH		 1563static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1564 struct mmc_ios *ios)
f2119df6 1565{
f2119df6
AN		 1566 u8 pwr;
1567 u16 clk, ctrl;
1568 u32 present_state;
1569
f2119df6
AN		 1570 /*
1571 * Signal Voltage Switching is only applicable for Host Controllers
1572 * v3.00 and above.
1573 */
1574 if (host->version < SDHCI_SPEC_300)
1575 return 0;
1576
1577 /*
1578 * We first check whether the request is to set signalling voltage
1579 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1580 */
1581 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1582 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1583 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1584 ctrl &= ~SDHCI_CTRL_VDD_180;
1585 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1586
1587 /* Wait for 5ms */
1588 usleep_range(5000, 5500);
1589
1590 /* 3.3V regulator output should be stable within 5 ms */
1591 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1592 if (!(ctrl & SDHCI_CTRL_VDD_180))
1593 return 0;
1594 else {
a3c76eb9 1595 pr_info(DRIVER_NAME ": Switching to 3.3V "
f2119df6
AN		 1596 "signalling voltage failed\n");
1597 return -EIO;
1598 }
1599 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1600 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1601 /* Stop SDCLK */
1602 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1603 clk &= ~SDHCI_CLOCK_CARD_EN;
1604 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1605
1606 /* Check whether DAT[3:0] is 0000 */
1607 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1608 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1609 SDHCI_DATA_LVL_SHIFT)) {
1610 /*
1611 * Enable 1.8V Signal Enable in the Host Control2
1612 * register
1613 */
1614 ctrl |= SDHCI_CTRL_VDD_180;
1615 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1616
1617 /* Wait for 5ms */
1618 usleep_range(5000, 5500);
1619
1620 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1621 if (ctrl & SDHCI_CTRL_VDD_180) {
1622 /* Provide SDCLK again and wait for 1ms*/
1623 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1624 clk |= SDHCI_CLOCK_CARD_EN;
1625 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1626 usleep_range(1000, 1500);
1627
1628 /*
1629 * If DAT[3:0] level is 1111b, then the card
1630 * was successfully switched to 1.8V signaling.
1631 */
1632 present_state = sdhci_readl(host,
1633 SDHCI_PRESENT_STATE);
1634 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1635 SDHCI_DATA_LVL_MASK)
1636 return 0;
1637 }
1638 }
1639
1640 /*
1641 * If we are here, that means the switch to 1.8V signaling
1642 * failed. We power cycle the card, and retry initialization
1643 * sequence by setting S18R to 0.
1644 */
1645 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1646 pwr &= ~SDHCI_POWER_ON;
1647 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1648
1649 /* Wait for 1ms as per the spec */
1650 usleep_range(1000, 1500);
1651 pwr |= SDHCI_POWER_ON;
1652 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1653
a3c76eb9 1654 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
f2119df6
AN		 1655 "voltage failed, retrying with S18R set to 0\n");
1656 return -EAGAIN;
1657 } else
1658 /* No signal voltage switch required */
1659 return 0;
1660}
1661
66fd8ad5
AH		 1662static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1663 struct mmc_ios *ios)
1664{
1665 struct sdhci_host *host = mmc_priv(mmc);
1666 int err;
1667
1668 if (host->version < SDHCI_SPEC_300)
1669 return 0;
1670 sdhci_runtime_pm_get(host);
1671 err = sdhci_do_start_signal_voltage_switch(host, ios);
1672 sdhci_runtime_pm_put(host);
1673 return err;
1674}
1675
b513ea25
AN		 1676static int sdhci_execute_tuning(struct mmc_host *mmc)
1677{
1678 struct sdhci_host *host;
1679 u16 ctrl;
1680 u32 ier;
1681 int tuning_loop_counter = MAX_TUNING_LOOP;
1682 unsigned long timeout;
1683 int err = 0;
1684
1685 host = mmc_priv(mmc);
1686
66fd8ad5 1687 sdhci_runtime_pm_get(host);
b513ea25
AN		 1688 disable_irq(host->irq);
1689 spin_lock(&host->lock);
1690
1691 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1692
1693 /*
1694 * Host Controller needs tuning only in case of SDR104 mode
1695 * and for SDR50 mode when Use Tuning for SDR50 is set in
1696 * Capabilities register.
1697 */
1698 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1699 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1700 (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1701 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1702 else {
1703 spin_unlock(&host->lock);
1704 enable_irq(host->irq);
66fd8ad5 1705 sdhci_runtime_pm_put(host);
b513ea25
AN		 1706 return 0;
1707 }
1708
1709 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1710
1711 /*
1712 * As per the Host Controller spec v3.00, tuning command
1713 * generates Buffer Read Ready interrupt, so enable that.
1714 *
1715 * Note: The spec clearly says that when tuning sequence
1716 * is being performed, the controller does not generate
1717 * interrupts other than Buffer Read Ready interrupt. But
1718 * to make sure we don't hit a controller bug, we _only_
1719 * enable Buffer Read Ready interrupt here.
1720 */
1721 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1722 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1723
1724 /*
1725 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1726 * of loops reaches 40 times or a timeout of 150ms occurs.
1727 */
1728 timeout = 150;
1729 do {
1730 struct mmc_command cmd = {0};
66fd8ad5 1731 struct mmc_request mrq = {NULL};
b513ea25
AN		 1732
1733 if (!tuning_loop_counter && !timeout)
1734 break;
1735
1736 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1737 cmd.arg = 0;
1738 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1739 cmd.retries = 0;
1740 cmd.data = NULL;
1741 cmd.error = 0;
1742
1743 mrq.cmd = &cmd;
1744 host->mrq = &mrq;
1745
1746 /*
1747 * In response to CMD19, the card sends 64 bytes of tuning
1748 * block to the Host Controller. So we set the block size
1749 * to 64 here.
1750 */
1751 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1752
1753 /*
1754 * The tuning block is sent by the card to the host controller.
1755 * So we set the TRNS_READ bit in the Transfer Mode register.
1756 * This also takes care of setting DMA Enable and Multi Block
1757 * Select in the same register to 0.
1758 */
1759 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1760
1761 sdhci_send_command(host, &cmd);
1762
1763 host->cmd = NULL;
1764 host->mrq = NULL;
1765
1766 spin_unlock(&host->lock);
1767 enable_irq(host->irq);
1768
1769 /* Wait for Buffer Read Ready interrupt */
1770 wait_event_interruptible_timeout(host->buf_ready_int,
1771 (host->tuning_done == 1),
1772 msecs_to_jiffies(50));
1773 disable_irq(host->irq);
1774 spin_lock(&host->lock);
1775
1776 if (!host->tuning_done) {
a3c76eb9 1777 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1778 "Buffer Read Ready interrupt during tuning "
1779 "procedure, falling back to fixed sampling "
1780 "clock\n");
1781 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1782 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1783 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1784 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1785
1786 err = -EIO;
1787 goto out;
1788 }
1789
1790 host->tuning_done = 0;
1791
1792 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1793 tuning_loop_counter--;
1794 timeout--;
1795 mdelay(1);
1796 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1797
1798 /*
1799 * The Host Driver has exhausted the maximum number of loops allowed,
1800 * so use fixed sampling frequency.
1801 */
1802 if (!tuning_loop_counter || !timeout) {
1803 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1804 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1805 } else {
1806 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1807 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1808 " failed, falling back to fixed sampling"
1809 " clock\n");
1810 err = -EIO;
1811 }
1812 }
1813
1814out:
cf2b5eea
AN		 1815 /*
1816 * If this is the very first time we are here, we start the retuning
1817 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1818 * flag won't be set, we check this condition before actually starting
1819 * the timer.
1820 */
1821 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1822 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1823 mod_timer(&host->tuning_timer, jiffies +
1824 host->tuning_count * HZ);
1825 /* Tuning mode 1 limits the maximum data length to 4MB */
1826 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1827 } else {
1828 host->flags &= ~SDHCI_NEEDS_RETUNING;
1829 /* Reload the new initial value for timer */
1830 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1831 mod_timer(&host->tuning_timer, jiffies +
1832 host->tuning_count * HZ);
1833 }
1834
1835 /*
1836 * In case tuning fails, host controllers which support re-tuning can
1837 * try tuning again at a later time, when the re-tuning timer expires.
1838 * So for these controllers, we return 0. Since there might be other
1839 * controllers who do not have this capability, we return error for
1840 * them.
1841 */
1842 if (err && host->tuning_count &&
1843 host->tuning_mode == SDHCI_TUNING_MODE_1)
1844 err = 0;
1845
b513ea25
AN		 1846 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1847 spin_unlock(&host->lock);
1848 enable_irq(host->irq);
66fd8ad5 1849 sdhci_runtime_pm_put(host);
b513ea25
AN		 1850
1851 return err;
1852}
1853
66fd8ad5 1854static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 1855{
4d55c5a1
AN		 1856 u16 ctrl;
1857 unsigned long flags;
1858
4d55c5a1
AN		 1859 /* Host Controller v3.00 defines preset value registers */
1860 if (host->version < SDHCI_SPEC_300)
1861 return;
1862
1863 spin_lock_irqsave(&host->lock, flags);
1864
1865 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1866
1867 /*
1868 * We only enable or disable Preset Value if they are not already
1869 * enabled or disabled respectively. Otherwise, we bail out.
1870 */
1871 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1872 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1873 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1874 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 1875 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1876 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1877 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1878 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1
AN		 1879 }
1880
1881 spin_unlock_irqrestore(&host->lock, flags);
1882}
1883
66fd8ad5
AH		 1884static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1885{
1886 struct sdhci_host *host = mmc_priv(mmc);
1887
1888 sdhci_runtime_pm_get(host);
1889 sdhci_do_enable_preset_value(host, enable);
1890 sdhci_runtime_pm_put(host);
1891}
1892
ab7aefd0 1893static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1894 .request = sdhci_request,
1895 .set_ios = sdhci_set_ios,
1896 .get_ro = sdhci_get_ro,
20758b66 1897 .hw_reset = sdhci_hw_reset,
f75979b7 1898 .enable_sdio_irq = sdhci_enable_sdio_irq,
f2119df6 1899 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b513ea25 1900 .execute_tuning = sdhci_execute_tuning,
4d55c5a1 1901 .enable_preset_value = sdhci_enable_preset_value,
d129bceb
PO		 1902};
1903
1904/*****************************************************************************\
1905 * *
1906 * Tasklets *
1907 * *
1908\*****************************************************************************/
1909
1910static void sdhci_tasklet_card(unsigned long param)
1911{
1912 struct sdhci_host *host;
1913 unsigned long flags;
1914
1915 host = (struct sdhci_host*)param;
1916
1917 spin_lock_irqsave(&host->lock, flags);
1918
66fd8ad5
AH		 1919 /* Check host->mrq first in case we are runtime suspended */
1920 if (host->mrq &&
1921 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
a3c76eb9 1922 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 1923 mmc_hostname(host->mmc));
a3c76eb9 1924 pr_err("%s: Resetting controller.\n",
66fd8ad5 1925 mmc_hostname(host->mmc));
d129bceb 1926
66fd8ad5
AH		 1927 sdhci_reset(host, SDHCI_RESET_CMD);
1928 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 1929
66fd8ad5
AH		 1930 host->mrq->cmd->error = -ENOMEDIUM;
1931 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 1932 }
1933
1934 spin_unlock_irqrestore(&host->lock, flags);
1935
04cf585d 1936 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1937}
1938
1939static void sdhci_tasklet_finish(unsigned long param)
1940{
1941 struct sdhci_host *host;
1942 unsigned long flags;
1943 struct mmc_request *mrq;
1944
1945 host = (struct sdhci_host*)param;
1946
66fd8ad5
AH		 1947 spin_lock_irqsave(&host->lock, flags);
1948
0c9c99a7
CB		 1949 /*
1950 * If this tasklet gets rescheduled while running, it will
1951 * be run again afterwards but without any active request.
1952 */
66fd8ad5
AH		 1953 if (!host->mrq) {
1954 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 1955 return;
66fd8ad5 1956 }
d129bceb
PO		 1957
1958 del_timer(&host->timer);
1959
1960 mrq = host->mrq;
1961
d129bceb
PO		 1962 /*
1963 * The controller needs a reset of internal state machines
1964 * upon error conditions.
1965 */
1e72859e 1966 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 1967 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 1968 (mrq->data && (mrq->data->error ||
1969 (mrq->data->stop && mrq->data->stop->error))) ||
1970 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1971
1972 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1973 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1974 unsigned int clock;
1975
1976 /* This is to force an update */
1977 clock = host->clock;
1978 host->clock = 0;
1979 sdhci_set_clock(host, clock);
1980 }
1981
1982 /* Spec says we should do both at the same time, but Ricoh
1983 controllers do not like that. */
d129bceb
PO		 1984 sdhci_reset(host, SDHCI_RESET_CMD);
1985 sdhci_reset(host, SDHCI_RESET_DATA);
1986 }
1987
1988 host->mrq = NULL;
1989 host->cmd = NULL;
1990 host->data = NULL;
1991
f9134319 1992#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1993 sdhci_deactivate_led(host);
2f730fec 1994#endif
d129bceb 1995
5f25a66f 1996 mmiowb();
d129bceb
PO		 1997 spin_unlock_irqrestore(&host->lock, flags);
1998
1999 mmc_request_done(host->mmc, mrq);
66fd8ad5 2000 sdhci_runtime_pm_put(host);
d129bceb
PO		 2001}
2002
2003static void sdhci_timeout_timer(unsigned long data)
2004{
2005 struct sdhci_host *host;
2006 unsigned long flags;
2007
2008 host = (struct sdhci_host*)data;
2009
2010 spin_lock_irqsave(&host->lock, flags);
2011
2012 if (host->mrq) {
a3c76eb9 2013 pr_err("%s: Timeout waiting for hardware "
acf1da45 2014 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2015 sdhci_dumpregs(host);
2016
2017 if (host->data) {
17b0429d 2018 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2019 sdhci_finish_data(host);
2020 } else {
2021 if (host->cmd)
17b0429d 2022 host->cmd->error = -ETIMEDOUT;
d129bceb 2023 else
17b0429d 2024 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2025
2026 tasklet_schedule(&host->finish_tasklet);
2027 }
2028 }
2029
5f25a66f 2030 mmiowb();
d129bceb
PO		 2031 spin_unlock_irqrestore(&host->lock, flags);
2032}
2033
cf2b5eea
AN		 2034static void sdhci_tuning_timer(unsigned long data)
2035{
2036 struct sdhci_host *host;
2037 unsigned long flags;
2038
2039 host = (struct sdhci_host *)data;
2040
2041 spin_lock_irqsave(&host->lock, flags);
2042
2043 host->flags |= SDHCI_NEEDS_RETUNING;
2044
2045 spin_unlock_irqrestore(&host->lock, flags);
2046}
2047
d129bceb
PO		 2048/*****************************************************************************\
2049 * *
2050 * Interrupt handling *
2051 * *
2052\*****************************************************************************/
2053
2054static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2055{
2056 BUG_ON(intmask == 0);
2057
2058 if (!host->cmd) {
a3c76eb9 2059 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2060 "though no command operation was in progress.\n",
2061 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2062 sdhci_dumpregs(host);
2063 return;
2064 }
2065
43b58b36 2066 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2067 host->cmd->error = -ETIMEDOUT;
2068 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2069 SDHCI_INT_INDEX))
2070 host->cmd->error = -EILSEQ;
43b58b36 2071
e809517f 2072 if (host->cmd->error) {
d129bceb 2073 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2074 return;
2075 }
2076
2077 /*
2078 * The host can send and interrupt when the busy state has
2079 * ended, allowing us to wait without wasting CPU cycles.
2080 * Unfortunately this is overloaded on the "data complete"
2081 * interrupt, so we need to take some care when handling
2082 * it.
2083 *
2084 * Note: The 1.0 specification is a bit ambiguous about this
2085 * feature so there might be some problems with older
2086 * controllers.
2087 */
2088 if (host->cmd->flags & MMC_RSP_BUSY) {
2089 if (host->cmd->data)
2090 DBG("Cannot wait for busy signal when also "
2091 "doing a data transfer");
f945405c 2092 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2093 return;
f945405c
BD		 2094
2095 /* The controller does not support the end-of-busy IRQ,
2096 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2097 }
2098
2099 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2100 sdhci_finish_command(host);
d129bceb
PO		 2101}
2102
0957c333 2103#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2104static void sdhci_show_adma_error(struct sdhci_host *host)
2105{
2106 const char *name = mmc_hostname(host->mmc);
2107 u8 *desc = host->adma_desc;
2108 __le32 *dma;
2109 __le16 *len;
2110 u8 attr;
2111
2112 sdhci_dumpregs(host);
2113
2114 while (true) {
2115 dma = (__le32 *)(desc + 4);
2116 len = (__le16 *)(desc + 2);
2117 attr = *desc;
2118
2119 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2120 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2121
2122 desc += 8;
2123
2124 if (attr & 2)
2125 break;
2126 }
2127}
2128#else
2129static void sdhci_show_adma_error(struct sdhci_host *host) { }
2130#endif
2131
d129bceb
PO		 2132static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2133{
2134 BUG_ON(intmask == 0);
2135
b513ea25
AN		 2136 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2137 if (intmask & SDHCI_INT_DATA_AVAIL) {
2138 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2139 MMC_SEND_TUNING_BLOCK) {
2140 host->tuning_done = 1;
2141 wake_up(&host->buf_ready_int);
2142 return;
2143 }
2144 }
2145
d129bceb
PO		 2146 if (!host->data) {
2147 /*
e809517f
PO		 2148 * The "data complete" interrupt is also used to
2149 * indicate that a busy state has ended. See comment
2150 * above in sdhci_cmd_irq().
d129bceb 2151 */
e809517f
PO		 2152 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2153 if (intmask & SDHCI_INT_DATA_END) {
2154 sdhci_finish_command(host);
2155 return;
2156 }
2157 }
d129bceb 2158
a3c76eb9 2159 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2160 "though no data operation was in progress.\n",
2161 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2162 sdhci_dumpregs(host);
2163
2164 return;
2165 }
2166
2167 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2168 host->data->error = -ETIMEDOUT;
22113efd
AL		 2169 else if (intmask & SDHCI_INT_DATA_END_BIT)
2170 host->data->error = -EILSEQ;
2171 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2172 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2173 != MMC_BUS_TEST_R)
17b0429d 2174 host->data->error = -EILSEQ;
6882a8c0 2175 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2176 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2177 sdhci_show_adma_error(host);
2134a922 2178 host->data->error = -EIO;
6882a8c0 2179 }
d129bceb 2180
17b0429d 2181 if (host->data->error)
d129bceb
PO		 2182 sdhci_finish_data(host);
2183 else {
a406f5a3 2184 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2185 sdhci_transfer_pio(host);
2186
6ba736a1
PO		 2187 /*
2188 * We currently don't do anything fancy with DMA
2189 * boundaries, but as we can't disable the feature
2190 * we need to at least restart the transfer.
f6a03cbf
MV		 2191 *
2192 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2193 * should return a valid address to continue from, but as
2194 * some controllers are faulty, don't trust them.
6ba736a1 2195 */
f6a03cbf
MV		 2196 if (intmask & SDHCI_INT_DMA_END) {
2197 u32 dmastart, dmanow;
2198 dmastart = sg_dma_address(host->data->sg);
2199 dmanow = dmastart + host->data->bytes_xfered;
2200 /*
2201 * Force update to the next DMA block boundary.
2202 */
2203 dmanow = (dmanow &
2204 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2205 SDHCI_DEFAULT_BOUNDARY_SIZE;
2206 host->data->bytes_xfered = dmanow - dmastart;
2207 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2208 " next 0x%08x\n",
2209 mmc_hostname(host->mmc), dmastart,
2210 host->data->bytes_xfered, dmanow);
2211 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2212 }
6ba736a1 2213
e538fbe8
PO		 2214 if (intmask & SDHCI_INT_DATA_END) {
2215 if (host->cmd) {
2216 /*
2217 * Data managed to finish before the
2218 * command completed. Make sure we do
2219 * things in the proper order.
2220 */
2221 host->data_early = 1;
2222 } else {
2223 sdhci_finish_data(host);
2224 }
2225 }
d129bceb
PO		 2226 }
2227}
2228
7d12e780 2229static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2230{
2231 irqreturn_t result;
66fd8ad5 2232 struct sdhci_host *host = dev_id;
d129bceb 2233 u32 intmask;
f75979b7 2234 int cardint = 0;
d129bceb
PO		 2235
2236 spin_lock(&host->lock);
2237
66fd8ad5
AH		 2238 if (host->runtime_suspended) {
2239 spin_unlock(&host->lock);
a3c76eb9 2240 pr_warning("%s: got irq while runtime suspended\n",
66fd8ad5
AH		 2241 mmc_hostname(host->mmc));
2242 return IRQ_HANDLED;
2243 }
2244
4e4141a5 2245 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2246
62df67a5 2247 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2248 result = IRQ_NONE;
2249 goto out;
2250 }
2251
b69c9058
PO		 2252 DBG("*** %s got interrupt: 0x%08x\n",
2253 mmc_hostname(host->mmc), intmask);
d129bceb 2254
3192a28f 2255 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2256 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2257 SDHCI_CARD_PRESENT;
2258
2259 /*
2260 * There is a observation on i.mx esdhc. INSERT bit will be
2261 * immediately set again when it gets cleared, if a card is
2262 * inserted. We have to mask the irq to prevent interrupt
2263 * storm which will freeze the system. And the REMOVE gets
2264 * the same situation.
2265 *
2266 * More testing are needed here to ensure it works for other
2267 * platforms though.
2268 */
2269 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2270 SDHCI_INT_CARD_REMOVE);
2271 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2272 SDHCI_INT_CARD_INSERT);
2273
4e4141a5 2274 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2275 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2276 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2277 tasklet_schedule(&host->card_tasklet);
3192a28f 2278 }
d129bceb 2279
3192a28f 2280 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2281 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2282 SDHCI_INT_STATUS);
3192a28f 2283 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2284 }
2285
2286 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2287 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2288 SDHCI_INT_STATUS);
3192a28f 2289 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2290 }
2291
2292 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2293
964f9ce2
PO		 2294 intmask &= ~SDHCI_INT_ERROR;
2295
d129bceb 2296 if (intmask & SDHCI_INT_BUS_POWER) {
a3c76eb9 2297 pr_err("%s: Card is consuming too much power!\n",
d129bceb 2298 mmc_hostname(host->mmc));
4e4141a5 2299 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2300 }
2301
9d26a5d3 2302 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2303
f75979b7
PO		 2304 if (intmask & SDHCI_INT_CARD_INT)
2305 cardint = 1;
2306
2307 intmask &= ~SDHCI_INT_CARD_INT;
2308
3192a28f 2309 if (intmask) {
a3c76eb9 2310 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3192a28f 2311 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 2312 sdhci_dumpregs(host);
2313
4e4141a5 2314 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2315 }
d129bceb
PO		 2316
2317 result = IRQ_HANDLED;
2318
5f25a66f 2319 mmiowb();
d129bceb
PO		 2320out:
2321 spin_unlock(&host->lock);
2322
f75979b7
PO		 2323 /*
2324 * We have to delay this as it calls back into the driver.
2325 */
2326 if (cardint)
2327 mmc_signal_sdio_irq(host->mmc);
2328
d129bceb
PO		 2329 return result;
2330}
2331
2332/*****************************************************************************\
2333 * *
2334 * Suspend/resume *
2335 * *
2336\*****************************************************************************/
2337
2338#ifdef CONFIG_PM
2339
29495aa0 2340int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2341{
b8c86fc5 2342 int ret;
a715dfc7 2343
7260cf5e
AV		 2344 sdhci_disable_card_detection(host);
2345
cf2b5eea
AN		 2346 /* Disable tuning since we are suspending */
2347 if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2348 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2349 host->flags &= ~SDHCI_NEEDS_RETUNING;
2350 mod_timer(&host->tuning_timer, jiffies +
2351 host->tuning_count * HZ);
2352 }
2353
1a13f8fa 2354 ret = mmc_suspend_host(host->mmc);
b8c86fc5
PO		 2355 if (ret)
2356 return ret;
a715dfc7 2357
b8c86fc5 2358 free_irq(host->irq, host);
d129bceb 2359
9bea3c85
MS		 2360 if (host->vmmc)
2361 ret = regulator_disable(host->vmmc);
2362
2363 return ret;
d129bceb
PO		 2364}
2365
b8c86fc5 2366EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2367
b8c86fc5
PO		 2368int sdhci_resume_host(struct sdhci_host *host)
2369{
2370 int ret;
d129bceb 2371
9bea3c85
MS		 2372 if (host->vmmc) {
2373 int ret = regulator_enable(host->vmmc);
2374 if (ret)
2375 return ret;
2376 }
2377
a13abc7b 2378 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2379 if (host->ops->enable_dma)
2380 host->ops->enable_dma(host);
2381 }
d129bceb 2382
b8c86fc5
PO		 2383 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2384 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 2385 if (ret)
2386 return ret;
d129bceb 2387
2f4cbb3d 2388 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 2389 mmiowb();
2390
2391 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2392 sdhci_enable_card_detection(host);
2393
cf2b5eea
AN		 2394 /* Set the re-tuning expiration flag */
2395 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2396 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2397 host->flags |= SDHCI_NEEDS_RETUNING;
2398
2f4cbb3d 2399 return ret;
d129bceb
PO		 2400}
2401
b8c86fc5 2402EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 2403
5f619704
DD		 2404void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2405{
2406 u8 val;
2407 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2408 val |= SDHCI_WAKE_ON_INT;
2409 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2410}
2411
2412EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2413
d129bceb
PO		 2414#endif /* CONFIG_PM */
2415
66fd8ad5
AH		 2416#ifdef CONFIG_PM_RUNTIME
2417
2418static int sdhci_runtime_pm_get(struct sdhci_host *host)
2419{
2420 return pm_runtime_get_sync(host->mmc->parent);
2421}
2422
2423static int sdhci_runtime_pm_put(struct sdhci_host *host)
2424{
2425 pm_runtime_mark_last_busy(host->mmc->parent);
2426 return pm_runtime_put_autosuspend(host->mmc->parent);
2427}
2428
2429int sdhci_runtime_suspend_host(struct sdhci_host *host)
2430{
2431 unsigned long flags;
2432 int ret = 0;
2433
2434 /* Disable tuning since we are suspending */
2435 if (host->version >= SDHCI_SPEC_300 &&
2436 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2437 del_timer_sync(&host->tuning_timer);
2438 host->flags &= ~SDHCI_NEEDS_RETUNING;
2439 }
2440
2441 spin_lock_irqsave(&host->lock, flags);
2442 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2443 spin_unlock_irqrestore(&host->lock, flags);
2444
2445 synchronize_irq(host->irq);
2446
2447 spin_lock_irqsave(&host->lock, flags);
2448 host->runtime_suspended = true;
2449 spin_unlock_irqrestore(&host->lock, flags);
2450
2451 return ret;
2452}
2453EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2454
2455int sdhci_runtime_resume_host(struct sdhci_host *host)
2456{
2457 unsigned long flags;
2458 int ret = 0, host_flags = host->flags;
2459
2460 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2461 if (host->ops->enable_dma)
2462 host->ops->enable_dma(host);
2463 }
2464
2465 sdhci_init(host, 0);
2466
2467 /* Force clock and power re-program */
2468 host->pwr = 0;
2469 host->clock = 0;
2470 sdhci_do_set_ios(host, &host->mmc->ios);
2471
2472 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2473 if (host_flags & SDHCI_PV_ENABLED)
2474 sdhci_do_enable_preset_value(host, true);
2475
2476 /* Set the re-tuning expiration flag */
2477 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2478 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2479 host->flags |= SDHCI_NEEDS_RETUNING;
2480
2481 spin_lock_irqsave(&host->lock, flags);
2482
2483 host->runtime_suspended = false;
2484
2485 /* Enable SDIO IRQ */
2486 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2487 sdhci_enable_sdio_irq_nolock(host, true);
2488
2489 /* Enable Card Detection */
2490 sdhci_enable_card_detection(host);
2491
2492 spin_unlock_irqrestore(&host->lock, flags);
2493
2494 return ret;
2495}
2496EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2497
2498#endif
2499
d129bceb
PO		 2500/*****************************************************************************\
2501 * *
b8c86fc5 2502 * Device allocation/registration *
d129bceb
PO		 2503 * *
2504\*****************************************************************************/
2505
b8c86fc5
PO		 2506struct sdhci_host *sdhci_alloc_host(struct device *dev,
2507 size_t priv_size)
d129bceb 2508{
d129bceb
PO		 2509 struct mmc_host *mmc;
2510 struct sdhci_host *host;
2511
b8c86fc5 2512 WARN_ON(dev == NULL);
d129bceb 2513
b8c86fc5 2514 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2515 if (!mmc)
b8c86fc5 2516 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2517
2518 host = mmc_priv(mmc);
2519 host->mmc = mmc;
2520
b8c86fc5
PO		 2521 return host;
2522}
8a4da143 2523
b8c86fc5 2524EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2525
b8c86fc5
PO		 2526int sdhci_add_host(struct sdhci_host *host)
2527{
2528 struct mmc_host *mmc;
f2119df6
AN		 2529 u32 caps[2];
2530 u32 max_current_caps;
2531 unsigned int ocr_avail;
b8c86fc5 2532 int ret;
d129bceb 2533
b8c86fc5
PO		 2534 WARN_ON(host == NULL);
2535 if (host == NULL)
2536 return -EINVAL;
d129bceb 2537
b8c86fc5 2538 mmc = host->mmc;
d129bceb 2539
b8c86fc5
PO		 2540 if (debug_quirks)
2541 host->quirks = debug_quirks;
66fd8ad5
AH		 2542 if (debug_quirks2)
2543 host->quirks2 = debug_quirks2;
d129bceb 2544
d96649ed
PO		 2545 sdhci_reset(host, SDHCI_RESET_ALL);
2546
4e4141a5 2547 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2548 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2549 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2550 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2551 pr_err("%s: Unknown controller version (%d). "
b69c9058 2552 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2553 host->version);
4a965505
PO		 2554 }
2555
f2119df6 2556 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2557 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2558
f2119df6
AN		 2559 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2560 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2561
b8c86fc5 2562 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2563 host->flags |= SDHCI_USE_SDMA;
f2119df6 2564 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2565 DBG("Controller doesn't have SDMA capability\n");
67435274 2566 else
a13abc7b 2567 host->flags |= SDHCI_USE_SDMA;
d129bceb 2568
b8c86fc5 2569 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2570 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2571 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2572 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2573 }
2574
f2119df6
AN		 2575 if ((host->version >= SDHCI_SPEC_200) &&
2576 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2577 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2578
2579 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2580 (host->flags & SDHCI_USE_ADMA)) {
2581 DBG("Disabling ADMA as it is marked broken\n");
2582 host->flags &= ~SDHCI_USE_ADMA;
2583 }
2584
a13abc7b 2585 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2586 if (host->ops->enable_dma) {
2587 if (host->ops->enable_dma(host)) {
a3c76eb9 2588 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2589 "available. Falling back to PIO.\n",
2590 mmc_hostname(mmc));
a13abc7b
RR		 2591 host->flags &=
2592 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2593 }
d129bceb
PO		 2594 }
2595 }
2596
2134a922
PO		 2597 if (host->flags & SDHCI_USE_ADMA) {
2598 /*
2599 * We need to allocate descriptors for all sg entries
2600 * (128) and potentially one alignment transfer for
2601 * each of those entries.
2602 */
2603 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2604 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2605 if (!host->adma_desc || !host->align_buffer) {
2606 kfree(host->adma_desc);
2607 kfree(host->align_buffer);
a3c76eb9 2608 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2609 "buffers. Falling back to standard DMA.\n",
2610 mmc_hostname(mmc));
2611 host->flags &= ~SDHCI_USE_ADMA;
2612 }
2613 }
2614
7659150c
PO		 2615 /*
2616 * If we use DMA, then it's up to the caller to set the DMA
2617 * mask, but PIO does not need the hw shim so we set a new
2618 * mask here in that case.
2619 */
a13abc7b 2620 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2621 host->dma_mask = DMA_BIT_MASK(64);
2622 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2623 }
d129bceb 2624
c4687d5f 2625 if (host->version >= SDHCI_SPEC_300)
f2119df6 2626 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2627 >> SDHCI_CLOCK_BASE_SHIFT;
2628 else
f2119df6 2629 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2630 >> SDHCI_CLOCK_BASE_SHIFT;
2631
4240ff0a 2632 host->max_clk *= 1000000;
f27f47ef
AV		 2633 if (host->max_clk == 0 || host->quirks &
2634 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2635 if (!host->ops->get_max_clock) {
a3c76eb9 2636 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2637 "frequency.\n", mmc_hostname(mmc));
2638 return -ENODEV;
2639 }
2640 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2641 }
d129bceb 2642
c3ed3877
AN		 2643 /*
2644 * In case of Host Controller v3.00, find out whether clock
2645 * multiplier is supported.
2646 */
2647 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2648 SDHCI_CLOCK_MUL_SHIFT;
2649
2650 /*
2651 * In case the value in Clock Multiplier is 0, then programmable
2652 * clock mode is not supported, otherwise the actual clock
2653 * multiplier is one more than the value of Clock Multiplier
2654 * in the Capabilities Register.
2655 */
2656 if (host->clk_mul)
2657 host->clk_mul += 1;
2658
d129bceb
PO		 2659 /*
2660 * Set host parameters.
2661 */
2662 mmc->ops = &sdhci_ops;
c3ed3877 2663 mmc->f_max = host->max_clk;
ce5f036b 2664 if (host->ops->get_min_clock)
a9e58f25 2665 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2666 else if (host->version >= SDHCI_SPEC_300) {
2667 if (host->clk_mul) {
2668 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2669 mmc->f_max = host->max_clk * host->clk_mul;
2670 } else
2671 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2672 } else
0397526d 2673 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2674
272308ca
AS		 2675 host->timeout_clk =
2676 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2677 if (host->timeout_clk == 0) {
2678 if (host->ops->get_timeout_clock) {
2679 host->timeout_clk = host->ops->get_timeout_clock(host);
2680 } else if (!(host->quirks &
2681 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2682 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2683 "frequency.\n", mmc_hostname(mmc));
2684 return -ENODEV;
2685 }
2686 }
2687 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2688 host->timeout_clk *= 1000;
2689
2690 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2691 host->timeout_clk = mmc->f_max / 1000;
272308ca 2692
65be3fef 2693 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
58d1246d 2694
e89d456f
AW		 2695 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2696
2697 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2698 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2699
8edf6371 2700 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2701 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2702 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2703 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2704 host->flags |= SDHCI_AUTO_CMD23;
2705 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2706 } else {
2707 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2708 }
2709
15ec4461
PR		 2710 /*
2711 * A controller may support 8-bit width, but the board itself
2712 * might not have the pins brought out. Boards that support
2713 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2714 * their platform code before calling sdhci_add_host(), and we
2715 * won't assume 8-bit width for hosts without that CAP.
2716 */
5fe23c7f 2717 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2718 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2719
f2119df6 2720 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2721 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2722
176d1ed4
JC		 2723 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2724 mmc_card_is_removable(mmc))
68d1fb7e
AV		 2725 mmc->caps |= MMC_CAP_NEEDS_POLL;
2726
f2119df6
AN		 2727 /* UHS-I mode(s) supported by the host controller. */
2728 if (host->version >= SDHCI_SPEC_300)
2729 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2730
2731 /* SDR104 supports also implies SDR50 support */
2732 if (caps[1] & SDHCI_SUPPORT_SDR104)
2733 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2734 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2735 mmc->caps |= MMC_CAP_UHS_SDR50;
2736
2737 if (caps[1] & SDHCI_SUPPORT_DDR50)
2738 mmc->caps |= MMC_CAP_UHS_DDR50;
2739
b513ea25
AN		 2740 /* Does the host needs tuning for SDR50? */
2741 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2742 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2743
d6d50a15
AN		 2744 /* Driver Type(s) (A, C, D) supported by the host */
2745 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2746 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2747 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2748 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2749 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2750 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2751
bec8726a
G		 2752 /*
2753 * If Power Off Notify capability is enabled by the host,
2754 * set notify to short power off notify timeout value.
2755 */
2756 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2757 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2758 else
2759 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2760
cf2b5eea
AN		 2761 /* Initial value for re-tuning timer count */
2762 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2763 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2764
2765 /*
2766 * In case Re-tuning Timer is not disabled, the actual value of
2767 * re-tuning timer will be 2 ^ (n - 1).
2768 */
2769 if (host->tuning_count)
2770 host->tuning_count = 1 << (host->tuning_count - 1);
2771
2772 /* Re-tuning mode supported by the Host Controller */
2773 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2774 SDHCI_RETUNING_MODE_SHIFT;
2775
8f230f45 2776 ocr_avail = 0;
f2119df6
AN		 2777 /*
2778 * According to SD Host Controller spec v3.00, if the Host System
2779 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2780 * the value is meaningful only if Voltage Support in the Capabilities
2781 * register is set. The actual current value is 4 times the register
2782 * value.
2783 */
2784 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2785
2786 if (caps[0] & SDHCI_CAN_VDD_330) {
2787 int max_current_330;
2788
8f230f45 2789 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6
AN		 2790
2791 max_current_330 = ((max_current_caps &
2792 SDHCI_MAX_CURRENT_330_MASK) >>
2793 SDHCI_MAX_CURRENT_330_SHIFT) *
2794 SDHCI_MAX_CURRENT_MULTIPLIER;
2795
2796 if (max_current_330 > 150)
2797 mmc->caps |= MMC_CAP_SET_XPC_330;
2798 }
2799 if (caps[0] & SDHCI_CAN_VDD_300) {
2800 int max_current_300;
2801
8f230f45 2802 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6
AN		 2803
2804 max_current_300 = ((max_current_caps &
2805 SDHCI_MAX_CURRENT_300_MASK) >>
2806 SDHCI_MAX_CURRENT_300_SHIFT) *
2807 SDHCI_MAX_CURRENT_MULTIPLIER;
2808
2809 if (max_current_300 > 150)
2810 mmc->caps |= MMC_CAP_SET_XPC_300;
2811 }
2812 if (caps[0] & SDHCI_CAN_VDD_180) {
2813 int max_current_180;
2814
8f230f45
TI		 2815 ocr_avail |= MMC_VDD_165_195;
2816
f2119df6
AN		 2817 max_current_180 = ((max_current_caps &
2818 SDHCI_MAX_CURRENT_180_MASK) >>
2819 SDHCI_MAX_CURRENT_180_SHIFT) *
2820 SDHCI_MAX_CURRENT_MULTIPLIER;
2821
2822 if (max_current_180 > 150)
2823 mmc->caps |= MMC_CAP_SET_XPC_180;
5371c927
AN		 2824
2825 /* Maximum current capabilities of the host at 1.8V */
2826 if (max_current_180 >= 800)
2827 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2828 else if (max_current_180 >= 600)
2829 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2830 else if (max_current_180 >= 400)
2831 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2832 else
2833 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
f2119df6
AN		 2834 }
2835
8f230f45
TI		 2836 mmc->ocr_avail = ocr_avail;
2837 mmc->ocr_avail_sdio = ocr_avail;
2838 if (host->ocr_avail_sdio)
2839 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2840 mmc->ocr_avail_sd = ocr_avail;
2841 if (host->ocr_avail_sd)
2842 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2843 else /* normal SD controllers don't support 1.8V */
2844 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2845 mmc->ocr_avail_mmc = ocr_avail;
2846 if (host->ocr_avail_mmc)
2847 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 2848
2849 if (mmc->ocr_avail == 0) {
a3c76eb9 2850 pr_err("%s: Hardware doesn't report any "
b69c9058 2851 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 2852 return -ENODEV;
146ad66e
PO		 2853 }
2854
d129bceb
PO		 2855 spin_lock_init(&host->lock);
2856
2857 /*
2134a922
PO		 2858 * Maximum number of segments. Depends on if the hardware
2859 * can do scatter/gather or not.
d129bceb 2860 */
2134a922 2861 if (host->flags & SDHCI_USE_ADMA)
a36274e0 2862 mmc->max_segs = 128;
a13abc7b 2863 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 2864 mmc->max_segs = 1;
2134a922 2865 else /* PIO */
a36274e0 2866 mmc->max_segs = 128;
d129bceb
PO		 2867
2868 /*
bab76961 2869 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 2870 * size (512KiB).
d129bceb 2871 */
55db890a 2872 mmc->max_req_size = 524288;
d129bceb
PO		 2873
2874 /*
2875 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 2876 * of bytes. When doing hardware scatter/gather, each entry cannot
2877 * be larger than 64 KiB though.
d129bceb 2878 */
30652aa3
OJ		 2879 if (host->flags & SDHCI_USE_ADMA) {
2880 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2881 mmc->max_seg_size = 65535;
2882 else
2883 mmc->max_seg_size = 65536;
2884 } else {
2134a922 2885 mmc->max_seg_size = mmc->max_req_size;
30652aa3 2886 }
d129bceb 2887
fe4a3c7a
PO		 2888 /*
2889 * Maximum block size. This varies from controller to controller and
2890 * is specified in the capabilities register.
2891 */
0633f654
AV		 2892 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2893 mmc->max_blk_size = 2;
2894 } else {
f2119df6 2895 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 2896 SDHCI_MAX_BLOCK_SHIFT;
2897 if (mmc->max_blk_size >= 3) {
a3c76eb9 2898 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 2899 "assuming 512 bytes\n", mmc_hostname(mmc));
2900 mmc->max_blk_size = 0;
2901 }
2902 }
2903
2904 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 2905
55db890a
PO		 2906 /*
2907 * Maximum block count.
2908 */
1388eefd 2909 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 2910
d129bceb
PO		 2911 /*
2912 * Init tasklets.
2913 */
2914 tasklet_init(&host->card_tasklet,
2915 sdhci_tasklet_card, (unsigned long)host);
2916 tasklet_init(&host->finish_tasklet,
2917 sdhci_tasklet_finish, (unsigned long)host);
2918
e4cad1b5 2919 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 2920
cf2b5eea 2921 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 2922 init_waitqueue_head(&host->buf_ready_int);
2923
cf2b5eea
AN		 2924 /* Initialize re-tuning timer */
2925 init_timer(&host->tuning_timer);
2926 host->tuning_timer.data = (unsigned long)host;
2927 host->tuning_timer.function = sdhci_tuning_timer;
2928 }
2929
dace1453 2930 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 2931 mmc_hostname(mmc), host);
d129bceb 2932 if (ret)
8ef1a143 2933 goto untasklet;
d129bceb 2934
9bea3c85
MS		 2935 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2936 if (IS_ERR(host->vmmc)) {
a3c76eb9 2937 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
9bea3c85
MS		 2938 host->vmmc = NULL;
2939 } else {
2940 regulator_enable(host->vmmc);
2941 }
2942
2f4cbb3d 2943 sdhci_init(host, 0);
d129bceb
PO		 2944
2945#ifdef CONFIG_MMC_DEBUG
2946 sdhci_dumpregs(host);
2947#endif
2948
f9134319 2949#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 2950 snprintf(host->led_name, sizeof(host->led_name),
2951 "%s::", mmc_hostname(mmc));
2952 host->led.name = host->led_name;
2f730fec
PO		 2953 host->led.brightness = LED_OFF;
2954 host->led.default_trigger = mmc_hostname(mmc);
2955 host->led.brightness_set = sdhci_led_control;
2956
b8c86fc5 2957 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 2958 if (ret)
2959 goto reset;
2960#endif
2961
5f25a66f
PO		 2962 mmiowb();
2963
d129bceb
PO		 2964 mmc_add_host(mmc);
2965
a3c76eb9 2966 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 2967 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 2968 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2969 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 2970
7260cf5e
AV		 2971 sdhci_enable_card_detection(host);
2972
d129bceb
PO		 2973 return 0;
2974
f9134319 2975#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2976reset:
2977 sdhci_reset(host, SDHCI_RESET_ALL);
2978 free_irq(host->irq, host);
2979#endif
8ef1a143 2980untasklet:
d129bceb
PO		 2981 tasklet_kill(&host->card_tasklet);
2982 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 2983
2984 return ret;
2985}
2986
b8c86fc5 2987EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 2988
1e72859e 2989void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 2990{
1e72859e
PO		 2991 unsigned long flags;
2992
2993 if (dead) {
2994 spin_lock_irqsave(&host->lock, flags);
2995
2996 host->flags |= SDHCI_DEVICE_DEAD;
2997
2998 if (host->mrq) {
a3c76eb9 2999 pr_err("%s: Controller removed during "
1e72859e
PO		 3000 " transfer!\n", mmc_hostname(host->mmc));
3001
3002 host->mrq->cmd->error = -ENOMEDIUM;
3003 tasklet_schedule(&host->finish_tasklet);
3004 }
3005
3006 spin_unlock_irqrestore(&host->lock, flags);
3007 }
3008
7260cf5e
AV		 3009 sdhci_disable_card_detection(host);
3010
b8c86fc5 3011 mmc_remove_host(host->mmc);
d129bceb 3012
f9134319 3013#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3014 led_classdev_unregister(&host->led);
3015#endif
3016
1e72859e
PO		 3017 if (!dead)
3018 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 3019
3020 free_irq(host->irq, host);
3021
3022 del_timer_sync(&host->timer);
cf2b5eea
AN		 3023 if (host->version >= SDHCI_SPEC_300)
3024 del_timer_sync(&host->tuning_timer);
d129bceb
PO		 3025
3026 tasklet_kill(&host->card_tasklet);
3027 tasklet_kill(&host->finish_tasklet);
2134a922 3028
9bea3c85
MS		 3029 if (host->vmmc) {
3030 regulator_disable(host->vmmc);
3031 regulator_put(host->vmmc);
3032 }
3033
2134a922
PO		 3034 kfree(host->adma_desc);
3035 kfree(host->align_buffer);
3036
3037 host->adma_desc = NULL;
3038 host->align_buffer = NULL;
d129bceb
PO		 3039}
3040
b8c86fc5 3041EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3042
b8c86fc5 3043void sdhci_free_host(struct sdhci_host *host)
d129bceb 3044{
b8c86fc5 3045 mmc_free_host(host->mmc);
d129bceb
PO		 3046}
3047
b8c86fc5 3048EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3049
3050/*****************************************************************************\
3051 * *
3052 * Driver init/exit *
3053 * *
3054\*****************************************************************************/
3055
3056static int __init sdhci_drv_init(void)
3057{
a3c76eb9 3058 pr_info(DRIVER_NAME
52fbf9c9 3059 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3060 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3061
b8c86fc5 3062 return 0;
d129bceb
PO		 3063}
3064
3065static void __exit sdhci_drv_exit(void)
3066{
d129bceb
PO		 3067}
3068
3069module_init(sdhci_drv_init);
3070module_exit(sdhci_drv_exit);
3071
df673b22 3072module_param(debug_quirks, uint, 0444);
66fd8ad5 3073module_param(debug_quirks2, uint, 0444);
67435274 3074
32710e8f 3075MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3076MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3077MODULE_LICENSE("GPL");
67435274 3078
df673b22 3079MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3080MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux 6.x block layer and io_uring tree(s)