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mmc: sdhci: move setting mmc->actual_clock into set_clock handlers
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
d1e49f77
RK		 47#define ADMA_SIZE ((128 * 2 + 1) * 4)
48
df673b22 49static unsigned int debug_quirks = 0;
66fd8ad5 50static unsigned int debug_quirks2;
67435274 51
d129bceb
PO		 52static void sdhci_finish_data(struct sdhci_host *);
53
d129bceb 54static void sdhci_finish_command(struct sdhci_host *);
069c9f14 55static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 56static void sdhci_tuning_timer(unsigned long data);
52983382 57static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 58
66fd8ad5
AH		 59#ifdef CONFIG_PM_RUNTIME
60static int sdhci_runtime_pm_get(struct sdhci_host *host);
61static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 62static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
63static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 64#else
65static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
66{
67 return 0;
68}
69static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
70{
71 return 0;
72}
f0710a55
AH		 73static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
74{
75}
76static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
77{
78}
66fd8ad5
AH		 79#endif
80
d129bceb
PO		 81static void sdhci_dumpregs(struct sdhci_host *host)
82{
a3c76eb9 83 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 84 mmc_hostname(host->mmc));
d129bceb 85
a3c76eb9 86 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 87 sdhci_readl(host, SDHCI_DMA_ADDRESS),
88 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 89 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 90 sdhci_readw(host, SDHCI_BLOCK_SIZE),
91 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 92 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 93 sdhci_readl(host, SDHCI_ARGUMENT),
94 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 95 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 96 sdhci_readl(host, SDHCI_PRESENT_STATE),
97 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 98 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 99 sdhci_readb(host, SDHCI_POWER_CONTROL),
100 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 101 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 102 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
103 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 104 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 105 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
106 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 107 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 108 sdhci_readl(host, SDHCI_INT_ENABLE),
109 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 110 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 111 sdhci_readw(host, SDHCI_ACMD12_ERR),
112 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 113 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 114 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 115 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 117 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 118 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 120 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 121
be3f4ae0 122 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
126
a3c76eb9 127 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 128}
129
130/*****************************************************************************\
131 * *
132 * Low level functions *
133 * *
134\*****************************************************************************/
135
7260cf5e
AV		 136static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
137{
5b4f1f6c 138 u32 present;
7260cf5e 139
c79396c1 140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 141 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 142 return;
143
5b4f1f6c
RK		 144 if (enable) {
145 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
146 SDHCI_CARD_PRESENT;
d25928d1 147
5b4f1f6c
RK		 148 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
149 SDHCI_INT_CARD_INSERT;
150 } else {
151 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
152 }
b537f94c
RK		 153
154 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
155 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 156}
157
158static void sdhci_enable_card_detection(struct sdhci_host *host)
159{
160 sdhci_set_card_detection(host, true);
161}
162
163static void sdhci_disable_card_detection(struct sdhci_host *host)
164{
165 sdhci_set_card_detection(host, false);
166}
167
03231f9b 168void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 169{
e16514d8 170 unsigned long timeout;
393c1a34 171
4e4141a5 172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 173
f0710a55 174 if (mask & SDHCI_RESET_ALL) {
d129bceb 175 host->clock = 0;
f0710a55
AH		 176 /* Reset-all turns off SD Bus Power */
177 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
178 sdhci_runtime_pm_bus_off(host);
179 }
d129bceb 180
e16514d8
PO		 181 /* Wait max 100 ms */
182 timeout = 100;
183
184 /* hw clears the bit when it's done */
4e4141a5 185 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 186 if (timeout == 0) {
a3c76eb9 187 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 188 mmc_hostname(host->mmc), (int)mask);
189 sdhci_dumpregs(host);
190 return;
191 }
192 timeout--;
193 mdelay(1);
d129bceb 194 }
03231f9b
RK		 195}
196EXPORT_SYMBOL_GPL(sdhci_reset);
197
198static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
199{
200 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
201 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
202 SDHCI_CARD_PRESENT))
203 return;
204 }
063a9dbb 205
03231f9b 206 host->ops->reset(host, mask);
393c1a34 207
3abc1e80
SX		 208 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
209 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
210 host->ops->enable_dma(host);
211 }
d129bceb
PO		 212}
213
2f4cbb3d
NP		 214static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
215
216static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 217{
2f4cbb3d 218 if (soft)
03231f9b 219 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 220 else
03231f9b 221 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 222
b537f94c
RK		 223 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
224 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
225 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
226 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
227 SDHCI_INT_RESPONSE;
228
229 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
230 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 231
232 if (soft) {
233 /* force clock reconfiguration */
234 host->clock = 0;
235 sdhci_set_ios(host->mmc, &host->mmc->ios);
236 }
7260cf5e 237}
d129bceb 238
7260cf5e
AV		 239static void sdhci_reinit(struct sdhci_host *host)
240{
2f4cbb3d 241 sdhci_init(host, 0);
b67c6b41
AL		 242 /*
243 * Retuning stuffs are affected by different cards inserted and only
244 * applicable to UHS-I cards. So reset these fields to their initial
245 * value when card is removed.
246 */
973905fe
AL		 247 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
248 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
249
b67c6b41
AL		 250 del_timer_sync(&host->tuning_timer);
251 host->flags &= ~SDHCI_NEEDS_RETUNING;
252 host->mmc->max_blk_count =
253 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
254 }
7260cf5e 255 sdhci_enable_card_detection(host);
d129bceb
PO		 256}
257
258static void sdhci_activate_led(struct sdhci_host *host)
259{
260 u8 ctrl;
261
4e4141a5 262 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 263 ctrl |= SDHCI_CTRL_LED;
4e4141a5 264 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 265}
266
267static void sdhci_deactivate_led(struct sdhci_host *host)
268{
269 u8 ctrl;
270
4e4141a5 271 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 272 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 273 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 274}
275
f9134319 276#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 277static void sdhci_led_control(struct led_classdev *led,
278 enum led_brightness brightness)
279{
280 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
281 unsigned long flags;
282
283 spin_lock_irqsave(&host->lock, flags);
284
66fd8ad5
AH		 285 if (host->runtime_suspended)
286 goto out;
287
2f730fec
PO		 288 if (brightness == LED_OFF)
289 sdhci_deactivate_led(host);
290 else
291 sdhci_activate_led(host);
66fd8ad5 292out:
2f730fec
PO		 293 spin_unlock_irqrestore(&host->lock, flags);
294}
295#endif
296
d129bceb
PO		 297/*****************************************************************************\
298 * *
299 * Core functions *
300 * *
301\*****************************************************************************/
302
a406f5a3 303static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 304{
7659150c
PO		 305 unsigned long flags;
306 size_t blksize, len, chunk;
7244b85b 307 u32 uninitialized_var(scratch);
7659150c 308 u8 *buf;
d129bceb 309
a406f5a3 310 DBG("PIO reading\n");
d129bceb 311
a406f5a3 312 blksize = host->data->blksz;
7659150c 313 chunk = 0;
d129bceb 314
7659150c 315 local_irq_save(flags);
d129bceb 316
a406f5a3 317 while (blksize) {
7659150c
PO		 318 if (!sg_miter_next(&host->sg_miter))
319 BUG();
d129bceb 320
7659150c 321 len = min(host->sg_miter.length, blksize);
d129bceb 322
7659150c
PO		 323 blksize -= len;
324 host->sg_miter.consumed = len;
14d836e7 325
7659150c 326 buf = host->sg_miter.addr;
d129bceb 327
7659150c
PO		 328 while (len) {
329 if (chunk == 0) {
4e4141a5 330 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 331 chunk = 4;
a406f5a3 332 }
7659150c
PO		 333
334 *buf = scratch & 0xFF;
335
336 buf++;
337 scratch >>= 8;
338 chunk--;
339 len--;
d129bceb 340 }
a406f5a3 341 }
7659150c
PO		 342
343 sg_miter_stop(&host->sg_miter);
344
345 local_irq_restore(flags);
a406f5a3 346}
d129bceb 347
a406f5a3
PO		 348static void sdhci_write_block_pio(struct sdhci_host *host)
349{
7659150c
PO		 350 unsigned long flags;
351 size_t blksize, len, chunk;
352 u32 scratch;
353 u8 *buf;
d129bceb 354
a406f5a3
PO		 355 DBG("PIO writing\n");
356
357 blksize = host->data->blksz;
7659150c
PO		 358 chunk = 0;
359 scratch = 0;
d129bceb 360
7659150c 361 local_irq_save(flags);
d129bceb 362
a406f5a3 363 while (blksize) {
7659150c
PO		 364 if (!sg_miter_next(&host->sg_miter))
365 BUG();
a406f5a3 366
7659150c
PO		 367 len = min(host->sg_miter.length, blksize);
368
369 blksize -= len;
370 host->sg_miter.consumed = len;
371
372 buf = host->sg_miter.addr;
d129bceb 373
7659150c
PO		 374 while (len) {
375 scratch |= (u32)*buf << (chunk * 8);
376
377 buf++;
378 chunk++;
379 len--;
380
381 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 382 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 383 chunk = 0;
384 scratch = 0;
d129bceb 385 }
d129bceb
PO		 386 }
387 }
7659150c
PO		 388
389 sg_miter_stop(&host->sg_miter);
390
391 local_irq_restore(flags);
a406f5a3
PO		 392}
393
394static void sdhci_transfer_pio(struct sdhci_host *host)
395{
396 u32 mask;
397
398 BUG_ON(!host->data);
399
7659150c 400 if (host->blocks == 0)
a406f5a3
PO		 401 return;
402
403 if (host->data->flags & MMC_DATA_READ)
404 mask = SDHCI_DATA_AVAILABLE;
405 else
406 mask = SDHCI_SPACE_AVAILABLE;
407
4a3cba32
PO		 408 /*
409 * Some controllers (JMicron JMB38x) mess up the buffer bits
410 * for transfers < 4 bytes. As long as it is just one block,
411 * we can ignore the bits.
412 */
413 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
414 (host->data->blocks == 1))
415 mask = ~0;
416
4e4141a5 417 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 418 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
419 udelay(100);
420
a406f5a3
PO		 421 if (host->data->flags & MMC_DATA_READ)
422 sdhci_read_block_pio(host);
423 else
424 sdhci_write_block_pio(host);
d129bceb 425
7659150c
PO		 426 host->blocks--;
427 if (host->blocks == 0)
a406f5a3 428 break;
a406f5a3 429 }
d129bceb 430
a406f5a3 431 DBG("PIO transfer complete.\n");
d129bceb
PO		 432}
433
2134a922
PO		 434static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
435{
436 local_irq_save(*flags);
482fce99 437 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 438}
439
440static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
441{
482fce99 442 kunmap_atomic(buffer);
2134a922
PO		 443 local_irq_restore(*flags);
444}
445
118cd17d
BD		 446static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
447{
9e506f35
BD		 448 __le32 *dataddr = (__le32 __force *)(desc + 4);
449 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 450
9e506f35
BD		 451 /* SDHCI specification says ADMA descriptors should be 4 byte
452 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 453
9e506f35
BD		 454 cmdlen[0] = cpu_to_le16(cmd);
455 cmdlen[1] = cpu_to_le16(len);
456
457 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 458}
459
8f1934ce 460static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 461 struct mmc_data *data)
462{
463 int direction;
464
465 u8 *desc;
466 u8 *align;
467 dma_addr_t addr;
468 dma_addr_t align_addr;
469 int len, offset;
470
471 struct scatterlist *sg;
472 int i;
473 char *buffer;
474 unsigned long flags;
475
476 /*
477 * The spec does not specify endianness of descriptor table.
478 * We currently guess that it is LE.
479 */
480
481 if (data->flags & MMC_DATA_READ)
482 direction = DMA_FROM_DEVICE;
483 else
484 direction = DMA_TO_DEVICE;
485
2134a922
PO		 486 host->align_addr = dma_map_single(mmc_dev(host->mmc),
487 host->align_buffer, 128 * 4, direction);
8d8bb39b 488 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 489 goto fail;
2134a922
PO		 490 BUG_ON(host->align_addr & 0x3);
491
492 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
493 data->sg, data->sg_len, direction);
8f1934ce
PO		 494 if (host->sg_count == 0)
495 goto unmap_align;
2134a922
PO		 496
497 desc = host->adma_desc;
498 align = host->align_buffer;
499
500 align_addr = host->align_addr;
501
502 for_each_sg(data->sg, sg, host->sg_count, i) {
503 addr = sg_dma_address(sg);
504 len = sg_dma_len(sg);
505
506 /*
507 * The SDHCI specification states that ADMA
508 * addresses must be 32-bit aligned. If they
509 * aren't, then we use a bounce buffer for
510 * the (up to three) bytes that screw up the
511 * alignment.
512 */
513 offset = (4 - (addr & 0x3)) & 0x3;
514 if (offset) {
515 if (data->flags & MMC_DATA_WRITE) {
516 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 517 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 518 memcpy(align, buffer, offset);
519 sdhci_kunmap_atomic(buffer, &flags);
520 }
521
118cd17d
BD		 522 /* tran, valid */
523 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 524
525 BUG_ON(offset > 65536);
526
2134a922
PO		 527 align += 4;
528 align_addr += 4;
529
530 desc += 8;
531
532 addr += offset;
533 len -= offset;
534 }
535
2134a922
PO		 536 BUG_ON(len > 65536);
537
118cd17d
BD		 538 /* tran, valid */
539 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 540 desc += 8;
541
542 /*
543 * If this triggers then we have a calculation bug
544 * somewhere. :/
545 */
d1e49f77 546 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
2134a922
PO		 547 }
548
70764a90
TA		 549 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
550 /*
551 * Mark the last descriptor as the terminating descriptor
552 */
553 if (desc != host->adma_desc) {
554 desc -= 8;
555 desc[0] |= 0x2; /* end */
556 }
557 } else {
558 /*
559 * Add a terminating entry.
560 */
2134a922 561
70764a90
TA		 562 /* nop, end, valid */
563 sdhci_set_adma_desc(desc, 0, 0, 0x3);
564 }
2134a922
PO		 565
566 /*
567 * Resync align buffer as we might have changed it.
568 */
569 if (data->flags & MMC_DATA_WRITE) {
570 dma_sync_single_for_device(mmc_dev(host->mmc),
571 host->align_addr, 128 * 4, direction);
572 }
573
8f1934ce
PO		 574 return 0;
575
8f1934ce
PO		 576unmap_align:
577 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
578 128 * 4, direction);
579fail:
580 return -EINVAL;
2134a922
PO		 581}
582
583static void sdhci_adma_table_post(struct sdhci_host *host,
584 struct mmc_data *data)
585{
586 int direction;
587
588 struct scatterlist *sg;
589 int i, size;
590 u8 *align;
591 char *buffer;
592 unsigned long flags;
de0b65a7 593 bool has_unaligned;
2134a922
PO		 594
595 if (data->flags & MMC_DATA_READ)
596 direction = DMA_FROM_DEVICE;
597 else
598 direction = DMA_TO_DEVICE;
599
2134a922
PO		 600 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
601 128 * 4, direction);
602
de0b65a7
RK		 603 /* Do a quick scan of the SG list for any unaligned mappings */
604 has_unaligned = false;
605 for_each_sg(data->sg, sg, host->sg_count, i)
606 if (sg_dma_address(sg) & 3) {
607 has_unaligned = true;
608 break;
609 }
610
611 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 612 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
613 data->sg_len, direction);
614
615 align = host->align_buffer;
616
617 for_each_sg(data->sg, sg, host->sg_count, i) {
618 if (sg_dma_address(sg) & 0x3) {
619 size = 4 - (sg_dma_address(sg) & 0x3);
620
621 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 622 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 623 memcpy(buffer, align, size);
624 sdhci_kunmap_atomic(buffer, &flags);
625
626 align += 4;
627 }
628 }
629 }
630
631 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
632 data->sg_len, direction);
633}
634
a3c7778f 635static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 636{
1c8cde92 637 u8 count;
a3c7778f 638 struct mmc_data *data = cmd->data;
1c8cde92 639 unsigned target_timeout, current_timeout;
d129bceb 640
ee53ab5d
PO		 641 /*
642 * If the host controller provides us with an incorrect timeout
643 * value, just skip the check and use 0xE. The hardware may take
644 * longer to time out, but that's much better than having a too-short
645 * timeout value.
646 */
11a2f1b7 647 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 648 return 0xE;
e538fbe8 649
a3c7778f 650 /* Unspecified timeout, assume max */
1d4d7744 651 if (!data && !cmd->busy_timeout)
a3c7778f 652 return 0xE;
d129bceb 653
a3c7778f
AW		 654 /* timeout in us */
655 if (!data)
1d4d7744 656 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 657 else {
658 target_timeout = data->timeout_ns / 1000;
659 if (host->clock)
660 target_timeout += data->timeout_clks / host->clock;
661 }
81b39802 662
1c8cde92
PO		 663 /*
664 * Figure out needed cycles.
665 * We do this in steps in order to fit inside a 32 bit int.
666 * The first step is the minimum timeout, which will have a
667 * minimum resolution of 6 bits:
668 * (1) 2^13*1000 > 2^22,
669 * (2) host->timeout_clk < 2^16
670 * =>
671 * (1) / (2) > 2^6
672 */
673 count = 0;
674 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
675 while (current_timeout < target_timeout) {
676 count++;
677 current_timeout <<= 1;
678 if (count >= 0xF)
679 break;
680 }
681
682 if (count >= 0xF) {
09eeff52
CB		 683 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
684 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 685 count = 0xE;
686 }
687
ee53ab5d
PO		 688 return count;
689}
690
6aa943ab
AV		 691static void sdhci_set_transfer_irqs(struct sdhci_host *host)
692{
693 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
694 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
695
696 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 697 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 698 else
b537f94c
RK		 699 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
700
701 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
702 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 703}
704
a3c7778f 705static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 706{
707 u8 count;
2134a922 708 u8 ctrl;
a3c7778f 709 struct mmc_data *data = cmd->data;
8f1934ce 710 int ret;
ee53ab5d
PO		 711
712 WARN_ON(host->data);
713
a3c7778f
AW		 714 if (data || (cmd->flags & MMC_RSP_BUSY)) {
715 count = sdhci_calc_timeout(host, cmd);
716 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
717 }
718
719 if (!data)
ee53ab5d
PO		 720 return;
721
722 /* Sanity checks */
723 BUG_ON(data->blksz * data->blocks > 524288);
724 BUG_ON(data->blksz > host->mmc->max_blk_size);
725 BUG_ON(data->blocks > 65535);
726
727 host->data = data;
728 host->data_early = 0;
f6a03cbf 729 host->data->bytes_xfered = 0;
ee53ab5d 730
a13abc7b 731 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 732 host->flags |= SDHCI_REQ_USE_DMA;
733
2134a922
PO		 734 /*
735 * FIXME: This doesn't account for merging when mapping the
736 * scatterlist.
737 */
738 if (host->flags & SDHCI_REQ_USE_DMA) {
739 int broken, i;
740 struct scatterlist *sg;
741
742 broken = 0;
743 if (host->flags & SDHCI_USE_ADMA) {
744 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
745 broken = 1;
746 } else {
747 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
748 broken = 1;
749 }
750
751 if (unlikely(broken)) {
752 for_each_sg(data->sg, sg, data->sg_len, i) {
753 if (sg->length & 0x3) {
754 DBG("Reverting to PIO because of "
755 "transfer size (%d)\n",
756 sg->length);
757 host->flags &= ~SDHCI_REQ_USE_DMA;
758 break;
759 }
760 }
761 }
c9fddbc4
PO		 762 }
763
764 /*
765 * The assumption here being that alignment is the same after
766 * translation to device address space.
767 */
2134a922
PO		 768 if (host->flags & SDHCI_REQ_USE_DMA) {
769 int broken, i;
770 struct scatterlist *sg;
771
772 broken = 0;
773 if (host->flags & SDHCI_USE_ADMA) {
774 /*
775 * As we use 3 byte chunks to work around
776 * alignment problems, we need to check this
777 * quirk.
778 */
779 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
780 broken = 1;
781 } else {
782 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
783 broken = 1;
784 }
785
786 if (unlikely(broken)) {
787 for_each_sg(data->sg, sg, data->sg_len, i) {
788 if (sg->offset & 0x3) {
789 DBG("Reverting to PIO because of "
790 "bad alignment\n");
791 host->flags &= ~SDHCI_REQ_USE_DMA;
792 break;
793 }
794 }
795 }
796 }
797
8f1934ce
PO		 798 if (host->flags & SDHCI_REQ_USE_DMA) {
799 if (host->flags & SDHCI_USE_ADMA) {
800 ret = sdhci_adma_table_pre(host, data);
801 if (ret) {
802 /*
803 * This only happens when someone fed
804 * us an invalid request.
805 */
806 WARN_ON(1);
ebd6d357 807 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 808 } else {
4e4141a5
AV		 809 sdhci_writel(host, host->adma_addr,
810 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 811 }
812 } else {
c8b3e02e 813 int sg_cnt;
8f1934ce 814
c8b3e02e 815 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 816 data->sg, data->sg_len,
817 (data->flags & MMC_DATA_READ) ?
818 DMA_FROM_DEVICE :
819 DMA_TO_DEVICE);
c8b3e02e 820 if (sg_cnt == 0) {
8f1934ce
PO		 821 /*
822 * This only happens when someone fed
823 * us an invalid request.
824 */
825 WARN_ON(1);
ebd6d357 826 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 827 } else {
719a61b4 828 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 829 sdhci_writel(host, sg_dma_address(data->sg),
830 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 831 }
832 }
833 }
834
2134a922
PO		 835 /*
836 * Always adjust the DMA selection as some controllers
837 * (e.g. JMicron) can't do PIO properly when the selection
838 * is ADMA.
839 */
840 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 841 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 842 ctrl &= ~SDHCI_CTRL_DMA_MASK;
843 if ((host->flags & SDHCI_REQ_USE_DMA) &&
844 (host->flags & SDHCI_USE_ADMA))
845 ctrl |= SDHCI_CTRL_ADMA32;
846 else
847 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 848 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 849 }
850
8f1934ce 851 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 852 int flags;
853
854 flags = SG_MITER_ATOMIC;
855 if (host->data->flags & MMC_DATA_READ)
856 flags |= SG_MITER_TO_SG;
857 else
858 flags |= SG_MITER_FROM_SG;
859 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 860 host->blocks = data->blocks;
d129bceb 861 }
c7fa9963 862
6aa943ab
AV		 863 sdhci_set_transfer_irqs(host);
864
f6a03cbf
MV		 865 /* Set the DMA boundary value and block size */
866 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
867 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 868 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 869}
870
871static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 872 struct mmc_command *cmd)
c7fa9963
PO		 873{
874 u16 mode;
e89d456f 875 struct mmc_data *data = cmd->data;
c7fa9963 876
2b558c13
DA		 877 if (data == NULL) {
878 /* clear Auto CMD settings for no data CMDs */
879 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
880 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
881 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
c7fa9963 882 return;
2b558c13 883 }
c7fa9963 884
e538fbe8
PO		 885 WARN_ON(!host->data);
886
c7fa9963 887 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 888 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
889 mode |= SDHCI_TRNS_MULTI;
890 /*
891 * If we are sending CMD23, CMD12 never gets sent
892 * on successful completion (so no Auto-CMD12).
893 */
894 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
895 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 896 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
897 mode |= SDHCI_TRNS_AUTO_CMD23;
898 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
899 }
c4512f79 900 }
8edf6371 901
c7fa9963
PO		 902 if (data->flags & MMC_DATA_READ)
903 mode |= SDHCI_TRNS_READ;
c9fddbc4 904 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 905 mode |= SDHCI_TRNS_DMA;
906
4e4141a5 907 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 908}
909
910static void sdhci_finish_data(struct sdhci_host *host)
911{
912 struct mmc_data *data;
d129bceb
PO		 913
914 BUG_ON(!host->data);
915
916 data = host->data;
917 host->data = NULL;
918
c9fddbc4 919 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 920 if (host->flags & SDHCI_USE_ADMA)
921 sdhci_adma_table_post(host, data);
922 else {
923 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
924 data->sg_len, (data->flags & MMC_DATA_READ) ?
925 DMA_FROM_DEVICE : DMA_TO_DEVICE);
926 }
d129bceb
PO		 927 }
928
929 /*
c9b74c5b
PO		 930 * The specification states that the block count register must
931 * be updated, but it does not specify at what point in the
932 * data flow. That makes the register entirely useless to read
933 * back so we have to assume that nothing made it to the card
934 * in the event of an error.
d129bceb 935 */
c9b74c5b
PO		 936 if (data->error)
937 data->bytes_xfered = 0;
d129bceb 938 else
c9b74c5b 939 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 940
e89d456f
AW		 941 /*
942 * Need to send CMD12 if -
943 * a) open-ended multiblock transfer (no CMD23)
944 * b) error in multiblock transfer
945 */
946 if (data->stop &&
947 (data->error ||
948 !host->mrq->sbc)) {
949
d129bceb
PO		 950 /*
951 * The controller needs a reset of internal state machines
952 * upon error conditions.
953 */
17b0429d 954 if (data->error) {
03231f9b
RK		 955 sdhci_do_reset(host, SDHCI_RESET_CMD);
956 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 957 }
958
959 sdhci_send_command(host, data->stop);
960 } else
961 tasklet_schedule(&host->finish_tasklet);
962}
963
c0e55129 964void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 965{
966 int flags;
fd2208d7 967 u32 mask;
7cb2c76f 968 unsigned long timeout;
d129bceb
PO		 969
970 WARN_ON(host->cmd);
971
d129bceb 972 /* Wait max 10 ms */
7cb2c76f 973 timeout = 10;
fd2208d7
PO		 974
975 mask = SDHCI_CMD_INHIBIT;
976 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
977 mask |= SDHCI_DATA_INHIBIT;
978
979 /* We shouldn't wait for data inihibit for stop commands, even
980 though they might use busy signaling */
981 if (host->mrq->data && (cmd == host->mrq->data->stop))
982 mask &= ~SDHCI_DATA_INHIBIT;
983
4e4141a5 984 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 985 if (timeout == 0) {
a3c76eb9 986 pr_err("%s: Controller never released "
acf1da45 987 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 988 sdhci_dumpregs(host);
17b0429d 989 cmd->error = -EIO;
d129bceb
PO		 990 tasklet_schedule(&host->finish_tasklet);
991 return;
992 }
7cb2c76f
PO		 993 timeout--;
994 mdelay(1);
995 }
d129bceb 996
3e1a6892 997 timeout = jiffies;
1d4d7744
UH		 998 if (!cmd->data && cmd->busy_timeout > 9000)
999 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1000 else
1001 timeout += 10 * HZ;
1002 mod_timer(&host->timer, timeout);
d129bceb
PO		 1003
1004 host->cmd = cmd;
1005
a3c7778f 1006 sdhci_prepare_data(host, cmd);
d129bceb 1007
4e4141a5 1008 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1009
e89d456f 1010 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1011
d129bceb 1012 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1013 pr_err("%s: Unsupported response type!\n",
d129bceb 1014 mmc_hostname(host->mmc));
17b0429d 1015 cmd->error = -EINVAL;
d129bceb
PO		 1016 tasklet_schedule(&host->finish_tasklet);
1017 return;
1018 }
1019
1020 if (!(cmd->flags & MMC_RSP_PRESENT))
1021 flags = SDHCI_CMD_RESP_NONE;
1022 else if (cmd->flags & MMC_RSP_136)
1023 flags = SDHCI_CMD_RESP_LONG;
1024 else if (cmd->flags & MMC_RSP_BUSY)
1025 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1026 else
1027 flags = SDHCI_CMD_RESP_SHORT;
1028
1029 if (cmd->flags & MMC_RSP_CRC)
1030 flags |= SDHCI_CMD_CRC;
1031 if (cmd->flags & MMC_RSP_OPCODE)
1032 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1033
1034 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1035 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1036 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1037 flags |= SDHCI_CMD_DATA;
1038
4e4141a5 1039 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1040}
c0e55129 1041EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1042
1043static void sdhci_finish_command(struct sdhci_host *host)
1044{
1045 int i;
1046
1047 BUG_ON(host->cmd == NULL);
1048
1049 if (host->cmd->flags & MMC_RSP_PRESENT) {
1050 if (host->cmd->flags & MMC_RSP_136) {
1051 /* CRC is stripped so we need to do some shifting. */
1052 for (i = 0;i < 4;i++) {
4e4141a5 1053 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1054 SDHCI_RESPONSE + (3-i)*4) << 8;
1055 if (i != 3)
1056 host->cmd->resp[i] |=
4e4141a5 1057 sdhci_readb(host,
d129bceb
PO		 1058 SDHCI_RESPONSE + (3-i)*4-1);
1059 }
1060 } else {
4e4141a5 1061 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1062 }
1063 }
1064
17b0429d 1065 host->cmd->error = 0;
d129bceb 1066
e89d456f
AW		 1067 /* Finished CMD23, now send actual command. */
1068 if (host->cmd == host->mrq->sbc) {
1069 host->cmd = NULL;
1070 sdhci_send_command(host, host->mrq->cmd);
1071 } else {
e538fbe8 1072
e89d456f
AW		 1073 /* Processed actual command. */
1074 if (host->data && host->data_early)
1075 sdhci_finish_data(host);
d129bceb 1076
e89d456f
AW		 1077 if (!host->cmd->data)
1078 tasklet_schedule(&host->finish_tasklet);
1079
1080 host->cmd = NULL;
1081 }
d129bceb
PO		 1082}
1083
52983382
KL		 1084static u16 sdhci_get_preset_value(struct sdhci_host *host)
1085{
1086 u16 ctrl, preset = 0;
1087
1088 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1089
1090 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1091 case SDHCI_CTRL_UHS_SDR12:
1092 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1093 break;
1094 case SDHCI_CTRL_UHS_SDR25:
1095 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1096 break;
1097 case SDHCI_CTRL_UHS_SDR50:
1098 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1099 break;
1100 case SDHCI_CTRL_UHS_SDR104:
1101 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1102 break;
1103 case SDHCI_CTRL_UHS_DDR50:
1104 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1105 break;
1106 default:
1107 pr_warn("%s: Invalid UHS-I mode selected\n",
1108 mmc_hostname(host->mmc));
1109 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1110 break;
1111 }
1112 return preset;
1113}
1114
d129bceb
PO		 1115static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1116{
c3ed3877 1117 int div = 0; /* Initialized for compiler warning */
df16219f 1118 int real_div = div, clk_mul = 1;
c3ed3877 1119 u16 clk = 0;
7cb2c76f 1120 unsigned long timeout;
d129bceb 1121
8114634c
AV		 1122 if (host->ops->set_clock) {
1123 host->ops->set_clock(host, clock);
1124 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1125 return;
1126 }
1127
1650d0c7
RK		 1128 host->mmc->actual_clock = 0;
1129
4e4141a5 1130 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1131
1132 if (clock == 0)
373073ef 1133 return;
d129bceb 1134
85105c53 1135 if (host->version >= SDHCI_SPEC_300) {
52983382
KL		 1136 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1137 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1138 u16 pre_val;
1139
1140 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1141 pre_val = sdhci_get_preset_value(host);
1142 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1143 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1144 if (host->clk_mul &&
1145 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1146 clk = SDHCI_PROG_CLOCK_MODE;
1147 real_div = div + 1;
1148 clk_mul = host->clk_mul;
1149 } else {
1150 real_div = max_t(int, 1, div << 1);
1151 }
1152 goto clock_set;
1153 }
1154
c3ed3877
AN		 1155 /*
1156 * Check if the Host Controller supports Programmable Clock
1157 * Mode.
1158 */
1159 if (host->clk_mul) {
52983382
KL		 1160 for (div = 1; div <= 1024; div++) {
1161 if ((host->max_clk * host->clk_mul / div)
1162 <= clock)
1163 break;
1164 }
c3ed3877 1165 /*
52983382
KL		 1166 * Set Programmable Clock Mode in the Clock
1167 * Control register.
c3ed3877 1168 */
52983382
KL		 1169 clk = SDHCI_PROG_CLOCK_MODE;
1170 real_div = div;
1171 clk_mul = host->clk_mul;
1172 div--;
c3ed3877
AN		 1173 } else {
1174 /* Version 3.00 divisors must be a multiple of 2. */
1175 if (host->max_clk <= clock)
1176 div = 1;
1177 else {
1178 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1179 div += 2) {
1180 if ((host->max_clk / div) <= clock)
1181 break;
1182 }
85105c53 1183 }
df16219f 1184 real_div = div;
c3ed3877 1185 div >>= 1;
85105c53
ZG		 1186 }
1187 } else {
1188 /* Version 2.00 divisors must be a power of 2. */
0397526d 1189 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1190 if ((host->max_clk / div) <= clock)
1191 break;
1192 }
df16219f 1193 real_div = div;
c3ed3877 1194 div >>= 1;
d129bceb 1195 }
d129bceb 1196
52983382 1197clock_set:
df16219f
GC		 1198 if (real_div)
1199 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1200
c3ed3877 1201 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1202 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1203 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1204 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1205 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1206
27f6cb16
CB		 1207 /* Wait max 20 ms */
1208 timeout = 20;
4e4141a5 1209 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1210 & SDHCI_CLOCK_INT_STABLE)) {
1211 if (timeout == 0) {
a3c76eb9 1212 pr_err("%s: Internal clock never "
acf1da45 1213 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1214 sdhci_dumpregs(host);
1215 return;
1216 }
7cb2c76f
PO		 1217 timeout--;
1218 mdelay(1);
1219 }
d129bceb
PO		 1220
1221 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1222 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1223}
1224
ceb6143b 1225static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1226{
8364248a 1227 u8 pwr = 0;
146ad66e 1228
8364248a 1229 if (power != (unsigned short)-1) {
ae628903
PO		 1230 switch (1 << power) {
1231 case MMC_VDD_165_195:
1232 pwr = SDHCI_POWER_180;
1233 break;
1234 case MMC_VDD_29_30:
1235 case MMC_VDD_30_31:
1236 pwr = SDHCI_POWER_300;
1237 break;
1238 case MMC_VDD_32_33:
1239 case MMC_VDD_33_34:
1240 pwr = SDHCI_POWER_330;
1241 break;
1242 default:
1243 BUG();
1244 }
1245 }
1246
1247 if (host->pwr == pwr)
ceb6143b 1248 return -1;
146ad66e 1249
ae628903
PO		 1250 host->pwr = pwr;
1251
1252 if (pwr == 0) {
4e4141a5 1253 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1254 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1255 sdhci_runtime_pm_bus_off(host);
ceb6143b 1256 return 0;
9e9dc5f2
DS		 1257 }
1258
1259 /*
1260 * Spec says that we should clear the power reg before setting
1261 * a new value. Some controllers don't seem to like this though.
1262 */
b8c86fc5 1263 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1264 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1265
e08c1694 1266 /*
c71f6512 1267 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1268 * and set turn on power at the same time, so set the voltage first.
1269 */
11a2f1b7 1270 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1271 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1272
ae628903 1273 pwr |= SDHCI_POWER_ON;
146ad66e 1274
ae628903 1275 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1276
f0710a55
AH		 1277 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1278 sdhci_runtime_pm_bus_on(host);
1279
557b0697
HW		 1280 /*
1281 * Some controllers need an extra 10ms delay of 10ms before they
1282 * can apply clock after applying power
1283 */
11a2f1b7 1284 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1285 mdelay(10);
ceb6143b
AH		 1286
1287 return power;
146ad66e
PO		 1288}
1289
d129bceb
PO		 1290/*****************************************************************************\
1291 * *
1292 * MMC callbacks *
1293 * *
1294\*****************************************************************************/
1295
1296static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1297{
1298 struct sdhci_host *host;
505a8680 1299 int present;
d129bceb 1300 unsigned long flags;
473b095a 1301 u32 tuning_opcode;
d129bceb
PO		 1302
1303 host = mmc_priv(mmc);
1304
66fd8ad5
AH		 1305 sdhci_runtime_pm_get(host);
1306
d129bceb
PO		 1307 spin_lock_irqsave(&host->lock, flags);
1308
1309 WARN_ON(host->mrq != NULL);
1310
f9134319 1311#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1312 sdhci_activate_led(host);
2f730fec 1313#endif
e89d456f
AW		 1314
1315 /*
1316 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1317 * requests if Auto-CMD12 is enabled.
1318 */
1319 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1320 if (mrq->stop) {
1321 mrq->data->stop = NULL;
1322 mrq->stop = NULL;
1323 }
1324 }
d129bceb
PO		 1325
1326 host->mrq = mrq;
1327
505a8680
SG		 1328 /*
1329 * Firstly check card presence from cd-gpio. The return could
1330 * be one of the following possibilities:
1331 * negative: cd-gpio is not available
1332 * zero: cd-gpio is used, and card is removed
1333 * one: cd-gpio is used, and card is present
1334 */
1335 present = mmc_gpio_get_cd(host->mmc);
1336 if (present < 0) {
1337 /* If polling, assume that the card is always present. */
1338 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1339 present = 1;
1340 else
1341 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1342 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1343 }
1344
68d1fb7e 1345 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1346 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1347 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1348 } else {
1349 u32 present_state;
1350
1351 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1352 /*
1353 * Check if the re-tuning timer has already expired and there
1354 * is no on-going data transfer. If so, we need to execute
1355 * tuning procedure before sending command.
1356 */
1357 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1358 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1359 if (mmc->card) {
1360 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1361 tuning_opcode =
1362 mmc->card->type == MMC_TYPE_MMC ?
1363 MMC_SEND_TUNING_BLOCK_HS200 :
1364 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1365
1366 /* Here we need to set the host->mrq to NULL,
1367 * in case the pending finish_tasklet
1368 * finishes it incorrectly.
1369 */
1370 host->mrq = NULL;
1371
14efd957
CB		 1372 spin_unlock_irqrestore(&host->lock, flags);
1373 sdhci_execute_tuning(mmc, tuning_opcode);
1374 spin_lock_irqsave(&host->lock, flags);
1375
1376 /* Restore original mmc_request structure */
1377 host->mrq = mrq;
1378 }
cf2b5eea
AN		 1379 }
1380
8edf6371 1381 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1382 sdhci_send_command(host, mrq->sbc);
1383 else
1384 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1385 }
d129bceb 1386
5f25a66f 1387 mmiowb();
d129bceb
PO		 1388 spin_unlock_irqrestore(&host->lock, flags);
1389}
1390
2317f56c
RK		 1391void sdhci_set_bus_width(struct sdhci_host *host, int width)
1392{
1393 u8 ctrl;
1394
1395 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1396 if (width == MMC_BUS_WIDTH_8) {
1397 ctrl &= ~SDHCI_CTRL_4BITBUS;
1398 if (host->version >= SDHCI_SPEC_300)
1399 ctrl |= SDHCI_CTRL_8BITBUS;
1400 } else {
1401 if (host->version >= SDHCI_SPEC_300)
1402 ctrl &= ~SDHCI_CTRL_8BITBUS;
1403 if (width == MMC_BUS_WIDTH_4)
1404 ctrl |= SDHCI_CTRL_4BITBUS;
1405 else
1406 ctrl &= ~SDHCI_CTRL_4BITBUS;
1407 }
1408 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1409}
1410EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1411
66fd8ad5 1412static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1413{
d129bceb 1414 unsigned long flags;
ceb6143b 1415 int vdd_bit = -1;
d129bceb
PO		 1416 u8 ctrl;
1417
d129bceb
PO		 1418 spin_lock_irqsave(&host->lock, flags);
1419
ceb6143b
AH		 1420 if (host->flags & SDHCI_DEVICE_DEAD) {
1421 spin_unlock_irqrestore(&host->lock, flags);
1422 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1423 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1424 return;
1425 }
1e72859e 1426
d129bceb
PO		 1427 /*
1428 * Reset the chip on each power off.
1429 * Should clear out any weird states.
1430 */
1431 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1432 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1433 sdhci_reinit(host);
d129bceb
PO		 1434 }
1435
52983382 1436 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1437 (ios->power_mode == MMC_POWER_UP) &&
1438 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1439 sdhci_enable_preset_value(host, false);
1440
373073ef 1441 if (!ios->clock || ios->clock != host->clock) {
91138ca5 1442 sdhci_set_clock(host, ios->clock);
373073ef
RK		 1443 host->clock = ios->clock;
1444 }
d129bceb
PO		 1445
1446 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1447 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1448 else
ceb6143b
AH		 1449 vdd_bit = sdhci_set_power(host, ios->vdd);
1450
1451 if (host->vmmc && vdd_bit != -1) {
1452 spin_unlock_irqrestore(&host->lock, flags);
1453 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1454 spin_lock_irqsave(&host->lock, flags);
1455 }
d129bceb 1456
643a81ff
PR		 1457 if (host->ops->platform_send_init_74_clocks)
1458 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1459
2317f56c 1460 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1461
15ec4461 1462 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1463
3ab9c8da
PR		 1464 if ((ios->timing == MMC_TIMING_SD_HS ||
1465 ios->timing == MMC_TIMING_MMC_HS)
1466 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1467 ctrl |= SDHCI_CTRL_HISPD;
1468 else
1469 ctrl &= ~SDHCI_CTRL_HISPD;
1470
d6d50a15 1471 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1472 u16 clk, ctrl_2;
49c468fc
AN		 1473
1474 /* In case of UHS-I modes, set High Speed Enable */
069c9f14 1475 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1476 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1477 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1478 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1479 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1480 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1481 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1482
1483 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1484 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1485 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1486 /*
1487 * We only need to set Driver Strength if the
1488 * preset value enable is not set.
1489 */
1490 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1491 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1492 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1493 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1494 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1495
1496 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1497 } else {
1498 /*
1499 * According to SDHC Spec v3.00, if the Preset Value
1500 * Enable in the Host Control 2 register is set, we
1501 * need to reset SD Clock Enable before changing High
1502 * Speed Enable to avoid generating clock gliches.
1503 */
758535c4
AN		 1504
1505 /* Reset SD Clock Enable */
1506 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1507 clk &= ~SDHCI_CLOCK_CARD_EN;
1508 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1509
1510 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1511
1512 /* Re-enable SD Clock */
91138ca5 1513 sdhci_set_clock(host, host->clock);
d6d50a15 1514 }
49c468fc 1515
49c468fc
AN		 1516
1517 /* Reset SD Clock Enable */
1518 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1519 clk &= ~SDHCI_CLOCK_CARD_EN;
1520 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1521
6322cdd0
PR		 1522 if (host->ops->set_uhs_signaling)
1523 host->ops->set_uhs_signaling(host, ios->timing);
1524 else {
1525 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1526 /* Select Bus Speed Mode for host */
1527 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
59911568
GC		 1528 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1529 (ios->timing == MMC_TIMING_UHS_SDR104))
1530 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
069c9f14 1531 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1532 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1533 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1534 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1535 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1536 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
bb8175a8
SJ		 1537 else if ((ios->timing == MMC_TIMING_UHS_DDR50) ||
1538 (ios->timing == MMC_TIMING_MMC_DDR52))
6322cdd0
PR		 1539 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1540 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1541 }
49c468fc 1542
52983382
KL		 1543 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1544 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1545 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1546 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1547 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1548 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1549 u16 preset;
1550
1551 sdhci_enable_preset_value(host, true);
1552 preset = sdhci_get_preset_value(host);
1553 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1554 >> SDHCI_PRESET_DRV_SHIFT;
1555 }
1556
49c468fc 1557 /* Re-enable SD Clock */
91138ca5 1558 sdhci_set_clock(host, host->clock);
758535c4
AN		 1559 } else
1560 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1561
b8352260
LD		 1562 /*
1563 * Some (ENE) controllers go apeshit on some ios operation,
1564 * signalling timeout and CRC errors even on CMD0. Resetting
1565 * it on each ios seems to solve the problem.
1566 */
b8c86fc5 1567 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1568 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1569
5f25a66f 1570 mmiowb();
d129bceb
PO		 1571 spin_unlock_irqrestore(&host->lock, flags);
1572}
1573
66fd8ad5
AH		 1574static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1575{
1576 struct sdhci_host *host = mmc_priv(mmc);
1577
1578 sdhci_runtime_pm_get(host);
1579 sdhci_do_set_ios(host, ios);
1580 sdhci_runtime_pm_put(host);
1581}
1582
94144a46
KL		 1583static int sdhci_do_get_cd(struct sdhci_host *host)
1584{
1585 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1586
1587 if (host->flags & SDHCI_DEVICE_DEAD)
1588 return 0;
1589
1590 /* If polling/nonremovable, assume that the card is always present. */
1591 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1592 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1593 return 1;
1594
1595 /* Try slot gpio detect */
1596 if (!IS_ERR_VALUE(gpio_cd))
1597 return !!gpio_cd;
1598
1599 /* Host native card detect */
1600 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1601}
1602
1603static int sdhci_get_cd(struct mmc_host *mmc)
1604{
1605 struct sdhci_host *host = mmc_priv(mmc);
1606 int ret;
1607
1608 sdhci_runtime_pm_get(host);
1609 ret = sdhci_do_get_cd(host);
1610 sdhci_runtime_pm_put(host);
1611 return ret;
1612}
1613
66fd8ad5 1614static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1615{
d129bceb 1616 unsigned long flags;
2dfb579c 1617 int is_readonly;
d129bceb 1618
d129bceb
PO		 1619 spin_lock_irqsave(&host->lock, flags);
1620
1e72859e 1621 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1622 is_readonly = 0;
1623 else if (host->ops->get_ro)
1624 is_readonly = host->ops->get_ro(host);
1e72859e 1625 else
2dfb579c
WS		 1626 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1627 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1628
1629 spin_unlock_irqrestore(&host->lock, flags);
1630
2dfb579c
WS		 1631 /* This quirk needs to be replaced by a callback-function later */
1632 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1633 !is_readonly : is_readonly;
d129bceb
PO		 1634}
1635
82b0e23a
TI		 1636#define SAMPLE_COUNT 5
1637
66fd8ad5 1638static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1639{
82b0e23a
TI		 1640 int i, ro_count;
1641
82b0e23a 1642 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1643 return sdhci_check_ro(host);
82b0e23a
TI		 1644
1645 ro_count = 0;
1646 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1647 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1648 if (++ro_count > SAMPLE_COUNT / 2)
1649 return 1;
1650 }
1651 msleep(30);
1652 }
1653 return 0;
1654}
1655
20758b66
AH		 1656static void sdhci_hw_reset(struct mmc_host *mmc)
1657{
1658 struct sdhci_host *host = mmc_priv(mmc);
1659
1660 if (host->ops && host->ops->hw_reset)
1661 host->ops->hw_reset(host);
1662}
1663
66fd8ad5 1664static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1665{
66fd8ad5
AH		 1666 struct sdhci_host *host = mmc_priv(mmc);
1667 int ret;
f75979b7 1668
66fd8ad5
AH		 1669 sdhci_runtime_pm_get(host);
1670 ret = sdhci_do_get_ro(host);
1671 sdhci_runtime_pm_put(host);
1672 return ret;
1673}
f75979b7 1674
66fd8ad5
AH		 1675static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1676{
be138554 1677 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1678 if (enable)
b537f94c 1679 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1680 else
b537f94c
RK		 1681 host->ier &= ~SDHCI_INT_CARD_INT;
1682
1683 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1684 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1685 mmiowb();
1686 }
66fd8ad5
AH		 1687}
1688
1689static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1690{
1691 struct sdhci_host *host = mmc_priv(mmc);
1692 unsigned long flags;
f75979b7 1693
ef104333
RK		 1694 sdhci_runtime_pm_get(host);
1695
66fd8ad5 1696 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1697 if (enable)
1698 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1699 else
1700 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1701
66fd8ad5 1702 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1703 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1704
1705 sdhci_runtime_pm_put(host);
f75979b7
PO		 1706}
1707
20b92a30 1708static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1709 struct mmc_ios *ios)
f2119df6 1710{
20b92a30 1711 u16 ctrl;
6231f3de 1712 int ret;
f2119df6 1713
20b92a30
KL		 1714 /*
1715 * Signal Voltage Switching is only applicable for Host Controllers
1716 * v3.00 and above.
1717 */
1718 if (host->version < SDHCI_SPEC_300)
1719 return 0;
6231f3de 1720
f2119df6 1721 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1722
21f5998f 1723 switch (ios->signal_voltage) {
20b92a30
KL		 1724 case MMC_SIGNAL_VOLTAGE_330:
1725 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1726 ctrl &= ~SDHCI_CTRL_VDD_180;
1727 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1728
20b92a30
KL		 1729 if (host->vqmmc) {
1730 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1731 if (ret) {
1732 pr_warning("%s: Switching to 3.3V signalling voltage "
1733 " failed\n", mmc_hostname(host->mmc));
1734 return -EIO;
1735 }
1736 }
1737 /* Wait for 5ms */
1738 usleep_range(5000, 5500);
f2119df6 1739
20b92a30
KL		 1740 /* 3.3V regulator output should be stable within 5 ms */
1741 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1742 if (!(ctrl & SDHCI_CTRL_VDD_180))
1743 return 0;
6231f3de 1744
20b92a30
KL		 1745 pr_warning("%s: 3.3V regulator output did not became stable\n",
1746 mmc_hostname(host->mmc));
1747
1748 return -EAGAIN;
1749 case MMC_SIGNAL_VOLTAGE_180:
1750 if (host->vqmmc) {
1751 ret = regulator_set_voltage(host->vqmmc,
1752 1700000, 1950000);
1753 if (ret) {
1754 pr_warning("%s: Switching to 1.8V signalling voltage "
1755 " failed\n", mmc_hostname(host->mmc));
1756 return -EIO;
1757 }
1758 }
6231f3de 1759
6231f3de
PR		 1760 /*
1761 * Enable 1.8V Signal Enable in the Host Control2
1762 * register
1763 */
20b92a30
KL		 1764 ctrl |= SDHCI_CTRL_VDD_180;
1765 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1766
20b92a30
KL		 1767 /* Wait for 5ms */
1768 usleep_range(5000, 5500);
f2119df6 1769
20b92a30
KL		 1770 /* 1.8V regulator output should be stable within 5 ms */
1771 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1772 if (ctrl & SDHCI_CTRL_VDD_180)
1773 return 0;
f2119df6 1774
20b92a30
KL		 1775 pr_warning("%s: 1.8V regulator output did not became stable\n",
1776 mmc_hostname(host->mmc));
f2119df6 1777
20b92a30
KL		 1778 return -EAGAIN;
1779 case MMC_SIGNAL_VOLTAGE_120:
1780 if (host->vqmmc) {
1781 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1782 if (ret) {
1783 pr_warning("%s: Switching to 1.2V signalling voltage "
1784 " failed\n", mmc_hostname(host->mmc));
1785 return -EIO;
f2119df6
AN		 1786 }
1787 }
6231f3de 1788 return 0;
20b92a30 1789 default:
f2119df6
AN		 1790 /* No signal voltage switch required */
1791 return 0;
20b92a30 1792 }
f2119df6
AN		 1793}
1794
66fd8ad5 1795static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1796 struct mmc_ios *ios)
66fd8ad5
AH		 1797{
1798 struct sdhci_host *host = mmc_priv(mmc);
1799 int err;
1800
1801 if (host->version < SDHCI_SPEC_300)
1802 return 0;
1803 sdhci_runtime_pm_get(host);
21f5998f 1804 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1805 sdhci_runtime_pm_put(host);
1806 return err;
1807}
1808
20b92a30
KL		 1809static int sdhci_card_busy(struct mmc_host *mmc)
1810{
1811 struct sdhci_host *host = mmc_priv(mmc);
1812 u32 present_state;
1813
1814 sdhci_runtime_pm_get(host);
1815 /* Check whether DAT[3:0] is 0000 */
1816 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1817 sdhci_runtime_pm_put(host);
1818
1819 return !(present_state & SDHCI_DATA_LVL_MASK);
1820}
1821
069c9f14 1822static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1823{
1824 struct sdhci_host *host;
1825 u16 ctrl;
b513ea25
AN		 1826 int tuning_loop_counter = MAX_TUNING_LOOP;
1827 unsigned long timeout;
1828 int err = 0;
069c9f14 1829 bool requires_tuning_nonuhs = false;
2b35bd83 1830 unsigned long flags;
b513ea25
AN		 1831
1832 host = mmc_priv(mmc);
1833
66fd8ad5 1834 sdhci_runtime_pm_get(host);
2b35bd83 1835 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1836
1837 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1838
1839 /*
069c9f14
G		 1840 * The Host Controller needs tuning only in case of SDR104 mode
1841 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1842 * Capabilities register.
069c9f14
G		 1843 * If the Host Controller supports the HS200 mode then the
1844 * tuning function has to be executed.
b513ea25 1845 */
069c9f14
G		 1846 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1847 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
156e14b1 1848 host->flags & SDHCI_SDR104_NEEDS_TUNING))
069c9f14
G		 1849 requires_tuning_nonuhs = true;
1850
b513ea25 1851 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1852 requires_tuning_nonuhs)
b513ea25
AN		 1853 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1854 else {
2b35bd83 1855 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 1856 sdhci_runtime_pm_put(host);
b513ea25
AN		 1857 return 0;
1858 }
1859
45251812 1860 if (host->ops->platform_execute_tuning) {
2b35bd83 1861 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1862 err = host->ops->platform_execute_tuning(host, opcode);
1863 sdhci_runtime_pm_put(host);
1864 return err;
1865 }
1866
b513ea25
AN		 1867 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1868
1869 /*
1870 * As per the Host Controller spec v3.00, tuning command
1871 * generates Buffer Read Ready interrupt, so enable that.
1872 *
1873 * Note: The spec clearly says that when tuning sequence
1874 * is being performed, the controller does not generate
1875 * interrupts other than Buffer Read Ready interrupt. But
1876 * to make sure we don't hit a controller bug, we _only_
1877 * enable Buffer Read Ready interrupt here.
1878 */
b537f94c
RK		 1879 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1880 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1881
1882 /*
1883 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1884 * of loops reaches 40 times or a timeout of 150ms occurs.
1885 */
1886 timeout = 150;
1887 do {
1888 struct mmc_command cmd = {0};
66fd8ad5 1889 struct mmc_request mrq = {NULL};
b513ea25
AN		 1890
1891 if (!tuning_loop_counter && !timeout)
1892 break;
1893
069c9f14 1894 cmd.opcode = opcode;
b513ea25
AN		 1895 cmd.arg = 0;
1896 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1897 cmd.retries = 0;
1898 cmd.data = NULL;
1899 cmd.error = 0;
1900
1901 mrq.cmd = &cmd;
1902 host->mrq = &mrq;
1903
1904 /*
1905 * In response to CMD19, the card sends 64 bytes of tuning
1906 * block to the Host Controller. So we set the block size
1907 * to 64 here.
1908 */
069c9f14
G		 1909 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1910 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1911 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1912 SDHCI_BLOCK_SIZE);
1913 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1914 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1915 SDHCI_BLOCK_SIZE);
1916 } else {
1917 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1918 SDHCI_BLOCK_SIZE);
1919 }
b513ea25
AN		 1920
1921 /*
1922 * The tuning block is sent by the card to the host controller.
1923 * So we set the TRNS_READ bit in the Transfer Mode register.
1924 * This also takes care of setting DMA Enable and Multi Block
1925 * Select in the same register to 0.
1926 */
1927 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1928
1929 sdhci_send_command(host, &cmd);
1930
1931 host->cmd = NULL;
1932 host->mrq = NULL;
1933
2b35bd83 1934 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1935 /* Wait for Buffer Read Ready interrupt */
1936 wait_event_interruptible_timeout(host->buf_ready_int,
1937 (host->tuning_done == 1),
1938 msecs_to_jiffies(50));
2b35bd83 1939 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1940
1941 if (!host->tuning_done) {
a3c76eb9 1942 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1943 "Buffer Read Ready interrupt during tuning "
1944 "procedure, falling back to fixed sampling "
1945 "clock\n");
1946 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1947 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1948 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1949 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1950
1951 err = -EIO;
1952 goto out;
1953 }
1954
1955 host->tuning_done = 0;
1956
1957 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1958 tuning_loop_counter--;
1959 timeout--;
197160d5
NS		 1960
1961 /* eMMC spec does not require a delay between tuning cycles */
1962 if (opcode == MMC_SEND_TUNING_BLOCK)
1963 mdelay(1);
b513ea25
AN		 1964 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1965
1966 /*
1967 * The Host Driver has exhausted the maximum number of loops allowed,
1968 * so use fixed sampling frequency.
1969 */
1970 if (!tuning_loop_counter || !timeout) {
1971 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1972 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
114f2bf6 1973 err = -EIO;
b513ea25
AN		 1974 } else {
1975 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1976 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1977 " failed, falling back to fixed sampling"
1978 " clock\n");
1979 err = -EIO;
1980 }
1981 }
1982
1983out:
cf2b5eea
AN		 1984 /*
1985 * If this is the very first time we are here, we start the retuning
1986 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1987 * flag won't be set, we check this condition before actually starting
1988 * the timer.
1989 */
1990 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1991 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 1992 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 1993 mod_timer(&host->tuning_timer, jiffies +
1994 host->tuning_count * HZ);
1995 /* Tuning mode 1 limits the maximum data length to 4MB */
1996 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2bc02485 1997 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
cf2b5eea
AN		 1998 host->flags &= ~SDHCI_NEEDS_RETUNING;
1999 /* Reload the new initial value for timer */
2bc02485
AS		 2000 mod_timer(&host->tuning_timer, jiffies +
2001 host->tuning_count * HZ);
cf2b5eea
AN		 2002 }
2003
2004 /*
2005 * In case tuning fails, host controllers which support re-tuning can
2006 * try tuning again at a later time, when the re-tuning timer expires.
2007 * So for these controllers, we return 0. Since there might be other
2008 * controllers who do not have this capability, we return error for
973905fe
AL		 2009 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2010 * a retuning timer to do the retuning for the card.
cf2b5eea 2011 */
973905fe 2012 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2013 err = 0;
2014
b537f94c
RK		 2015 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2016 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2b35bd83 2017 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2018 sdhci_runtime_pm_put(host);
b513ea25
AN		 2019
2020 return err;
2021}
2022
52983382
KL		 2023
2024static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2025{
4d55c5a1 2026 u16 ctrl;
4d55c5a1 2027
4d55c5a1
AN		 2028 /* Host Controller v3.00 defines preset value registers */
2029 if (host->version < SDHCI_SPEC_300)
2030 return;
2031
4d55c5a1
AN		 2032 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2033
2034 /*
2035 * We only enable or disable Preset Value if they are not already
2036 * enabled or disabled respectively. Otherwise, we bail out.
2037 */
2038 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2039 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2040 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2041 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 2042 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2043 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2044 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2045 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1 2046 }
66fd8ad5
AH		 2047}
2048
71e69211 2049static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2050{
71e69211 2051 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2052 unsigned long flags;
2053
722e1280
CD		 2054 /* First check if client has provided their own card event */
2055 if (host->ops->card_event)
2056 host->ops->card_event(host);
2057
d129bceb
PO		 2058 spin_lock_irqsave(&host->lock, flags);
2059
66fd8ad5 2060 /* Check host->mrq first in case we are runtime suspended */
9668d765 2061 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2062 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2063 mmc_hostname(host->mmc));
a3c76eb9 2064 pr_err("%s: Resetting controller.\n",
66fd8ad5 2065 mmc_hostname(host->mmc));
d129bceb 2066
03231f9b
RK		 2067 sdhci_do_reset(host, SDHCI_RESET_CMD);
2068 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2069
66fd8ad5
AH		 2070 host->mrq->cmd->error = -ENOMEDIUM;
2071 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2072 }
2073
2074 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2075}
2076
2077static const struct mmc_host_ops sdhci_ops = {
2078 .request = sdhci_request,
2079 .set_ios = sdhci_set_ios,
94144a46 2080 .get_cd = sdhci_get_cd,
71e69211
GL		 2081 .get_ro = sdhci_get_ro,
2082 .hw_reset = sdhci_hw_reset,
2083 .enable_sdio_irq = sdhci_enable_sdio_irq,
2084 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2085 .execute_tuning = sdhci_execute_tuning,
71e69211 2086 .card_event = sdhci_card_event,
20b92a30 2087 .card_busy = sdhci_card_busy,
71e69211
GL		 2088};
2089
2090/*****************************************************************************\
2091 * *
2092 * Tasklets *
2093 * *
2094\*****************************************************************************/
2095
d129bceb
PO		 2096static void sdhci_tasklet_finish(unsigned long param)
2097{
2098 struct sdhci_host *host;
2099 unsigned long flags;
2100 struct mmc_request *mrq;
2101
2102 host = (struct sdhci_host*)param;
2103
66fd8ad5
AH		 2104 spin_lock_irqsave(&host->lock, flags);
2105
0c9c99a7
CB		 2106 /*
2107 * If this tasklet gets rescheduled while running, it will
2108 * be run again afterwards but without any active request.
2109 */
66fd8ad5
AH		 2110 if (!host->mrq) {
2111 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2112 return;
66fd8ad5 2113 }
d129bceb
PO		 2114
2115 del_timer(&host->timer);
2116
2117 mrq = host->mrq;
2118
d129bceb
PO		 2119 /*
2120 * The controller needs a reset of internal state machines
2121 * upon error conditions.
2122 */
1e72859e 2123 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2124 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2125 (mrq->data && (mrq->data->error ||
2126 (mrq->data->stop && mrq->data->stop->error))) ||
2127 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2128
2129 /* Some controllers need this kick or reset won't work here */
8213af3b 2130 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2131 /* This is to force an update */
91138ca5 2132 sdhci_set_clock(host, host->clock);
645289dc
PO		 2133
2134 /* Spec says we should do both at the same time, but Ricoh
2135 controllers do not like that. */
03231f9b
RK		 2136 sdhci_do_reset(host, SDHCI_RESET_CMD);
2137 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2138 }
2139
2140 host->mrq = NULL;
2141 host->cmd = NULL;
2142 host->data = NULL;
2143
f9134319 2144#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2145 sdhci_deactivate_led(host);
2f730fec 2146#endif
d129bceb 2147
5f25a66f 2148 mmiowb();
d129bceb
PO		 2149 spin_unlock_irqrestore(&host->lock, flags);
2150
2151 mmc_request_done(host->mmc, mrq);
66fd8ad5 2152 sdhci_runtime_pm_put(host);
d129bceb
PO		 2153}
2154
2155static void sdhci_timeout_timer(unsigned long data)
2156{
2157 struct sdhci_host *host;
2158 unsigned long flags;
2159
2160 host = (struct sdhci_host*)data;
2161
2162 spin_lock_irqsave(&host->lock, flags);
2163
2164 if (host->mrq) {
a3c76eb9 2165 pr_err("%s: Timeout waiting for hardware "
acf1da45 2166 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2167 sdhci_dumpregs(host);
2168
2169 if (host->data) {
17b0429d 2170 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2171 sdhci_finish_data(host);
2172 } else {
2173 if (host->cmd)
17b0429d 2174 host->cmd->error = -ETIMEDOUT;
d129bceb 2175 else
17b0429d 2176 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2177
2178 tasklet_schedule(&host->finish_tasklet);
2179 }
2180 }
2181
5f25a66f 2182 mmiowb();
d129bceb
PO		 2183 spin_unlock_irqrestore(&host->lock, flags);
2184}
2185
cf2b5eea
AN		 2186static void sdhci_tuning_timer(unsigned long data)
2187{
2188 struct sdhci_host *host;
2189 unsigned long flags;
2190
2191 host = (struct sdhci_host *)data;
2192
2193 spin_lock_irqsave(&host->lock, flags);
2194
2195 host->flags |= SDHCI_NEEDS_RETUNING;
2196
2197 spin_unlock_irqrestore(&host->lock, flags);
2198}
2199
d129bceb
PO		 2200/*****************************************************************************\
2201 * *
2202 * Interrupt handling *
2203 * *
2204\*****************************************************************************/
2205
2206static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2207{
2208 BUG_ON(intmask == 0);
2209
2210 if (!host->cmd) {
a3c76eb9 2211 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2212 "though no command operation was in progress.\n",
2213 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2214 sdhci_dumpregs(host);
2215 return;
2216 }
2217
43b58b36 2218 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2219 host->cmd->error = -ETIMEDOUT;
2220 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2221 SDHCI_INT_INDEX))
2222 host->cmd->error = -EILSEQ;
43b58b36 2223
e809517f 2224 if (host->cmd->error) {
d129bceb 2225 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2226 return;
2227 }
2228
2229 /*
2230 * The host can send and interrupt when the busy state has
2231 * ended, allowing us to wait without wasting CPU cycles.
2232 * Unfortunately this is overloaded on the "data complete"
2233 * interrupt, so we need to take some care when handling
2234 * it.
2235 *
2236 * Note: The 1.0 specification is a bit ambiguous about this
2237 * feature so there might be some problems with older
2238 * controllers.
2239 */
2240 if (host->cmd->flags & MMC_RSP_BUSY) {
2241 if (host->cmd->data)
2242 DBG("Cannot wait for busy signal when also "
2243 "doing a data transfer");
f945405c 2244 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2245 return;
f945405c
BD		 2246
2247 /* The controller does not support the end-of-busy IRQ,
2248 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2249 }
2250
2251 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2252 sdhci_finish_command(host);
d129bceb
PO		 2253}
2254
0957c333 2255#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2256static void sdhci_show_adma_error(struct sdhci_host *host)
2257{
2258 const char *name = mmc_hostname(host->mmc);
2259 u8 *desc = host->adma_desc;
2260 __le32 *dma;
2261 __le16 *len;
2262 u8 attr;
2263
2264 sdhci_dumpregs(host);
2265
2266 while (true) {
2267 dma = (__le32 *)(desc + 4);
2268 len = (__le16 *)(desc + 2);
2269 attr = *desc;
2270
2271 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2272 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2273
2274 desc += 8;
2275
2276 if (attr & 2)
2277 break;
2278 }
2279}
2280#else
2281static void sdhci_show_adma_error(struct sdhci_host *host) { }
2282#endif
2283
d129bceb
PO		 2284static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2285{
069c9f14 2286 u32 command;
d129bceb
PO		 2287 BUG_ON(intmask == 0);
2288
b513ea25
AN		 2289 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2290 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2291 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2292 if (command == MMC_SEND_TUNING_BLOCK ||
2293 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2294 host->tuning_done = 1;
2295 wake_up(&host->buf_ready_int);
2296 return;
2297 }
2298 }
2299
d129bceb
PO		 2300 if (!host->data) {
2301 /*
e809517f
PO		 2302 * The "data complete" interrupt is also used to
2303 * indicate that a busy state has ended. See comment
2304 * above in sdhci_cmd_irq().
d129bceb 2305 */
e809517f
PO		 2306 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2307 if (intmask & SDHCI_INT_DATA_END) {
2308 sdhci_finish_command(host);
2309 return;
2310 }
2311 }
d129bceb 2312
a3c76eb9 2313 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2314 "though no data operation was in progress.\n",
2315 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2316 sdhci_dumpregs(host);
2317
2318 return;
2319 }
2320
2321 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2322 host->data->error = -ETIMEDOUT;
22113efd
AL		 2323 else if (intmask & SDHCI_INT_DATA_END_BIT)
2324 host->data->error = -EILSEQ;
2325 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2326 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2327 != MMC_BUS_TEST_R)
17b0429d 2328 host->data->error = -EILSEQ;
6882a8c0 2329 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2330 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2331 sdhci_show_adma_error(host);
2134a922 2332 host->data->error = -EIO;
a4071fbb
HZ		 2333 if (host->ops->adma_workaround)
2334 host->ops->adma_workaround(host, intmask);
6882a8c0 2335 }
d129bceb 2336
17b0429d 2337 if (host->data->error)
d129bceb
PO		 2338 sdhci_finish_data(host);
2339 else {
a406f5a3 2340 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2341 sdhci_transfer_pio(host);
2342
6ba736a1
PO		 2343 /*
2344 * We currently don't do anything fancy with DMA
2345 * boundaries, but as we can't disable the feature
2346 * we need to at least restart the transfer.
f6a03cbf
MV		 2347 *
2348 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2349 * should return a valid address to continue from, but as
2350 * some controllers are faulty, don't trust them.
6ba736a1 2351 */
f6a03cbf
MV		 2352 if (intmask & SDHCI_INT_DMA_END) {
2353 u32 dmastart, dmanow;
2354 dmastart = sg_dma_address(host->data->sg);
2355 dmanow = dmastart + host->data->bytes_xfered;
2356 /*
2357 * Force update to the next DMA block boundary.
2358 */
2359 dmanow = (dmanow &
2360 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2361 SDHCI_DEFAULT_BOUNDARY_SIZE;
2362 host->data->bytes_xfered = dmanow - dmastart;
2363 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2364 " next 0x%08x\n",
2365 mmc_hostname(host->mmc), dmastart,
2366 host->data->bytes_xfered, dmanow);
2367 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2368 }
6ba736a1 2369
e538fbe8
PO		 2370 if (intmask & SDHCI_INT_DATA_END) {
2371 if (host->cmd) {
2372 /*
2373 * Data managed to finish before the
2374 * command completed. Make sure we do
2375 * things in the proper order.
2376 */
2377 host->data_early = 1;
2378 } else {
2379 sdhci_finish_data(host);
2380 }
2381 }
d129bceb
PO		 2382 }
2383}
2384
7d12e780 2385static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2386{
781e989c 2387 irqreturn_t result = IRQ_NONE;
66fd8ad5 2388 struct sdhci_host *host = dev_id;
41005003 2389 u32 intmask, mask, unexpected = 0;
781e989c 2390 int max_loops = 16;
d129bceb
PO		 2391
2392 spin_lock(&host->lock);
2393
be138554 2394 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2395 spin_unlock(&host->lock);
655bca76 2396 return IRQ_NONE;
66fd8ad5
AH		 2397 }
2398
4e4141a5 2399 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2400 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2401 result = IRQ_NONE;
2402 goto out;
2403 }
2404
41005003
RK		 2405 do {
2406 /* Clear selected interrupts. */
2407 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2408 SDHCI_INT_BUS_POWER);
2409 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2410
41005003
RK		 2411 DBG("*** %s got interrupt: 0x%08x\n",
2412 mmc_hostname(host->mmc), intmask);
d129bceb 2413
41005003
RK		 2414 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2415 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2416 SDHCI_CARD_PRESENT;
d129bceb 2417
41005003
RK		 2418 /*
2419 * There is a observation on i.mx esdhc. INSERT
2420 * bit will be immediately set again when it gets
2421 * cleared, if a card is inserted. We have to mask
2422 * the irq to prevent interrupt storm which will
2423 * freeze the system. And the REMOVE gets the
2424 * same situation.
2425 *
2426 * More testing are needed here to ensure it works
2427 * for other platforms though.
2428 */
b537f94c
RK		 2429 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2430 SDHCI_INT_CARD_REMOVE);
2431 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2432 SDHCI_INT_CARD_INSERT;
2433 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2434 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2435
2436 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2437 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2438
2439 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2440 SDHCI_INT_CARD_REMOVE);
2441 result = IRQ_WAKE_THREAD;
41005003 2442 }
d129bceb 2443
41005003
RK		 2444 if (intmask & SDHCI_INT_CMD_MASK)
2445 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
964f9ce2 2446
41005003
RK		 2447 if (intmask & SDHCI_INT_DATA_MASK)
2448 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2449
41005003
RK		 2450 if (intmask & SDHCI_INT_BUS_POWER)
2451 pr_err("%s: Card is consuming too much power!\n",
2452 mmc_hostname(host->mmc));
3192a28f 2453
781e989c
RK		 2454 if (intmask & SDHCI_INT_CARD_INT) {
2455 sdhci_enable_sdio_irq_nolock(host, false);
2456 host->thread_isr |= SDHCI_INT_CARD_INT;
2457 result = IRQ_WAKE_THREAD;
2458 }
f75979b7 2459
41005003
RK		 2460 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2461 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2462 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2463 SDHCI_INT_CARD_INT);
f75979b7 2464
41005003
RK		 2465 if (intmask) {
2466 unexpected |= intmask;
2467 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2468 }
d129bceb 2469
781e989c
RK		 2470 if (result == IRQ_NONE)
2471 result = IRQ_HANDLED;
d129bceb 2472
41005003 2473 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2474 } while (intmask && --max_loops);
d129bceb
PO		 2475out:
2476 spin_unlock(&host->lock);
2477
6379b237
AS		 2478 if (unexpected) {
2479 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2480 mmc_hostname(host->mmc), unexpected);
2481 sdhci_dumpregs(host);
2482 }
f75979b7 2483
d129bceb
PO		 2484 return result;
2485}
2486
781e989c
RK		 2487static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2488{
2489 struct sdhci_host *host = dev_id;
2490 unsigned long flags;
2491 u32 isr;
2492
2493 spin_lock_irqsave(&host->lock, flags);
2494 isr = host->thread_isr;
2495 host->thread_isr = 0;
2496 spin_unlock_irqrestore(&host->lock, flags);
2497
3560db8e
RK		 2498 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2499 sdhci_card_event(host->mmc);
2500 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2501 }
2502
781e989c
RK		 2503 if (isr & SDHCI_INT_CARD_INT) {
2504 sdio_run_irqs(host->mmc);
2505
2506 spin_lock_irqsave(&host->lock, flags);
2507 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2508 sdhci_enable_sdio_irq_nolock(host, true);
2509 spin_unlock_irqrestore(&host->lock, flags);
2510 }
2511
2512 return isr ? IRQ_HANDLED : IRQ_NONE;
2513}
2514
d129bceb
PO		 2515/*****************************************************************************\
2516 * *
2517 * Suspend/resume *
2518 * *
2519\*****************************************************************************/
2520
2521#ifdef CONFIG_PM
ad080d79
KL		 2522void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2523{
2524 u8 val;
2525 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2526 | SDHCI_WAKE_ON_INT;
2527
2528 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2529 val |= mask ;
2530 /* Avoid fake wake up */
2531 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2532 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2533 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2534}
2535EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2536
2537void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2538{
2539 u8 val;
2540 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2541 | SDHCI_WAKE_ON_INT;
2542
2543 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2544 val &= ~mask;
2545 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2546}
2547EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2548
29495aa0 2549int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2550{
a1b13b4e
CB		 2551 if (host->ops->platform_suspend)
2552 host->ops->platform_suspend(host);
2553
7260cf5e
AV		 2554 sdhci_disable_card_detection(host);
2555
cf2b5eea 2556 /* Disable tuning since we are suspending */
973905fe 2557 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2558 del_timer_sync(&host->tuning_timer);
cf2b5eea 2559 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2560 }
2561
ad080d79 2562 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2563 host->ier = 0;
2564 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2565 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2566 free_irq(host->irq, host);
2567 } else {
2568 sdhci_enable_irq_wakeups(host);
2569 enable_irq_wake(host->irq);
2570 }
4ee14ec6 2571 return 0;
d129bceb
PO		 2572}
2573
b8c86fc5 2574EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2575
b8c86fc5
PO		 2576int sdhci_resume_host(struct sdhci_host *host)
2577{
4ee14ec6 2578 int ret = 0;
d129bceb 2579
a13abc7b 2580 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2581 if (host->ops->enable_dma)
2582 host->ops->enable_dma(host);
2583 }
d129bceb 2584
ad080d79 2585 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2586 ret = request_threaded_irq(host->irq, sdhci_irq,
2587 sdhci_thread_irq, IRQF_SHARED,
2588 mmc_hostname(host->mmc), host);
ad080d79
KL		 2589 if (ret)
2590 return ret;
2591 } else {
2592 sdhci_disable_irq_wakeups(host);
2593 disable_irq_wake(host->irq);
2594 }
d129bceb 2595
6308d290
AH		 2596 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2597 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2598 /* Card keeps power but host controller does not */
2599 sdhci_init(host, 0);
2600 host->pwr = 0;
2601 host->clock = 0;
2602 sdhci_do_set_ios(host, &host->mmc->ios);
2603 } else {
2604 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2605 mmiowb();
2606 }
b8c86fc5 2607
7260cf5e
AV		 2608 sdhci_enable_card_detection(host);
2609
a1b13b4e
CB		 2610 if (host->ops->platform_resume)
2611 host->ops->platform_resume(host);
2612
cf2b5eea 2613 /* Set the re-tuning expiration flag */
973905fe 2614 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2615 host->flags |= SDHCI_NEEDS_RETUNING;
2616
2f4cbb3d 2617 return ret;
d129bceb
PO		 2618}
2619
b8c86fc5 2620EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2621#endif /* CONFIG_PM */
2622
66fd8ad5
AH		 2623#ifdef CONFIG_PM_RUNTIME
2624
2625static int sdhci_runtime_pm_get(struct sdhci_host *host)
2626{
2627 return pm_runtime_get_sync(host->mmc->parent);
2628}
2629
2630static int sdhci_runtime_pm_put(struct sdhci_host *host)
2631{
2632 pm_runtime_mark_last_busy(host->mmc->parent);
2633 return pm_runtime_put_autosuspend(host->mmc->parent);
2634}
2635
f0710a55
AH		 2636static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2637{
2638 if (host->runtime_suspended || host->bus_on)
2639 return;
2640 host->bus_on = true;
2641 pm_runtime_get_noresume(host->mmc->parent);
2642}
2643
2644static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2645{
2646 if (host->runtime_suspended || !host->bus_on)
2647 return;
2648 host->bus_on = false;
2649 pm_runtime_put_noidle(host->mmc->parent);
2650}
2651
66fd8ad5
AH		 2652int sdhci_runtime_suspend_host(struct sdhci_host *host)
2653{
2654 unsigned long flags;
2655 int ret = 0;
2656
2657 /* Disable tuning since we are suspending */
973905fe 2658 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2659 del_timer_sync(&host->tuning_timer);
2660 host->flags &= ~SDHCI_NEEDS_RETUNING;
2661 }
2662
2663 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2664 host->ier &= SDHCI_INT_CARD_INT;
2665 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2666 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2667 spin_unlock_irqrestore(&host->lock, flags);
2668
781e989c 2669 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2670
2671 spin_lock_irqsave(&host->lock, flags);
2672 host->runtime_suspended = true;
2673 spin_unlock_irqrestore(&host->lock, flags);
2674
2675 return ret;
2676}
2677EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2678
2679int sdhci_runtime_resume_host(struct sdhci_host *host)
2680{
2681 unsigned long flags;
2682 int ret = 0, host_flags = host->flags;
2683
2684 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2685 if (host->ops->enable_dma)
2686 host->ops->enable_dma(host);
2687 }
2688
2689 sdhci_init(host, 0);
2690
2691 /* Force clock and power re-program */
2692 host->pwr = 0;
2693 host->clock = 0;
2694 sdhci_do_set_ios(host, &host->mmc->ios);
2695
2696 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2697 if ((host_flags & SDHCI_PV_ENABLED) &&
2698 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2699 spin_lock_irqsave(&host->lock, flags);
2700 sdhci_enable_preset_value(host, true);
2701 spin_unlock_irqrestore(&host->lock, flags);
2702 }
66fd8ad5
AH		 2703
2704 /* Set the re-tuning expiration flag */
973905fe 2705 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2706 host->flags |= SDHCI_NEEDS_RETUNING;
2707
2708 spin_lock_irqsave(&host->lock, flags);
2709
2710 host->runtime_suspended = false;
2711
2712 /* Enable SDIO IRQ */
ef104333 2713 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2714 sdhci_enable_sdio_irq_nolock(host, true);
2715
2716 /* Enable Card Detection */
2717 sdhci_enable_card_detection(host);
2718
2719 spin_unlock_irqrestore(&host->lock, flags);
2720
2721 return ret;
2722}
2723EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2724
2725#endif
2726
d129bceb
PO		 2727/*****************************************************************************\
2728 * *
b8c86fc5 2729 * Device allocation/registration *
d129bceb
PO		 2730 * *
2731\*****************************************************************************/
2732
b8c86fc5
PO		 2733struct sdhci_host *sdhci_alloc_host(struct device *dev,
2734 size_t priv_size)
d129bceb 2735{
d129bceb
PO		 2736 struct mmc_host *mmc;
2737 struct sdhci_host *host;
2738
b8c86fc5 2739 WARN_ON(dev == NULL);
d129bceb 2740
b8c86fc5 2741 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2742 if (!mmc)
b8c86fc5 2743 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2744
2745 host = mmc_priv(mmc);
2746 host->mmc = mmc;
2747
b8c86fc5
PO		 2748 return host;
2749}
8a4da143 2750
b8c86fc5 2751EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2752
b8c86fc5
PO		 2753int sdhci_add_host(struct sdhci_host *host)
2754{
2755 struct mmc_host *mmc;
bd6a8c30 2756 u32 caps[2] = {0, 0};
f2119df6
AN		 2757 u32 max_current_caps;
2758 unsigned int ocr_avail;
b8c86fc5 2759 int ret;
d129bceb 2760
b8c86fc5
PO		 2761 WARN_ON(host == NULL);
2762 if (host == NULL)
2763 return -EINVAL;
d129bceb 2764
b8c86fc5 2765 mmc = host->mmc;
d129bceb 2766
b8c86fc5
PO		 2767 if (debug_quirks)
2768 host->quirks = debug_quirks;
66fd8ad5
AH		 2769 if (debug_quirks2)
2770 host->quirks2 = debug_quirks2;
d129bceb 2771
03231f9b 2772 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2773
4e4141a5 2774 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2775 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2776 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2777 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2778 pr_err("%s: Unknown controller version (%d). "
b69c9058 2779 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2780 host->version);
4a965505
PO		 2781 }
2782
f2119df6 2783 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2784 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2785
bd6a8c30
PR		 2786 if (host->version >= SDHCI_SPEC_300)
2787 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2788 host->caps1 :
2789 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2790
b8c86fc5 2791 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2792 host->flags |= SDHCI_USE_SDMA;
f2119df6 2793 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2794 DBG("Controller doesn't have SDMA capability\n");
67435274 2795 else
a13abc7b 2796 host->flags |= SDHCI_USE_SDMA;
d129bceb 2797
b8c86fc5 2798 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2799 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2800 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2801 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2802 }
2803
f2119df6
AN		 2804 if ((host->version >= SDHCI_SPEC_200) &&
2805 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2806 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2807
2808 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2809 (host->flags & SDHCI_USE_ADMA)) {
2810 DBG("Disabling ADMA as it is marked broken\n");
2811 host->flags &= ~SDHCI_USE_ADMA;
2812 }
2813
a13abc7b 2814 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2815 if (host->ops->enable_dma) {
2816 if (host->ops->enable_dma(host)) {
a3c76eb9 2817 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2818 "available. Falling back to PIO.\n",
2819 mmc_hostname(mmc));
a13abc7b
RR		 2820 host->flags &=
2821 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2822 }
d129bceb
PO		 2823 }
2824 }
2825
2134a922
PO		 2826 if (host->flags & SDHCI_USE_ADMA) {
2827 /*
2828 * We need to allocate descriptors for all sg entries
2829 * (128) and potentially one alignment transfer for
2830 * each of those entries.
2831 */
d1e49f77
RK		 2832 host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc),
2833 ADMA_SIZE, &host->adma_addr,
2834 GFP_KERNEL);
2134a922
PO		 2835 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2836 if (!host->adma_desc || !host->align_buffer) {
d1e49f77
RK		 2837 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2838 host->adma_desc, host->adma_addr);
2134a922 2839 kfree(host->align_buffer);
a3c76eb9 2840 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2841 "buffers. Falling back to standard DMA.\n",
2842 mmc_hostname(mmc));
2843 host->flags &= ~SDHCI_USE_ADMA;
d1e49f77
RK		 2844 host->adma_desc = NULL;
2845 host->align_buffer = NULL;
2846 } else if (host->adma_addr & 3) {
2847 pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2848 mmc_hostname(mmc));
2849 host->flags &= ~SDHCI_USE_ADMA;
2850 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2851 host->adma_desc, host->adma_addr);
2852 kfree(host->align_buffer);
2853 host->adma_desc = NULL;
2854 host->align_buffer = NULL;
2134a922
PO		 2855 }
2856 }
2857
7659150c
PO		 2858 /*
2859 * If we use DMA, then it's up to the caller to set the DMA
2860 * mask, but PIO does not need the hw shim so we set a new
2861 * mask here in that case.
2862 */
a13abc7b 2863 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2864 host->dma_mask = DMA_BIT_MASK(64);
2865 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2866 }
d129bceb 2867
c4687d5f 2868 if (host->version >= SDHCI_SPEC_300)
f2119df6 2869 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2870 >> SDHCI_CLOCK_BASE_SHIFT;
2871 else
f2119df6 2872 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2873 >> SDHCI_CLOCK_BASE_SHIFT;
2874
4240ff0a 2875 host->max_clk *= 1000000;
f27f47ef
AV		 2876 if (host->max_clk == 0 || host->quirks &
2877 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2878 if (!host->ops->get_max_clock) {
a3c76eb9 2879 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2880 "frequency.\n", mmc_hostname(mmc));
2881 return -ENODEV;
2882 }
2883 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2884 }
d129bceb 2885
c3ed3877
AN		 2886 /*
2887 * In case of Host Controller v3.00, find out whether clock
2888 * multiplier is supported.
2889 */
2890 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2891 SDHCI_CLOCK_MUL_SHIFT;
2892
2893 /*
2894 * In case the value in Clock Multiplier is 0, then programmable
2895 * clock mode is not supported, otherwise the actual clock
2896 * multiplier is one more than the value of Clock Multiplier
2897 * in the Capabilities Register.
2898 */
2899 if (host->clk_mul)
2900 host->clk_mul += 1;
2901
d129bceb
PO		 2902 /*
2903 * Set host parameters.
2904 */
2905 mmc->ops = &sdhci_ops;
c3ed3877 2906 mmc->f_max = host->max_clk;
ce5f036b 2907 if (host->ops->get_min_clock)
a9e58f25 2908 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2909 else if (host->version >= SDHCI_SPEC_300) {
2910 if (host->clk_mul) {
2911 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2912 mmc->f_max = host->max_clk * host->clk_mul;
2913 } else
2914 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2915 } else
0397526d 2916 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2917
272308ca
AS		 2918 host->timeout_clk =
2919 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2920 if (host->timeout_clk == 0) {
2921 if (host->ops->get_timeout_clock) {
2922 host->timeout_clk = host->ops->get_timeout_clock(host);
2923 } else if (!(host->quirks &
2924 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2925 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2926 "frequency.\n", mmc_hostname(mmc));
2927 return -ENODEV;
2928 }
2929 }
2930 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2931 host->timeout_clk *= 1000;
2932
2933 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2934 host->timeout_clk = mmc->f_max / 1000;
272308ca 2935
68eb80e0 2936 mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
58d1246d 2937
e89d456f 2938 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 2939 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 2940
2941 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2942 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2943
8edf6371 2944 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2945 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2946 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2947 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2948 host->flags |= SDHCI_AUTO_CMD23;
2949 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2950 } else {
2951 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2952 }
2953
15ec4461
PR		 2954 /*
2955 * A controller may support 8-bit width, but the board itself
2956 * might not have the pins brought out. Boards that support
2957 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2958 * their platform code before calling sdhci_add_host(), and we
2959 * won't assume 8-bit width for hosts without that CAP.
2960 */
5fe23c7f 2961 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2962 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2963
63ef5d8c
JH		 2964 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2965 mmc->caps &= ~MMC_CAP_CMD23;
2966
f2119df6 2967 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2968 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2969
176d1ed4 2970 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2971 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2972 mmc->caps |= MMC_CAP_NEEDS_POLL;
2973
6231f3de 2974 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
462849aa 2975 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2976 if (IS_ERR_OR_NULL(host->vqmmc)) {
2977 if (PTR_ERR(host->vqmmc) < 0) {
2978 pr_info("%s: no vqmmc regulator found\n",
2979 mmc_hostname(mmc));
2980 host->vqmmc = NULL;
2981 }
8363c374 2982 } else {
a3361aba 2983 ret = regulator_enable(host->vqmmc);
cec2e216
KL		 2984 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2985 1950000))
8363c374
KL		 2986 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2987 SDHCI_SUPPORT_SDR50 |
2988 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 2989 if (ret) {
2990 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2991 mmc_hostname(mmc), ret);
2992 host->vqmmc = NULL;
2993 }
8363c374 2994 }
6231f3de 2995
6a66180a
DD		 2996 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2997 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2998 SDHCI_SUPPORT_DDR50);
2999
4188bba0
AC		 3000 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3001 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3002 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3003 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3004
3005 /* SDR104 supports also implies SDR50 support */
156e14b1 3006 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3007 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3008 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3009 * field can be promoted to support HS200.
3010 */
13868bf2
DC		 3011 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3012 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3013 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3014 mmc->caps |= MMC_CAP_UHS_SDR50;
3015
9107ebbf
MC		 3016 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3017 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3018 mmc->caps |= MMC_CAP_UHS_DDR50;
3019
069c9f14 3020 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3021 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3022 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3023
156e14b1 3024 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3025 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3026 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3027
d6d50a15
AN		 3028 /* Driver Type(s) (A, C, D) supported by the host */
3029 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3030 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3031 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3032 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3033 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3034 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3035
cf2b5eea
AN		 3036 /* Initial value for re-tuning timer count */
3037 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3038 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3039
3040 /*
3041 * In case Re-tuning Timer is not disabled, the actual value of
3042 * re-tuning timer will be 2 ^ (n - 1).
3043 */
3044 if (host->tuning_count)
3045 host->tuning_count = 1 << (host->tuning_count - 1);
3046
3047 /* Re-tuning mode supported by the Host Controller */
3048 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3049 SDHCI_RETUNING_MODE_SHIFT;
3050
8f230f45 3051 ocr_avail = 0;
bad37e1a 3052
462849aa 3053 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
657d5982
KL		 3054 if (IS_ERR_OR_NULL(host->vmmc)) {
3055 if (PTR_ERR(host->vmmc) < 0) {
3056 pr_info("%s: no vmmc regulator found\n",
3057 mmc_hostname(mmc));
3058 host->vmmc = NULL;
3059 }
8363c374 3060 }
bad37e1a 3061
68737043 3062#ifdef CONFIG_REGULATOR
a4f8f257
MS		 3063 /*
3064 * Voltage range check makes sense only if regulator reports
3065 * any voltage value.
3066 */
3067 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
cec2e216
KL		 3068 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3069 3600000);
68737043
PR		 3070 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3071 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 3072 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3073 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 3074 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3075 1950000);
68737043
PR		 3076 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3077 caps[0] &= ~SDHCI_CAN_VDD_180;
3078 }
3079#endif /* CONFIG_REGULATOR */
3080
f2119df6
AN		 3081 /*
3082 * According to SD Host Controller spec v3.00, if the Host System
3083 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3084 * the value is meaningful only if Voltage Support in the Capabilities
3085 * register is set. The actual current value is 4 times the register
3086 * value.
3087 */
3088 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 3089 if (!max_current_caps && host->vmmc) {
3090 u32 curr = regulator_get_current_limit(host->vmmc);
3091 if (curr > 0) {
3092
3093 /* convert to SDHCI_MAX_CURRENT format */
3094 curr = curr/1000; /* convert to mA */
3095 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3096
3097 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3098 max_current_caps =
3099 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3100 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3101 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3102 }
3103 }
f2119df6
AN		 3104
3105 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3106 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3107
55c4665e 3108 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3109 SDHCI_MAX_CURRENT_330_MASK) >>
3110 SDHCI_MAX_CURRENT_330_SHIFT) *
3111 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3112 }
3113 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3114 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3115
55c4665e 3116 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3117 SDHCI_MAX_CURRENT_300_MASK) >>
3118 SDHCI_MAX_CURRENT_300_SHIFT) *
3119 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3120 }
3121 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3122 ocr_avail |= MMC_VDD_165_195;
3123
55c4665e 3124 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3125 SDHCI_MAX_CURRENT_180_MASK) >>
3126 SDHCI_MAX_CURRENT_180_SHIFT) *
3127 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3128 }
3129
c0b887b6
HZ		 3130 if (host->ocr_mask)
3131 ocr_avail = host->ocr_mask;
3132
8f230f45
TI		 3133 mmc->ocr_avail = ocr_avail;
3134 mmc->ocr_avail_sdio = ocr_avail;
3135 if (host->ocr_avail_sdio)
3136 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3137 mmc->ocr_avail_sd = ocr_avail;
3138 if (host->ocr_avail_sd)
3139 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3140 else /* normal SD controllers don't support 1.8V */
3141 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3142 mmc->ocr_avail_mmc = ocr_avail;
3143 if (host->ocr_avail_mmc)
3144 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3145
3146 if (mmc->ocr_avail == 0) {
a3c76eb9 3147 pr_err("%s: Hardware doesn't report any "
b69c9058 3148 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3149 return -ENODEV;
146ad66e
PO		 3150 }
3151
d129bceb
PO		 3152 spin_lock_init(&host->lock);
3153
3154 /*
2134a922
PO		 3155 * Maximum number of segments. Depends on if the hardware
3156 * can do scatter/gather or not.
d129bceb 3157 */
2134a922 3158 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3159 mmc->max_segs = 128;
a13abc7b 3160 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3161 mmc->max_segs = 1;
2134a922 3162 else /* PIO */
a36274e0 3163 mmc->max_segs = 128;
d129bceb
PO		 3164
3165 /*
bab76961 3166 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3167 * size (512KiB).
d129bceb 3168 */
55db890a 3169 mmc->max_req_size = 524288;
d129bceb
PO		 3170
3171 /*
3172 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3173 * of bytes. When doing hardware scatter/gather, each entry cannot
3174 * be larger than 64 KiB though.
d129bceb 3175 */
30652aa3
OJ		 3176 if (host->flags & SDHCI_USE_ADMA) {
3177 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3178 mmc->max_seg_size = 65535;
3179 else
3180 mmc->max_seg_size = 65536;
3181 } else {
2134a922 3182 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3183 }
d129bceb 3184
fe4a3c7a
PO		 3185 /*
3186 * Maximum block size. This varies from controller to controller and
3187 * is specified in the capabilities register.
3188 */
0633f654
AV		 3189 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3190 mmc->max_blk_size = 2;
3191 } else {
f2119df6 3192 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3193 SDHCI_MAX_BLOCK_SHIFT;
3194 if (mmc->max_blk_size >= 3) {
a3c76eb9 3195 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3196 "assuming 512 bytes\n", mmc_hostname(mmc));
3197 mmc->max_blk_size = 0;
3198 }
3199 }
3200
3201 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3202
55db890a
PO		 3203 /*
3204 * Maximum block count.
3205 */
1388eefd 3206 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3207
d129bceb
PO		 3208 /*
3209 * Init tasklets.
3210 */
d129bceb
PO		 3211 tasklet_init(&host->finish_tasklet,
3212 sdhci_tasklet_finish, (unsigned long)host);
3213
e4cad1b5 3214 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3215
cf2b5eea 3216 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3217 init_waitqueue_head(&host->buf_ready_int);
3218
cf2b5eea
AN		 3219 /* Initialize re-tuning timer */
3220 init_timer(&host->tuning_timer);
3221 host->tuning_timer.data = (unsigned long)host;
3222 host->tuning_timer.function = sdhci_tuning_timer;
3223 }
3224
2af502ca
SG		 3225 sdhci_init(host, 0);
3226
781e989c
RK		 3227 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3228 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3229 if (ret) {
3230 pr_err("%s: Failed to request IRQ %d: %d\n",
3231 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3232 goto untasklet;
0fc81ee3 3233 }
d129bceb 3234
d129bceb
PO		 3235#ifdef CONFIG_MMC_DEBUG
3236 sdhci_dumpregs(host);
3237#endif
3238
f9134319 3239#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3240 snprintf(host->led_name, sizeof(host->led_name),
3241 "%s::", mmc_hostname(mmc));
3242 host->led.name = host->led_name;
2f730fec
PO		 3243 host->led.brightness = LED_OFF;
3244 host->led.default_trigger = mmc_hostname(mmc);
3245 host->led.brightness_set = sdhci_led_control;
3246
b8c86fc5 3247 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3248 if (ret) {
3249 pr_err("%s: Failed to register LED device: %d\n",
3250 mmc_hostname(mmc), ret);
2f730fec 3251 goto reset;
0fc81ee3 3252 }
2f730fec
PO		 3253#endif
3254
5f25a66f
PO		 3255 mmiowb();
3256
d129bceb
PO		 3257 mmc_add_host(mmc);
3258
a3c76eb9 3259 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3260 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3261 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3262 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3263
7260cf5e
AV		 3264 sdhci_enable_card_detection(host);
3265
d129bceb
PO		 3266 return 0;
3267
f9134319 3268#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3269reset:
03231f9b 3270 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3271 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3272 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3273 free_irq(host->irq, host);
3274#endif
8ef1a143 3275untasklet:
d129bceb 3276 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3277
3278 return ret;
3279}
3280
b8c86fc5 3281EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3282
1e72859e 3283void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3284{
1e72859e
PO		 3285 unsigned long flags;
3286
3287 if (dead) {
3288 spin_lock_irqsave(&host->lock, flags);
3289
3290 host->flags |= SDHCI_DEVICE_DEAD;
3291
3292 if (host->mrq) {
a3c76eb9 3293 pr_err("%s: Controller removed during "
1e72859e
PO		 3294 " transfer!\n", mmc_hostname(host->mmc));
3295
3296 host->mrq->cmd->error = -ENOMEDIUM;
3297 tasklet_schedule(&host->finish_tasklet);
3298 }
3299
3300 spin_unlock_irqrestore(&host->lock, flags);
3301 }
3302
7260cf5e
AV		 3303 sdhci_disable_card_detection(host);
3304
b8c86fc5 3305 mmc_remove_host(host->mmc);
d129bceb 3306
f9134319 3307#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3308 led_classdev_unregister(&host->led);
3309#endif
3310
1e72859e 3311 if (!dead)
03231f9b 3312 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3313
b537f94c
RK		 3314 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3315 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3316 free_irq(host->irq, host);
3317
3318 del_timer_sync(&host->timer);
3319
d129bceb 3320 tasklet_kill(&host->finish_tasklet);
2134a922 3321
77dcb3f4
PR		 3322 if (host->vmmc) {
3323 regulator_disable(host->vmmc);
9bea3c85 3324 regulator_put(host->vmmc);
77dcb3f4 3325 }
9bea3c85 3326
6231f3de
PR		 3327 if (host->vqmmc) {
3328 regulator_disable(host->vqmmc);
3329 regulator_put(host->vqmmc);
3330 }
3331
d1e49f77
RK		 3332 if (host->adma_desc)
3333 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
3334 host->adma_desc, host->adma_addr);
2134a922
PO		 3335 kfree(host->align_buffer);
3336
3337 host->adma_desc = NULL;
3338 host->align_buffer = NULL;
d129bceb
PO		 3339}
3340
b8c86fc5 3341EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3342
b8c86fc5 3343void sdhci_free_host(struct sdhci_host *host)
d129bceb 3344{
b8c86fc5 3345 mmc_free_host(host->mmc);
d129bceb
PO		 3346}
3347
b8c86fc5 3348EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3349
3350/*****************************************************************************\
3351 * *
3352 * Driver init/exit *
3353 * *
3354\*****************************************************************************/
3355
3356static int __init sdhci_drv_init(void)
3357{
a3c76eb9 3358 pr_info(DRIVER_NAME
52fbf9c9 3359 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3360 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3361
b8c86fc5 3362 return 0;
d129bceb
PO		 3363}
3364
3365static void __exit sdhci_drv_exit(void)
3366{
d129bceb
PO		 3367}
3368
3369module_init(sdhci_drv_init);
3370module_exit(sdhci_drv_exit);
3371
df673b22 3372module_param(debug_quirks, uint, 0444);
66fd8ad5 3373module_param(debug_quirks2, uint, 0444);
67435274 3374
32710e8f 3375MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3376MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3377MODULE_LICENSE("GPL");
67435274 3378
df673b22 3379MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3380MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux 6.x block layer and io_uring tree(s)