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mmc: core: enhance card removal judgement for slow removal
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
52static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 55static void sdhci_tuning_timer(unsigned long data);
52983382 56static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 57
66fd8ad5
AH		 58#ifdef CONFIG_PM_RUNTIME
59static int sdhci_runtime_pm_get(struct sdhci_host *host);
60static int sdhci_runtime_pm_put(struct sdhci_host *host);
61#else
62static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
63{
64 return 0;
65}
66static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
67{
68 return 0;
69}
70#endif
71
d129bceb
PO		 72static void sdhci_dumpregs(struct sdhci_host *host)
73{
a3c76eb9 74 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 75 mmc_hostname(host->mmc));
d129bceb 76
a3c76eb9 77 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 78 sdhci_readl(host, SDHCI_DMA_ADDRESS),
79 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 80 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 81 sdhci_readw(host, SDHCI_BLOCK_SIZE),
82 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 83 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 84 sdhci_readl(host, SDHCI_ARGUMENT),
85 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 86 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 87 sdhci_readl(host, SDHCI_PRESENT_STATE),
88 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 89 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 90 sdhci_readb(host, SDHCI_POWER_CONTROL),
91 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 92 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 93 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
94 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 95 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 96 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
97 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 98 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 99 sdhci_readl(host, SDHCI_INT_ENABLE),
100 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 101 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 102 sdhci_readw(host, SDHCI_ACMD12_ERR),
103 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 104 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 105 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 106 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 107 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 108 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 109 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 110 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 111 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 112
be3f4ae0 113 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 114 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 115 readl(host->ioaddr + SDHCI_ADMA_ERROR),
116 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
117
a3c76eb9 118 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 119}
120
121/*****************************************************************************\
122 * *
123 * Low level functions *
124 * *
125\*****************************************************************************/
126
7260cf5e
AV		 127static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
128{
129 u32 ier;
130
131 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
132 ier &= ~clear;
133 ier |= set;
134 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
135 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
136}
137
138static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
139{
140 sdhci_clear_set_irqs(host, 0, irqs);
141}
142
143static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
144{
145 sdhci_clear_set_irqs(host, irqs, 0);
146}
147
148static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
149{
d25928d1 150 u32 present, irqs;
7260cf5e 151
c79396c1 152 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 153 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 154 return;
155
d25928d1
SG		 156 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
157 SDHCI_CARD_PRESENT;
158 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
159
7260cf5e
AV		 160 if (enable)
161 sdhci_unmask_irqs(host, irqs);
162 else
163 sdhci_mask_irqs(host, irqs);
164}
165
166static void sdhci_enable_card_detection(struct sdhci_host *host)
167{
168 sdhci_set_card_detection(host, true);
169}
170
171static void sdhci_disable_card_detection(struct sdhci_host *host)
172{
173 sdhci_set_card_detection(host, false);
174}
175
d129bceb
PO		 176static void sdhci_reset(struct sdhci_host *host, u8 mask)
177{
e16514d8 178 unsigned long timeout;
063a9dbb 179 u32 uninitialized_var(ier);
e16514d8 180
b8c86fc5 181 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 182 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 183 SDHCI_CARD_PRESENT))
184 return;
185 }
186
063a9dbb
AV		 187 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
188 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
189
393c1a34
PR		 190 if (host->ops->platform_reset_enter)
191 host->ops->platform_reset_enter(host, mask);
192
4e4141a5 193 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 194
e16514d8 195 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 196 host->clock = 0;
197
e16514d8
PO		 198 /* Wait max 100 ms */
199 timeout = 100;
200
201 /* hw clears the bit when it's done */
4e4141a5 202 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 203 if (timeout == 0) {
a3c76eb9 204 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 205 mmc_hostname(host->mmc), (int)mask);
206 sdhci_dumpregs(host);
207 return;
208 }
209 timeout--;
210 mdelay(1);
d129bceb 211 }
063a9dbb 212
393c1a34
PR		 213 if (host->ops->platform_reset_exit)
214 host->ops->platform_reset_exit(host, mask);
215
063a9dbb
AV		 216 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
217 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
3abc1e80
SX		 218
219 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
220 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
221 host->ops->enable_dma(host);
222 }
d129bceb
PO		 223}
224
2f4cbb3d
NP		 225static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
226
227static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 228{
2f4cbb3d
NP		 229 if (soft)
230 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
231 else
232 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 233
7260cf5e
AV		 234 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
235 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 236 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
237 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 238 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 239
240 if (soft) {
241 /* force clock reconfiguration */
242 host->clock = 0;
243 sdhci_set_ios(host->mmc, &host->mmc->ios);
244 }
7260cf5e 245}
d129bceb 246
7260cf5e
AV		 247static void sdhci_reinit(struct sdhci_host *host)
248{
2f4cbb3d 249 sdhci_init(host, 0);
b67c6b41
AL		 250 /*
251 * Retuning stuffs are affected by different cards inserted and only
252 * applicable to UHS-I cards. So reset these fields to their initial
253 * value when card is removed.
254 */
973905fe
AL		 255 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
256 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
257
b67c6b41
AL		 258 del_timer_sync(&host->tuning_timer);
259 host->flags &= ~SDHCI_NEEDS_RETUNING;
260 host->mmc->max_blk_count =
261 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
262 }
7260cf5e 263 sdhci_enable_card_detection(host);
d129bceb
PO		 264}
265
266static void sdhci_activate_led(struct sdhci_host *host)
267{
268 u8 ctrl;
269
4e4141a5 270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 271 ctrl |= SDHCI_CTRL_LED;
4e4141a5 272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 273}
274
275static void sdhci_deactivate_led(struct sdhci_host *host)
276{
277 u8 ctrl;
278
4e4141a5 279 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 280 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 281 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 282}
283
f9134319 284#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 285static void sdhci_led_control(struct led_classdev *led,
286 enum led_brightness brightness)
287{
288 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
289 unsigned long flags;
290
291 spin_lock_irqsave(&host->lock, flags);
292
66fd8ad5
AH		 293 if (host->runtime_suspended)
294 goto out;
295
2f730fec
PO		 296 if (brightness == LED_OFF)
297 sdhci_deactivate_led(host);
298 else
299 sdhci_activate_led(host);
66fd8ad5 300out:
2f730fec
PO		 301 spin_unlock_irqrestore(&host->lock, flags);
302}
303#endif
304
d129bceb
PO		 305/*****************************************************************************\
306 * *
307 * Core functions *
308 * *
309\*****************************************************************************/
310
a406f5a3 311static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 312{
7659150c
PO		 313 unsigned long flags;
314 size_t blksize, len, chunk;
7244b85b 315 u32 uninitialized_var(scratch);
7659150c 316 u8 *buf;
d129bceb 317
a406f5a3 318 DBG("PIO reading\n");
d129bceb 319
a406f5a3 320 blksize = host->data->blksz;
7659150c 321 chunk = 0;
d129bceb 322
7659150c 323 local_irq_save(flags);
d129bceb 324
a406f5a3 325 while (blksize) {
7659150c
PO		 326 if (!sg_miter_next(&host->sg_miter))
327 BUG();
d129bceb 328
7659150c 329 len = min(host->sg_miter.length, blksize);
d129bceb 330
7659150c
PO		 331 blksize -= len;
332 host->sg_miter.consumed = len;
14d836e7 333
7659150c 334 buf = host->sg_miter.addr;
d129bceb 335
7659150c
PO		 336 while (len) {
337 if (chunk == 0) {
4e4141a5 338 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 339 chunk = 4;
a406f5a3 340 }
7659150c
PO		 341
342 *buf = scratch & 0xFF;
343
344 buf++;
345 scratch >>= 8;
346 chunk--;
347 len--;
d129bceb 348 }
a406f5a3 349 }
7659150c
PO		 350
351 sg_miter_stop(&host->sg_miter);
352
353 local_irq_restore(flags);
a406f5a3 354}
d129bceb 355
a406f5a3
PO		 356static void sdhci_write_block_pio(struct sdhci_host *host)
357{
7659150c
PO		 358 unsigned long flags;
359 size_t blksize, len, chunk;
360 u32 scratch;
361 u8 *buf;
d129bceb 362
a406f5a3
PO		 363 DBG("PIO writing\n");
364
365 blksize = host->data->blksz;
7659150c
PO		 366 chunk = 0;
367 scratch = 0;
d129bceb 368
7659150c 369 local_irq_save(flags);
d129bceb 370
a406f5a3 371 while (blksize) {
7659150c
PO		 372 if (!sg_miter_next(&host->sg_miter))
373 BUG();
a406f5a3 374
7659150c
PO		 375 len = min(host->sg_miter.length, blksize);
376
377 blksize -= len;
378 host->sg_miter.consumed = len;
379
380 buf = host->sg_miter.addr;
d129bceb 381
7659150c
PO		 382 while (len) {
383 scratch |= (u32)*buf << (chunk * 8);
384
385 buf++;
386 chunk++;
387 len--;
388
389 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 390 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 391 chunk = 0;
392 scratch = 0;
d129bceb 393 }
d129bceb
PO		 394 }
395 }
7659150c
PO		 396
397 sg_miter_stop(&host->sg_miter);
398
399 local_irq_restore(flags);
a406f5a3
PO		 400}
401
402static void sdhci_transfer_pio(struct sdhci_host *host)
403{
404 u32 mask;
405
406 BUG_ON(!host->data);
407
7659150c 408 if (host->blocks == 0)
a406f5a3
PO		 409 return;
410
411 if (host->data->flags & MMC_DATA_READ)
412 mask = SDHCI_DATA_AVAILABLE;
413 else
414 mask = SDHCI_SPACE_AVAILABLE;
415
4a3cba32
PO		 416 /*
417 * Some controllers (JMicron JMB38x) mess up the buffer bits
418 * for transfers < 4 bytes. As long as it is just one block,
419 * we can ignore the bits.
420 */
421 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
422 (host->data->blocks == 1))
423 mask = ~0;
424
4e4141a5 425 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 426 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
427 udelay(100);
428
a406f5a3
PO		 429 if (host->data->flags & MMC_DATA_READ)
430 sdhci_read_block_pio(host);
431 else
432 sdhci_write_block_pio(host);
d129bceb 433
7659150c
PO		 434 host->blocks--;
435 if (host->blocks == 0)
a406f5a3 436 break;
a406f5a3 437 }
d129bceb 438
a406f5a3 439 DBG("PIO transfer complete.\n");
d129bceb
PO		 440}
441
2134a922
PO		 442static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
443{
444 local_irq_save(*flags);
482fce99 445 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 446}
447
448static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
449{
482fce99 450 kunmap_atomic(buffer);
2134a922
PO		 451 local_irq_restore(*flags);
452}
453
118cd17d
BD		 454static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
455{
9e506f35
BD		 456 __le32 *dataddr = (__le32 __force *)(desc + 4);
457 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 458
9e506f35
BD		 459 /* SDHCI specification says ADMA descriptors should be 4 byte
460 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 461
9e506f35
BD		 462 cmdlen[0] = cpu_to_le16(cmd);
463 cmdlen[1] = cpu_to_le16(len);
464
465 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 466}
467
8f1934ce 468static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 469 struct mmc_data *data)
470{
471 int direction;
472
473 u8 *desc;
474 u8 *align;
475 dma_addr_t addr;
476 dma_addr_t align_addr;
477 int len, offset;
478
479 struct scatterlist *sg;
480 int i;
481 char *buffer;
482 unsigned long flags;
483
484 /*
485 * The spec does not specify endianness of descriptor table.
486 * We currently guess that it is LE.
487 */
488
489 if (data->flags & MMC_DATA_READ)
490 direction = DMA_FROM_DEVICE;
491 else
492 direction = DMA_TO_DEVICE;
493
494 /*
495 * The ADMA descriptor table is mapped further down as we
496 * need to fill it with data first.
497 */
498
499 host->align_addr = dma_map_single(mmc_dev(host->mmc),
500 host->align_buffer, 128 * 4, direction);
8d8bb39b 501 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 502 goto fail;
2134a922
PO		 503 BUG_ON(host->align_addr & 0x3);
504
505 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
506 data->sg, data->sg_len, direction);
8f1934ce
PO		 507 if (host->sg_count == 0)
508 goto unmap_align;
2134a922
PO		 509
510 desc = host->adma_desc;
511 align = host->align_buffer;
512
513 align_addr = host->align_addr;
514
515 for_each_sg(data->sg, sg, host->sg_count, i) {
516 addr = sg_dma_address(sg);
517 len = sg_dma_len(sg);
518
519 /*
520 * The SDHCI specification states that ADMA
521 * addresses must be 32-bit aligned. If they
522 * aren't, then we use a bounce buffer for
523 * the (up to three) bytes that screw up the
524 * alignment.
525 */
526 offset = (4 - (addr & 0x3)) & 0x3;
527 if (offset) {
528 if (data->flags & MMC_DATA_WRITE) {
529 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 530 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 531 memcpy(align, buffer, offset);
532 sdhci_kunmap_atomic(buffer, &flags);
533 }
534
118cd17d
BD		 535 /* tran, valid */
536 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 537
538 BUG_ON(offset > 65536);
539
2134a922
PO		 540 align += 4;
541 align_addr += 4;
542
543 desc += 8;
544
545 addr += offset;
546 len -= offset;
547 }
548
2134a922
PO		 549 BUG_ON(len > 65536);
550
118cd17d
BD		 551 /* tran, valid */
552 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 553 desc += 8;
554
555 /*
556 * If this triggers then we have a calculation bug
557 * somewhere. :/
558 */
559 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
560 }
561
70764a90
TA		 562 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
563 /*
564 * Mark the last descriptor as the terminating descriptor
565 */
566 if (desc != host->adma_desc) {
567 desc -= 8;
568 desc[0] |= 0x2; /* end */
569 }
570 } else {
571 /*
572 * Add a terminating entry.
573 */
2134a922 574
70764a90
TA		 575 /* nop, end, valid */
576 sdhci_set_adma_desc(desc, 0, 0, 0x3);
577 }
2134a922
PO		 578
579 /*
580 * Resync align buffer as we might have changed it.
581 */
582 if (data->flags & MMC_DATA_WRITE) {
583 dma_sync_single_for_device(mmc_dev(host->mmc),
584 host->align_addr, 128 * 4, direction);
585 }
586
587 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
588 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 589 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 590 goto unmap_entries;
2134a922 591 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 592
593 return 0;
594
595unmap_entries:
596 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
597 data->sg_len, direction);
598unmap_align:
599 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
600 128 * 4, direction);
601fail:
602 return -EINVAL;
2134a922
PO		 603}
604
605static void sdhci_adma_table_post(struct sdhci_host *host,
606 struct mmc_data *data)
607{
608 int direction;
609
610 struct scatterlist *sg;
611 int i, size;
612 u8 *align;
613 char *buffer;
614 unsigned long flags;
615
616 if (data->flags & MMC_DATA_READ)
617 direction = DMA_FROM_DEVICE;
618 else
619 direction = DMA_TO_DEVICE;
620
621 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
622 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
623
624 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
625 128 * 4, direction);
626
627 if (data->flags & MMC_DATA_READ) {
628 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
629 data->sg_len, direction);
630
631 align = host->align_buffer;
632
633 for_each_sg(data->sg, sg, host->sg_count, i) {
634 if (sg_dma_address(sg) & 0x3) {
635 size = 4 - (sg_dma_address(sg) & 0x3);
636
637 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 638 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 639 memcpy(buffer, align, size);
640 sdhci_kunmap_atomic(buffer, &flags);
641
642 align += 4;
643 }
644 }
645 }
646
647 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
648 data->sg_len, direction);
649}
650
a3c7778f 651static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 652{
1c8cde92 653 u8 count;
a3c7778f 654 struct mmc_data *data = cmd->data;
1c8cde92 655 unsigned target_timeout, current_timeout;
d129bceb 656
ee53ab5d
PO		 657 /*
658 * If the host controller provides us with an incorrect timeout
659 * value, just skip the check and use 0xE. The hardware may take
660 * longer to time out, but that's much better than having a too-short
661 * timeout value.
662 */
11a2f1b7 663 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 664 return 0xE;
e538fbe8 665
a3c7778f
AW		 666 /* Unspecified timeout, assume max */
667 if (!data && !cmd->cmd_timeout_ms)
668 return 0xE;
d129bceb 669
a3c7778f
AW		 670 /* timeout in us */
671 if (!data)
672 target_timeout = cmd->cmd_timeout_ms * 1000;
78a2ca27
AS		 673 else {
674 target_timeout = data->timeout_ns / 1000;
675 if (host->clock)
676 target_timeout += data->timeout_clks / host->clock;
677 }
81b39802 678
1c8cde92
PO		 679 /*
680 * Figure out needed cycles.
681 * We do this in steps in order to fit inside a 32 bit int.
682 * The first step is the minimum timeout, which will have a
683 * minimum resolution of 6 bits:
684 * (1) 2^13*1000 > 2^22,
685 * (2) host->timeout_clk < 2^16
686 * =>
687 * (1) / (2) > 2^6
688 */
689 count = 0;
690 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
691 while (current_timeout < target_timeout) {
692 count++;
693 current_timeout <<= 1;
694 if (count >= 0xF)
695 break;
696 }
697
698 if (count >= 0xF) {
09eeff52
CB		 699 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
700 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 701 count = 0xE;
702 }
703
ee53ab5d
PO		 704 return count;
705}
706
6aa943ab
AV		 707static void sdhci_set_transfer_irqs(struct sdhci_host *host)
708{
709 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
710 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
711
712 if (host->flags & SDHCI_REQ_USE_DMA)
713 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
714 else
715 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
716}
717
a3c7778f 718static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 719{
720 u8 count;
2134a922 721 u8 ctrl;
a3c7778f 722 struct mmc_data *data = cmd->data;
8f1934ce 723 int ret;
ee53ab5d
PO		 724
725 WARN_ON(host->data);
726
a3c7778f
AW		 727 if (data || (cmd->flags & MMC_RSP_BUSY)) {
728 count = sdhci_calc_timeout(host, cmd);
729 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
730 }
731
732 if (!data)
ee53ab5d
PO		 733 return;
734
735 /* Sanity checks */
736 BUG_ON(data->blksz * data->blocks > 524288);
737 BUG_ON(data->blksz > host->mmc->max_blk_size);
738 BUG_ON(data->blocks > 65535);
739
740 host->data = data;
741 host->data_early = 0;
f6a03cbf 742 host->data->bytes_xfered = 0;
ee53ab5d 743
a13abc7b 744 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 745 host->flags |= SDHCI_REQ_USE_DMA;
746
2134a922
PO		 747 /*
748 * FIXME: This doesn't account for merging when mapping the
749 * scatterlist.
750 */
751 if (host->flags & SDHCI_REQ_USE_DMA) {
752 int broken, i;
753 struct scatterlist *sg;
754
755 broken = 0;
756 if (host->flags & SDHCI_USE_ADMA) {
757 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
758 broken = 1;
759 } else {
760 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
761 broken = 1;
762 }
763
764 if (unlikely(broken)) {
765 for_each_sg(data->sg, sg, data->sg_len, i) {
766 if (sg->length & 0x3) {
767 DBG("Reverting to PIO because of "
768 "transfer size (%d)\n",
769 sg->length);
770 host->flags &= ~SDHCI_REQ_USE_DMA;
771 break;
772 }
773 }
774 }
c9fddbc4
PO		 775 }
776
777 /*
778 * The assumption here being that alignment is the same after
779 * translation to device address space.
780 */
2134a922
PO		 781 if (host->flags & SDHCI_REQ_USE_DMA) {
782 int broken, i;
783 struct scatterlist *sg;
784
785 broken = 0;
786 if (host->flags & SDHCI_USE_ADMA) {
787 /*
788 * As we use 3 byte chunks to work around
789 * alignment problems, we need to check this
790 * quirk.
791 */
792 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
793 broken = 1;
794 } else {
795 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
796 broken = 1;
797 }
798
799 if (unlikely(broken)) {
800 for_each_sg(data->sg, sg, data->sg_len, i) {
801 if (sg->offset & 0x3) {
802 DBG("Reverting to PIO because of "
803 "bad alignment\n");
804 host->flags &= ~SDHCI_REQ_USE_DMA;
805 break;
806 }
807 }
808 }
809 }
810
8f1934ce
PO		 811 if (host->flags & SDHCI_REQ_USE_DMA) {
812 if (host->flags & SDHCI_USE_ADMA) {
813 ret = sdhci_adma_table_pre(host, data);
814 if (ret) {
815 /*
816 * This only happens when someone fed
817 * us an invalid request.
818 */
819 WARN_ON(1);
ebd6d357 820 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 821 } else {
4e4141a5
AV		 822 sdhci_writel(host, host->adma_addr,
823 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 824 }
825 } else {
c8b3e02e 826 int sg_cnt;
8f1934ce 827
c8b3e02e 828 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 829 data->sg, data->sg_len,
830 (data->flags & MMC_DATA_READ) ?
831 DMA_FROM_DEVICE :
832 DMA_TO_DEVICE);
c8b3e02e 833 if (sg_cnt == 0) {
8f1934ce
PO		 834 /*
835 * This only happens when someone fed
836 * us an invalid request.
837 */
838 WARN_ON(1);
ebd6d357 839 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 840 } else {
719a61b4 841 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 842 sdhci_writel(host, sg_dma_address(data->sg),
843 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 844 }
845 }
846 }
847
2134a922
PO		 848 /*
849 * Always adjust the DMA selection as some controllers
850 * (e.g. JMicron) can't do PIO properly when the selection
851 * is ADMA.
852 */
853 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 854 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 855 ctrl &= ~SDHCI_CTRL_DMA_MASK;
856 if ((host->flags & SDHCI_REQ_USE_DMA) &&
857 (host->flags & SDHCI_USE_ADMA))
858 ctrl |= SDHCI_CTRL_ADMA32;
859 else
860 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 861 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 862 }
863
8f1934ce 864 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 865 int flags;
866
867 flags = SG_MITER_ATOMIC;
868 if (host->data->flags & MMC_DATA_READ)
869 flags |= SG_MITER_TO_SG;
870 else
871 flags |= SG_MITER_FROM_SG;
872 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 873 host->blocks = data->blocks;
d129bceb 874 }
c7fa9963 875
6aa943ab
AV		 876 sdhci_set_transfer_irqs(host);
877
f6a03cbf
MV		 878 /* Set the DMA boundary value and block size */
879 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
880 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 881 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 882}
883
884static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 885 struct mmc_command *cmd)
c7fa9963
PO		 886{
887 u16 mode;
e89d456f 888 struct mmc_data *data = cmd->data;
c7fa9963 889
c7fa9963
PO		 890 if (data == NULL)
891 return;
892
e538fbe8
PO		 893 WARN_ON(!host->data);
894
c7fa9963 895 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 896 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
897 mode |= SDHCI_TRNS_MULTI;
898 /*
899 * If we are sending CMD23, CMD12 never gets sent
900 * on successful completion (so no Auto-CMD12).
901 */
902 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
903 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 904 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
905 mode |= SDHCI_TRNS_AUTO_CMD23;
906 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
907 }
c4512f79 908 }
8edf6371 909
c7fa9963
PO		 910 if (data->flags & MMC_DATA_READ)
911 mode |= SDHCI_TRNS_READ;
c9fddbc4 912 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 913 mode |= SDHCI_TRNS_DMA;
914
4e4141a5 915 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 916}
917
918static void sdhci_finish_data(struct sdhci_host *host)
919{
920 struct mmc_data *data;
d129bceb
PO		 921
922 BUG_ON(!host->data);
923
924 data = host->data;
925 host->data = NULL;
926
c9fddbc4 927 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 928 if (host->flags & SDHCI_USE_ADMA)
929 sdhci_adma_table_post(host, data);
930 else {
931 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
932 data->sg_len, (data->flags & MMC_DATA_READ) ?
933 DMA_FROM_DEVICE : DMA_TO_DEVICE);
934 }
d129bceb
PO		 935 }
936
937 /*
c9b74c5b
PO		 938 * The specification states that the block count register must
939 * be updated, but it does not specify at what point in the
940 * data flow. That makes the register entirely useless to read
941 * back so we have to assume that nothing made it to the card
942 * in the event of an error.
d129bceb 943 */
c9b74c5b
PO		 944 if (data->error)
945 data->bytes_xfered = 0;
d129bceb 946 else
c9b74c5b 947 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 948
e89d456f
AW		 949 /*
950 * Need to send CMD12 if -
951 * a) open-ended multiblock transfer (no CMD23)
952 * b) error in multiblock transfer
953 */
954 if (data->stop &&
955 (data->error ||
956 !host->mrq->sbc)) {
957
d129bceb
PO		 958 /*
959 * The controller needs a reset of internal state machines
960 * upon error conditions.
961 */
17b0429d 962 if (data->error) {
d129bceb
PO		 963 sdhci_reset(host, SDHCI_RESET_CMD);
964 sdhci_reset(host, SDHCI_RESET_DATA);
965 }
966
967 sdhci_send_command(host, data->stop);
968 } else
969 tasklet_schedule(&host->finish_tasklet);
970}
971
972static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
973{
974 int flags;
fd2208d7 975 u32 mask;
7cb2c76f 976 unsigned long timeout;
d129bceb
PO		 977
978 WARN_ON(host->cmd);
979
d129bceb 980 /* Wait max 10 ms */
7cb2c76f 981 timeout = 10;
fd2208d7
PO		 982
983 mask = SDHCI_CMD_INHIBIT;
984 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
985 mask |= SDHCI_DATA_INHIBIT;
986
987 /* We shouldn't wait for data inihibit for stop commands, even
988 though they might use busy signaling */
989 if (host->mrq->data && (cmd == host->mrq->data->stop))
990 mask &= ~SDHCI_DATA_INHIBIT;
991
4e4141a5 992 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 993 if (timeout == 0) {
a3c76eb9 994 pr_err("%s: Controller never released "
acf1da45 995 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 996 sdhci_dumpregs(host);
17b0429d 997 cmd->error = -EIO;
d129bceb
PO		 998 tasklet_schedule(&host->finish_tasklet);
999 return;
1000 }
7cb2c76f
PO		 1001 timeout--;
1002 mdelay(1);
1003 }
d129bceb
PO		 1004
1005 mod_timer(&host->timer, jiffies + 10 * HZ);
1006
1007 host->cmd = cmd;
1008
a3c7778f 1009 sdhci_prepare_data(host, cmd);
d129bceb 1010
4e4141a5 1011 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1012
e89d456f 1013 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1014
d129bceb 1015 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1016 pr_err("%s: Unsupported response type!\n",
d129bceb 1017 mmc_hostname(host->mmc));
17b0429d 1018 cmd->error = -EINVAL;
d129bceb
PO		 1019 tasklet_schedule(&host->finish_tasklet);
1020 return;
1021 }
1022
1023 if (!(cmd->flags & MMC_RSP_PRESENT))
1024 flags = SDHCI_CMD_RESP_NONE;
1025 else if (cmd->flags & MMC_RSP_136)
1026 flags = SDHCI_CMD_RESP_LONG;
1027 else if (cmd->flags & MMC_RSP_BUSY)
1028 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1029 else
1030 flags = SDHCI_CMD_RESP_SHORT;
1031
1032 if (cmd->flags & MMC_RSP_CRC)
1033 flags |= SDHCI_CMD_CRC;
1034 if (cmd->flags & MMC_RSP_OPCODE)
1035 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1036
1037 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1038 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1039 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1040 flags |= SDHCI_CMD_DATA;
1041
4e4141a5 1042 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 1043}
1044
1045static void sdhci_finish_command(struct sdhci_host *host)
1046{
1047 int i;
1048
1049 BUG_ON(host->cmd == NULL);
1050
1051 if (host->cmd->flags & MMC_RSP_PRESENT) {
1052 if (host->cmd->flags & MMC_RSP_136) {
1053 /* CRC is stripped so we need to do some shifting. */
1054 for (i = 0;i < 4;i++) {
4e4141a5 1055 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1056 SDHCI_RESPONSE + (3-i)*4) << 8;
1057 if (i != 3)
1058 host->cmd->resp[i] |=
4e4141a5 1059 sdhci_readb(host,
d129bceb
PO		 1060 SDHCI_RESPONSE + (3-i)*4-1);
1061 }
1062 } else {
4e4141a5 1063 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1064 }
1065 }
1066
17b0429d 1067 host->cmd->error = 0;
d129bceb 1068
e89d456f
AW		 1069 /* Finished CMD23, now send actual command. */
1070 if (host->cmd == host->mrq->sbc) {
1071 host->cmd = NULL;
1072 sdhci_send_command(host, host->mrq->cmd);
1073 } else {
e538fbe8 1074
e89d456f
AW		 1075 /* Processed actual command. */
1076 if (host->data && host->data_early)
1077 sdhci_finish_data(host);
d129bceb 1078
e89d456f
AW		 1079 if (!host->cmd->data)
1080 tasklet_schedule(&host->finish_tasklet);
1081
1082 host->cmd = NULL;
1083 }
d129bceb
PO		 1084}
1085
52983382
KL		 1086static u16 sdhci_get_preset_value(struct sdhci_host *host)
1087{
1088 u16 ctrl, preset = 0;
1089
1090 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1091
1092 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1093 case SDHCI_CTRL_UHS_SDR12:
1094 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1095 break;
1096 case SDHCI_CTRL_UHS_SDR25:
1097 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1098 break;
1099 case SDHCI_CTRL_UHS_SDR50:
1100 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1101 break;
1102 case SDHCI_CTRL_UHS_SDR104:
1103 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1104 break;
1105 case SDHCI_CTRL_UHS_DDR50:
1106 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1107 break;
1108 default:
1109 pr_warn("%s: Invalid UHS-I mode selected\n",
1110 mmc_hostname(host->mmc));
1111 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1112 break;
1113 }
1114 return preset;
1115}
1116
d129bceb
PO		 1117static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1118{
c3ed3877 1119 int div = 0; /* Initialized for compiler warning */
df16219f 1120 int real_div = div, clk_mul = 1;
c3ed3877 1121 u16 clk = 0;
7cb2c76f 1122 unsigned long timeout;
d129bceb 1123
30832ab5 1124 if (clock && clock == host->clock)
d129bceb
PO		 1125 return;
1126
df16219f
GC		 1127 host->mmc->actual_clock = 0;
1128
8114634c
AV		 1129 if (host->ops->set_clock) {
1130 host->ops->set_clock(host, clock);
1131 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1132 return;
1133 }
1134
4e4141a5 1135 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1136
1137 if (clock == 0)
1138 goto out;
1139
85105c53 1140 if (host->version >= SDHCI_SPEC_300) {
52983382
KL		 1141 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1142 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1143 u16 pre_val;
1144
1145 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1146 pre_val = sdhci_get_preset_value(host);
1147 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1148 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1149 if (host->clk_mul &&
1150 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1151 clk = SDHCI_PROG_CLOCK_MODE;
1152 real_div = div + 1;
1153 clk_mul = host->clk_mul;
1154 } else {
1155 real_div = max_t(int, 1, div << 1);
1156 }
1157 goto clock_set;
1158 }
1159
c3ed3877
AN		 1160 /*
1161 * Check if the Host Controller supports Programmable Clock
1162 * Mode.
1163 */
1164 if (host->clk_mul) {
52983382
KL		 1165 for (div = 1; div <= 1024; div++) {
1166 if ((host->max_clk * host->clk_mul / div)
1167 <= clock)
1168 break;
1169 }
c3ed3877 1170 /*
52983382
KL		 1171 * Set Programmable Clock Mode in the Clock
1172 * Control register.
c3ed3877 1173 */
52983382
KL		 1174 clk = SDHCI_PROG_CLOCK_MODE;
1175 real_div = div;
1176 clk_mul = host->clk_mul;
1177 div--;
c3ed3877
AN		 1178 } else {
1179 /* Version 3.00 divisors must be a multiple of 2. */
1180 if (host->max_clk <= clock)
1181 div = 1;
1182 else {
1183 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1184 div += 2) {
1185 if ((host->max_clk / div) <= clock)
1186 break;
1187 }
85105c53 1188 }
df16219f 1189 real_div = div;
c3ed3877 1190 div >>= 1;
85105c53
ZG		 1191 }
1192 } else {
1193 /* Version 2.00 divisors must be a power of 2. */
0397526d 1194 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1195 if ((host->max_clk / div) <= clock)
1196 break;
1197 }
df16219f 1198 real_div = div;
c3ed3877 1199 div >>= 1;
d129bceb 1200 }
d129bceb 1201
52983382 1202clock_set:
df16219f
GC		 1203 if (real_div)
1204 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1205
c3ed3877 1206 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1207 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1208 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1209 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1210 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1211
27f6cb16
CB		 1212 /* Wait max 20 ms */
1213 timeout = 20;
4e4141a5 1214 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1215 & SDHCI_CLOCK_INT_STABLE)) {
1216 if (timeout == 0) {
a3c76eb9 1217 pr_err("%s: Internal clock never "
acf1da45 1218 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1219 sdhci_dumpregs(host);
1220 return;
1221 }
7cb2c76f
PO		 1222 timeout--;
1223 mdelay(1);
1224 }
d129bceb
PO		 1225
1226 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1227 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1228
1229out:
1230 host->clock = clock;
1231}
1232
8213af3b
AS		 1233static inline void sdhci_update_clock(struct sdhci_host *host)
1234{
1235 unsigned int clock;
1236
1237 clock = host->clock;
1238 host->clock = 0;
1239 sdhci_set_clock(host, clock);
1240}
1241
ceb6143b 1242static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
146ad66e 1243{
8364248a 1244 u8 pwr = 0;
146ad66e 1245
8364248a 1246 if (power != (unsigned short)-1) {
ae628903
PO		 1247 switch (1 << power) {
1248 case MMC_VDD_165_195:
1249 pwr = SDHCI_POWER_180;
1250 break;
1251 case MMC_VDD_29_30:
1252 case MMC_VDD_30_31:
1253 pwr = SDHCI_POWER_300;
1254 break;
1255 case MMC_VDD_32_33:
1256 case MMC_VDD_33_34:
1257 pwr = SDHCI_POWER_330;
1258 break;
1259 default:
1260 BUG();
1261 }
1262 }
1263
1264 if (host->pwr == pwr)
ceb6143b 1265 return -1;
146ad66e 1266
ae628903
PO		 1267 host->pwr = pwr;
1268
1269 if (pwr == 0) {
4e4141a5 1270 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ceb6143b 1271 return 0;
9e9dc5f2
DS		 1272 }
1273
1274 /*
1275 * Spec says that we should clear the power reg before setting
1276 * a new value. Some controllers don't seem to like this though.
1277 */
b8c86fc5 1278 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1279 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1280
e08c1694 1281 /*
c71f6512 1282 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1283 * and set turn on power at the same time, so set the voltage first.
1284 */
11a2f1b7 1285 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1286 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1287
ae628903 1288 pwr |= SDHCI_POWER_ON;
146ad66e 1289
ae628903 1290 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1291
1292 /*
1293 * Some controllers need an extra 10ms delay of 10ms before they
1294 * can apply clock after applying power
1295 */
11a2f1b7 1296 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1297 mdelay(10);
ceb6143b
AH		 1298
1299 return power;
146ad66e
PO		 1300}
1301
d129bceb
PO		 1302/*****************************************************************************\
1303 * *
1304 * MMC callbacks *
1305 * *
1306\*****************************************************************************/
1307
1308static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1309{
1310 struct sdhci_host *host;
505a8680 1311 int present;
d129bceb 1312 unsigned long flags;
473b095a 1313 u32 tuning_opcode;
d129bceb
PO		 1314
1315 host = mmc_priv(mmc);
1316
66fd8ad5
AH		 1317 sdhci_runtime_pm_get(host);
1318
d129bceb
PO		 1319 spin_lock_irqsave(&host->lock, flags);
1320
1321 WARN_ON(host->mrq != NULL);
1322
f9134319 1323#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1324 sdhci_activate_led(host);
2f730fec 1325#endif
e89d456f
AW		 1326
1327 /*
1328 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1329 * requests if Auto-CMD12 is enabled.
1330 */
1331 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1332 if (mrq->stop) {
1333 mrq->data->stop = NULL;
1334 mrq->stop = NULL;
1335 }
1336 }
d129bceb
PO		 1337
1338 host->mrq = mrq;
1339
505a8680
SG		 1340 /*
1341 * Firstly check card presence from cd-gpio. The return could
1342 * be one of the following possibilities:
1343 * negative: cd-gpio is not available
1344 * zero: cd-gpio is used, and card is removed
1345 * one: cd-gpio is used, and card is present
1346 */
1347 present = mmc_gpio_get_cd(host->mmc);
1348 if (present < 0) {
1349 /* If polling, assume that the card is always present. */
1350 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1351 present = 1;
1352 else
1353 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1354 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1355 }
1356
68d1fb7e 1357 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1358 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1359 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1360 } else {
1361 u32 present_state;
1362
1363 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1364 /*
1365 * Check if the re-tuning timer has already expired and there
1366 * is no on-going data transfer. If so, we need to execute
1367 * tuning procedure before sending command.
1368 */
1369 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1370 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1371 if (mmc->card) {
1372 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1373 tuning_opcode =
1374 mmc->card->type == MMC_TYPE_MMC ?
1375 MMC_SEND_TUNING_BLOCK_HS200 :
1376 MMC_SEND_TUNING_BLOCK;
1377 spin_unlock_irqrestore(&host->lock, flags);
1378 sdhci_execute_tuning(mmc, tuning_opcode);
1379 spin_lock_irqsave(&host->lock, flags);
1380
1381 /* Restore original mmc_request structure */
1382 host->mrq = mrq;
1383 }
cf2b5eea
AN		 1384 }
1385
8edf6371 1386 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1387 sdhci_send_command(host, mrq->sbc);
1388 else
1389 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1390 }
d129bceb 1391
5f25a66f 1392 mmiowb();
d129bceb
PO		 1393 spin_unlock_irqrestore(&host->lock, flags);
1394}
1395
66fd8ad5 1396static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1397{
d129bceb 1398 unsigned long flags;
ceb6143b 1399 int vdd_bit = -1;
d129bceb
PO		 1400 u8 ctrl;
1401
d129bceb
PO		 1402 spin_lock_irqsave(&host->lock, flags);
1403
ceb6143b
AH		 1404 if (host->flags & SDHCI_DEVICE_DEAD) {
1405 spin_unlock_irqrestore(&host->lock, flags);
1406 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1407 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1408 return;
1409 }
1e72859e 1410
d129bceb
PO		 1411 /*
1412 * Reset the chip on each power off.
1413 * Should clear out any weird states.
1414 */
1415 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1416 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1417 sdhci_reinit(host);
d129bceb
PO		 1418 }
1419
52983382
KL		 1420 if (host->version >= SDHCI_SPEC_300 &&
1421 (ios->power_mode == MMC_POWER_UP))
1422 sdhci_enable_preset_value(host, false);
1423
d129bceb
PO		 1424 sdhci_set_clock(host, ios->clock);
1425
1426 if (ios->power_mode == MMC_POWER_OFF)
ceb6143b 1427 vdd_bit = sdhci_set_power(host, -1);
d129bceb 1428 else
ceb6143b
AH		 1429 vdd_bit = sdhci_set_power(host, ios->vdd);
1430
1431 if (host->vmmc && vdd_bit != -1) {
1432 spin_unlock_irqrestore(&host->lock, flags);
1433 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1434 spin_lock_irqsave(&host->lock, flags);
1435 }
d129bceb 1436
643a81ff
PR		 1437 if (host->ops->platform_send_init_74_clocks)
1438 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1439
15ec4461
PR		 1440 /*
1441 * If your platform has 8-bit width support but is not a v3 controller,
1442 * or if it requires special setup code, you should implement that in
7bc088d3 1443 * platform_bus_width().
15ec4461 1444 */
7bc088d3
SH		 1445 if (host->ops->platform_bus_width) {
1446 host->ops->platform_bus_width(host, ios->bus_width);
1447 } else {
15ec4461
PR		 1448 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1449 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1450 ctrl &= ~SDHCI_CTRL_4BITBUS;
1451 if (host->version >= SDHCI_SPEC_300)
1452 ctrl |= SDHCI_CTRL_8BITBUS;
1453 } else {
1454 if (host->version >= SDHCI_SPEC_300)
1455 ctrl &= ~SDHCI_CTRL_8BITBUS;
1456 if (ios->bus_width == MMC_BUS_WIDTH_4)
1457 ctrl |= SDHCI_CTRL_4BITBUS;
1458 else
1459 ctrl &= ~SDHCI_CTRL_4BITBUS;
1460 }
1461 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1462 }
ae6d6c92 1463
15ec4461 1464 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1465
3ab9c8da
PR		 1466 if ((ios->timing == MMC_TIMING_SD_HS ||
1467 ios->timing == MMC_TIMING_MMC_HS)
1468 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1469 ctrl |= SDHCI_CTRL_HISPD;
1470 else
1471 ctrl &= ~SDHCI_CTRL_HISPD;
1472
d6d50a15 1473 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1474 u16 clk, ctrl_2;
49c468fc
AN		 1475
1476 /* In case of UHS-I modes, set High Speed Enable */
069c9f14
G		 1477 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1478 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1479 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1480 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1481 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1482 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1483
1484 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1485 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1486 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1487 /*
1488 * We only need to set Driver Strength if the
1489 * preset value enable is not set.
1490 */
1491 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1492 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1493 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1494 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1495 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1496
1497 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1498 } else {
1499 /*
1500 * According to SDHC Spec v3.00, if the Preset Value
1501 * Enable in the Host Control 2 register is set, we
1502 * need to reset SD Clock Enable before changing High
1503 * Speed Enable to avoid generating clock gliches.
1504 */
758535c4
AN		 1505
1506 /* Reset SD Clock Enable */
1507 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1508 clk &= ~SDHCI_CLOCK_CARD_EN;
1509 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1510
1511 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1512
1513 /* Re-enable SD Clock */
8213af3b 1514 sdhci_update_clock(host);
d6d50a15 1515 }
49c468fc 1516
49c468fc
AN		 1517
1518 /* Reset SD Clock Enable */
1519 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1520 clk &= ~SDHCI_CLOCK_CARD_EN;
1521 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1522
6322cdd0
PR		 1523 if (host->ops->set_uhs_signaling)
1524 host->ops->set_uhs_signaling(host, ios->timing);
1525 else {
1526 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1527 /* Select Bus Speed Mode for host */
1528 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
069c9f14
G		 1529 if (ios->timing == MMC_TIMING_MMC_HS200)
1530 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1531 else if (ios->timing == MMC_TIMING_UHS_SDR12)
6322cdd0
PR		 1532 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1533 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1534 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1535 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1536 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1537 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1538 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1539 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1540 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1541 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1542 }
49c468fc 1543
52983382
KL		 1544 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1545 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1546 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1547 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1548 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1549 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1550 u16 preset;
1551
1552 sdhci_enable_preset_value(host, true);
1553 preset = sdhci_get_preset_value(host);
1554 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1555 >> SDHCI_PRESET_DRV_SHIFT;
1556 }
1557
49c468fc 1558 /* Re-enable SD Clock */
8213af3b 1559 sdhci_update_clock(host);
758535c4
AN		 1560 } else
1561 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1562
b8352260
LD		 1563 /*
1564 * Some (ENE) controllers go apeshit on some ios operation,
1565 * signalling timeout and CRC errors even on CMD0. Resetting
1566 * it on each ios seems to solve the problem.
1567 */
b8c86fc5 1568 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1569 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1570
5f25a66f 1571 mmiowb();
d129bceb
PO		 1572 spin_unlock_irqrestore(&host->lock, flags);
1573}
1574
66fd8ad5
AH		 1575static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1576{
1577 struct sdhci_host *host = mmc_priv(mmc);
1578
1579 sdhci_runtime_pm_get(host);
1580 sdhci_do_set_ios(host, ios);
1581 sdhci_runtime_pm_put(host);
1582}
1583
1584static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1585{
d129bceb 1586 unsigned long flags;
2dfb579c 1587 int is_readonly;
d129bceb 1588
d129bceb
PO		 1589 spin_lock_irqsave(&host->lock, flags);
1590
1e72859e 1591 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1592 is_readonly = 0;
1593 else if (host->ops->get_ro)
1594 is_readonly = host->ops->get_ro(host);
1e72859e 1595 else
2dfb579c
WS		 1596 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1597 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1598
1599 spin_unlock_irqrestore(&host->lock, flags);
1600
2dfb579c
WS		 1601 /* This quirk needs to be replaced by a callback-function later */
1602 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1603 !is_readonly : is_readonly;
d129bceb
PO		 1604}
1605
82b0e23a
TI		 1606#define SAMPLE_COUNT 5
1607
66fd8ad5 1608static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1609{
82b0e23a
TI		 1610 int i, ro_count;
1611
82b0e23a 1612 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1613 return sdhci_check_ro(host);
82b0e23a
TI		 1614
1615 ro_count = 0;
1616 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1617 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1618 if (++ro_count > SAMPLE_COUNT / 2)
1619 return 1;
1620 }
1621 msleep(30);
1622 }
1623 return 0;
1624}
1625
20758b66
AH		 1626static void sdhci_hw_reset(struct mmc_host *mmc)
1627{
1628 struct sdhci_host *host = mmc_priv(mmc);
1629
1630 if (host->ops && host->ops->hw_reset)
1631 host->ops->hw_reset(host);
1632}
1633
66fd8ad5 1634static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1635{
66fd8ad5
AH		 1636 struct sdhci_host *host = mmc_priv(mmc);
1637 int ret;
f75979b7 1638
66fd8ad5
AH		 1639 sdhci_runtime_pm_get(host);
1640 ret = sdhci_do_get_ro(host);
1641 sdhci_runtime_pm_put(host);
1642 return ret;
1643}
f75979b7 1644
66fd8ad5
AH		 1645static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1646{
1e72859e
PO		 1647 if (host->flags & SDHCI_DEVICE_DEAD)
1648 goto out;
1649
66fd8ad5
AH		 1650 if (enable)
1651 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1652 else
1653 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1654
1655 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1656 if (host->runtime_suspended)
1657 goto out;
1658
f75979b7 1659 if (enable)
7260cf5e
AV		 1660 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1661 else
1662 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1663out:
f75979b7 1664 mmiowb();
66fd8ad5
AH		 1665}
1666
1667static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1668{
1669 struct sdhci_host *host = mmc_priv(mmc);
1670 unsigned long flags;
f75979b7 1671
66fd8ad5
AH		 1672 spin_lock_irqsave(&host->lock, flags);
1673 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1674 spin_unlock_irqrestore(&host->lock, flags);
1675}
1676
20b92a30 1677static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1678 struct mmc_ios *ios)
f2119df6 1679{
20b92a30 1680 u16 ctrl;
6231f3de 1681 int ret;
f2119df6 1682
20b92a30
KL		 1683 /*
1684 * Signal Voltage Switching is only applicable for Host Controllers
1685 * v3.00 and above.
1686 */
1687 if (host->version < SDHCI_SPEC_300)
1688 return 0;
6231f3de 1689
f2119df6 1690 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1691
21f5998f 1692 switch (ios->signal_voltage) {
20b92a30
KL		 1693 case MMC_SIGNAL_VOLTAGE_330:
1694 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1695 ctrl &= ~SDHCI_CTRL_VDD_180;
1696 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1697
20b92a30
KL		 1698 if (host->vqmmc) {
1699 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1700 if (ret) {
1701 pr_warning("%s: Switching to 3.3V signalling voltage "
1702 " failed\n", mmc_hostname(host->mmc));
1703 return -EIO;
1704 }
1705 }
1706 /* Wait for 5ms */
1707 usleep_range(5000, 5500);
f2119df6 1708
20b92a30
KL		 1709 /* 3.3V regulator output should be stable within 5 ms */
1710 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1711 if (!(ctrl & SDHCI_CTRL_VDD_180))
1712 return 0;
6231f3de 1713
20b92a30
KL		 1714 pr_warning("%s: 3.3V regulator output did not became stable\n",
1715 mmc_hostname(host->mmc));
1716
1717 return -EAGAIN;
1718 case MMC_SIGNAL_VOLTAGE_180:
1719 if (host->vqmmc) {
1720 ret = regulator_set_voltage(host->vqmmc,
1721 1700000, 1950000);
1722 if (ret) {
1723 pr_warning("%s: Switching to 1.8V signalling voltage "
1724 " failed\n", mmc_hostname(host->mmc));
1725 return -EIO;
1726 }
1727 }
6231f3de 1728
6231f3de
PR		 1729 /*
1730 * Enable 1.8V Signal Enable in the Host Control2
1731 * register
1732 */
20b92a30
KL		 1733 ctrl |= SDHCI_CTRL_VDD_180;
1734 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1735
20b92a30
KL		 1736 /* Wait for 5ms */
1737 usleep_range(5000, 5500);
f2119df6 1738
20b92a30
KL		 1739 /* 1.8V regulator output should be stable within 5 ms */
1740 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1741 if (ctrl & SDHCI_CTRL_VDD_180)
1742 return 0;
f2119df6 1743
20b92a30
KL		 1744 pr_warning("%s: 1.8V regulator output did not became stable\n",
1745 mmc_hostname(host->mmc));
f2119df6 1746
20b92a30
KL		 1747 return -EAGAIN;
1748 case MMC_SIGNAL_VOLTAGE_120:
1749 if (host->vqmmc) {
1750 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1751 if (ret) {
1752 pr_warning("%s: Switching to 1.2V signalling voltage "
1753 " failed\n", mmc_hostname(host->mmc));
1754 return -EIO;
f2119df6
AN		 1755 }
1756 }
6231f3de 1757 return 0;
20b92a30 1758 default:
f2119df6
AN		 1759 /* No signal voltage switch required */
1760 return 0;
20b92a30 1761 }
f2119df6
AN		 1762}
1763
66fd8ad5 1764static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1765 struct mmc_ios *ios)
66fd8ad5
AH		 1766{
1767 struct sdhci_host *host = mmc_priv(mmc);
1768 int err;
1769
1770 if (host->version < SDHCI_SPEC_300)
1771 return 0;
1772 sdhci_runtime_pm_get(host);
21f5998f 1773 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1774 sdhci_runtime_pm_put(host);
1775 return err;
1776}
1777
20b92a30
KL		 1778static int sdhci_card_busy(struct mmc_host *mmc)
1779{
1780 struct sdhci_host *host = mmc_priv(mmc);
1781 u32 present_state;
1782
1783 sdhci_runtime_pm_get(host);
1784 /* Check whether DAT[3:0] is 0000 */
1785 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1786 sdhci_runtime_pm_put(host);
1787
1788 return !(present_state & SDHCI_DATA_LVL_MASK);
1789}
1790
069c9f14 1791static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25
AN		 1792{
1793 struct sdhci_host *host;
1794 u16 ctrl;
1795 u32 ier;
1796 int tuning_loop_counter = MAX_TUNING_LOOP;
1797 unsigned long timeout;
1798 int err = 0;
069c9f14 1799 bool requires_tuning_nonuhs = false;
b513ea25
AN		 1800
1801 host = mmc_priv(mmc);
1802
66fd8ad5 1803 sdhci_runtime_pm_get(host);
b513ea25
AN		 1804 disable_irq(host->irq);
1805 spin_lock(&host->lock);
1806
1807 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1808
1809 /*
069c9f14
G		 1810 * The Host Controller needs tuning only in case of SDR104 mode
1811 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1812 * Capabilities register.
069c9f14
G		 1813 * If the Host Controller supports the HS200 mode then the
1814 * tuning function has to be executed.
b513ea25 1815 */
069c9f14
G		 1816 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1817 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1818 host->flags & SDHCI_HS200_NEEDS_TUNING))
1819 requires_tuning_nonuhs = true;
1820
b513ea25 1821 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
069c9f14 1822 requires_tuning_nonuhs)
b513ea25
AN		 1823 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1824 else {
1825 spin_unlock(&host->lock);
1826 enable_irq(host->irq);
66fd8ad5 1827 sdhci_runtime_pm_put(host);
b513ea25
AN		 1828 return 0;
1829 }
1830
1831 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1832
1833 /*
1834 * As per the Host Controller spec v3.00, tuning command
1835 * generates Buffer Read Ready interrupt, so enable that.
1836 *
1837 * Note: The spec clearly says that when tuning sequence
1838 * is being performed, the controller does not generate
1839 * interrupts other than Buffer Read Ready interrupt. But
1840 * to make sure we don't hit a controller bug, we _only_
1841 * enable Buffer Read Ready interrupt here.
1842 */
1843 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1844 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1845
1846 /*
1847 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1848 * of loops reaches 40 times or a timeout of 150ms occurs.
1849 */
1850 timeout = 150;
1851 do {
1852 struct mmc_command cmd = {0};
66fd8ad5 1853 struct mmc_request mrq = {NULL};
b513ea25
AN		 1854
1855 if (!tuning_loop_counter && !timeout)
1856 break;
1857
069c9f14 1858 cmd.opcode = opcode;
b513ea25
AN		 1859 cmd.arg = 0;
1860 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1861 cmd.retries = 0;
1862 cmd.data = NULL;
1863 cmd.error = 0;
1864
1865 mrq.cmd = &cmd;
1866 host->mrq = &mrq;
1867
1868 /*
1869 * In response to CMD19, the card sends 64 bytes of tuning
1870 * block to the Host Controller. So we set the block size
1871 * to 64 here.
1872 */
069c9f14
G		 1873 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1874 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1875 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1876 SDHCI_BLOCK_SIZE);
1877 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1878 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1879 SDHCI_BLOCK_SIZE);
1880 } else {
1881 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1882 SDHCI_BLOCK_SIZE);
1883 }
b513ea25
AN		 1884
1885 /*
1886 * The tuning block is sent by the card to the host controller.
1887 * So we set the TRNS_READ bit in the Transfer Mode register.
1888 * This also takes care of setting DMA Enable and Multi Block
1889 * Select in the same register to 0.
1890 */
1891 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1892
1893 sdhci_send_command(host, &cmd);
1894
1895 host->cmd = NULL;
1896 host->mrq = NULL;
1897
1898 spin_unlock(&host->lock);
1899 enable_irq(host->irq);
1900
1901 /* Wait for Buffer Read Ready interrupt */
1902 wait_event_interruptible_timeout(host->buf_ready_int,
1903 (host->tuning_done == 1),
1904 msecs_to_jiffies(50));
1905 disable_irq(host->irq);
1906 spin_lock(&host->lock);
1907
1908 if (!host->tuning_done) {
a3c76eb9 1909 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1910 "Buffer Read Ready interrupt during tuning "
1911 "procedure, falling back to fixed sampling "
1912 "clock\n");
1913 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1914 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1915 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1916 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1917
1918 err = -EIO;
1919 goto out;
1920 }
1921
1922 host->tuning_done = 0;
1923
1924 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1925 tuning_loop_counter--;
1926 timeout--;
1927 mdelay(1);
1928 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1929
1930 /*
1931 * The Host Driver has exhausted the maximum number of loops allowed,
1932 * so use fixed sampling frequency.
1933 */
1934 if (!tuning_loop_counter || !timeout) {
1935 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1936 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1937 } else {
1938 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1939 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1940 " failed, falling back to fixed sampling"
1941 " clock\n");
1942 err = -EIO;
1943 }
1944 }
1945
1946out:
cf2b5eea
AN		 1947 /*
1948 * If this is the very first time we are here, we start the retuning
1949 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1950 * flag won't be set, we check this condition before actually starting
1951 * the timer.
1952 */
1953 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1954 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 1955 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 1956 mod_timer(&host->tuning_timer, jiffies +
1957 host->tuning_count * HZ);
1958 /* Tuning mode 1 limits the maximum data length to 4MB */
1959 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1960 } else {
1961 host->flags &= ~SDHCI_NEEDS_RETUNING;
1962 /* Reload the new initial value for timer */
1963 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1964 mod_timer(&host->tuning_timer, jiffies +
1965 host->tuning_count * HZ);
1966 }
1967
1968 /*
1969 * In case tuning fails, host controllers which support re-tuning can
1970 * try tuning again at a later time, when the re-tuning timer expires.
1971 * So for these controllers, we return 0. Since there might be other
1972 * controllers who do not have this capability, we return error for
973905fe
AL		 1973 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
1974 * a retuning timer to do the retuning for the card.
cf2b5eea 1975 */
973905fe 1976 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 1977 err = 0;
1978
b513ea25
AN		 1979 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1980 spin_unlock(&host->lock);
1981 enable_irq(host->irq);
66fd8ad5 1982 sdhci_runtime_pm_put(host);
b513ea25
AN		 1983
1984 return err;
1985}
1986
52983382
KL		 1987
1988static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 1989{
4d55c5a1 1990 u16 ctrl;
4d55c5a1 1991
4d55c5a1
AN		 1992 /* Host Controller v3.00 defines preset value registers */
1993 if (host->version < SDHCI_SPEC_300)
1994 return;
1995
4d55c5a1
AN		 1996 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1997
1998 /*
1999 * We only enable or disable Preset Value if they are not already
2000 * enabled or disabled respectively. Otherwise, we bail out.
2001 */
2002 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2003 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2004 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2005 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 2006 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2007 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2008 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 2009 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1 2010 }
66fd8ad5
AH		 2011}
2012
71e69211 2013static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2014{
71e69211 2015 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2016 unsigned long flags;
2017
d129bceb
PO		 2018 spin_lock_irqsave(&host->lock, flags);
2019
66fd8ad5
AH		 2020 /* Check host->mrq first in case we are runtime suspended */
2021 if (host->mrq &&
2022 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
a3c76eb9 2023 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2024 mmc_hostname(host->mmc));
a3c76eb9 2025 pr_err("%s: Resetting controller.\n",
66fd8ad5 2026 mmc_hostname(host->mmc));
d129bceb 2027
66fd8ad5
AH		 2028 sdhci_reset(host, SDHCI_RESET_CMD);
2029 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 2030
66fd8ad5
AH		 2031 host->mrq->cmd->error = -ENOMEDIUM;
2032 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2033 }
2034
2035 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2036}
2037
2038static const struct mmc_host_ops sdhci_ops = {
2039 .request = sdhci_request,
2040 .set_ios = sdhci_set_ios,
2041 .get_ro = sdhci_get_ro,
2042 .hw_reset = sdhci_hw_reset,
2043 .enable_sdio_irq = sdhci_enable_sdio_irq,
2044 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2045 .execute_tuning = sdhci_execute_tuning,
71e69211 2046 .card_event = sdhci_card_event,
20b92a30 2047 .card_busy = sdhci_card_busy,
71e69211
GL		 2048};
2049
2050/*****************************************************************************\
2051 * *
2052 * Tasklets *
2053 * *
2054\*****************************************************************************/
2055
2056static void sdhci_tasklet_card(unsigned long param)
2057{
2058 struct sdhci_host *host = (struct sdhci_host*)param;
2059
2060 sdhci_card_event(host->mmc);
d129bceb 2061
04cf585d 2062 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 2063}
2064
2065static void sdhci_tasklet_finish(unsigned long param)
2066{
2067 struct sdhci_host *host;
2068 unsigned long flags;
2069 struct mmc_request *mrq;
2070
2071 host = (struct sdhci_host*)param;
2072
66fd8ad5
AH		 2073 spin_lock_irqsave(&host->lock, flags);
2074
0c9c99a7
CB		 2075 /*
2076 * If this tasklet gets rescheduled while running, it will
2077 * be run again afterwards but without any active request.
2078 */
66fd8ad5
AH		 2079 if (!host->mrq) {
2080 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2081 return;
66fd8ad5 2082 }
d129bceb
PO		 2083
2084 del_timer(&host->timer);
2085
2086 mrq = host->mrq;
2087
d129bceb
PO		 2088 /*
2089 * The controller needs a reset of internal state machines
2090 * upon error conditions.
2091 */
1e72859e 2092 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2093 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2094 (mrq->data && (mrq->data->error ||
2095 (mrq->data->stop && mrq->data->stop->error))) ||
2096 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2097
2098 /* Some controllers need this kick or reset won't work here */
8213af3b 2099 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2100 /* This is to force an update */
8213af3b 2101 sdhci_update_clock(host);
645289dc
PO		 2102
2103 /* Spec says we should do both at the same time, but Ricoh
2104 controllers do not like that. */
d129bceb
PO		 2105 sdhci_reset(host, SDHCI_RESET_CMD);
2106 sdhci_reset(host, SDHCI_RESET_DATA);
2107 }
2108
2109 host->mrq = NULL;
2110 host->cmd = NULL;
2111 host->data = NULL;
2112
f9134319 2113#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2114 sdhci_deactivate_led(host);
2f730fec 2115#endif
d129bceb 2116
5f25a66f 2117 mmiowb();
d129bceb
PO		 2118 spin_unlock_irqrestore(&host->lock, flags);
2119
2120 mmc_request_done(host->mmc, mrq);
66fd8ad5 2121 sdhci_runtime_pm_put(host);
d129bceb
PO		 2122}
2123
2124static void sdhci_timeout_timer(unsigned long data)
2125{
2126 struct sdhci_host *host;
2127 unsigned long flags;
2128
2129 host = (struct sdhci_host*)data;
2130
2131 spin_lock_irqsave(&host->lock, flags);
2132
2133 if (host->mrq) {
a3c76eb9 2134 pr_err("%s: Timeout waiting for hardware "
acf1da45 2135 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2136 sdhci_dumpregs(host);
2137
2138 if (host->data) {
17b0429d 2139 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2140 sdhci_finish_data(host);
2141 } else {
2142 if (host->cmd)
17b0429d 2143 host->cmd->error = -ETIMEDOUT;
d129bceb 2144 else
17b0429d 2145 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2146
2147 tasklet_schedule(&host->finish_tasklet);
2148 }
2149 }
2150
5f25a66f 2151 mmiowb();
d129bceb
PO		 2152 spin_unlock_irqrestore(&host->lock, flags);
2153}
2154
cf2b5eea
AN		 2155static void sdhci_tuning_timer(unsigned long data)
2156{
2157 struct sdhci_host *host;
2158 unsigned long flags;
2159
2160 host = (struct sdhci_host *)data;
2161
2162 spin_lock_irqsave(&host->lock, flags);
2163
2164 host->flags |= SDHCI_NEEDS_RETUNING;
2165
2166 spin_unlock_irqrestore(&host->lock, flags);
2167}
2168
d129bceb
PO		 2169/*****************************************************************************\
2170 * *
2171 * Interrupt handling *
2172 * *
2173\*****************************************************************************/
2174
2175static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2176{
2177 BUG_ON(intmask == 0);
2178
2179 if (!host->cmd) {
a3c76eb9 2180 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2181 "though no command operation was in progress.\n",
2182 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2183 sdhci_dumpregs(host);
2184 return;
2185 }
2186
43b58b36 2187 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2188 host->cmd->error = -ETIMEDOUT;
2189 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2190 SDHCI_INT_INDEX))
2191 host->cmd->error = -EILSEQ;
43b58b36 2192
e809517f 2193 if (host->cmd->error) {
d129bceb 2194 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2195 return;
2196 }
2197
2198 /*
2199 * The host can send and interrupt when the busy state has
2200 * ended, allowing us to wait without wasting CPU cycles.
2201 * Unfortunately this is overloaded on the "data complete"
2202 * interrupt, so we need to take some care when handling
2203 * it.
2204 *
2205 * Note: The 1.0 specification is a bit ambiguous about this
2206 * feature so there might be some problems with older
2207 * controllers.
2208 */
2209 if (host->cmd->flags & MMC_RSP_BUSY) {
2210 if (host->cmd->data)
2211 DBG("Cannot wait for busy signal when also "
2212 "doing a data transfer");
f945405c 2213 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2214 return;
f945405c
BD		 2215
2216 /* The controller does not support the end-of-busy IRQ,
2217 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2218 }
2219
2220 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2221 sdhci_finish_command(host);
d129bceb
PO		 2222}
2223
0957c333 2224#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2225static void sdhci_show_adma_error(struct sdhci_host *host)
2226{
2227 const char *name = mmc_hostname(host->mmc);
2228 u8 *desc = host->adma_desc;
2229 __le32 *dma;
2230 __le16 *len;
2231 u8 attr;
2232
2233 sdhci_dumpregs(host);
2234
2235 while (true) {
2236 dma = (__le32 *)(desc + 4);
2237 len = (__le16 *)(desc + 2);
2238 attr = *desc;
2239
2240 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2241 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2242
2243 desc += 8;
2244
2245 if (attr & 2)
2246 break;
2247 }
2248}
2249#else
2250static void sdhci_show_adma_error(struct sdhci_host *host) { }
2251#endif
2252
d129bceb
PO		 2253static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2254{
069c9f14 2255 u32 command;
d129bceb
PO		 2256 BUG_ON(intmask == 0);
2257
b513ea25
AN		 2258 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2259 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2260 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2261 if (command == MMC_SEND_TUNING_BLOCK ||
2262 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2263 host->tuning_done = 1;
2264 wake_up(&host->buf_ready_int);
2265 return;
2266 }
2267 }
2268
d129bceb
PO		 2269 if (!host->data) {
2270 /*
e809517f
PO		 2271 * The "data complete" interrupt is also used to
2272 * indicate that a busy state has ended. See comment
2273 * above in sdhci_cmd_irq().
d129bceb 2274 */
e809517f
PO		 2275 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2276 if (intmask & SDHCI_INT_DATA_END) {
2277 sdhci_finish_command(host);
2278 return;
2279 }
2280 }
d129bceb 2281
a3c76eb9 2282 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2283 "though no data operation was in progress.\n",
2284 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2285 sdhci_dumpregs(host);
2286
2287 return;
2288 }
2289
2290 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2291 host->data->error = -ETIMEDOUT;
22113efd
AL		 2292 else if (intmask & SDHCI_INT_DATA_END_BIT)
2293 host->data->error = -EILSEQ;
2294 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2295 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2296 != MMC_BUS_TEST_R)
17b0429d 2297 host->data->error = -EILSEQ;
6882a8c0 2298 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2299 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2300 sdhci_show_adma_error(host);
2134a922 2301 host->data->error = -EIO;
a4071fbb
HZ		 2302 if (host->ops->adma_workaround)
2303 host->ops->adma_workaround(host, intmask);
6882a8c0 2304 }
d129bceb 2305
17b0429d 2306 if (host->data->error)
d129bceb
PO		 2307 sdhci_finish_data(host);
2308 else {
a406f5a3 2309 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2310 sdhci_transfer_pio(host);
2311
6ba736a1
PO		 2312 /*
2313 * We currently don't do anything fancy with DMA
2314 * boundaries, but as we can't disable the feature
2315 * we need to at least restart the transfer.
f6a03cbf
MV		 2316 *
2317 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2318 * should return a valid address to continue from, but as
2319 * some controllers are faulty, don't trust them.
6ba736a1 2320 */
f6a03cbf
MV		 2321 if (intmask & SDHCI_INT_DMA_END) {
2322 u32 dmastart, dmanow;
2323 dmastart = sg_dma_address(host->data->sg);
2324 dmanow = dmastart + host->data->bytes_xfered;
2325 /*
2326 * Force update to the next DMA block boundary.
2327 */
2328 dmanow = (dmanow &
2329 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2330 SDHCI_DEFAULT_BOUNDARY_SIZE;
2331 host->data->bytes_xfered = dmanow - dmastart;
2332 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2333 " next 0x%08x\n",
2334 mmc_hostname(host->mmc), dmastart,
2335 host->data->bytes_xfered, dmanow);
2336 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2337 }
6ba736a1 2338
e538fbe8
PO		 2339 if (intmask & SDHCI_INT_DATA_END) {
2340 if (host->cmd) {
2341 /*
2342 * Data managed to finish before the
2343 * command completed. Make sure we do
2344 * things in the proper order.
2345 */
2346 host->data_early = 1;
2347 } else {
2348 sdhci_finish_data(host);
2349 }
2350 }
d129bceb
PO		 2351 }
2352}
2353
7d12e780 2354static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2355{
2356 irqreturn_t result;
66fd8ad5 2357 struct sdhci_host *host = dev_id;
6379b237
AS		 2358 u32 intmask, unexpected = 0;
2359 int cardint = 0, max_loops = 16;
d129bceb
PO		 2360
2361 spin_lock(&host->lock);
2362
66fd8ad5
AH		 2363 if (host->runtime_suspended) {
2364 spin_unlock(&host->lock);
a3c76eb9 2365 pr_warning("%s: got irq while runtime suspended\n",
66fd8ad5
AH		 2366 mmc_hostname(host->mmc));
2367 return IRQ_HANDLED;
2368 }
2369
4e4141a5 2370 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2371
62df67a5 2372 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2373 result = IRQ_NONE;
2374 goto out;
2375 }
2376
6379b237 2377again:
b69c9058
PO		 2378 DBG("*** %s got interrupt: 0x%08x\n",
2379 mmc_hostname(host->mmc), intmask);
d129bceb 2380
3192a28f 2381 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2382 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2383 SDHCI_CARD_PRESENT;
2384
2385 /*
2386 * There is a observation on i.mx esdhc. INSERT bit will be
2387 * immediately set again when it gets cleared, if a card is
2388 * inserted. We have to mask the irq to prevent interrupt
2389 * storm which will freeze the system. And the REMOVE gets
2390 * the same situation.
2391 *
2392 * More testing are needed here to ensure it works for other
2393 * platforms though.
2394 */
2395 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2396 SDHCI_INT_CARD_REMOVE);
2397 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2398 SDHCI_INT_CARD_INSERT);
2399
4e4141a5 2400 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2401 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2402 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2403 tasklet_schedule(&host->card_tasklet);
3192a28f 2404 }
d129bceb 2405
3192a28f 2406 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2407 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2408 SDHCI_INT_STATUS);
3192a28f 2409 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2410 }
2411
2412 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2413 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2414 SDHCI_INT_STATUS);
3192a28f 2415 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2416 }
2417
2418 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2419
964f9ce2
PO		 2420 intmask &= ~SDHCI_INT_ERROR;
2421
d129bceb 2422 if (intmask & SDHCI_INT_BUS_POWER) {
a3c76eb9 2423 pr_err("%s: Card is consuming too much power!\n",
d129bceb 2424 mmc_hostname(host->mmc));
4e4141a5 2425 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2426 }
2427
9d26a5d3 2428 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2429
f75979b7
PO		 2430 if (intmask & SDHCI_INT_CARD_INT)
2431 cardint = 1;
2432
2433 intmask &= ~SDHCI_INT_CARD_INT;
2434
3192a28f 2435 if (intmask) {
6379b237 2436 unexpected |= intmask;
4e4141a5 2437 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2438 }
d129bceb
PO		 2439
2440 result = IRQ_HANDLED;
2441
6379b237
AS		 2442 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2443 if (intmask && --max_loops)
2444 goto again;
d129bceb
PO		 2445out:
2446 spin_unlock(&host->lock);
2447
6379b237
AS		 2448 if (unexpected) {
2449 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2450 mmc_hostname(host->mmc), unexpected);
2451 sdhci_dumpregs(host);
2452 }
f75979b7
PO		 2453 /*
2454 * We have to delay this as it calls back into the driver.
2455 */
2456 if (cardint)
2457 mmc_signal_sdio_irq(host->mmc);
2458
d129bceb
PO		 2459 return result;
2460}
2461
2462/*****************************************************************************\
2463 * *
2464 * Suspend/resume *
2465 * *
2466\*****************************************************************************/
2467
2468#ifdef CONFIG_PM
ad080d79
KL		 2469void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2470{
2471 u8 val;
2472 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2473 | SDHCI_WAKE_ON_INT;
2474
2475 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2476 val |= mask ;
2477 /* Avoid fake wake up */
2478 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2479 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2480 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2481}
2482EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2483
2484void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2485{
2486 u8 val;
2487 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2488 | SDHCI_WAKE_ON_INT;
2489
2490 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2491 val &= ~mask;
2492 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2493}
2494EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2495
29495aa0 2496int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2497{
b8c86fc5 2498 int ret;
a715dfc7 2499
a1b13b4e
CB		 2500 if (host->ops->platform_suspend)
2501 host->ops->platform_suspend(host);
2502
7260cf5e
AV		 2503 sdhci_disable_card_detection(host);
2504
cf2b5eea 2505 /* Disable tuning since we are suspending */
973905fe 2506 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2507 del_timer_sync(&host->tuning_timer);
cf2b5eea 2508 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2509 }
2510
1a13f8fa 2511 ret = mmc_suspend_host(host->mmc);
38a60ea2 2512 if (ret) {
973905fe 2513 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
38a60ea2
AL		 2514 host->flags |= SDHCI_NEEDS_RETUNING;
2515 mod_timer(&host->tuning_timer, jiffies +
2516 host->tuning_count * HZ);
2517 }
2518
2519 sdhci_enable_card_detection(host);
2520
b8c86fc5 2521 return ret;
38a60ea2 2522 }
a715dfc7 2523
ad080d79
KL		 2524 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2525 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2526 free_irq(host->irq, host);
2527 } else {
2528 sdhci_enable_irq_wakeups(host);
2529 enable_irq_wake(host->irq);
2530 }
9bea3c85 2531 return ret;
d129bceb
PO		 2532}
2533
b8c86fc5 2534EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2535
b8c86fc5
PO		 2536int sdhci_resume_host(struct sdhci_host *host)
2537{
2538 int ret;
d129bceb 2539
a13abc7b 2540 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2541 if (host->ops->enable_dma)
2542 host->ops->enable_dma(host);
2543 }
d129bceb 2544
ad080d79
KL		 2545 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2546 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2547 mmc_hostname(host->mmc), host);
2548 if (ret)
2549 return ret;
2550 } else {
2551 sdhci_disable_irq_wakeups(host);
2552 disable_irq_wake(host->irq);
2553 }
d129bceb 2554
6308d290
AH		 2555 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2556 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2557 /* Card keeps power but host controller does not */
2558 sdhci_init(host, 0);
2559 host->pwr = 0;
2560 host->clock = 0;
2561 sdhci_do_set_ios(host, &host->mmc->ios);
2562 } else {
2563 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2564 mmiowb();
2565 }
b8c86fc5
PO		 2566
2567 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2568 sdhci_enable_card_detection(host);
2569
a1b13b4e
CB		 2570 if (host->ops->platform_resume)
2571 host->ops->platform_resume(host);
2572
cf2b5eea 2573 /* Set the re-tuning expiration flag */
973905fe 2574 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2575 host->flags |= SDHCI_NEEDS_RETUNING;
2576
2f4cbb3d 2577 return ret;
d129bceb
PO		 2578}
2579
b8c86fc5 2580EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2581#endif /* CONFIG_PM */
2582
66fd8ad5
AH		 2583#ifdef CONFIG_PM_RUNTIME
2584
2585static int sdhci_runtime_pm_get(struct sdhci_host *host)
2586{
2587 return pm_runtime_get_sync(host->mmc->parent);
2588}
2589
2590static int sdhci_runtime_pm_put(struct sdhci_host *host)
2591{
2592 pm_runtime_mark_last_busy(host->mmc->parent);
2593 return pm_runtime_put_autosuspend(host->mmc->parent);
2594}
2595
2596int sdhci_runtime_suspend_host(struct sdhci_host *host)
2597{
2598 unsigned long flags;
2599 int ret = 0;
2600
2601 /* Disable tuning since we are suspending */
973905fe 2602 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2603 del_timer_sync(&host->tuning_timer);
2604 host->flags &= ~SDHCI_NEEDS_RETUNING;
2605 }
2606
2607 spin_lock_irqsave(&host->lock, flags);
2608 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2609 spin_unlock_irqrestore(&host->lock, flags);
2610
2611 synchronize_irq(host->irq);
2612
2613 spin_lock_irqsave(&host->lock, flags);
2614 host->runtime_suspended = true;
2615 spin_unlock_irqrestore(&host->lock, flags);
2616
2617 return ret;
2618}
2619EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2620
2621int sdhci_runtime_resume_host(struct sdhci_host *host)
2622{
2623 unsigned long flags;
2624 int ret = 0, host_flags = host->flags;
2625
2626 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2627 if (host->ops->enable_dma)
2628 host->ops->enable_dma(host);
2629 }
2630
2631 sdhci_init(host, 0);
2632
2633 /* Force clock and power re-program */
2634 host->pwr = 0;
2635 host->clock = 0;
2636 sdhci_do_set_ios(host, &host->mmc->ios);
2637
2638 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2639 if ((host_flags & SDHCI_PV_ENABLED) &&
2640 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2641 spin_lock_irqsave(&host->lock, flags);
2642 sdhci_enable_preset_value(host, true);
2643 spin_unlock_irqrestore(&host->lock, flags);
2644 }
66fd8ad5
AH		 2645
2646 /* Set the re-tuning expiration flag */
973905fe 2647 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2648 host->flags |= SDHCI_NEEDS_RETUNING;
2649
2650 spin_lock_irqsave(&host->lock, flags);
2651
2652 host->runtime_suspended = false;
2653
2654 /* Enable SDIO IRQ */
2655 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2656 sdhci_enable_sdio_irq_nolock(host, true);
2657
2658 /* Enable Card Detection */
2659 sdhci_enable_card_detection(host);
2660
2661 spin_unlock_irqrestore(&host->lock, flags);
2662
2663 return ret;
2664}
2665EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2666
2667#endif
2668
d129bceb
PO		 2669/*****************************************************************************\
2670 * *
b8c86fc5 2671 * Device allocation/registration *
d129bceb
PO		 2672 * *
2673\*****************************************************************************/
2674
b8c86fc5
PO		 2675struct sdhci_host *sdhci_alloc_host(struct device *dev,
2676 size_t priv_size)
d129bceb 2677{
d129bceb
PO		 2678 struct mmc_host *mmc;
2679 struct sdhci_host *host;
2680
b8c86fc5 2681 WARN_ON(dev == NULL);
d129bceb 2682
b8c86fc5 2683 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2684 if (!mmc)
b8c86fc5 2685 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2686
2687 host = mmc_priv(mmc);
2688 host->mmc = mmc;
2689
b8c86fc5
PO		 2690 return host;
2691}
8a4da143 2692
b8c86fc5 2693EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2694
b8c86fc5
PO		 2695int sdhci_add_host(struct sdhci_host *host)
2696{
2697 struct mmc_host *mmc;
bd6a8c30 2698 u32 caps[2] = {0, 0};
f2119df6
AN		 2699 u32 max_current_caps;
2700 unsigned int ocr_avail;
b8c86fc5 2701 int ret;
d129bceb 2702
b8c86fc5
PO		 2703 WARN_ON(host == NULL);
2704 if (host == NULL)
2705 return -EINVAL;
d129bceb 2706
b8c86fc5 2707 mmc = host->mmc;
d129bceb 2708
b8c86fc5
PO		 2709 if (debug_quirks)
2710 host->quirks = debug_quirks;
66fd8ad5
AH		 2711 if (debug_quirks2)
2712 host->quirks2 = debug_quirks2;
d129bceb 2713
d96649ed
PO		 2714 sdhci_reset(host, SDHCI_RESET_ALL);
2715
4e4141a5 2716 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2717 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2718 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2719 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2720 pr_err("%s: Unknown controller version (%d). "
b69c9058 2721 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2722 host->version);
4a965505
PO		 2723 }
2724
f2119df6 2725 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2726 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2727
bd6a8c30
PR		 2728 if (host->version >= SDHCI_SPEC_300)
2729 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2730 host->caps1 :
2731 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2732
b8c86fc5 2733 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2734 host->flags |= SDHCI_USE_SDMA;
f2119df6 2735 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2736 DBG("Controller doesn't have SDMA capability\n");
67435274 2737 else
a13abc7b 2738 host->flags |= SDHCI_USE_SDMA;
d129bceb 2739
b8c86fc5 2740 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2741 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2742 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2743 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2744 }
2745
f2119df6
AN		 2746 if ((host->version >= SDHCI_SPEC_200) &&
2747 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2748 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2749
2750 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2751 (host->flags & SDHCI_USE_ADMA)) {
2752 DBG("Disabling ADMA as it is marked broken\n");
2753 host->flags &= ~SDHCI_USE_ADMA;
2754 }
2755
a13abc7b 2756 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2757 if (host->ops->enable_dma) {
2758 if (host->ops->enable_dma(host)) {
a3c76eb9 2759 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2760 "available. Falling back to PIO.\n",
2761 mmc_hostname(mmc));
a13abc7b
RR		 2762 host->flags &=
2763 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2764 }
d129bceb
PO		 2765 }
2766 }
2767
2134a922
PO		 2768 if (host->flags & SDHCI_USE_ADMA) {
2769 /*
2770 * We need to allocate descriptors for all sg entries
2771 * (128) and potentially one alignment transfer for
2772 * each of those entries.
2773 */
2774 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2775 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2776 if (!host->adma_desc || !host->align_buffer) {
2777 kfree(host->adma_desc);
2778 kfree(host->align_buffer);
a3c76eb9 2779 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2780 "buffers. Falling back to standard DMA.\n",
2781 mmc_hostname(mmc));
2782 host->flags &= ~SDHCI_USE_ADMA;
2783 }
2784 }
2785
7659150c
PO		 2786 /*
2787 * If we use DMA, then it's up to the caller to set the DMA
2788 * mask, but PIO does not need the hw shim so we set a new
2789 * mask here in that case.
2790 */
a13abc7b 2791 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2792 host->dma_mask = DMA_BIT_MASK(64);
2793 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2794 }
d129bceb 2795
c4687d5f 2796 if (host->version >= SDHCI_SPEC_300)
f2119df6 2797 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2798 >> SDHCI_CLOCK_BASE_SHIFT;
2799 else
f2119df6 2800 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2801 >> SDHCI_CLOCK_BASE_SHIFT;
2802
4240ff0a 2803 host->max_clk *= 1000000;
f27f47ef
AV		 2804 if (host->max_clk == 0 || host->quirks &
2805 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2806 if (!host->ops->get_max_clock) {
a3c76eb9 2807 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2808 "frequency.\n", mmc_hostname(mmc));
2809 return -ENODEV;
2810 }
2811 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2812 }
d129bceb 2813
c3ed3877
AN		 2814 /*
2815 * In case of Host Controller v3.00, find out whether clock
2816 * multiplier is supported.
2817 */
2818 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2819 SDHCI_CLOCK_MUL_SHIFT;
2820
2821 /*
2822 * In case the value in Clock Multiplier is 0, then programmable
2823 * clock mode is not supported, otherwise the actual clock
2824 * multiplier is one more than the value of Clock Multiplier
2825 * in the Capabilities Register.
2826 */
2827 if (host->clk_mul)
2828 host->clk_mul += 1;
2829
d129bceb
PO		 2830 /*
2831 * Set host parameters.
2832 */
2833 mmc->ops = &sdhci_ops;
c3ed3877 2834 mmc->f_max = host->max_clk;
ce5f036b 2835 if (host->ops->get_min_clock)
a9e58f25 2836 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2837 else if (host->version >= SDHCI_SPEC_300) {
2838 if (host->clk_mul) {
2839 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2840 mmc->f_max = host->max_clk * host->clk_mul;
2841 } else
2842 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2843 } else
0397526d 2844 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2845
272308ca
AS		 2846 host->timeout_clk =
2847 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2848 if (host->timeout_clk == 0) {
2849 if (host->ops->get_timeout_clock) {
2850 host->timeout_clk = host->ops->get_timeout_clock(host);
2851 } else if (!(host->quirks &
2852 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2853 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2854 "frequency.\n", mmc_hostname(mmc));
2855 return -ENODEV;
2856 }
2857 }
2858 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2859 host->timeout_clk *= 1000;
2860
2861 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2862 host->timeout_clk = mmc->f_max / 1000;
272308ca 2863
65be3fef 2864 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
58d1246d 2865
e89d456f
AW		 2866 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2867
2868 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2869 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2870
8edf6371 2871 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2872 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2873 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2874 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2875 host->flags |= SDHCI_AUTO_CMD23;
2876 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2877 } else {
2878 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2879 }
2880
15ec4461
PR		 2881 /*
2882 * A controller may support 8-bit width, but the board itself
2883 * might not have the pins brought out. Boards that support
2884 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2885 * their platform code before calling sdhci_add_host(), and we
2886 * won't assume 8-bit width for hosts without that CAP.
2887 */
5fe23c7f 2888 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2889 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2890
63ef5d8c
JH		 2891 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2892 mmc->caps &= ~MMC_CAP_CMD23;
2893
f2119df6 2894 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2895 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2896
176d1ed4 2897 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
eb6d5ae1 2898 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2899 mmc->caps |= MMC_CAP_NEEDS_POLL;
2900
6231f3de
PR		 2901 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2902 host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
657d5982
KL		 2903 if (IS_ERR_OR_NULL(host->vqmmc)) {
2904 if (PTR_ERR(host->vqmmc) < 0) {
2905 pr_info("%s: no vqmmc regulator found\n",
2906 mmc_hostname(mmc));
2907 host->vqmmc = NULL;
2908 }
8363c374 2909 } else {
6231f3de 2910 regulator_enable(host->vqmmc);
cec2e216
KL		 2911 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2912 1950000))
8363c374
KL		 2913 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2914 SDHCI_SUPPORT_SDR50 |
2915 SDHCI_SUPPORT_DDR50);
2916 }
6231f3de 2917
6a66180a
DD		 2918 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2919 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2920 SDHCI_SUPPORT_DDR50);
2921
4188bba0
AC		 2922 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2923 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2924 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 2925 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2926
2927 /* SDR104 supports also implies SDR50 support */
2928 if (caps[1] & SDHCI_SUPPORT_SDR104)
2929 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2930 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2931 mmc->caps |= MMC_CAP_UHS_SDR50;
2932
2933 if (caps[1] & SDHCI_SUPPORT_DDR50)
2934 mmc->caps |= MMC_CAP_UHS_DDR50;
2935
069c9f14 2936 /* Does the host need tuning for SDR50? */
b513ea25
AN		 2937 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2938 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2939
069c9f14
G		 2940 /* Does the host need tuning for HS200? */
2941 if (mmc->caps2 & MMC_CAP2_HS200)
2942 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2943
d6d50a15
AN		 2944 /* Driver Type(s) (A, C, D) supported by the host */
2945 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2946 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2947 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2948 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2949 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2950 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2951
cf2b5eea
AN		 2952 /* Initial value for re-tuning timer count */
2953 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2954 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2955
2956 /*
2957 * In case Re-tuning Timer is not disabled, the actual value of
2958 * re-tuning timer will be 2 ^ (n - 1).
2959 */
2960 if (host->tuning_count)
2961 host->tuning_count = 1 << (host->tuning_count - 1);
2962
2963 /* Re-tuning mode supported by the Host Controller */
2964 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2965 SDHCI_RETUNING_MODE_SHIFT;
2966
8f230f45 2967 ocr_avail = 0;
bad37e1a
PR		 2968
2969 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
657d5982
KL		 2970 if (IS_ERR_OR_NULL(host->vmmc)) {
2971 if (PTR_ERR(host->vmmc) < 0) {
2972 pr_info("%s: no vmmc regulator found\n",
2973 mmc_hostname(mmc));
2974 host->vmmc = NULL;
2975 }
8363c374 2976 }
bad37e1a 2977
68737043 2978#ifdef CONFIG_REGULATOR
a4f8f257
MS		 2979 /*
2980 * Voltage range check makes sense only if regulator reports
2981 * any voltage value.
2982 */
2983 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
cec2e216
KL		 2984 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
2985 3600000);
68737043
PR		 2986 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
2987 caps[0] &= ~SDHCI_CAN_VDD_330;
68737043
PR		 2988 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
2989 caps[0] &= ~SDHCI_CAN_VDD_300;
cec2e216
KL		 2990 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
2991 1950000);
68737043
PR		 2992 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
2993 caps[0] &= ~SDHCI_CAN_VDD_180;
2994 }
2995#endif /* CONFIG_REGULATOR */
2996
f2119df6
AN		 2997 /*
2998 * According to SD Host Controller spec v3.00, if the Host System
2999 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3000 * the value is meaningful only if Voltage Support in the Capabilities
3001 * register is set. The actual current value is 4 times the register
3002 * value.
3003 */
3004 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
bad37e1a
PR		 3005 if (!max_current_caps && host->vmmc) {
3006 u32 curr = regulator_get_current_limit(host->vmmc);
3007 if (curr > 0) {
3008
3009 /* convert to SDHCI_MAX_CURRENT format */
3010 curr = curr/1000; /* convert to mA */
3011 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3012
3013 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3014 max_current_caps =
3015 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3016 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3017 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3018 }
3019 }
f2119df6
AN		 3020
3021 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3022 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3023
55c4665e 3024 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3025 SDHCI_MAX_CURRENT_330_MASK) >>
3026 SDHCI_MAX_CURRENT_330_SHIFT) *
3027 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3028 }
3029 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3030 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3031
55c4665e 3032 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3033 SDHCI_MAX_CURRENT_300_MASK) >>
3034 SDHCI_MAX_CURRENT_300_SHIFT) *
3035 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3036 }
3037 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3038 ocr_avail |= MMC_VDD_165_195;
3039
55c4665e 3040 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3041 SDHCI_MAX_CURRENT_180_MASK) >>
3042 SDHCI_MAX_CURRENT_180_SHIFT) *
3043 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3044 }
3045
8f230f45
TI		 3046 mmc->ocr_avail = ocr_avail;
3047 mmc->ocr_avail_sdio = ocr_avail;
3048 if (host->ocr_avail_sdio)
3049 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3050 mmc->ocr_avail_sd = ocr_avail;
3051 if (host->ocr_avail_sd)
3052 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3053 else /* normal SD controllers don't support 1.8V */
3054 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3055 mmc->ocr_avail_mmc = ocr_avail;
3056 if (host->ocr_avail_mmc)
3057 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3058
3059 if (mmc->ocr_avail == 0) {
a3c76eb9 3060 pr_err("%s: Hardware doesn't report any "
b69c9058 3061 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3062 return -ENODEV;
146ad66e
PO		 3063 }
3064
d129bceb
PO		 3065 spin_lock_init(&host->lock);
3066
3067 /*
2134a922
PO		 3068 * Maximum number of segments. Depends on if the hardware
3069 * can do scatter/gather or not.
d129bceb 3070 */
2134a922 3071 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3072 mmc->max_segs = 128;
a13abc7b 3073 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3074 mmc->max_segs = 1;
2134a922 3075 else /* PIO */
a36274e0 3076 mmc->max_segs = 128;
d129bceb
PO		 3077
3078 /*
bab76961 3079 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3080 * size (512KiB).
d129bceb 3081 */
55db890a 3082 mmc->max_req_size = 524288;
d129bceb
PO		 3083
3084 /*
3085 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3086 * of bytes. When doing hardware scatter/gather, each entry cannot
3087 * be larger than 64 KiB though.
d129bceb 3088 */
30652aa3
OJ		 3089 if (host->flags & SDHCI_USE_ADMA) {
3090 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3091 mmc->max_seg_size = 65535;
3092 else
3093 mmc->max_seg_size = 65536;
3094 } else {
2134a922 3095 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3096 }
d129bceb 3097
fe4a3c7a
PO		 3098 /*
3099 * Maximum block size. This varies from controller to controller and
3100 * is specified in the capabilities register.
3101 */
0633f654
AV		 3102 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3103 mmc->max_blk_size = 2;
3104 } else {
f2119df6 3105 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3106 SDHCI_MAX_BLOCK_SHIFT;
3107 if (mmc->max_blk_size >= 3) {
a3c76eb9 3108 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3109 "assuming 512 bytes\n", mmc_hostname(mmc));
3110 mmc->max_blk_size = 0;
3111 }
3112 }
3113
3114 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3115
55db890a
PO		 3116 /*
3117 * Maximum block count.
3118 */
1388eefd 3119 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3120
d129bceb
PO		 3121 /*
3122 * Init tasklets.
3123 */
3124 tasklet_init(&host->card_tasklet,
3125 sdhci_tasklet_card, (unsigned long)host);
3126 tasklet_init(&host->finish_tasklet,
3127 sdhci_tasklet_finish, (unsigned long)host);
3128
e4cad1b5 3129 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3130
cf2b5eea 3131 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3132 init_waitqueue_head(&host->buf_ready_int);
3133
cf2b5eea
AN		 3134 /* Initialize re-tuning timer */
3135 init_timer(&host->tuning_timer);
3136 host->tuning_timer.data = (unsigned long)host;
3137 host->tuning_timer.function = sdhci_tuning_timer;
3138 }
3139
dace1453 3140 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 3141 mmc_hostname(mmc), host);
0fc81ee3
MB		 3142 if (ret) {
3143 pr_err("%s: Failed to request IRQ %d: %d\n",
3144 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3145 goto untasklet;
0fc81ee3 3146 }
d129bceb 3147
2f4cbb3d 3148 sdhci_init(host, 0);
d129bceb
PO		 3149
3150#ifdef CONFIG_MMC_DEBUG
3151 sdhci_dumpregs(host);
3152#endif
3153
f9134319 3154#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3155 snprintf(host->led_name, sizeof(host->led_name),
3156 "%s::", mmc_hostname(mmc));
3157 host->led.name = host->led_name;
2f730fec
PO		 3158 host->led.brightness = LED_OFF;
3159 host->led.default_trigger = mmc_hostname(mmc);
3160 host->led.brightness_set = sdhci_led_control;
3161
b8c86fc5 3162 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3163 if (ret) {
3164 pr_err("%s: Failed to register LED device: %d\n",
3165 mmc_hostname(mmc), ret);
2f730fec 3166 goto reset;
0fc81ee3 3167 }
2f730fec
PO		 3168#endif
3169
5f25a66f
PO		 3170 mmiowb();
3171
d129bceb
PO		 3172 mmc_add_host(mmc);
3173
a3c76eb9 3174 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3175 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3176 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3177 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3178
7260cf5e
AV		 3179 sdhci_enable_card_detection(host);
3180
d129bceb
PO		 3181 return 0;
3182
f9134319 3183#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3184reset:
3185 sdhci_reset(host, SDHCI_RESET_ALL);
b0a8dece 3186 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2f730fec
PO		 3187 free_irq(host->irq, host);
3188#endif
8ef1a143 3189untasklet:
d129bceb
PO		 3190 tasklet_kill(&host->card_tasklet);
3191 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3192
3193 return ret;
3194}
3195
b8c86fc5 3196EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3197
1e72859e 3198void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3199{
1e72859e
PO		 3200 unsigned long flags;
3201
3202 if (dead) {
3203 spin_lock_irqsave(&host->lock, flags);
3204
3205 host->flags |= SDHCI_DEVICE_DEAD;
3206
3207 if (host->mrq) {
a3c76eb9 3208 pr_err("%s: Controller removed during "
1e72859e
PO		 3209 " transfer!\n", mmc_hostname(host->mmc));
3210
3211 host->mrq->cmd->error = -ENOMEDIUM;
3212 tasklet_schedule(&host->finish_tasklet);
3213 }
3214
3215 spin_unlock_irqrestore(&host->lock, flags);
3216 }
3217
7260cf5e
AV		 3218 sdhci_disable_card_detection(host);
3219
b8c86fc5 3220 mmc_remove_host(host->mmc);
d129bceb 3221
f9134319 3222#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3223 led_classdev_unregister(&host->led);
3224#endif
3225
1e72859e
PO		 3226 if (!dead)
3227 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 3228
b0a8dece 3229 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
d129bceb
PO		 3230 free_irq(host->irq, host);
3231
3232 del_timer_sync(&host->timer);
3233
3234 tasklet_kill(&host->card_tasklet);
3235 tasklet_kill(&host->finish_tasklet);
2134a922 3236
77dcb3f4
PR		 3237 if (host->vmmc) {
3238 regulator_disable(host->vmmc);
9bea3c85 3239 regulator_put(host->vmmc);
77dcb3f4 3240 }
9bea3c85 3241
6231f3de
PR		 3242 if (host->vqmmc) {
3243 regulator_disable(host->vqmmc);
3244 regulator_put(host->vqmmc);
3245 }
3246
2134a922
PO		 3247 kfree(host->adma_desc);
3248 kfree(host->align_buffer);
3249
3250 host->adma_desc = NULL;
3251 host->align_buffer = NULL;
d129bceb
PO		 3252}
3253
b8c86fc5 3254EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3255
b8c86fc5 3256void sdhci_free_host(struct sdhci_host *host)
d129bceb 3257{
b8c86fc5 3258 mmc_free_host(host->mmc);
d129bceb
PO		 3259}
3260
b8c86fc5 3261EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3262
3263/*****************************************************************************\
3264 * *
3265 * Driver init/exit *
3266 * *
3267\*****************************************************************************/
3268
3269static int __init sdhci_drv_init(void)
3270{
a3c76eb9 3271 pr_info(DRIVER_NAME
52fbf9c9 3272 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3273 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3274
b8c86fc5 3275 return 0;
d129bceb
PO		 3276}
3277
3278static void __exit sdhci_drv_exit(void)
3279{
d129bceb
PO		 3280}
3281
3282module_init(sdhci_drv_init);
3283module_exit(sdhci_drv_exit);
3284
df673b22 3285module_param(debug_quirks, uint, 0444);
66fd8ad5 3286module_param(debug_quirks2, uint, 0444);
67435274 3287
32710e8f 3288MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3289MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3290MODULE_LICENSE("GPL");
67435274 3291
df673b22 3292MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3293MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux 6.x block layer and io_uring tree(s)