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mmc: sdhci-esdhc-imx: fix incorrect max timeout cout for uSDHC
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
d1e49f77
RK		 47#define ADMA_SIZE ((128 * 2 + 1) * 4)
48
df673b22 49static unsigned int debug_quirks = 0;
66fd8ad5 50static unsigned int debug_quirks2;
67435274 51
d129bceb
PO		 52static void sdhci_finish_data(struct sdhci_host *);
53
d129bceb 54static void sdhci_finish_command(struct sdhci_host *);
069c9f14 55static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 56static void sdhci_tuning_timer(unsigned long data);
52983382 57static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 58
66fd8ad5
AH		 59#ifdef CONFIG_PM_RUNTIME
60static int sdhci_runtime_pm_get(struct sdhci_host *host);
61static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 62static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
63static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 64#else
65static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
66{
67 return 0;
68}
69static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
70{
71 return 0;
72}
f0710a55
AH		 73static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
74{
75}
76static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
77{
78}
66fd8ad5
AH		 79#endif
80
d129bceb
PO		 81static void sdhci_dumpregs(struct sdhci_host *host)
82{
a3c76eb9 83 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 84 mmc_hostname(host->mmc));
d129bceb 85
a3c76eb9 86 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 87 sdhci_readl(host, SDHCI_DMA_ADDRESS),
88 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 89 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 90 sdhci_readw(host, SDHCI_BLOCK_SIZE),
91 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 92 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 93 sdhci_readl(host, SDHCI_ARGUMENT),
94 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 95 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 96 sdhci_readl(host, SDHCI_PRESENT_STATE),
97 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 98 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 99 sdhci_readb(host, SDHCI_POWER_CONTROL),
100 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 101 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 102 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
103 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 104 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 105 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
106 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 107 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 108 sdhci_readl(host, SDHCI_INT_ENABLE),
109 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 110 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 111 sdhci_readw(host, SDHCI_ACMD12_ERR),
112 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 113 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 114 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 115 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 117 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 118 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 120 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 121
be3f4ae0 122 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
126
a3c76eb9 127 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 128}
129
130/*****************************************************************************\
131 * *
132 * Low level functions *
133 * *
134\*****************************************************************************/
135
7260cf5e
AV		 136static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
137{
5b4f1f6c 138 u32 present;
7260cf5e 139
c79396c1 140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 141 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 142 return;
143
5b4f1f6c
RK		 144 if (enable) {
145 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
146 SDHCI_CARD_PRESENT;
d25928d1 147
5b4f1f6c
RK		 148 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
149 SDHCI_INT_CARD_INSERT;
150 } else {
151 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
152 }
b537f94c
RK		 153
154 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
155 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 156}
157
158static void sdhci_enable_card_detection(struct sdhci_host *host)
159{
160 sdhci_set_card_detection(host, true);
161}
162
163static void sdhci_disable_card_detection(struct sdhci_host *host)
164{
165 sdhci_set_card_detection(host, false);
166}
167
03231f9b 168void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 169{
e16514d8 170 unsigned long timeout;
393c1a34 171
4e4141a5 172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 173
f0710a55 174 if (mask & SDHCI_RESET_ALL) {
d129bceb 175 host->clock = 0;
f0710a55
AH		 176 /* Reset-all turns off SD Bus Power */
177 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
178 sdhci_runtime_pm_bus_off(host);
179 }
d129bceb 180
e16514d8
PO		 181 /* Wait max 100 ms */
182 timeout = 100;
183
184 /* hw clears the bit when it's done */
4e4141a5 185 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 186 if (timeout == 0) {
a3c76eb9 187 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 188 mmc_hostname(host->mmc), (int)mask);
189 sdhci_dumpregs(host);
190 return;
191 }
192 timeout--;
193 mdelay(1);
d129bceb 194 }
03231f9b
RK		 195}
196EXPORT_SYMBOL_GPL(sdhci_reset);
197
198static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
199{
200 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
201 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
202 SDHCI_CARD_PRESENT))
203 return;
204 }
063a9dbb 205
03231f9b 206 host->ops->reset(host, mask);
393c1a34 207
da91a8f9
RK		 208 if (mask & SDHCI_RESET_ALL) {
209 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
210 if (host->ops->enable_dma)
211 host->ops->enable_dma(host);
212 }
213
214 /* Resetting the controller clears many */
215 host->preset_enabled = false;
3abc1e80 216 }
d129bceb
PO		 217}
218
2f4cbb3d
NP		 219static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
220
221static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 222{
2f4cbb3d 223 if (soft)
03231f9b 224 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 225 else
03231f9b 226 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 227
b537f94c
RK		 228 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
229 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
230 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
231 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
232 SDHCI_INT_RESPONSE;
233
234 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
235 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 236
237 if (soft) {
238 /* force clock reconfiguration */
239 host->clock = 0;
240 sdhci_set_ios(host->mmc, &host->mmc->ios);
241 }
7260cf5e 242}
d129bceb 243
7260cf5e
AV		 244static void sdhci_reinit(struct sdhci_host *host)
245{
2f4cbb3d 246 sdhci_init(host, 0);
b67c6b41
AL		 247 /*
248 * Retuning stuffs are affected by different cards inserted and only
249 * applicable to UHS-I cards. So reset these fields to their initial
250 * value when card is removed.
251 */
973905fe
AL		 252 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
253 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
254
b67c6b41
AL		 255 del_timer_sync(&host->tuning_timer);
256 host->flags &= ~SDHCI_NEEDS_RETUNING;
257 host->mmc->max_blk_count =
258 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
259 }
7260cf5e 260 sdhci_enable_card_detection(host);
d129bceb
PO		 261}
262
263static void sdhci_activate_led(struct sdhci_host *host)
264{
265 u8 ctrl;
266
4e4141a5 267 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 268 ctrl |= SDHCI_CTRL_LED;
4e4141a5 269 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 270}
271
272static void sdhci_deactivate_led(struct sdhci_host *host)
273{
274 u8 ctrl;
275
4e4141a5 276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 277 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 279}
280
f9134319 281#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 282static void sdhci_led_control(struct led_classdev *led,
283 enum led_brightness brightness)
284{
285 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
286 unsigned long flags;
287
288 spin_lock_irqsave(&host->lock, flags);
289
66fd8ad5
AH		 290 if (host->runtime_suspended)
291 goto out;
292
2f730fec
PO		 293 if (brightness == LED_OFF)
294 sdhci_deactivate_led(host);
295 else
296 sdhci_activate_led(host);
66fd8ad5 297out:
2f730fec
PO		 298 spin_unlock_irqrestore(&host->lock, flags);
299}
300#endif
301
d129bceb
PO		 302/*****************************************************************************\
303 * *
304 * Core functions *
305 * *
306\*****************************************************************************/
307
a406f5a3 308static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 309{
7659150c
PO		 310 unsigned long flags;
311 size_t blksize, len, chunk;
7244b85b 312 u32 uninitialized_var(scratch);
7659150c 313 u8 *buf;
d129bceb 314
a406f5a3 315 DBG("PIO reading\n");
d129bceb 316
a406f5a3 317 blksize = host->data->blksz;
7659150c 318 chunk = 0;
d129bceb 319
7659150c 320 local_irq_save(flags);
d129bceb 321
a406f5a3 322 while (blksize) {
7659150c
PO		 323 if (!sg_miter_next(&host->sg_miter))
324 BUG();
d129bceb 325
7659150c 326 len = min(host->sg_miter.length, blksize);
d129bceb 327
7659150c
PO		 328 blksize -= len;
329 host->sg_miter.consumed = len;
14d836e7 330
7659150c 331 buf = host->sg_miter.addr;
d129bceb 332
7659150c
PO		 333 while (len) {
334 if (chunk == 0) {
4e4141a5 335 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 336 chunk = 4;
a406f5a3 337 }
7659150c
PO		 338
339 *buf = scratch & 0xFF;
340
341 buf++;
342 scratch >>= 8;
343 chunk--;
344 len--;
d129bceb 345 }
a406f5a3 346 }
7659150c
PO		 347
348 sg_miter_stop(&host->sg_miter);
349
350 local_irq_restore(flags);
a406f5a3 351}
d129bceb 352
a406f5a3
PO		 353static void sdhci_write_block_pio(struct sdhci_host *host)
354{
7659150c
PO		 355 unsigned long flags;
356 size_t blksize, len, chunk;
357 u32 scratch;
358 u8 *buf;
d129bceb 359
a406f5a3
PO		 360 DBG("PIO writing\n");
361
362 blksize = host->data->blksz;
7659150c
PO		 363 chunk = 0;
364 scratch = 0;
d129bceb 365
7659150c 366 local_irq_save(flags);
d129bceb 367
a406f5a3 368 while (blksize) {
7659150c
PO		 369 if (!sg_miter_next(&host->sg_miter))
370 BUG();
a406f5a3 371
7659150c
PO		 372 len = min(host->sg_miter.length, blksize);
373
374 blksize -= len;
375 host->sg_miter.consumed = len;
376
377 buf = host->sg_miter.addr;
d129bceb 378
7659150c
PO		 379 while (len) {
380 scratch |= (u32)*buf << (chunk * 8);
381
382 buf++;
383 chunk++;
384 len--;
385
386 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 387 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 388 chunk = 0;
389 scratch = 0;
d129bceb 390 }
d129bceb
PO		 391 }
392 }
7659150c
PO		 393
394 sg_miter_stop(&host->sg_miter);
395
396 local_irq_restore(flags);
a406f5a3
PO		 397}
398
399static void sdhci_transfer_pio(struct sdhci_host *host)
400{
401 u32 mask;
402
403 BUG_ON(!host->data);
404
7659150c 405 if (host->blocks == 0)
a406f5a3
PO		 406 return;
407
408 if (host->data->flags & MMC_DATA_READ)
409 mask = SDHCI_DATA_AVAILABLE;
410 else
411 mask = SDHCI_SPACE_AVAILABLE;
412
4a3cba32
PO		 413 /*
414 * Some controllers (JMicron JMB38x) mess up the buffer bits
415 * for transfers < 4 bytes. As long as it is just one block,
416 * we can ignore the bits.
417 */
418 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
419 (host->data->blocks == 1))
420 mask = ~0;
421
4e4141a5 422 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 423 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
424 udelay(100);
425
a406f5a3
PO		 426 if (host->data->flags & MMC_DATA_READ)
427 sdhci_read_block_pio(host);
428 else
429 sdhci_write_block_pio(host);
d129bceb 430
7659150c
PO		 431 host->blocks--;
432 if (host->blocks == 0)
a406f5a3 433 break;
a406f5a3 434 }
d129bceb 435
a406f5a3 436 DBG("PIO transfer complete.\n");
d129bceb
PO		 437}
438
2134a922
PO		 439static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
440{
441 local_irq_save(*flags);
482fce99 442 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 443}
444
445static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
446{
482fce99 447 kunmap_atomic(buffer);
2134a922
PO		 448 local_irq_restore(*flags);
449}
450
118cd17d
BD		 451static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
452{
9e506f35
BD		 453 __le32 *dataddr = (__le32 __force *)(desc + 4);
454 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 455
9e506f35
BD		 456 /* SDHCI specification says ADMA descriptors should be 4 byte
457 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 458
9e506f35
BD		 459 cmdlen[0] = cpu_to_le16(cmd);
460 cmdlen[1] = cpu_to_le16(len);
461
462 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 463}
464
8f1934ce 465static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 466 struct mmc_data *data)
467{
468 int direction;
469
470 u8 *desc;
471 u8 *align;
472 dma_addr_t addr;
473 dma_addr_t align_addr;
474 int len, offset;
475
476 struct scatterlist *sg;
477 int i;
478 char *buffer;
479 unsigned long flags;
480
481 /*
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
484 */
485
486 if (data->flags & MMC_DATA_READ)
487 direction = DMA_FROM_DEVICE;
488 else
489 direction = DMA_TO_DEVICE;
490
2134a922
PO		 491 host->align_addr = dma_map_single(mmc_dev(host->mmc),
492 host->align_buffer, 128 * 4, direction);
8d8bb39b 493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 494 goto fail;
2134a922
PO		 495 BUG_ON(host->align_addr & 0x3);
496
497 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
498 data->sg, data->sg_len, direction);
8f1934ce
PO		 499 if (host->sg_count == 0)
500 goto unmap_align;
2134a922
PO		 501
502 desc = host->adma_desc;
503 align = host->align_buffer;
504
505 align_addr = host->align_addr;
506
507 for_each_sg(data->sg, sg, host->sg_count, i) {
508 addr = sg_dma_address(sg);
509 len = sg_dma_len(sg);
510
511 /*
512 * The SDHCI specification states that ADMA
513 * addresses must be 32-bit aligned. If they
514 * aren't, then we use a bounce buffer for
515 * the (up to three) bytes that screw up the
516 * alignment.
517 */
518 offset = (4 - (addr & 0x3)) & 0x3;
519 if (offset) {
520 if (data->flags & MMC_DATA_WRITE) {
521 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 522 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 523 memcpy(align, buffer, offset);
524 sdhci_kunmap_atomic(buffer, &flags);
525 }
526
118cd17d
BD		 527 /* tran, valid */
528 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 529
530 BUG_ON(offset > 65536);
531
2134a922
PO		 532 align += 4;
533 align_addr += 4;
534
535 desc += 8;
536
537 addr += offset;
538 len -= offset;
539 }
540
2134a922
PO		 541 BUG_ON(len > 65536);
542
118cd17d
BD		 543 /* tran, valid */
544 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 545 desc += 8;
546
547 /*
548 * If this triggers then we have a calculation bug
549 * somewhere. :/
550 */
d1e49f77 551 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
2134a922
PO		 552 }
553
70764a90
TA		 554 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
555 /*
556 * Mark the last descriptor as the terminating descriptor
557 */
558 if (desc != host->adma_desc) {
559 desc -= 8;
560 desc[0] |= 0x2; /* end */
561 }
562 } else {
563 /*
564 * Add a terminating entry.
565 */
2134a922 566
70764a90
TA		 567 /* nop, end, valid */
568 sdhci_set_adma_desc(desc, 0, 0, 0x3);
569 }
2134a922
PO		 570
571 /*
572 * Resync align buffer as we might have changed it.
573 */
574 if (data->flags & MMC_DATA_WRITE) {
575 dma_sync_single_for_device(mmc_dev(host->mmc),
576 host->align_addr, 128 * 4, direction);
577 }
578
8f1934ce
PO		 579 return 0;
580
8f1934ce
PO		 581unmap_align:
582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
583 128 * 4, direction);
584fail:
585 return -EINVAL;
2134a922
PO		 586}
587
588static void sdhci_adma_table_post(struct sdhci_host *host,
589 struct mmc_data *data)
590{
591 int direction;
592
593 struct scatterlist *sg;
594 int i, size;
595 u8 *align;
596 char *buffer;
597 unsigned long flags;
de0b65a7 598 bool has_unaligned;
2134a922
PO		 599
600 if (data->flags & MMC_DATA_READ)
601 direction = DMA_FROM_DEVICE;
602 else
603 direction = DMA_TO_DEVICE;
604
2134a922
PO		 605 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
606 128 * 4, direction);
607
de0b65a7
RK		 608 /* Do a quick scan of the SG list for any unaligned mappings */
609 has_unaligned = false;
610 for_each_sg(data->sg, sg, host->sg_count, i)
611 if (sg_dma_address(sg) & 3) {
612 has_unaligned = true;
613 break;
614 }
615
616 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 617 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
618 data->sg_len, direction);
619
620 align = host->align_buffer;
621
622 for_each_sg(data->sg, sg, host->sg_count, i) {
623 if (sg_dma_address(sg) & 0x3) {
624 size = 4 - (sg_dma_address(sg) & 0x3);
625
626 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 627 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 628 memcpy(buffer, align, size);
629 sdhci_kunmap_atomic(buffer, &flags);
630
631 align += 4;
632 }
633 }
634 }
635
636 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
637 data->sg_len, direction);
638}
639
a3c7778f 640static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 641{
1c8cde92 642 u8 count;
a3c7778f 643 struct mmc_data *data = cmd->data;
1c8cde92 644 unsigned target_timeout, current_timeout;
d129bceb 645
ee53ab5d
PO		 646 /*
647 * If the host controller provides us with an incorrect timeout
648 * value, just skip the check and use 0xE. The hardware may take
649 * longer to time out, but that's much better than having a too-short
650 * timeout value.
651 */
11a2f1b7 652 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 653 return 0xE;
e538fbe8 654
a3c7778f 655 /* Unspecified timeout, assume max */
1d4d7744 656 if (!data && !cmd->busy_timeout)
a3c7778f 657 return 0xE;
d129bceb 658
a3c7778f
AW		 659 /* timeout in us */
660 if (!data)
1d4d7744 661 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 662 else {
663 target_timeout = data->timeout_ns / 1000;
664 if (host->clock)
665 target_timeout += data->timeout_clks / host->clock;
666 }
81b39802 667
1c8cde92
PO		 668 /*
669 * Figure out needed cycles.
670 * We do this in steps in order to fit inside a 32 bit int.
671 * The first step is the minimum timeout, which will have a
672 * minimum resolution of 6 bits:
673 * (1) 2^13*1000 > 2^22,
674 * (2) host->timeout_clk < 2^16
675 * =>
676 * (1) / (2) > 2^6
677 */
678 count = 0;
679 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
680 while (current_timeout < target_timeout) {
681 count++;
682 current_timeout <<= 1;
683 if (count >= 0xF)
684 break;
685 }
686
687 if (count >= 0xF) {
09eeff52
CB		 688 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
689 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 690 count = 0xE;
691 }
692
ee53ab5d
PO		 693 return count;
694}
695
6aa943ab
AV		 696static void sdhci_set_transfer_irqs(struct sdhci_host *host)
697{
698 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
699 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
700
701 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 702 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 703 else
b537f94c
RK		 704 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
705
706 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
707 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 708}
709
a3c7778f 710static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 711{
712 u8 count;
2134a922 713 u8 ctrl;
a3c7778f 714 struct mmc_data *data = cmd->data;
8f1934ce 715 int ret;
ee53ab5d
PO		 716
717 WARN_ON(host->data);
718
a3c7778f
AW		 719 if (data || (cmd->flags & MMC_RSP_BUSY)) {
720 count = sdhci_calc_timeout(host, cmd);
721 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
722 }
723
724 if (!data)
ee53ab5d
PO		 725 return;
726
727 /* Sanity checks */
728 BUG_ON(data->blksz * data->blocks > 524288);
729 BUG_ON(data->blksz > host->mmc->max_blk_size);
730 BUG_ON(data->blocks > 65535);
731
732 host->data = data;
733 host->data_early = 0;
f6a03cbf 734 host->data->bytes_xfered = 0;
ee53ab5d 735
a13abc7b 736 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 737 host->flags |= SDHCI_REQ_USE_DMA;
738
2134a922
PO		 739 /*
740 * FIXME: This doesn't account for merging when mapping the
741 * scatterlist.
742 */
743 if (host->flags & SDHCI_REQ_USE_DMA) {
744 int broken, i;
745 struct scatterlist *sg;
746
747 broken = 0;
748 if (host->flags & SDHCI_USE_ADMA) {
749 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
750 broken = 1;
751 } else {
752 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
753 broken = 1;
754 }
755
756 if (unlikely(broken)) {
757 for_each_sg(data->sg, sg, data->sg_len, i) {
758 if (sg->length & 0x3) {
759 DBG("Reverting to PIO because of "
760 "transfer size (%d)\n",
761 sg->length);
762 host->flags &= ~SDHCI_REQ_USE_DMA;
763 break;
764 }
765 }
766 }
c9fddbc4
PO		 767 }
768
769 /*
770 * The assumption here being that alignment is the same after
771 * translation to device address space.
772 */
2134a922
PO		 773 if (host->flags & SDHCI_REQ_USE_DMA) {
774 int broken, i;
775 struct scatterlist *sg;
776
777 broken = 0;
778 if (host->flags & SDHCI_USE_ADMA) {
779 /*
780 * As we use 3 byte chunks to work around
781 * alignment problems, we need to check this
782 * quirk.
783 */
784 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
785 broken = 1;
786 } else {
787 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
788 broken = 1;
789 }
790
791 if (unlikely(broken)) {
792 for_each_sg(data->sg, sg, data->sg_len, i) {
793 if (sg->offset & 0x3) {
794 DBG("Reverting to PIO because of "
795 "bad alignment\n");
796 host->flags &= ~SDHCI_REQ_USE_DMA;
797 break;
798 }
799 }
800 }
801 }
802
8f1934ce
PO		 803 if (host->flags & SDHCI_REQ_USE_DMA) {
804 if (host->flags & SDHCI_USE_ADMA) {
805 ret = sdhci_adma_table_pre(host, data);
806 if (ret) {
807 /*
808 * This only happens when someone fed
809 * us an invalid request.
810 */
811 WARN_ON(1);
ebd6d357 812 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 813 } else {
4e4141a5
AV		 814 sdhci_writel(host, host->adma_addr,
815 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 816 }
817 } else {
c8b3e02e 818 int sg_cnt;
8f1934ce 819
c8b3e02e 820 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 821 data->sg, data->sg_len,
822 (data->flags & MMC_DATA_READ) ?
823 DMA_FROM_DEVICE :
824 DMA_TO_DEVICE);
c8b3e02e 825 if (sg_cnt == 0) {
8f1934ce
PO		 826 /*
827 * This only happens when someone fed
828 * us an invalid request.
829 */
830 WARN_ON(1);
ebd6d357 831 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 832 } else {
719a61b4 833 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 834 sdhci_writel(host, sg_dma_address(data->sg),
835 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 836 }
837 }
838 }
839
2134a922
PO		 840 /*
841 * Always adjust the DMA selection as some controllers
842 * (e.g. JMicron) can't do PIO properly when the selection
843 * is ADMA.
844 */
845 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 846 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 847 ctrl &= ~SDHCI_CTRL_DMA_MASK;
848 if ((host->flags & SDHCI_REQ_USE_DMA) &&
849 (host->flags & SDHCI_USE_ADMA))
850 ctrl |= SDHCI_CTRL_ADMA32;
851 else
852 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 853 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 854 }
855
8f1934ce 856 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 857 int flags;
858
859 flags = SG_MITER_ATOMIC;
860 if (host->data->flags & MMC_DATA_READ)
861 flags |= SG_MITER_TO_SG;
862 else
863 flags |= SG_MITER_FROM_SG;
864 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 865 host->blocks = data->blocks;
d129bceb 866 }
c7fa9963 867
6aa943ab
AV		 868 sdhci_set_transfer_irqs(host);
869
f6a03cbf
MV		 870 /* Set the DMA boundary value and block size */
871 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
872 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 873 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 874}
875
876static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 877 struct mmc_command *cmd)
c7fa9963
PO		 878{
879 u16 mode;
e89d456f 880 struct mmc_data *data = cmd->data;
c7fa9963 881
2b558c13
DA		 882 if (data == NULL) {
883 /* clear Auto CMD settings for no data CMDs */
884 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
885 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
886 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
c7fa9963 887 return;
2b558c13 888 }
c7fa9963 889
e538fbe8
PO		 890 WARN_ON(!host->data);
891
c7fa9963 892 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 893 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
894 mode |= SDHCI_TRNS_MULTI;
895 /*
896 * If we are sending CMD23, CMD12 never gets sent
897 * on successful completion (so no Auto-CMD12).
898 */
899 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
900 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 901 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
902 mode |= SDHCI_TRNS_AUTO_CMD23;
903 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
904 }
c4512f79 905 }
8edf6371 906
c7fa9963
PO		 907 if (data->flags & MMC_DATA_READ)
908 mode |= SDHCI_TRNS_READ;
c9fddbc4 909 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 910 mode |= SDHCI_TRNS_DMA;
911
4e4141a5 912 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 913}
914
915static void sdhci_finish_data(struct sdhci_host *host)
916{
917 struct mmc_data *data;
d129bceb
PO		 918
919 BUG_ON(!host->data);
920
921 data = host->data;
922 host->data = NULL;
923
c9fddbc4 924 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 925 if (host->flags & SDHCI_USE_ADMA)
926 sdhci_adma_table_post(host, data);
927 else {
928 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
929 data->sg_len, (data->flags & MMC_DATA_READ) ?
930 DMA_FROM_DEVICE : DMA_TO_DEVICE);
931 }
d129bceb
PO		 932 }
933
934 /*
c9b74c5b
PO		 935 * The specification states that the block count register must
936 * be updated, but it does not specify at what point in the
937 * data flow. That makes the register entirely useless to read
938 * back so we have to assume that nothing made it to the card
939 * in the event of an error.
d129bceb 940 */
c9b74c5b
PO		 941 if (data->error)
942 data->bytes_xfered = 0;
d129bceb 943 else
c9b74c5b 944 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 945
e89d456f
AW		 946 /*
947 * Need to send CMD12 if -
948 * a) open-ended multiblock transfer (no CMD23)
949 * b) error in multiblock transfer
950 */
951 if (data->stop &&
952 (data->error ||
953 !host->mrq->sbc)) {
954
d129bceb
PO		 955 /*
956 * The controller needs a reset of internal state machines
957 * upon error conditions.
958 */
17b0429d 959 if (data->error) {
03231f9b
RK		 960 sdhci_do_reset(host, SDHCI_RESET_CMD);
961 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 962 }
963
964 sdhci_send_command(host, data->stop);
965 } else
966 tasklet_schedule(&host->finish_tasklet);
967}
968
c0e55129 969void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 970{
971 int flags;
fd2208d7 972 u32 mask;
7cb2c76f 973 unsigned long timeout;
d129bceb
PO		 974
975 WARN_ON(host->cmd);
976
d129bceb 977 /* Wait max 10 ms */
7cb2c76f 978 timeout = 10;
fd2208d7
PO		 979
980 mask = SDHCI_CMD_INHIBIT;
981 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
982 mask |= SDHCI_DATA_INHIBIT;
983
984 /* We shouldn't wait for data inihibit for stop commands, even
985 though they might use busy signaling */
986 if (host->mrq->data && (cmd == host->mrq->data->stop))
987 mask &= ~SDHCI_DATA_INHIBIT;
988
4e4141a5 989 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 990 if (timeout == 0) {
a3c76eb9 991 pr_err("%s: Controller never released "
acf1da45 992 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 993 sdhci_dumpregs(host);
17b0429d 994 cmd->error = -EIO;
d129bceb
PO		 995 tasklet_schedule(&host->finish_tasklet);
996 return;
997 }
7cb2c76f
PO		 998 timeout--;
999 mdelay(1);
1000 }
d129bceb 1001
3e1a6892 1002 timeout = jiffies;
1d4d7744
UH		 1003 if (!cmd->data && cmd->busy_timeout > 9000)
1004 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1005 else
1006 timeout += 10 * HZ;
1007 mod_timer(&host->timer, timeout);
d129bceb
PO		 1008
1009 host->cmd = cmd;
1010
a3c7778f 1011 sdhci_prepare_data(host, cmd);
d129bceb 1012
4e4141a5 1013 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1014
e89d456f 1015 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1016
d129bceb 1017 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1018 pr_err("%s: Unsupported response type!\n",
d129bceb 1019 mmc_hostname(host->mmc));
17b0429d 1020 cmd->error = -EINVAL;
d129bceb
PO		 1021 tasklet_schedule(&host->finish_tasklet);
1022 return;
1023 }
1024
1025 if (!(cmd->flags & MMC_RSP_PRESENT))
1026 flags = SDHCI_CMD_RESP_NONE;
1027 else if (cmd->flags & MMC_RSP_136)
1028 flags = SDHCI_CMD_RESP_LONG;
1029 else if (cmd->flags & MMC_RSP_BUSY)
1030 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1031 else
1032 flags = SDHCI_CMD_RESP_SHORT;
1033
1034 if (cmd->flags & MMC_RSP_CRC)
1035 flags |= SDHCI_CMD_CRC;
1036 if (cmd->flags & MMC_RSP_OPCODE)
1037 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1038
1039 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1040 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1041 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1042 flags |= SDHCI_CMD_DATA;
1043
4e4141a5 1044 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1045}
c0e55129 1046EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1047
1048static void sdhci_finish_command(struct sdhci_host *host)
1049{
1050 int i;
1051
1052 BUG_ON(host->cmd == NULL);
1053
1054 if (host->cmd->flags & MMC_RSP_PRESENT) {
1055 if (host->cmd->flags & MMC_RSP_136) {
1056 /* CRC is stripped so we need to do some shifting. */
1057 for (i = 0;i < 4;i++) {
4e4141a5 1058 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1059 SDHCI_RESPONSE + (3-i)*4) << 8;
1060 if (i != 3)
1061 host->cmd->resp[i] |=
4e4141a5 1062 sdhci_readb(host,
d129bceb
PO		 1063 SDHCI_RESPONSE + (3-i)*4-1);
1064 }
1065 } else {
4e4141a5 1066 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1067 }
1068 }
1069
17b0429d 1070 host->cmd->error = 0;
d129bceb 1071
e89d456f
AW		 1072 /* Finished CMD23, now send actual command. */
1073 if (host->cmd == host->mrq->sbc) {
1074 host->cmd = NULL;
1075 sdhci_send_command(host, host->mrq->cmd);
1076 } else {
e538fbe8 1077
e89d456f
AW		 1078 /* Processed actual command. */
1079 if (host->data && host->data_early)
1080 sdhci_finish_data(host);
d129bceb 1081
e89d456f
AW		 1082 if (!host->cmd->data)
1083 tasklet_schedule(&host->finish_tasklet);
1084
1085 host->cmd = NULL;
1086 }
d129bceb
PO		 1087}
1088
52983382
KL		 1089static u16 sdhci_get_preset_value(struct sdhci_host *host)
1090{
d975f121 1091 u16 preset = 0;
52983382 1092
d975f121
RK		 1093 switch (host->timing) {
1094 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1095 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1096 break;
d975f121 1097 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1098 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1099 break;
d975f121 1100 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1101 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1102 break;
d975f121
RK		 1103 case MMC_TIMING_UHS_SDR104:
1104 case MMC_TIMING_MMC_HS200:
52983382
KL		 1105 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1106 break;
d975f121 1107 case MMC_TIMING_UHS_DDR50:
52983382
KL		 1108 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1109 break;
1110 default:
1111 pr_warn("%s: Invalid UHS-I mode selected\n",
1112 mmc_hostname(host->mmc));
1113 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1114 break;
1115 }
1116 return preset;
1117}
1118
1771059c 1119void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1120{
c3ed3877 1121 int div = 0; /* Initialized for compiler warning */
df16219f 1122 int real_div = div, clk_mul = 1;
c3ed3877 1123 u16 clk = 0;
7cb2c76f 1124 unsigned long timeout;
d129bceb 1125
1650d0c7
RK		 1126 host->mmc->actual_clock = 0;
1127
4e4141a5 1128 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1129
1130 if (clock == 0)
373073ef 1131 return;
d129bceb 1132
85105c53 1133 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1134 if (host->preset_enabled) {
52983382
KL		 1135 u16 pre_val;
1136
1137 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1138 pre_val = sdhci_get_preset_value(host);
1139 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1140 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1141 if (host->clk_mul &&
1142 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1143 clk = SDHCI_PROG_CLOCK_MODE;
1144 real_div = div + 1;
1145 clk_mul = host->clk_mul;
1146 } else {
1147 real_div = max_t(int, 1, div << 1);
1148 }
1149 goto clock_set;
1150 }
1151
c3ed3877
AN		 1152 /*
1153 * Check if the Host Controller supports Programmable Clock
1154 * Mode.
1155 */
1156 if (host->clk_mul) {
52983382
KL		 1157 for (div = 1; div <= 1024; div++) {
1158 if ((host->max_clk * host->clk_mul / div)
1159 <= clock)
1160 break;
1161 }
c3ed3877 1162 /*
52983382
KL		 1163 * Set Programmable Clock Mode in the Clock
1164 * Control register.
c3ed3877 1165 */
52983382
KL		 1166 clk = SDHCI_PROG_CLOCK_MODE;
1167 real_div = div;
1168 clk_mul = host->clk_mul;
1169 div--;
c3ed3877
AN		 1170 } else {
1171 /* Version 3.00 divisors must be a multiple of 2. */
1172 if (host->max_clk <= clock)
1173 div = 1;
1174 else {
1175 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1176 div += 2) {
1177 if ((host->max_clk / div) <= clock)
1178 break;
1179 }
85105c53 1180 }
df16219f 1181 real_div = div;
c3ed3877 1182 div >>= 1;
85105c53
ZG		 1183 }
1184 } else {
1185 /* Version 2.00 divisors must be a power of 2. */
0397526d 1186 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1187 if ((host->max_clk / div) <= clock)
1188 break;
1189 }
df16219f 1190 real_div = div;
c3ed3877 1191 div >>= 1;
d129bceb 1192 }
d129bceb 1193
52983382 1194clock_set:
fac6a52f 1195 if (real_div) {
df16219f 1196 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
fac6a52f
MC		 1197 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
1198 host->timeout_clk = host->mmc->actual_clock / 1000;
1199 host->mmc->max_busy_timeout =
a6ff5aeb
AD		 1200 host->ops->get_max_timeout_count ?
1201 host->ops->get_max_timeout_count(host) :
1202 1 << 27;
1203 host->mmc->max_busy_timeout /= host->timeout_clk;
fac6a52f
MC		 1204 }
1205 }
df16219f 1206
c3ed3877 1207 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1208 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1209 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1210 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1211 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1212
27f6cb16
CB		 1213 /* Wait max 20 ms */
1214 timeout = 20;
4e4141a5 1215 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1216 & SDHCI_CLOCK_INT_STABLE)) {
1217 if (timeout == 0) {
a3c76eb9 1218 pr_err("%s: Internal clock never "
acf1da45 1219 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1220 sdhci_dumpregs(host);
1221 return;
1222 }
7cb2c76f
PO		 1223 timeout--;
1224 mdelay(1);
1225 }
d129bceb
PO		 1226
1227 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1228 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1229}
1771059c 1230EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1231
24fbb3ca
RK		 1232static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1233 unsigned short vdd)
146ad66e 1234{
3a48edc4 1235 struct mmc_host *mmc = host->mmc;
8364248a 1236 u8 pwr = 0;
146ad66e 1237
52221610
TK		 1238 if (!IS_ERR(mmc->supply.vmmc)) {
1239 spin_unlock_irq(&host->lock);
4e743f1f 1240 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
52221610
TK		 1241 spin_lock_irq(&host->lock);
1242 return;
1243 }
1244
24fbb3ca
RK		 1245 if (mode != MMC_POWER_OFF) {
1246 switch (1 << vdd) {
ae628903
PO		 1247 case MMC_VDD_165_195:
1248 pwr = SDHCI_POWER_180;
1249 break;
1250 case MMC_VDD_29_30:
1251 case MMC_VDD_30_31:
1252 pwr = SDHCI_POWER_300;
1253 break;
1254 case MMC_VDD_32_33:
1255 case MMC_VDD_33_34:
1256 pwr = SDHCI_POWER_330;
1257 break;
1258 default:
1259 BUG();
1260 }
1261 }
1262
1263 if (host->pwr == pwr)
e921a8b6 1264 return;
146ad66e 1265
ae628903
PO		 1266 host->pwr = pwr;
1267
1268 if (pwr == 0) {
4e4141a5 1269 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1270 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1271 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1272 vdd = 0;
e921a8b6
RK		 1273 } else {
1274 /*
1275 * Spec says that we should clear the power reg before setting
1276 * a new value. Some controllers don't seem to like this though.
1277 */
1278 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1279 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1280
e921a8b6
RK		 1281 /*
1282 * At least the Marvell CaFe chip gets confused if we set the
1283 * voltage and set turn on power at the same time, so set the
1284 * voltage first.
1285 */
1286 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1287 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1288
e921a8b6 1289 pwr |= SDHCI_POWER_ON;
146ad66e 1290
e921a8b6 1291 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1292
e921a8b6
RK		 1293 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1294 sdhci_runtime_pm_bus_on(host);
f0710a55 1295
e921a8b6
RK		 1296 /*
1297 * Some controllers need an extra 10ms delay of 10ms before
1298 * they can apply clock after applying power
1299 */
1300 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1301 mdelay(10);
1302 }
146ad66e
PO		 1303}
1304
d129bceb
PO		 1305/*****************************************************************************\
1306 * *
1307 * MMC callbacks *
1308 * *
1309\*****************************************************************************/
1310
1311static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1312{
1313 struct sdhci_host *host;
505a8680 1314 int present;
d129bceb 1315 unsigned long flags;
473b095a 1316 u32 tuning_opcode;
d129bceb
PO		 1317
1318 host = mmc_priv(mmc);
1319
66fd8ad5
AH		 1320 sdhci_runtime_pm_get(host);
1321
d129bceb
PO		 1322 spin_lock_irqsave(&host->lock, flags);
1323
1324 WARN_ON(host->mrq != NULL);
1325
f9134319 1326#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1327 sdhci_activate_led(host);
2f730fec 1328#endif
e89d456f
AW		 1329
1330 /*
1331 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1332 * requests if Auto-CMD12 is enabled.
1333 */
1334 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1335 if (mrq->stop) {
1336 mrq->data->stop = NULL;
1337 mrq->stop = NULL;
1338 }
1339 }
d129bceb
PO		 1340
1341 host->mrq = mrq;
1342
505a8680
SG		 1343 /*
1344 * Firstly check card presence from cd-gpio. The return could
1345 * be one of the following possibilities:
1346 * negative: cd-gpio is not available
1347 * zero: cd-gpio is used, and card is removed
1348 * one: cd-gpio is used, and card is present
1349 */
1350 present = mmc_gpio_get_cd(host->mmc);
1351 if (present < 0) {
1352 /* If polling, assume that the card is always present. */
1353 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1354 present = 1;
1355 else
1356 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1357 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1358 }
1359
68d1fb7e 1360 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1361 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1362 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1363 } else {
1364 u32 present_state;
1365
1366 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1367 /*
1368 * Check if the re-tuning timer has already expired and there
1369 * is no on-going data transfer. If so, we need to execute
1370 * tuning procedure before sending command.
1371 */
1372 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1373 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1374 if (mmc->card) {
1375 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1376 tuning_opcode =
1377 mmc->card->type == MMC_TYPE_MMC ?
1378 MMC_SEND_TUNING_BLOCK_HS200 :
1379 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1380
1381 /* Here we need to set the host->mrq to NULL,
1382 * in case the pending finish_tasklet
1383 * finishes it incorrectly.
1384 */
1385 host->mrq = NULL;
1386
14efd957
CB		 1387 spin_unlock_irqrestore(&host->lock, flags);
1388 sdhci_execute_tuning(mmc, tuning_opcode);
1389 spin_lock_irqsave(&host->lock, flags);
1390
1391 /* Restore original mmc_request structure */
1392 host->mrq = mrq;
1393 }
cf2b5eea
AN		 1394 }
1395
8edf6371 1396 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1397 sdhci_send_command(host, mrq->sbc);
1398 else
1399 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1400 }
d129bceb 1401
5f25a66f 1402 mmiowb();
d129bceb
PO		 1403 spin_unlock_irqrestore(&host->lock, flags);
1404}
1405
2317f56c
RK		 1406void sdhci_set_bus_width(struct sdhci_host *host, int width)
1407{
1408 u8 ctrl;
1409
1410 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1411 if (width == MMC_BUS_WIDTH_8) {
1412 ctrl &= ~SDHCI_CTRL_4BITBUS;
1413 if (host->version >= SDHCI_SPEC_300)
1414 ctrl |= SDHCI_CTRL_8BITBUS;
1415 } else {
1416 if (host->version >= SDHCI_SPEC_300)
1417 ctrl &= ~SDHCI_CTRL_8BITBUS;
1418 if (width == MMC_BUS_WIDTH_4)
1419 ctrl |= SDHCI_CTRL_4BITBUS;
1420 else
1421 ctrl &= ~SDHCI_CTRL_4BITBUS;
1422 }
1423 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1424}
1425EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1426
96d7b78c
RK		 1427void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1428{
1429 u16 ctrl_2;
1430
1431 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1432 /* Select Bus Speed Mode for host */
1433 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1434 if ((timing == MMC_TIMING_MMC_HS200) ||
1435 (timing == MMC_TIMING_UHS_SDR104))
1436 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1437 else if (timing == MMC_TIMING_UHS_SDR12)
1438 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1439 else if (timing == MMC_TIMING_UHS_SDR25)
1440 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1441 else if (timing == MMC_TIMING_UHS_SDR50)
1442 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1443 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1444 (timing == MMC_TIMING_MMC_DDR52))
1445 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1446 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1447}
1448EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1449
66fd8ad5 1450static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1451{
d129bceb
PO		 1452 unsigned long flags;
1453 u8 ctrl;
3a48edc4 1454 struct mmc_host *mmc = host->mmc;
d129bceb 1455
d129bceb
PO		 1456 spin_lock_irqsave(&host->lock, flags);
1457
ceb6143b
AH		 1458 if (host->flags & SDHCI_DEVICE_DEAD) {
1459 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1460 if (!IS_ERR(mmc->supply.vmmc) &&
1461 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1462 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1463 return;
1464 }
1e72859e 1465
d129bceb
PO		 1466 /*
1467 * Reset the chip on each power off.
1468 * Should clear out any weird states.
1469 */
1470 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1471 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1472 sdhci_reinit(host);
d129bceb
PO		 1473 }
1474
52983382 1475 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1476 (ios->power_mode == MMC_POWER_UP) &&
1477 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1478 sdhci_enable_preset_value(host, false);
1479
373073ef 1480 if (!ios->clock || ios->clock != host->clock) {
1771059c 1481 host->ops->set_clock(host, ios->clock);
373073ef
RK		 1482 host->clock = ios->clock;
1483 }
d129bceb 1484
24fbb3ca 1485 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1486
643a81ff
PR		 1487 if (host->ops->platform_send_init_74_clocks)
1488 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1489
2317f56c 1490 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1491
15ec4461 1492 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1493
3ab9c8da
PR		 1494 if ((ios->timing == MMC_TIMING_SD_HS ||
1495 ios->timing == MMC_TIMING_MMC_HS)
1496 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1497 ctrl |= SDHCI_CTRL_HISPD;
1498 else
1499 ctrl &= ~SDHCI_CTRL_HISPD;
1500
d6d50a15 1501 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1502 u16 clk, ctrl_2;
49c468fc
AN		 1503
1504 /* In case of UHS-I modes, set High Speed Enable */
069c9f14 1505 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1506 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1507 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1508 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1509 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1510 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1511 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1512
da91a8f9 1513 if (!host->preset_enabled) {
758535c4 1514 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1515 /*
1516 * We only need to set Driver Strength if the
1517 * preset value enable is not set.
1518 */
da91a8f9 1519 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1520 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1521 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1522 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1523 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1524 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1525
1526 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1527 } else {
1528 /*
1529 * According to SDHC Spec v3.00, if the Preset Value
1530 * Enable in the Host Control 2 register is set, we
1531 * need to reset SD Clock Enable before changing High
1532 * Speed Enable to avoid generating clock gliches.
1533 */
758535c4
AN		 1534
1535 /* Reset SD Clock Enable */
1536 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1537 clk &= ~SDHCI_CLOCK_CARD_EN;
1538 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1539
1540 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1541
1542 /* Re-enable SD Clock */
1771059c 1543 host->ops->set_clock(host, host->clock);
d6d50a15 1544 }
49c468fc 1545
49c468fc
AN		 1546 /* Reset SD Clock Enable */
1547 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1548 clk &= ~SDHCI_CLOCK_CARD_EN;
1549 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1550
96d7b78c 1551 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1552 host->timing = ios->timing;
49c468fc 1553
52983382
KL		 1554 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1555 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1556 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1557 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1558 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1559 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1560 u16 preset;
1561
1562 sdhci_enable_preset_value(host, true);
1563 preset = sdhci_get_preset_value(host);
1564 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1565 >> SDHCI_PRESET_DRV_SHIFT;
1566 }
1567
49c468fc 1568 /* Re-enable SD Clock */
1771059c 1569 host->ops->set_clock(host, host->clock);
758535c4
AN		 1570 } else
1571 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1572
b8352260
LD		 1573 /*
1574 * Some (ENE) controllers go apeshit on some ios operation,
1575 * signalling timeout and CRC errors even on CMD0. Resetting
1576 * it on each ios seems to solve the problem.
1577 */
b8c86fc5 1578 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1579 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1580
5f25a66f 1581 mmiowb();
d129bceb
PO		 1582 spin_unlock_irqrestore(&host->lock, flags);
1583}
1584
66fd8ad5
AH		 1585static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1586{
1587 struct sdhci_host *host = mmc_priv(mmc);
1588
1589 sdhci_runtime_pm_get(host);
1590 sdhci_do_set_ios(host, ios);
1591 sdhci_runtime_pm_put(host);
1592}
1593
94144a46
KL		 1594static int sdhci_do_get_cd(struct sdhci_host *host)
1595{
1596 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1597
1598 if (host->flags & SDHCI_DEVICE_DEAD)
1599 return 0;
1600
1601 /* If polling/nonremovable, assume that the card is always present. */
1602 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1603 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1604 return 1;
1605
1606 /* Try slot gpio detect */
1607 if (!IS_ERR_VALUE(gpio_cd))
1608 return !!gpio_cd;
1609
1610 /* Host native card detect */
1611 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1612}
1613
1614static int sdhci_get_cd(struct mmc_host *mmc)
1615{
1616 struct sdhci_host *host = mmc_priv(mmc);
1617 int ret;
1618
1619 sdhci_runtime_pm_get(host);
1620 ret = sdhci_do_get_cd(host);
1621 sdhci_runtime_pm_put(host);
1622 return ret;
1623}
1624
66fd8ad5 1625static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1626{
d129bceb 1627 unsigned long flags;
2dfb579c 1628 int is_readonly;
d129bceb 1629
d129bceb
PO		 1630 spin_lock_irqsave(&host->lock, flags);
1631
1e72859e 1632 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1633 is_readonly = 0;
1634 else if (host->ops->get_ro)
1635 is_readonly = host->ops->get_ro(host);
1e72859e 1636 else
2dfb579c
WS		 1637 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1638 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1639
1640 spin_unlock_irqrestore(&host->lock, flags);
1641
2dfb579c
WS		 1642 /* This quirk needs to be replaced by a callback-function later */
1643 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1644 !is_readonly : is_readonly;
d129bceb
PO		 1645}
1646
82b0e23a
TI		 1647#define SAMPLE_COUNT 5
1648
66fd8ad5 1649static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1650{
82b0e23a
TI		 1651 int i, ro_count;
1652
82b0e23a 1653 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1654 return sdhci_check_ro(host);
82b0e23a
TI		 1655
1656 ro_count = 0;
1657 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1658 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1659 if (++ro_count > SAMPLE_COUNT / 2)
1660 return 1;
1661 }
1662 msleep(30);
1663 }
1664 return 0;
1665}
1666
20758b66
AH		 1667static void sdhci_hw_reset(struct mmc_host *mmc)
1668{
1669 struct sdhci_host *host = mmc_priv(mmc);
1670
1671 if (host->ops && host->ops->hw_reset)
1672 host->ops->hw_reset(host);
1673}
1674
66fd8ad5 1675static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1676{
66fd8ad5
AH		 1677 struct sdhci_host *host = mmc_priv(mmc);
1678 int ret;
f75979b7 1679
66fd8ad5
AH		 1680 sdhci_runtime_pm_get(host);
1681 ret = sdhci_do_get_ro(host);
1682 sdhci_runtime_pm_put(host);
1683 return ret;
1684}
f75979b7 1685
66fd8ad5
AH		 1686static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1687{
be138554 1688 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1689 if (enable)
b537f94c 1690 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1691 else
b537f94c
RK		 1692 host->ier &= ~SDHCI_INT_CARD_INT;
1693
1694 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1695 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1696 mmiowb();
1697 }
66fd8ad5
AH		 1698}
1699
1700static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1701{
1702 struct sdhci_host *host = mmc_priv(mmc);
1703 unsigned long flags;
f75979b7 1704
ef104333
RK		 1705 sdhci_runtime_pm_get(host);
1706
66fd8ad5 1707 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1708 if (enable)
1709 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1710 else
1711 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1712
66fd8ad5 1713 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1714 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1715
1716 sdhci_runtime_pm_put(host);
f75979b7
PO		 1717}
1718
20b92a30 1719static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1720 struct mmc_ios *ios)
f2119df6 1721{
3a48edc4 1722 struct mmc_host *mmc = host->mmc;
20b92a30 1723 u16 ctrl;
6231f3de 1724 int ret;
f2119df6 1725
20b92a30
KL		 1726 /*
1727 * Signal Voltage Switching is only applicable for Host Controllers
1728 * v3.00 and above.
1729 */
1730 if (host->version < SDHCI_SPEC_300)
1731 return 0;
6231f3de 1732
f2119df6 1733 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1734
21f5998f 1735 switch (ios->signal_voltage) {
20b92a30
KL		 1736 case MMC_SIGNAL_VOLTAGE_330:
1737 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1738 ctrl &= ~SDHCI_CTRL_VDD_180;
1739 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1740
3a48edc4
TK		 1741 if (!IS_ERR(mmc->supply.vqmmc)) {
1742 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1743 3600000);
20b92a30
KL		 1744 if (ret) {
1745 pr_warning("%s: Switching to 3.3V signalling voltage "
4e743f1f 1746 " failed\n", mmc_hostname(mmc));
20b92a30
KL		 1747 return -EIO;
1748 }
1749 }
1750 /* Wait for 5ms */
1751 usleep_range(5000, 5500);
f2119df6 1752
20b92a30
KL		 1753 /* 3.3V regulator output should be stable within 5 ms */
1754 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1755 if (!(ctrl & SDHCI_CTRL_VDD_180))
1756 return 0;
6231f3de 1757
20b92a30 1758 pr_warning("%s: 3.3V regulator output did not became stable\n",
4e743f1f 1759 mmc_hostname(mmc));
20b92a30
KL		 1760
1761 return -EAGAIN;
1762 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1763 if (!IS_ERR(mmc->supply.vqmmc)) {
1764 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1765 1700000, 1950000);
1766 if (ret) {
1767 pr_warning("%s: Switching to 1.8V signalling voltage "
4e743f1f 1768 " failed\n", mmc_hostname(mmc));
20b92a30
KL		 1769 return -EIO;
1770 }
1771 }
6231f3de 1772
6231f3de
PR		 1773 /*
1774 * Enable 1.8V Signal Enable in the Host Control2
1775 * register
1776 */
20b92a30
KL		 1777 ctrl |= SDHCI_CTRL_VDD_180;
1778 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1779
20b92a30
KL		 1780 /* 1.8V regulator output should be stable within 5 ms */
1781 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1782 if (ctrl & SDHCI_CTRL_VDD_180)
1783 return 0;
f2119df6 1784
20b92a30 1785 pr_warning("%s: 1.8V regulator output did not became stable\n",
4e743f1f 1786 mmc_hostname(mmc));
f2119df6 1787
20b92a30
KL		 1788 return -EAGAIN;
1789 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1790 if (!IS_ERR(mmc->supply.vqmmc)) {
1791 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1792 1300000);
20b92a30
KL		 1793 if (ret) {
1794 pr_warning("%s: Switching to 1.2V signalling voltage "
4e743f1f 1795 " failed\n", mmc_hostname(mmc));
20b92a30 1796 return -EIO;
f2119df6
AN		 1797 }
1798 }
6231f3de 1799 return 0;
20b92a30 1800 default:
f2119df6
AN		 1801 /* No signal voltage switch required */
1802 return 0;
20b92a30 1803 }
f2119df6
AN		 1804}
1805
66fd8ad5 1806static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1807 struct mmc_ios *ios)
66fd8ad5
AH		 1808{
1809 struct sdhci_host *host = mmc_priv(mmc);
1810 int err;
1811
1812 if (host->version < SDHCI_SPEC_300)
1813 return 0;
1814 sdhci_runtime_pm_get(host);
21f5998f 1815 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1816 sdhci_runtime_pm_put(host);
1817 return err;
1818}
1819
20b92a30
KL		 1820static int sdhci_card_busy(struct mmc_host *mmc)
1821{
1822 struct sdhci_host *host = mmc_priv(mmc);
1823 u32 present_state;
1824
1825 sdhci_runtime_pm_get(host);
1826 /* Check whether DAT[3:0] is 0000 */
1827 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1828 sdhci_runtime_pm_put(host);
1829
1830 return !(present_state & SDHCI_DATA_LVL_MASK);
1831}
1832
069c9f14 1833static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1834{
4b6f37d3 1835 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1836 u16 ctrl;
b513ea25 1837 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1838 int err = 0;
2b35bd83 1839 unsigned long flags;
b513ea25 1840
66fd8ad5 1841 sdhci_runtime_pm_get(host);
2b35bd83 1842 spin_lock_irqsave(&host->lock, flags);
b513ea25 1843
b513ea25 1844 /*
069c9f14
G		 1845 * The Host Controller needs tuning only in case of SDR104 mode
1846 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1847 * Capabilities register.
069c9f14
G		 1848 * If the Host Controller supports the HS200 mode then the
1849 * tuning function has to be executed.
b513ea25 1850 */
4b6f37d3
RK		 1851 switch (host->timing) {
1852 case MMC_TIMING_MMC_HS200:
1853 case MMC_TIMING_UHS_SDR104:
1854 break;
1855
1856 case MMC_TIMING_UHS_SDR50:
1857 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1858 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1859 break;
1860 /* FALLTHROUGH */
1861
1862 default:
2b35bd83 1863 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 1864 sdhci_runtime_pm_put(host);
b513ea25
AN		 1865 return 0;
1866 }
1867
45251812 1868 if (host->ops->platform_execute_tuning) {
2b35bd83 1869 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1870 err = host->ops->platform_execute_tuning(host, opcode);
1871 sdhci_runtime_pm_put(host);
1872 return err;
1873 }
1874
4b6f37d3
RK		 1875 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1876 ctrl |= SDHCI_CTRL_EXEC_TUNING;
b513ea25
AN		 1877 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1878
1879 /*
1880 * As per the Host Controller spec v3.00, tuning command
1881 * generates Buffer Read Ready interrupt, so enable that.
1882 *
1883 * Note: The spec clearly says that when tuning sequence
1884 * is being performed, the controller does not generate
1885 * interrupts other than Buffer Read Ready interrupt. But
1886 * to make sure we don't hit a controller bug, we _only_
1887 * enable Buffer Read Ready interrupt here.
1888 */
b537f94c
RK		 1889 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1890 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1891
1892 /*
1893 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1894 * of loops reaches 40 times or a timeout of 150ms occurs.
1895 */
b513ea25
AN		 1896 do {
1897 struct mmc_command cmd = {0};
66fd8ad5 1898 struct mmc_request mrq = {NULL};
b513ea25 1899
069c9f14 1900 cmd.opcode = opcode;
b513ea25
AN		 1901 cmd.arg = 0;
1902 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1903 cmd.retries = 0;
1904 cmd.data = NULL;
1905 cmd.error = 0;
1906
7ce45e95
AC		 1907 if (tuning_loop_counter-- == 0)
1908 break;
1909
b513ea25
AN		 1910 mrq.cmd = &cmd;
1911 host->mrq = &mrq;
1912
1913 /*
1914 * In response to CMD19, the card sends 64 bytes of tuning
1915 * block to the Host Controller. So we set the block size
1916 * to 64 here.
1917 */
069c9f14
G		 1918 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1919 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1920 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1921 SDHCI_BLOCK_SIZE);
1922 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1923 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1924 SDHCI_BLOCK_SIZE);
1925 } else {
1926 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1927 SDHCI_BLOCK_SIZE);
1928 }
b513ea25
AN		 1929
1930 /*
1931 * The tuning block is sent by the card to the host controller.
1932 * So we set the TRNS_READ bit in the Transfer Mode register.
1933 * This also takes care of setting DMA Enable and Multi Block
1934 * Select in the same register to 0.
1935 */
1936 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1937
1938 sdhci_send_command(host, &cmd);
1939
1940 host->cmd = NULL;
1941 host->mrq = NULL;
1942
2b35bd83 1943 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1944 /* Wait for Buffer Read Ready interrupt */
1945 wait_event_interruptible_timeout(host->buf_ready_int,
1946 (host->tuning_done == 1),
1947 msecs_to_jiffies(50));
2b35bd83 1948 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1949
1950 if (!host->tuning_done) {
a3c76eb9 1951 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1952 "Buffer Read Ready interrupt during tuning "
1953 "procedure, falling back to fixed sampling "
1954 "clock\n");
1955 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1956 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1957 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1958 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1959
1960 err = -EIO;
1961 goto out;
1962 }
1963
1964 host->tuning_done = 0;
1965
1966 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 1967
1968 /* eMMC spec does not require a delay between tuning cycles */
1969 if (opcode == MMC_SEND_TUNING_BLOCK)
1970 mdelay(1);
b513ea25
AN		 1971 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1972
1973 /*
1974 * The Host Driver has exhausted the maximum number of loops allowed,
1975 * so use fixed sampling frequency.
1976 */
7ce45e95 1977 if (tuning_loop_counter < 0) {
b513ea25
AN		 1978 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1979 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 1980 }
1981 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1982 pr_info(DRIVER_NAME ": Tuning procedure"
1983 " failed, falling back to fixed sampling"
1984 " clock\n");
114f2bf6 1985 err = -EIO;
b513ea25
AN		 1986 }
1987
1988out:
cf2b5eea
AN		 1989 /*
1990 * If this is the very first time we are here, we start the retuning
1991 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1992 * flag won't be set, we check this condition before actually starting
1993 * the timer.
1994 */
1995 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1996 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 1997 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 1998 mod_timer(&host->tuning_timer, jiffies +
1999 host->tuning_count * HZ);
2000 /* Tuning mode 1 limits the maximum data length to 4MB */
2001 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2bc02485 2002 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
cf2b5eea
AN		 2003 host->flags &= ~SDHCI_NEEDS_RETUNING;
2004 /* Reload the new initial value for timer */
2bc02485
AS		 2005 mod_timer(&host->tuning_timer, jiffies +
2006 host->tuning_count * HZ);
cf2b5eea
AN		 2007 }
2008
2009 /*
2010 * In case tuning fails, host controllers which support re-tuning can
2011 * try tuning again at a later time, when the re-tuning timer expires.
2012 * So for these controllers, we return 0. Since there might be other
2013 * controllers who do not have this capability, we return error for
973905fe
AL		 2014 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2015 * a retuning timer to do the retuning for the card.
cf2b5eea 2016 */
973905fe 2017 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2018 err = 0;
2019
b537f94c
RK		 2020 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2021 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2b35bd83 2022 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2023 sdhci_runtime_pm_put(host);
b513ea25
AN		 2024
2025 return err;
2026}
2027
52983382
KL		 2028
2029static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2030{
4d55c5a1
AN		 2031 /* Host Controller v3.00 defines preset value registers */
2032 if (host->version < SDHCI_SPEC_300)
2033 return;
2034
4d55c5a1
AN		 2035 /*
2036 * We only enable or disable Preset Value if they are not already
2037 * enabled or disabled respectively. Otherwise, we bail out.
2038 */
da91a8f9
RK		 2039 if (host->preset_enabled != enable) {
2040 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2041
2042 if (enable)
2043 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2044 else
2045 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2046
4d55c5a1 2047 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2048
2049 if (enable)
2050 host->flags |= SDHCI_PV_ENABLED;
2051 else
2052 host->flags &= ~SDHCI_PV_ENABLED;
2053
2054 host->preset_enabled = enable;
4d55c5a1 2055 }
66fd8ad5
AH		 2056}
2057
71e69211 2058static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2059{
71e69211 2060 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2061 unsigned long flags;
2062
722e1280
CD		 2063 /* First check if client has provided their own card event */
2064 if (host->ops->card_event)
2065 host->ops->card_event(host);
2066
d129bceb
PO		 2067 spin_lock_irqsave(&host->lock, flags);
2068
66fd8ad5 2069 /* Check host->mrq first in case we are runtime suspended */
9668d765 2070 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2071 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2072 mmc_hostname(host->mmc));
a3c76eb9 2073 pr_err("%s: Resetting controller.\n",
66fd8ad5 2074 mmc_hostname(host->mmc));
d129bceb 2075
03231f9b
RK		 2076 sdhci_do_reset(host, SDHCI_RESET_CMD);
2077 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2078
66fd8ad5
AH		 2079 host->mrq->cmd->error = -ENOMEDIUM;
2080 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2081 }
2082
2083 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2084}
2085
2086static const struct mmc_host_ops sdhci_ops = {
2087 .request = sdhci_request,
2088 .set_ios = sdhci_set_ios,
94144a46 2089 .get_cd = sdhci_get_cd,
71e69211
GL		 2090 .get_ro = sdhci_get_ro,
2091 .hw_reset = sdhci_hw_reset,
2092 .enable_sdio_irq = sdhci_enable_sdio_irq,
2093 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2094 .execute_tuning = sdhci_execute_tuning,
71e69211 2095 .card_event = sdhci_card_event,
20b92a30 2096 .card_busy = sdhci_card_busy,
71e69211
GL		 2097};
2098
2099/*****************************************************************************\
2100 * *
2101 * Tasklets *
2102 * *
2103\*****************************************************************************/
2104
d129bceb
PO		 2105static void sdhci_tasklet_finish(unsigned long param)
2106{
2107 struct sdhci_host *host;
2108 unsigned long flags;
2109 struct mmc_request *mrq;
2110
2111 host = (struct sdhci_host*)param;
2112
66fd8ad5
AH		 2113 spin_lock_irqsave(&host->lock, flags);
2114
0c9c99a7
CB		 2115 /*
2116 * If this tasklet gets rescheduled while running, it will
2117 * be run again afterwards but without any active request.
2118 */
66fd8ad5
AH		 2119 if (!host->mrq) {
2120 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2121 return;
66fd8ad5 2122 }
d129bceb
PO		 2123
2124 del_timer(&host->timer);
2125
2126 mrq = host->mrq;
2127
d129bceb
PO		 2128 /*
2129 * The controller needs a reset of internal state machines
2130 * upon error conditions.
2131 */
1e72859e 2132 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2133 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2134 (mrq->data && (mrq->data->error ||
2135 (mrq->data->stop && mrq->data->stop->error))) ||
2136 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2137
2138 /* Some controllers need this kick or reset won't work here */
8213af3b 2139 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2140 /* This is to force an update */
1771059c 2141 host->ops->set_clock(host, host->clock);
645289dc
PO		 2142
2143 /* Spec says we should do both at the same time, but Ricoh
2144 controllers do not like that. */
03231f9b
RK		 2145 sdhci_do_reset(host, SDHCI_RESET_CMD);
2146 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2147 }
2148
2149 host->mrq = NULL;
2150 host->cmd = NULL;
2151 host->data = NULL;
2152
f9134319 2153#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2154 sdhci_deactivate_led(host);
2f730fec 2155#endif
d129bceb 2156
5f25a66f 2157 mmiowb();
d129bceb
PO		 2158 spin_unlock_irqrestore(&host->lock, flags);
2159
2160 mmc_request_done(host->mmc, mrq);
66fd8ad5 2161 sdhci_runtime_pm_put(host);
d129bceb
PO		 2162}
2163
2164static void sdhci_timeout_timer(unsigned long data)
2165{
2166 struct sdhci_host *host;
2167 unsigned long flags;
2168
2169 host = (struct sdhci_host*)data;
2170
2171 spin_lock_irqsave(&host->lock, flags);
2172
2173 if (host->mrq) {
a3c76eb9 2174 pr_err("%s: Timeout waiting for hardware "
acf1da45 2175 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2176 sdhci_dumpregs(host);
2177
2178 if (host->data) {
17b0429d 2179 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2180 sdhci_finish_data(host);
2181 } else {
2182 if (host->cmd)
17b0429d 2183 host->cmd->error = -ETIMEDOUT;
d129bceb 2184 else
17b0429d 2185 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2186
2187 tasklet_schedule(&host->finish_tasklet);
2188 }
2189 }
2190
5f25a66f 2191 mmiowb();
d129bceb
PO		 2192 spin_unlock_irqrestore(&host->lock, flags);
2193}
2194
cf2b5eea
AN		 2195static void sdhci_tuning_timer(unsigned long data)
2196{
2197 struct sdhci_host *host;
2198 unsigned long flags;
2199
2200 host = (struct sdhci_host *)data;
2201
2202 spin_lock_irqsave(&host->lock, flags);
2203
2204 host->flags |= SDHCI_NEEDS_RETUNING;
2205
2206 spin_unlock_irqrestore(&host->lock, flags);
2207}
2208
d129bceb
PO		 2209/*****************************************************************************\
2210 * *
2211 * Interrupt handling *
2212 * *
2213\*****************************************************************************/
2214
2215static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2216{
2217 BUG_ON(intmask == 0);
2218
2219 if (!host->cmd) {
a3c76eb9 2220 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2221 "though no command operation was in progress.\n",
2222 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2223 sdhci_dumpregs(host);
2224 return;
2225 }
2226
43b58b36 2227 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2228 host->cmd->error = -ETIMEDOUT;
2229 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2230 SDHCI_INT_INDEX))
2231 host->cmd->error = -EILSEQ;
43b58b36 2232
e809517f 2233 if (host->cmd->error) {
d129bceb 2234 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2235 return;
2236 }
2237
2238 /*
2239 * The host can send and interrupt when the busy state has
2240 * ended, allowing us to wait without wasting CPU cycles.
2241 * Unfortunately this is overloaded on the "data complete"
2242 * interrupt, so we need to take some care when handling
2243 * it.
2244 *
2245 * Note: The 1.0 specification is a bit ambiguous about this
2246 * feature so there might be some problems with older
2247 * controllers.
2248 */
2249 if (host->cmd->flags & MMC_RSP_BUSY) {
2250 if (host->cmd->data)
2251 DBG("Cannot wait for busy signal when also "
2252 "doing a data transfer");
f945405c 2253 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2254 return;
f945405c
BD		 2255
2256 /* The controller does not support the end-of-busy IRQ,
2257 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2258 }
2259
2260 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2261 sdhci_finish_command(host);
d129bceb
PO		 2262}
2263
0957c333 2264#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2265static void sdhci_show_adma_error(struct sdhci_host *host)
2266{
2267 const char *name = mmc_hostname(host->mmc);
2268 u8 *desc = host->adma_desc;
2269 __le32 *dma;
2270 __le16 *len;
2271 u8 attr;
2272
2273 sdhci_dumpregs(host);
2274
2275 while (true) {
2276 dma = (__le32 *)(desc + 4);
2277 len = (__le16 *)(desc + 2);
2278 attr = *desc;
2279
2280 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2281 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2282
2283 desc += 8;
2284
2285 if (attr & 2)
2286 break;
2287 }
2288}
2289#else
2290static void sdhci_show_adma_error(struct sdhci_host *host) { }
2291#endif
2292
d129bceb
PO		 2293static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2294{
069c9f14 2295 u32 command;
d129bceb
PO		 2296 BUG_ON(intmask == 0);
2297
b513ea25
AN		 2298 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2299 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2300 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2301 if (command == MMC_SEND_TUNING_BLOCK ||
2302 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2303 host->tuning_done = 1;
2304 wake_up(&host->buf_ready_int);
2305 return;
2306 }
2307 }
2308
d129bceb
PO		 2309 if (!host->data) {
2310 /*
e809517f
PO		 2311 * The "data complete" interrupt is also used to
2312 * indicate that a busy state has ended. See comment
2313 * above in sdhci_cmd_irq().
d129bceb 2314 */
e809517f 2315 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2316 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2317 host->cmd->error = -ETIMEDOUT;
2318 tasklet_schedule(&host->finish_tasklet);
2319 return;
2320 }
e809517f
PO		 2321 if (intmask & SDHCI_INT_DATA_END) {
2322 sdhci_finish_command(host);
2323 return;
2324 }
2325 }
d129bceb 2326
a3c76eb9 2327 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2328 "though no data operation was in progress.\n",
2329 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2330 sdhci_dumpregs(host);
2331
2332 return;
2333 }
2334
2335 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2336 host->data->error = -ETIMEDOUT;
22113efd
AL		 2337 else if (intmask & SDHCI_INT_DATA_END_BIT)
2338 host->data->error = -EILSEQ;
2339 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2340 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2341 != MMC_BUS_TEST_R)
17b0429d 2342 host->data->error = -EILSEQ;
6882a8c0 2343 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2344 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2345 sdhci_show_adma_error(host);
2134a922 2346 host->data->error = -EIO;
a4071fbb
HZ		 2347 if (host->ops->adma_workaround)
2348 host->ops->adma_workaround(host, intmask);
6882a8c0 2349 }
d129bceb 2350
17b0429d 2351 if (host->data->error)
d129bceb
PO		 2352 sdhci_finish_data(host);
2353 else {
a406f5a3 2354 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2355 sdhci_transfer_pio(host);
2356
6ba736a1
PO		 2357 /*
2358 * We currently don't do anything fancy with DMA
2359 * boundaries, but as we can't disable the feature
2360 * we need to at least restart the transfer.
f6a03cbf
MV		 2361 *
2362 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2363 * should return a valid address to continue from, but as
2364 * some controllers are faulty, don't trust them.
6ba736a1 2365 */
f6a03cbf
MV		 2366 if (intmask & SDHCI_INT_DMA_END) {
2367 u32 dmastart, dmanow;
2368 dmastart = sg_dma_address(host->data->sg);
2369 dmanow = dmastart + host->data->bytes_xfered;
2370 /*
2371 * Force update to the next DMA block boundary.
2372 */
2373 dmanow = (dmanow &
2374 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2375 SDHCI_DEFAULT_BOUNDARY_SIZE;
2376 host->data->bytes_xfered = dmanow - dmastart;
2377 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2378 " next 0x%08x\n",
2379 mmc_hostname(host->mmc), dmastart,
2380 host->data->bytes_xfered, dmanow);
2381 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2382 }
6ba736a1 2383
e538fbe8
PO		 2384 if (intmask & SDHCI_INT_DATA_END) {
2385 if (host->cmd) {
2386 /*
2387 * Data managed to finish before the
2388 * command completed. Make sure we do
2389 * things in the proper order.
2390 */
2391 host->data_early = 1;
2392 } else {
2393 sdhci_finish_data(host);
2394 }
2395 }
d129bceb
PO		 2396 }
2397}
2398
7d12e780 2399static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2400{
781e989c 2401 irqreturn_t result = IRQ_NONE;
66fd8ad5 2402 struct sdhci_host *host = dev_id;
41005003 2403 u32 intmask, mask, unexpected = 0;
781e989c 2404 int max_loops = 16;
d129bceb
PO		 2405
2406 spin_lock(&host->lock);
2407
be138554 2408 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2409 spin_unlock(&host->lock);
655bca76 2410 return IRQ_NONE;
66fd8ad5
AH		 2411 }
2412
4e4141a5 2413 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2414 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2415 result = IRQ_NONE;
2416 goto out;
2417 }
2418
41005003
RK		 2419 do {
2420 /* Clear selected interrupts. */
2421 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2422 SDHCI_INT_BUS_POWER);
2423 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2424
41005003
RK		 2425 DBG("*** %s got interrupt: 0x%08x\n",
2426 mmc_hostname(host->mmc), intmask);
d129bceb 2427
41005003
RK		 2428 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2429 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2430 SDHCI_CARD_PRESENT;
d129bceb 2431
41005003
RK		 2432 /*
2433 * There is a observation on i.mx esdhc. INSERT
2434 * bit will be immediately set again when it gets
2435 * cleared, if a card is inserted. We have to mask
2436 * the irq to prevent interrupt storm which will
2437 * freeze the system. And the REMOVE gets the
2438 * same situation.
2439 *
2440 * More testing are needed here to ensure it works
2441 * for other platforms though.
2442 */
b537f94c
RK		 2443 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2444 SDHCI_INT_CARD_REMOVE);
2445 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2446 SDHCI_INT_CARD_INSERT;
2447 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2448 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2449
2450 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2451 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2452
2453 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2454 SDHCI_INT_CARD_REMOVE);
2455 result = IRQ_WAKE_THREAD;
41005003 2456 }
d129bceb 2457
41005003
RK		 2458 if (intmask & SDHCI_INT_CMD_MASK)
2459 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
964f9ce2 2460
41005003
RK		 2461 if (intmask & SDHCI_INT_DATA_MASK)
2462 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2463
41005003
RK		 2464 if (intmask & SDHCI_INT_BUS_POWER)
2465 pr_err("%s: Card is consuming too much power!\n",
2466 mmc_hostname(host->mmc));
3192a28f 2467
781e989c
RK		 2468 if (intmask & SDHCI_INT_CARD_INT) {
2469 sdhci_enable_sdio_irq_nolock(host, false);
2470 host->thread_isr |= SDHCI_INT_CARD_INT;
2471 result = IRQ_WAKE_THREAD;
2472 }
f75979b7 2473
41005003
RK		 2474 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2475 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2476 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2477 SDHCI_INT_CARD_INT);
f75979b7 2478
41005003
RK		 2479 if (intmask) {
2480 unexpected |= intmask;
2481 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2482 }
d129bceb 2483
781e989c
RK		 2484 if (result == IRQ_NONE)
2485 result = IRQ_HANDLED;
d129bceb 2486
41005003 2487 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2488 } while (intmask && --max_loops);
d129bceb
PO		 2489out:
2490 spin_unlock(&host->lock);
2491
6379b237
AS		 2492 if (unexpected) {
2493 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2494 mmc_hostname(host->mmc), unexpected);
2495 sdhci_dumpregs(host);
2496 }
f75979b7 2497
d129bceb
PO		 2498 return result;
2499}
2500
781e989c
RK		 2501static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2502{
2503 struct sdhci_host *host = dev_id;
2504 unsigned long flags;
2505 u32 isr;
2506
2507 spin_lock_irqsave(&host->lock, flags);
2508 isr = host->thread_isr;
2509 host->thread_isr = 0;
2510 spin_unlock_irqrestore(&host->lock, flags);
2511
3560db8e
RK		 2512 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2513 sdhci_card_event(host->mmc);
2514 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2515 }
2516
781e989c
RK		 2517 if (isr & SDHCI_INT_CARD_INT) {
2518 sdio_run_irqs(host->mmc);
2519
2520 spin_lock_irqsave(&host->lock, flags);
2521 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2522 sdhci_enable_sdio_irq_nolock(host, true);
2523 spin_unlock_irqrestore(&host->lock, flags);
2524 }
2525
2526 return isr ? IRQ_HANDLED : IRQ_NONE;
2527}
2528
d129bceb
PO		 2529/*****************************************************************************\
2530 * *
2531 * Suspend/resume *
2532 * *
2533\*****************************************************************************/
2534
2535#ifdef CONFIG_PM
ad080d79
KL		 2536void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2537{
2538 u8 val;
2539 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2540 | SDHCI_WAKE_ON_INT;
2541
2542 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2543 val |= mask ;
2544 /* Avoid fake wake up */
2545 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2546 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2547 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2548}
2549EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2550
2551void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2552{
2553 u8 val;
2554 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2555 | SDHCI_WAKE_ON_INT;
2556
2557 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2558 val &= ~mask;
2559 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2560}
2561EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
d129bceb 2562
29495aa0 2563int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2564{
7260cf5e
AV		 2565 sdhci_disable_card_detection(host);
2566
cf2b5eea 2567 /* Disable tuning since we are suspending */
973905fe 2568 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2569 del_timer_sync(&host->tuning_timer);
cf2b5eea 2570 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2571 }
2572
ad080d79 2573 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2574 host->ier = 0;
2575 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2576 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2577 free_irq(host->irq, host);
2578 } else {
2579 sdhci_enable_irq_wakeups(host);
2580 enable_irq_wake(host->irq);
2581 }
4ee14ec6 2582 return 0;
d129bceb
PO		 2583}
2584
b8c86fc5 2585EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2586
b8c86fc5
PO		 2587int sdhci_resume_host(struct sdhci_host *host)
2588{
4ee14ec6 2589 int ret = 0;
d129bceb 2590
a13abc7b 2591 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2592 if (host->ops->enable_dma)
2593 host->ops->enable_dma(host);
2594 }
d129bceb 2595
ad080d79 2596 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2597 ret = request_threaded_irq(host->irq, sdhci_irq,
2598 sdhci_thread_irq, IRQF_SHARED,
2599 mmc_hostname(host->mmc), host);
ad080d79
KL		 2600 if (ret)
2601 return ret;
2602 } else {
2603 sdhci_disable_irq_wakeups(host);
2604 disable_irq_wake(host->irq);
2605 }
d129bceb 2606
6308d290
AH		 2607 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2608 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2609 /* Card keeps power but host controller does not */
2610 sdhci_init(host, 0);
2611 host->pwr = 0;
2612 host->clock = 0;
2613 sdhci_do_set_ios(host, &host->mmc->ios);
2614 } else {
2615 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2616 mmiowb();
2617 }
b8c86fc5 2618
7260cf5e
AV		 2619 sdhci_enable_card_detection(host);
2620
cf2b5eea 2621 /* Set the re-tuning expiration flag */
973905fe 2622 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2623 host->flags |= SDHCI_NEEDS_RETUNING;
2624
2f4cbb3d 2625 return ret;
d129bceb
PO		 2626}
2627
b8c86fc5 2628EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2629#endif /* CONFIG_PM */
2630
66fd8ad5
AH		 2631#ifdef CONFIG_PM_RUNTIME
2632
2633static int sdhci_runtime_pm_get(struct sdhci_host *host)
2634{
2635 return pm_runtime_get_sync(host->mmc->parent);
2636}
2637
2638static int sdhci_runtime_pm_put(struct sdhci_host *host)
2639{
2640 pm_runtime_mark_last_busy(host->mmc->parent);
2641 return pm_runtime_put_autosuspend(host->mmc->parent);
2642}
2643
f0710a55
AH		 2644static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2645{
2646 if (host->runtime_suspended || host->bus_on)
2647 return;
2648 host->bus_on = true;
2649 pm_runtime_get_noresume(host->mmc->parent);
2650}
2651
2652static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2653{
2654 if (host->runtime_suspended || !host->bus_on)
2655 return;
2656 host->bus_on = false;
2657 pm_runtime_put_noidle(host->mmc->parent);
2658}
2659
66fd8ad5
AH		 2660int sdhci_runtime_suspend_host(struct sdhci_host *host)
2661{
2662 unsigned long flags;
66fd8ad5
AH		 2663
2664 /* Disable tuning since we are suspending */
973905fe 2665 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2666 del_timer_sync(&host->tuning_timer);
2667 host->flags &= ~SDHCI_NEEDS_RETUNING;
2668 }
2669
2670 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2671 host->ier &= SDHCI_INT_CARD_INT;
2672 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2673 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2674 spin_unlock_irqrestore(&host->lock, flags);
2675
781e989c 2676 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2677
2678 spin_lock_irqsave(&host->lock, flags);
2679 host->runtime_suspended = true;
2680 spin_unlock_irqrestore(&host->lock, flags);
2681
8a125bad 2682 return 0;
66fd8ad5
AH		 2683}
2684EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2685
2686int sdhci_runtime_resume_host(struct sdhci_host *host)
2687{
2688 unsigned long flags;
8a125bad 2689 int host_flags = host->flags;
66fd8ad5
AH		 2690
2691 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2692 if (host->ops->enable_dma)
2693 host->ops->enable_dma(host);
2694 }
2695
2696 sdhci_init(host, 0);
2697
2698 /* Force clock and power re-program */
2699 host->pwr = 0;
2700 host->clock = 0;
2701 sdhci_do_set_ios(host, &host->mmc->ios);
2702
2703 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2704 if ((host_flags & SDHCI_PV_ENABLED) &&
2705 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2706 spin_lock_irqsave(&host->lock, flags);
2707 sdhci_enable_preset_value(host, true);
2708 spin_unlock_irqrestore(&host->lock, flags);
2709 }
66fd8ad5
AH		 2710
2711 /* Set the re-tuning expiration flag */
973905fe 2712 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2713 host->flags |= SDHCI_NEEDS_RETUNING;
2714
2715 spin_lock_irqsave(&host->lock, flags);
2716
2717 host->runtime_suspended = false;
2718
2719 /* Enable SDIO IRQ */
ef104333 2720 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2721 sdhci_enable_sdio_irq_nolock(host, true);
2722
2723 /* Enable Card Detection */
2724 sdhci_enable_card_detection(host);
2725
2726 spin_unlock_irqrestore(&host->lock, flags);
2727
8a125bad 2728 return 0;
66fd8ad5
AH		 2729}
2730EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2731
2732#endif
2733
d129bceb
PO		 2734/*****************************************************************************\
2735 * *
b8c86fc5 2736 * Device allocation/registration *
d129bceb
PO		 2737 * *
2738\*****************************************************************************/
2739
b8c86fc5
PO		 2740struct sdhci_host *sdhci_alloc_host(struct device *dev,
2741 size_t priv_size)
d129bceb 2742{
d129bceb
PO		 2743 struct mmc_host *mmc;
2744 struct sdhci_host *host;
2745
b8c86fc5 2746 WARN_ON(dev == NULL);
d129bceb 2747
b8c86fc5 2748 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2749 if (!mmc)
b8c86fc5 2750 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2751
2752 host = mmc_priv(mmc);
2753 host->mmc = mmc;
2754
b8c86fc5
PO		 2755 return host;
2756}
8a4da143 2757
b8c86fc5 2758EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2759
b8c86fc5
PO		 2760int sdhci_add_host(struct sdhci_host *host)
2761{
2762 struct mmc_host *mmc;
bd6a8c30 2763 u32 caps[2] = {0, 0};
f2119df6
AN		 2764 u32 max_current_caps;
2765 unsigned int ocr_avail;
b8c86fc5 2766 int ret;
d129bceb 2767
b8c86fc5
PO		 2768 WARN_ON(host == NULL);
2769 if (host == NULL)
2770 return -EINVAL;
d129bceb 2771
b8c86fc5 2772 mmc = host->mmc;
d129bceb 2773
b8c86fc5
PO		 2774 if (debug_quirks)
2775 host->quirks = debug_quirks;
66fd8ad5
AH		 2776 if (debug_quirks2)
2777 host->quirks2 = debug_quirks2;
d129bceb 2778
03231f9b 2779 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2780
4e4141a5 2781 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2782 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2783 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2784 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2785 pr_err("%s: Unknown controller version (%d). "
b69c9058 2786 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2787 host->version);
4a965505
PO		 2788 }
2789
f2119df6 2790 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2791 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2792
bd6a8c30
PR		 2793 if (host->version >= SDHCI_SPEC_300)
2794 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2795 host->caps1 :
2796 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2797
b8c86fc5 2798 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2799 host->flags |= SDHCI_USE_SDMA;
f2119df6 2800 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2801 DBG("Controller doesn't have SDMA capability\n");
67435274 2802 else
a13abc7b 2803 host->flags |= SDHCI_USE_SDMA;
d129bceb 2804
b8c86fc5 2805 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2806 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2807 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2808 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2809 }
2810
f2119df6
AN		 2811 if ((host->version >= SDHCI_SPEC_200) &&
2812 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2813 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2814
2815 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2816 (host->flags & SDHCI_USE_ADMA)) {
2817 DBG("Disabling ADMA as it is marked broken\n");
2818 host->flags &= ~SDHCI_USE_ADMA;
2819 }
2820
a13abc7b 2821 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2822 if (host->ops->enable_dma) {
2823 if (host->ops->enable_dma(host)) {
a3c76eb9 2824 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2825 "available. Falling back to PIO.\n",
2826 mmc_hostname(mmc));
a13abc7b
RR		 2827 host->flags &=
2828 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2829 }
d129bceb
PO		 2830 }
2831 }
2832
2134a922
PO		 2833 if (host->flags & SDHCI_USE_ADMA) {
2834 /*
2835 * We need to allocate descriptors for all sg entries
2836 * (128) and potentially one alignment transfer for
2837 * each of those entries.
2838 */
4e743f1f 2839 host->adma_desc = dma_alloc_coherent(mmc_dev(mmc),
d1e49f77
RK		 2840 ADMA_SIZE, &host->adma_addr,
2841 GFP_KERNEL);
2134a922
PO		 2842 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2843 if (!host->adma_desc || !host->align_buffer) {
4e743f1f 2844 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
d1e49f77 2845 host->adma_desc, host->adma_addr);
2134a922 2846 kfree(host->align_buffer);
a3c76eb9 2847 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2848 "buffers. Falling back to standard DMA.\n",
2849 mmc_hostname(mmc));
2850 host->flags &= ~SDHCI_USE_ADMA;
d1e49f77
RK		 2851 host->adma_desc = NULL;
2852 host->align_buffer = NULL;
2853 } else if (host->adma_addr & 3) {
2854 pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2855 mmc_hostname(mmc));
2856 host->flags &= ~SDHCI_USE_ADMA;
4e743f1f 2857 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
d1e49f77
RK		 2858 host->adma_desc, host->adma_addr);
2859 kfree(host->align_buffer);
2860 host->adma_desc = NULL;
2861 host->align_buffer = NULL;
2134a922
PO		 2862 }
2863 }
2864
7659150c
PO		 2865 /*
2866 * If we use DMA, then it's up to the caller to set the DMA
2867 * mask, but PIO does not need the hw shim so we set a new
2868 * mask here in that case.
2869 */
a13abc7b 2870 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 2871 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 2872 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 2873 }
d129bceb 2874
c4687d5f 2875 if (host->version >= SDHCI_SPEC_300)
f2119df6 2876 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2877 >> SDHCI_CLOCK_BASE_SHIFT;
2878 else
f2119df6 2879 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2880 >> SDHCI_CLOCK_BASE_SHIFT;
2881
4240ff0a 2882 host->max_clk *= 1000000;
f27f47ef
AV		 2883 if (host->max_clk == 0 || host->quirks &
2884 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2885 if (!host->ops->get_max_clock) {
a3c76eb9 2886 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2887 "frequency.\n", mmc_hostname(mmc));
2888 return -ENODEV;
2889 }
2890 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2891 }
d129bceb 2892
c3ed3877
AN		 2893 /*
2894 * In case of Host Controller v3.00, find out whether clock
2895 * multiplier is supported.
2896 */
2897 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2898 SDHCI_CLOCK_MUL_SHIFT;
2899
2900 /*
2901 * In case the value in Clock Multiplier is 0, then programmable
2902 * clock mode is not supported, otherwise the actual clock
2903 * multiplier is one more than the value of Clock Multiplier
2904 * in the Capabilities Register.
2905 */
2906 if (host->clk_mul)
2907 host->clk_mul += 1;
2908
d129bceb
PO		 2909 /*
2910 * Set host parameters.
2911 */
2912 mmc->ops = &sdhci_ops;
c3ed3877 2913 mmc->f_max = host->max_clk;
ce5f036b 2914 if (host->ops->get_min_clock)
a9e58f25 2915 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2916 else if (host->version >= SDHCI_SPEC_300) {
2917 if (host->clk_mul) {
2918 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2919 mmc->f_max = host->max_clk * host->clk_mul;
2920 } else
2921 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2922 } else
0397526d 2923 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2924
272308ca
AS		 2925 host->timeout_clk =
2926 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2927 if (host->timeout_clk == 0) {
2928 if (host->ops->get_timeout_clock) {
2929 host->timeout_clk = host->ops->get_timeout_clock(host);
2930 } else if (!(host->quirks &
2931 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2932 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2933 "frequency.\n", mmc_hostname(mmc));
2934 return -ENODEV;
2935 }
2936 }
2937 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2938 host->timeout_clk *= 1000;
2939
2940 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2941 host->timeout_clk = mmc->f_max / 1000;
272308ca 2942
a6ff5aeb
AD		 2943 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
2944 host->ops->get_max_timeout_count(host) : 1 << 27;
2945 mmc->max_busy_timeout /= host->timeout_clk;
58d1246d 2946
e89d456f 2947 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 2948 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 2949
2950 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2951 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2952
8edf6371 2953 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2954 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2955 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2956 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2957 host->flags |= SDHCI_AUTO_CMD23;
2958 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2959 } else {
2960 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2961 }
2962
15ec4461
PR		 2963 /*
2964 * A controller may support 8-bit width, but the board itself
2965 * might not have the pins brought out. Boards that support
2966 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2967 * their platform code before calling sdhci_add_host(), and we
2968 * won't assume 8-bit width for hosts without that CAP.
2969 */
5fe23c7f 2970 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2971 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2972
63ef5d8c
JH		 2973 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2974 mmc->caps &= ~MMC_CAP_CMD23;
2975
f2119df6 2976 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2977 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2978
176d1ed4 2979 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4e743f1f 2980 !(mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 2981 mmc->caps |= MMC_CAP_NEEDS_POLL;
2982
3a48edc4
TK		 2983 /* If there are external regulators, get them */
2984 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
2985 return -EPROBE_DEFER;
2986
6231f3de 2987 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 2988 if (!IS_ERR(mmc->supply.vqmmc)) {
2989 ret = regulator_enable(mmc->supply.vqmmc);
2990 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
2991 1950000))
8363c374
KL		 2992 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2993 SDHCI_SUPPORT_SDR50 |
2994 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 2995 if (ret) {
2996 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2997 mmc_hostname(mmc), ret);
3a48edc4 2998 mmc->supply.vqmmc = NULL;
a3361aba 2999 }
8363c374 3000 }
6231f3de 3001
6a66180a
DD		 3002 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3003 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3004 SDHCI_SUPPORT_DDR50);
3005
4188bba0
AC		 3006 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3007 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3008 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3009 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3010
3011 /* SDR104 supports also implies SDR50 support */
156e14b1 3012 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3013 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3014 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3015 * field can be promoted to support HS200.
3016 */
13868bf2
DC		 3017 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3018 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3019 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3020 mmc->caps |= MMC_CAP_UHS_SDR50;
3021
9107ebbf
MC		 3022 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3023 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3024 mmc->caps |= MMC_CAP_UHS_DDR50;
3025
069c9f14 3026 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3027 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3028 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3029
156e14b1 3030 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3031 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3032 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3033
d6d50a15
AN		 3034 /* Driver Type(s) (A, C, D) supported by the host */
3035 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3036 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3037 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3038 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3039 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3040 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3041
cf2b5eea
AN		 3042 /* Initial value for re-tuning timer count */
3043 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3044 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3045
3046 /*
3047 * In case Re-tuning Timer is not disabled, the actual value of
3048 * re-tuning timer will be 2 ^ (n - 1).
3049 */
3050 if (host->tuning_count)
3051 host->tuning_count = 1 << (host->tuning_count - 1);
3052
3053 /* Re-tuning mode supported by the Host Controller */
3054 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3055 SDHCI_RETUNING_MODE_SHIFT;
3056
8f230f45 3057 ocr_avail = 0;
bad37e1a 3058
f2119df6
AN		 3059 /*
3060 * According to SD Host Controller spec v3.00, if the Host System
3061 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3062 * the value is meaningful only if Voltage Support in the Capabilities
3063 * register is set. The actual current value is 4 times the register
3064 * value.
3065 */
3066 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3067 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3068 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3069 if (curr > 0) {
3070
3071 /* convert to SDHCI_MAX_CURRENT format */
3072 curr = curr/1000; /* convert to mA */
3073 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3074
3075 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3076 max_current_caps =
3077 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3078 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3079 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3080 }
3081 }
f2119df6
AN		 3082
3083 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3084 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3085
55c4665e 3086 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3087 SDHCI_MAX_CURRENT_330_MASK) >>
3088 SDHCI_MAX_CURRENT_330_SHIFT) *
3089 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3090 }
3091 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3092 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3093
55c4665e 3094 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3095 SDHCI_MAX_CURRENT_300_MASK) >>
3096 SDHCI_MAX_CURRENT_300_SHIFT) *
3097 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3098 }
3099 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3100 ocr_avail |= MMC_VDD_165_195;
3101
55c4665e 3102 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3103 SDHCI_MAX_CURRENT_180_MASK) >>
3104 SDHCI_MAX_CURRENT_180_SHIFT) *
3105 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3106 }
3107
52221610 3108 /* If OCR set by external regulators, use it instead */
3a48edc4 3109 if (mmc->ocr_avail)
52221610 3110 ocr_avail = mmc->ocr_avail;
3a48edc4 3111
c0b887b6 3112 if (host->ocr_mask)
3a48edc4 3113 ocr_avail &= host->ocr_mask;
c0b887b6 3114
8f230f45
TI		 3115 mmc->ocr_avail = ocr_avail;
3116 mmc->ocr_avail_sdio = ocr_avail;
3117 if (host->ocr_avail_sdio)
3118 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3119 mmc->ocr_avail_sd = ocr_avail;
3120 if (host->ocr_avail_sd)
3121 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3122 else /* normal SD controllers don't support 1.8V */
3123 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3124 mmc->ocr_avail_mmc = ocr_avail;
3125 if (host->ocr_avail_mmc)
3126 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3127
3128 if (mmc->ocr_avail == 0) {
a3c76eb9 3129 pr_err("%s: Hardware doesn't report any "
b69c9058 3130 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3131 return -ENODEV;
146ad66e
PO		 3132 }
3133
d129bceb
PO		 3134 spin_lock_init(&host->lock);
3135
3136 /*
2134a922
PO		 3137 * Maximum number of segments. Depends on if the hardware
3138 * can do scatter/gather or not.
d129bceb 3139 */
2134a922 3140 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3141 mmc->max_segs = 128;
a13abc7b 3142 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3143 mmc->max_segs = 1;
2134a922 3144 else /* PIO */
a36274e0 3145 mmc->max_segs = 128;
d129bceb
PO		 3146
3147 /*
bab76961 3148 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3149 * size (512KiB).
d129bceb 3150 */
55db890a 3151 mmc->max_req_size = 524288;
d129bceb
PO		 3152
3153 /*
3154 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3155 * of bytes. When doing hardware scatter/gather, each entry cannot
3156 * be larger than 64 KiB though.
d129bceb 3157 */
30652aa3
OJ		 3158 if (host->flags & SDHCI_USE_ADMA) {
3159 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3160 mmc->max_seg_size = 65535;
3161 else
3162 mmc->max_seg_size = 65536;
3163 } else {
2134a922 3164 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3165 }
d129bceb 3166
fe4a3c7a
PO		 3167 /*
3168 * Maximum block size. This varies from controller to controller and
3169 * is specified in the capabilities register.
3170 */
0633f654
AV		 3171 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3172 mmc->max_blk_size = 2;
3173 } else {
f2119df6 3174 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3175 SDHCI_MAX_BLOCK_SHIFT;
3176 if (mmc->max_blk_size >= 3) {
a3c76eb9 3177 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3178 "assuming 512 bytes\n", mmc_hostname(mmc));
3179 mmc->max_blk_size = 0;
3180 }
3181 }
3182
3183 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3184
55db890a
PO		 3185 /*
3186 * Maximum block count.
3187 */
1388eefd 3188 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3189
d129bceb
PO		 3190 /*
3191 * Init tasklets.
3192 */
d129bceb
PO		 3193 tasklet_init(&host->finish_tasklet,
3194 sdhci_tasklet_finish, (unsigned long)host);
3195
e4cad1b5 3196 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3197
cf2b5eea 3198 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3199 init_waitqueue_head(&host->buf_ready_int);
3200
cf2b5eea
AN		 3201 /* Initialize re-tuning timer */
3202 init_timer(&host->tuning_timer);
3203 host->tuning_timer.data = (unsigned long)host;
3204 host->tuning_timer.function = sdhci_tuning_timer;
3205 }
3206
2af502ca
SG		 3207 sdhci_init(host, 0);
3208
781e989c
RK		 3209 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3210 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3211 if (ret) {
3212 pr_err("%s: Failed to request IRQ %d: %d\n",
3213 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3214 goto untasklet;
0fc81ee3 3215 }
d129bceb 3216
d129bceb
PO		 3217#ifdef CONFIG_MMC_DEBUG
3218 sdhci_dumpregs(host);
3219#endif
3220
f9134319 3221#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3222 snprintf(host->led_name, sizeof(host->led_name),
3223 "%s::", mmc_hostname(mmc));
3224 host->led.name = host->led_name;
2f730fec
PO		 3225 host->led.brightness = LED_OFF;
3226 host->led.default_trigger = mmc_hostname(mmc);
3227 host->led.brightness_set = sdhci_led_control;
3228
b8c86fc5 3229 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3230 if (ret) {
3231 pr_err("%s: Failed to register LED device: %d\n",
3232 mmc_hostname(mmc), ret);
2f730fec 3233 goto reset;
0fc81ee3 3234 }
2f730fec
PO		 3235#endif
3236
5f25a66f
PO		 3237 mmiowb();
3238
d129bceb
PO		 3239 mmc_add_host(mmc);
3240
a3c76eb9 3241 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3242 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3243 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3244 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3245
7260cf5e
AV		 3246 sdhci_enable_card_detection(host);
3247
d129bceb
PO		 3248 return 0;
3249
f9134319 3250#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3251reset:
03231f9b 3252 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3253 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3254 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3255 free_irq(host->irq, host);
3256#endif
8ef1a143 3257untasklet:
d129bceb 3258 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3259
3260 return ret;
3261}
3262
b8c86fc5 3263EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3264
1e72859e 3265void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3266{
3a48edc4 3267 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3268 unsigned long flags;
3269
3270 if (dead) {
3271 spin_lock_irqsave(&host->lock, flags);
3272
3273 host->flags |= SDHCI_DEVICE_DEAD;
3274
3275 if (host->mrq) {
a3c76eb9 3276 pr_err("%s: Controller removed during "
4e743f1f 3277 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3278
3279 host->mrq->cmd->error = -ENOMEDIUM;
3280 tasklet_schedule(&host->finish_tasklet);
3281 }
3282
3283 spin_unlock_irqrestore(&host->lock, flags);
3284 }
3285
7260cf5e
AV		 3286 sdhci_disable_card_detection(host);
3287
4e743f1f 3288 mmc_remove_host(mmc);
d129bceb 3289
f9134319 3290#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3291 led_classdev_unregister(&host->led);
3292#endif
3293
1e72859e 3294 if (!dead)
03231f9b 3295 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3296
b537f94c
RK		 3297 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3298 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3299 free_irq(host->irq, host);
3300
3301 del_timer_sync(&host->timer);
3302
d129bceb 3303 tasklet_kill(&host->finish_tasklet);
2134a922 3304
3a48edc4
TK		 3305 if (!IS_ERR(mmc->supply.vmmc))
3306 regulator_disable(mmc->supply.vmmc);
9bea3c85 3307
3a48edc4
TK		 3308 if (!IS_ERR(mmc->supply.vqmmc))
3309 regulator_disable(mmc->supply.vqmmc);
6231f3de 3310
d1e49f77 3311 if (host->adma_desc)
4e743f1f 3312 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
d1e49f77 3313 host->adma_desc, host->adma_addr);
2134a922
PO		 3314 kfree(host->align_buffer);
3315
3316 host->adma_desc = NULL;
3317 host->align_buffer = NULL;
d129bceb
PO		 3318}
3319
b8c86fc5 3320EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3321
b8c86fc5 3322void sdhci_free_host(struct sdhci_host *host)
d129bceb 3323{
b8c86fc5 3324 mmc_free_host(host->mmc);
d129bceb
PO		 3325}
3326
b8c86fc5 3327EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3328
3329/*****************************************************************************\
3330 * *
3331 * Driver init/exit *
3332 * *
3333\*****************************************************************************/
3334
3335static int __init sdhci_drv_init(void)
3336{
a3c76eb9 3337 pr_info(DRIVER_NAME
52fbf9c9 3338 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3339 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3340
b8c86fc5 3341 return 0;
d129bceb
PO		 3342}
3343
3344static void __exit sdhci_drv_exit(void)
3345{
d129bceb
PO		 3346}
3347
3348module_init(sdhci_drv_init);
3349module_exit(sdhci_drv_exit);
3350
df673b22 3351module_param(debug_quirks, uint, 0444);
66fd8ad5 3352module_param(debug_quirks2, uint, 0444);
67435274 3353
32710e8f 3354MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3355MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3356MODULE_LICENSE("GPL");
67435274 3357
df673b22 3358MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3359MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux 6.x block layer and io_uring tree(s)