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mmc: ignore bad max block size in sdhci
[linux-2.6-block.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
14d836e7 4 * Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
d129bceb
PO		 10 */
11
d129bceb
PO		 12#include <linux/delay.h>
13#include <linux/highmem.h>
14#include <linux/pci.h>
15#include <linux/dma-mapping.h>
16
17#include <linux/mmc/host.h>
d129bceb
PO		 18
19#include <asm/scatterlist.h>
20
21#include "sdhci.h"
22
23#define DRIVER_NAME "sdhci"
d129bceb 24
d129bceb 25#define DBG(f, x...) \
c6563178 26 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 27
67435274
PO		 28static unsigned int debug_nodma = 0;
29static unsigned int debug_forcedma = 0;
df673b22 30static unsigned int debug_quirks = 0;
67435274 31
645289dc 32#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
98608076 33#define SDHCI_QUIRK_FORCE_DMA (1<<1)
8a4da143
PO		 34/* Controller doesn't like some resets when there is no card inserted. */
35#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
9e9dc5f2 36#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
b8352260 37#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
645289dc 38
d129bceb 39static const struct pci_device_id pci_ids[] __devinitdata = {
645289dc
PO		 40 {
41 .vendor = PCI_VENDOR_ID_RICOH,
42 .device = PCI_DEVICE_ID_RICOH_R5C822,
43 .subvendor = PCI_VENDOR_ID_IBM,
44 .subdevice = PCI_ANY_ID,
98608076
PO		 45 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
46 SDHCI_QUIRK_FORCE_DMA,
47 },
48
49 {
50 .vendor = PCI_VENDOR_ID_RICOH,
51 .device = PCI_DEVICE_ID_RICOH_R5C822,
52 .subvendor = PCI_ANY_ID,
53 .subdevice = PCI_ANY_ID,
8a4da143
PO		 54 .driver_data = SDHCI_QUIRK_FORCE_DMA |
55 SDHCI_QUIRK_NO_CARD_NO_RESET,
98608076
PO		 56 },
57
58 {
59 .vendor = PCI_VENDOR_ID_TI,
60 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
61 .subvendor = PCI_ANY_ID,
62 .subdevice = PCI_ANY_ID,
63 .driver_data = SDHCI_QUIRK_FORCE_DMA,
645289dc
PO		 64 },
65
9e9dc5f2
DS		 66 {
67 .vendor = PCI_VENDOR_ID_ENE,
68 .device = PCI_DEVICE_ID_ENE_CB712_SD,
69 .subvendor = PCI_ANY_ID,
70 .subdevice = PCI_ANY_ID,
71 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE,
72 },
73
7de064eb
MK		 74 {
75 .vendor = PCI_VENDOR_ID_ENE,
76 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
77 .subvendor = PCI_ANY_ID,
78 .subdevice = PCI_ANY_ID,
79 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE,
80 },
81
b8352260
LD		 82 {
83 .vendor = PCI_VENDOR_ID_ENE,
84 .device = PCI_DEVICE_ID_ENE_CB714_SD,
85 .subvendor = PCI_ANY_ID,
86 .subdevice = PCI_ANY_ID,
87 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
88 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
89 },
90
91 {
92 .vendor = PCI_VENDOR_ID_ENE,
93 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
94 .subvendor = PCI_ANY_ID,
95 .subdevice = PCI_ANY_ID,
96 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
98 },
99
645289dc
PO		 100 { /* Generic SD host controller */
101 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
102 },
103
d129bceb
PO		 104 { /* end: all zeroes */ },
105};
106
107MODULE_DEVICE_TABLE(pci, pci_ids);
108
109static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
110static void sdhci_finish_data(struct sdhci_host *);
111
112static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
113static void sdhci_finish_command(struct sdhci_host *);
114
115static void sdhci_dumpregs(struct sdhci_host *host)
116{
117 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
118
119 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
120 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
121 readw(host->ioaddr + SDHCI_HOST_VERSION));
122 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
123 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
124 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
125 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
126 readl(host->ioaddr + SDHCI_ARGUMENT),
127 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
128 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
129 readl(host->ioaddr + SDHCI_PRESENT_STATE),
130 readb(host->ioaddr + SDHCI_HOST_CONTROL));
131 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
132 readb(host->ioaddr + SDHCI_POWER_CONTROL),
133 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
134 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
135 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
136 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
137 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
138 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
139 readl(host->ioaddr + SDHCI_INT_STATUS));
140 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
141 readl(host->ioaddr + SDHCI_INT_ENABLE),
142 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
143 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
144 readw(host->ioaddr + SDHCI_ACMD12_ERR),
145 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
146 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
147 readl(host->ioaddr + SDHCI_CAPABILITIES),
148 readl(host->ioaddr + SDHCI_MAX_CURRENT));
149
150 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
151}
152
153/*****************************************************************************\
154 * *
155 * Low level functions *
156 * *
157\*****************************************************************************/
158
159static void sdhci_reset(struct sdhci_host *host, u8 mask)
160{
e16514d8
PO		 161 unsigned long timeout;
162
8a4da143
PO		 163 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
164 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
165 SDHCI_CARD_PRESENT))
166 return;
167 }
168
d129bceb
PO		 169 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
170
e16514d8 171 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 172 host->clock = 0;
173
e16514d8
PO		 174 /* Wait max 100 ms */
175 timeout = 100;
176
177 /* hw clears the bit when it's done */
178 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
179 if (timeout == 0) {
acf1da45 180 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 181 mmc_hostname(host->mmc), (int)mask);
182 sdhci_dumpregs(host);
183 return;
184 }
185 timeout--;
186 mdelay(1);
d129bceb
PO		 187 }
188}
189
190static void sdhci_init(struct sdhci_host *host)
191{
192 u32 intmask;
193
194 sdhci_reset(host, SDHCI_RESET_ALL);
195
3192a28f
PO		 196 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
197 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
198 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
199 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 200 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
3192a28f 201 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
d129bceb
PO		 202
203 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
204 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 205}
206
207static void sdhci_activate_led(struct sdhci_host *host)
208{
209 u8 ctrl;
210
211 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
212 ctrl |= SDHCI_CTRL_LED;
213 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
214}
215
216static void sdhci_deactivate_led(struct sdhci_host *host)
217{
218 u8 ctrl;
219
220 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
221 ctrl &= ~SDHCI_CTRL_LED;
222 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
223}
224
225/*****************************************************************************\
226 * *
227 * Core functions *
228 * *
229\*****************************************************************************/
230
2a22b14e 231static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
d129bceb 232{
2a22b14e 233 return page_address(host->cur_sg->page) + host->cur_sg->offset;
d129bceb
PO		 234}
235
236static inline int sdhci_next_sg(struct sdhci_host* host)
237{
238 /*
239 * Skip to next SG entry.
240 */
241 host->cur_sg++;
242 host->num_sg--;
243
244 /*
245 * Any entries left?
246 */
247 if (host->num_sg > 0) {
248 host->offset = 0;
249 host->remain = host->cur_sg->length;
250 }
251
252 return host->num_sg;
253}
254
a406f5a3 255static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 256{
a406f5a3
PO		 257 int blksize, chunk_remain;
258 u32 data;
d129bceb 259 char *buffer;
a406f5a3 260 int size;
d129bceb 261
a406f5a3 262 DBG("PIO reading\n");
d129bceb 263
a406f5a3
PO		 264 blksize = host->data->blksz;
265 chunk_remain = 0;
266 data = 0;
d129bceb 267
2a22b14e 268 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 269
a406f5a3
PO		 270 while (blksize) {
271 if (chunk_remain == 0) {
272 data = readl(host->ioaddr + SDHCI_BUFFER);
273 chunk_remain = min(blksize, 4);
274 }
d129bceb 275
14d836e7 276 size = min(host->remain, chunk_remain);
d129bceb 277
a406f5a3
PO		 278 chunk_remain -= size;
279 blksize -= size;
280 host->offset += size;
281 host->remain -= size;
14d836e7 282
a406f5a3
PO		 283 while (size) {
284 *buffer = data & 0xFF;
285 buffer++;
286 data >>= 8;
287 size--;
288 }
d129bceb 289
a406f5a3 290 if (host->remain == 0) {
a406f5a3
PO		 291 if (sdhci_next_sg(host) == 0) {
292 BUG_ON(blksize != 0);
293 return;
294 }
2a22b14e 295 buffer = sdhci_sg_to_buffer(host);
d129bceb 296 }
a406f5a3 297 }
a406f5a3 298}
d129bceb 299
a406f5a3
PO		 300static void sdhci_write_block_pio(struct sdhci_host *host)
301{
302 int blksize, chunk_remain;
303 u32 data;
304 char *buffer;
305 int bytes, size;
d129bceb 306
a406f5a3
PO		 307 DBG("PIO writing\n");
308
309 blksize = host->data->blksz;
310 chunk_remain = 4;
311 data = 0;
d129bceb 312
a406f5a3 313 bytes = 0;
2a22b14e 314 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 315
a406f5a3 316 while (blksize) {
14d836e7 317 size = min(host->remain, chunk_remain);
a406f5a3
PO		 318
319 chunk_remain -= size;
320 blksize -= size;
d129bceb
PO		 321 host->offset += size;
322 host->remain -= size;
14d836e7 323
a406f5a3
PO		 324 while (size) {
325 data >>= 8;
326 data |= (u32)*buffer << 24;
327 buffer++;
328 size--;
329 }
330
331 if (chunk_remain == 0) {
332 writel(data, host->ioaddr + SDHCI_BUFFER);
333 chunk_remain = min(blksize, 4);
334 }
d129bceb
PO		 335
336 if (host->remain == 0) {
d129bceb 337 if (sdhci_next_sg(host) == 0) {
a406f5a3 338 BUG_ON(blksize != 0);
d129bceb
PO		 339 return;
340 }
2a22b14e 341 buffer = sdhci_sg_to_buffer(host);
d129bceb
PO		 342 }
343 }
a406f5a3
PO		 344}
345
346static void sdhci_transfer_pio(struct sdhci_host *host)
347{
348 u32 mask;
349
350 BUG_ON(!host->data);
351
14d836e7 352 if (host->num_sg == 0)
a406f5a3
PO		 353 return;
354
355 if (host->data->flags & MMC_DATA_READ)
356 mask = SDHCI_DATA_AVAILABLE;
357 else
358 mask = SDHCI_SPACE_AVAILABLE;
359
360 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
361 if (host->data->flags & MMC_DATA_READ)
362 sdhci_read_block_pio(host);
363 else
364 sdhci_write_block_pio(host);
d129bceb 365
14d836e7 366 if (host->num_sg == 0)
a406f5a3 367 break;
a406f5a3 368 }
d129bceb 369
a406f5a3 370 DBG("PIO transfer complete.\n");
d129bceb
PO		 371}
372
373static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
374{
1c8cde92
PO		 375 u8 count;
376 unsigned target_timeout, current_timeout;
d129bceb
PO		 377
378 WARN_ON(host->data);
379
c7fa9963 380 if (data == NULL)
d129bceb 381 return;
d129bceb 382
bab76961
PO		 383 /* Sanity checks */
384 BUG_ON(data->blksz * data->blocks > 524288);
fe4a3c7a 385 BUG_ON(data->blksz > host->mmc->max_blk_size);
1d676e02 386 BUG_ON(data->blocks > 65535);
d129bceb 387
1c8cde92
PO		 388 /* timeout in us */
389 target_timeout = data->timeout_ns / 1000 +
390 data->timeout_clks / host->clock;
d129bceb 391
1c8cde92
PO		 392 /*
393 * Figure out needed cycles.
394 * We do this in steps in order to fit inside a 32 bit int.
395 * The first step is the minimum timeout, which will have a
396 * minimum resolution of 6 bits:
397 * (1) 2^13*1000 > 2^22,
398 * (2) host->timeout_clk < 2^16
399 * =>
400 * (1) / (2) > 2^6
401 */
402 count = 0;
403 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
404 while (current_timeout < target_timeout) {
405 count++;
406 current_timeout <<= 1;
407 if (count >= 0xF)
408 break;
409 }
410
411 if (count >= 0xF) {
412 printk(KERN_WARNING "%s: Too large timeout requested!\n",
413 mmc_hostname(host->mmc));
414 count = 0xE;
415 }
416
417 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
d129bceb
PO		 418
419 if (host->flags & SDHCI_USE_DMA) {
420 int count;
421
422 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
423 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
424 BUG_ON(count != 1);
425
426 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
427 } else {
d129bceb
PO		 428 host->cur_sg = data->sg;
429 host->num_sg = data->sg_len;
430
431 host->offset = 0;
432 host->remain = host->cur_sg->length;
433 }
c7fa9963 434
bab76961
PO		 435 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
436 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
437 host->ioaddr + SDHCI_BLOCK_SIZE);
c7fa9963
PO		 438 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
439}
440
441static void sdhci_set_transfer_mode(struct sdhci_host *host,
442 struct mmc_data *data)
443{
444 u16 mode;
445
446 WARN_ON(host->data);
447
448 if (data == NULL)
449 return;
450
451 mode = SDHCI_TRNS_BLK_CNT_EN;
452 if (data->blocks > 1)
453 mode |= SDHCI_TRNS_MULTI;
454 if (data->flags & MMC_DATA_READ)
455 mode |= SDHCI_TRNS_READ;
456 if (host->flags & SDHCI_USE_DMA)
457 mode |= SDHCI_TRNS_DMA;
458
459 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
d129bceb
PO		 460}
461
462static void sdhci_finish_data(struct sdhci_host *host)
463{
464 struct mmc_data *data;
d129bceb
PO		 465 u16 blocks;
466
467 BUG_ON(!host->data);
468
469 data = host->data;
470 host->data = NULL;
471
472 if (host->flags & SDHCI_USE_DMA) {
473 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
474 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
d129bceb
PO		 475 }
476
477 /*
478 * Controller doesn't count down when in single block mode.
479 */
2b061973
PO		 480 if (data->blocks == 1)
481 blocks = (data->error == MMC_ERR_NONE) ? 0 : 1;
d129bceb
PO		 482 else
483 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
a3fd4a1b 484 data->bytes_xfered = data->blksz * (data->blocks - blocks);
d129bceb
PO		 485
486 if ((data->error == MMC_ERR_NONE) && blocks) {
487 printk(KERN_ERR "%s: Controller signalled completion even "
acf1da45
PO		 488 "though there were blocks left.\n",
489 mmc_hostname(host->mmc));
d129bceb 490 data->error = MMC_ERR_FAILED;
d129bceb
PO		 491 }
492
d129bceb
PO		 493 if (data->stop) {
494 /*
495 * The controller needs a reset of internal state machines
496 * upon error conditions.
497 */
498 if (data->error != MMC_ERR_NONE) {
499 sdhci_reset(host, SDHCI_RESET_CMD);
500 sdhci_reset(host, SDHCI_RESET_DATA);
501 }
502
503 sdhci_send_command(host, data->stop);
504 } else
505 tasklet_schedule(&host->finish_tasklet);
506}
507
508static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
509{
510 int flags;
fd2208d7 511 u32 mask;
7cb2c76f 512 unsigned long timeout;
d129bceb
PO		 513
514 WARN_ON(host->cmd);
515
d129bceb 516 /* Wait max 10 ms */
7cb2c76f 517 timeout = 10;
fd2208d7
PO		 518
519 mask = SDHCI_CMD_INHIBIT;
520 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
521 mask |= SDHCI_DATA_INHIBIT;
522
523 /* We shouldn't wait for data inihibit for stop commands, even
524 though they might use busy signaling */
525 if (host->mrq->data && (cmd == host->mrq->data->stop))
526 mask &= ~SDHCI_DATA_INHIBIT;
527
528 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 529 if (timeout == 0) {
d129bceb 530 printk(KERN_ERR "%s: Controller never released "
acf1da45 531 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb
PO		 532 sdhci_dumpregs(host);
533 cmd->error = MMC_ERR_FAILED;
534 tasklet_schedule(&host->finish_tasklet);
535 return;
536 }
7cb2c76f
PO		 537 timeout--;
538 mdelay(1);
539 }
d129bceb
PO		 540
541 mod_timer(&host->timer, jiffies + 10 * HZ);
542
543 host->cmd = cmd;
544
545 sdhci_prepare_data(host, cmd->data);
546
547 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
548
c7fa9963
PO		 549 sdhci_set_transfer_mode(host, cmd->data);
550
d129bceb 551 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 552 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb
PO		 553 mmc_hostname(host->mmc));
554 cmd->error = MMC_ERR_INVALID;
555 tasklet_schedule(&host->finish_tasklet);
556 return;
557 }
558
559 if (!(cmd->flags & MMC_RSP_PRESENT))
560 flags = SDHCI_CMD_RESP_NONE;
561 else if (cmd->flags & MMC_RSP_136)
562 flags = SDHCI_CMD_RESP_LONG;
563 else if (cmd->flags & MMC_RSP_BUSY)
564 flags = SDHCI_CMD_RESP_SHORT_BUSY;
565 else
566 flags = SDHCI_CMD_RESP_SHORT;
567
568 if (cmd->flags & MMC_RSP_CRC)
569 flags |= SDHCI_CMD_CRC;
570 if (cmd->flags & MMC_RSP_OPCODE)
571 flags |= SDHCI_CMD_INDEX;
572 if (cmd->data)
573 flags |= SDHCI_CMD_DATA;
574
fb61e289 575 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
d129bceb
PO		 576 host->ioaddr + SDHCI_COMMAND);
577}
578
579static void sdhci_finish_command(struct sdhci_host *host)
580{
581 int i;
582
583 BUG_ON(host->cmd == NULL);
584
585 if (host->cmd->flags & MMC_RSP_PRESENT) {
586 if (host->cmd->flags & MMC_RSP_136) {
587 /* CRC is stripped so we need to do some shifting. */
588 for (i = 0;i < 4;i++) {
589 host->cmd->resp[i] = readl(host->ioaddr +
590 SDHCI_RESPONSE + (3-i)*4) << 8;
591 if (i != 3)
592 host->cmd->resp[i] |=
593 readb(host->ioaddr +
594 SDHCI_RESPONSE + (3-i)*4-1);
595 }
596 } else {
597 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
598 }
599 }
600
601 host->cmd->error = MMC_ERR_NONE;
602
3192a28f 603 if (host->cmd->data)
d129bceb 604 host->data = host->cmd->data;
3192a28f 605 else
d129bceb
PO		 606 tasklet_schedule(&host->finish_tasklet);
607
608 host->cmd = NULL;
609}
610
611static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
612{
613 int div;
614 u16 clk;
7cb2c76f 615 unsigned long timeout;
d129bceb
PO		 616
617 if (clock == host->clock)
618 return;
619
620 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
621
622 if (clock == 0)
623 goto out;
624
625 for (div = 1;div < 256;div *= 2) {
626 if ((host->max_clk / div) <= clock)
627 break;
628 }
629 div >>= 1;
630
631 clk = div << SDHCI_DIVIDER_SHIFT;
632 clk |= SDHCI_CLOCK_INT_EN;
633 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
634
635 /* Wait max 10 ms */
7cb2c76f
PO		 636 timeout = 10;
637 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
638 & SDHCI_CLOCK_INT_STABLE)) {
639 if (timeout == 0) {
acf1da45
PO		 640 printk(KERN_ERR "%s: Internal clock never "
641 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 642 sdhci_dumpregs(host);
643 return;
644 }
7cb2c76f
PO		 645 timeout--;
646 mdelay(1);
647 }
d129bceb
PO		 648
649 clk |= SDHCI_CLOCK_CARD_EN;
650 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
651
652out:
653 host->clock = clock;
654}
655
146ad66e
PO		 656static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
657{
658 u8 pwr;
659
660 if (host->power == power)
661 return;
662
9e9dc5f2
DS		 663 if (power == (unsigned short)-1) {
664 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e 665 goto out;
9e9dc5f2
DS		 666 }
667
668 /*
669 * Spec says that we should clear the power reg before setting
670 * a new value. Some controllers don't seem to like this though.
671 */
672 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
673 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e
PO		 674
675 pwr = SDHCI_POWER_ON;
676
4be34c99 677 switch (1 << power) {
55556da0 678 case MMC_VDD_165_195:
146ad66e
PO		 679 pwr |= SDHCI_POWER_180;
680 break;
4be34c99
PL		 681 case MMC_VDD_29_30:
682 case MMC_VDD_30_31:
146ad66e
PO		 683 pwr |= SDHCI_POWER_300;
684 break;
4be34c99
PL		 685 case MMC_VDD_32_33:
686 case MMC_VDD_33_34:
146ad66e
PO		 687 pwr |= SDHCI_POWER_330;
688 break;
689 default:
690 BUG();
691 }
692
693 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
694
695out:
696 host->power = power;
697}
698
d129bceb
PO		 699/*****************************************************************************\
700 * *
701 * MMC callbacks *
702 * *
703\*****************************************************************************/
704
705static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
706{
707 struct sdhci_host *host;
708 unsigned long flags;
709
710 host = mmc_priv(mmc);
711
712 spin_lock_irqsave(&host->lock, flags);
713
714 WARN_ON(host->mrq != NULL);
715
716 sdhci_activate_led(host);
717
718 host->mrq = mrq;
719
720 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
721 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
722 tasklet_schedule(&host->finish_tasklet);
723 } else
724 sdhci_send_command(host, mrq->cmd);
725
5f25a66f 726 mmiowb();
d129bceb
PO		 727 spin_unlock_irqrestore(&host->lock, flags);
728}
729
730static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
731{
732 struct sdhci_host *host;
733 unsigned long flags;
734 u8 ctrl;
735
736 host = mmc_priv(mmc);
737
738 spin_lock_irqsave(&host->lock, flags);
739
d129bceb
PO		 740 /*
741 * Reset the chip on each power off.
742 * Should clear out any weird states.
743 */
744 if (ios->power_mode == MMC_POWER_OFF) {
745 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb 746 sdhci_init(host);
d129bceb
PO		 747 }
748
749 sdhci_set_clock(host, ios->clock);
750
751 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 752 sdhci_set_power(host, -1);
d129bceb 753 else
146ad66e 754 sdhci_set_power(host, ios->vdd);
d129bceb
PO		 755
756 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
cd9277c0 757
d129bceb
PO		 758 if (ios->bus_width == MMC_BUS_WIDTH_4)
759 ctrl |= SDHCI_CTRL_4BITBUS;
760 else
761 ctrl &= ~SDHCI_CTRL_4BITBUS;
cd9277c0
PO		 762
763 if (ios->timing == MMC_TIMING_SD_HS)
764 ctrl |= SDHCI_CTRL_HISPD;
765 else
766 ctrl &= ~SDHCI_CTRL_HISPD;
767
d129bceb
PO		 768 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
769
b8352260
LD		 770 /*
771 * Some (ENE) controllers go apeshit on some ios operation,
772 * signalling timeout and CRC errors even on CMD0. Resetting
773 * it on each ios seems to solve the problem.
774 */
775 if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
776 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
777
5f25a66f 778 mmiowb();
d129bceb
PO		 779 spin_unlock_irqrestore(&host->lock, flags);
780}
781
782static int sdhci_get_ro(struct mmc_host *mmc)
783{
784 struct sdhci_host *host;
785 unsigned long flags;
786 int present;
787
788 host = mmc_priv(mmc);
789
790 spin_lock_irqsave(&host->lock, flags);
791
792 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
793
794 spin_unlock_irqrestore(&host->lock, flags);
795
796 return !(present & SDHCI_WRITE_PROTECT);
797}
798
ab7aefd0 799static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 800 .request = sdhci_request,
801 .set_ios = sdhci_set_ios,
802 .get_ro = sdhci_get_ro,
803};
804
805/*****************************************************************************\
806 * *
807 * Tasklets *
808 * *
809\*****************************************************************************/
810
811static void sdhci_tasklet_card(unsigned long param)
812{
813 struct sdhci_host *host;
814 unsigned long flags;
815
816 host = (struct sdhci_host*)param;
817
818 spin_lock_irqsave(&host->lock, flags);
819
820 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
821 if (host->mrq) {
822 printk(KERN_ERR "%s: Card removed during transfer!\n",
823 mmc_hostname(host->mmc));
824 printk(KERN_ERR "%s: Resetting controller.\n",
825 mmc_hostname(host->mmc));
826
827 sdhci_reset(host, SDHCI_RESET_CMD);
828 sdhci_reset(host, SDHCI_RESET_DATA);
829
830 host->mrq->cmd->error = MMC_ERR_FAILED;
831 tasklet_schedule(&host->finish_tasklet);
832 }
833 }
834
835 spin_unlock_irqrestore(&host->lock, flags);
836
837 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
838}
839
840static void sdhci_tasklet_finish(unsigned long param)
841{
842 struct sdhci_host *host;
843 unsigned long flags;
844 struct mmc_request *mrq;
845
846 host = (struct sdhci_host*)param;
847
848 spin_lock_irqsave(&host->lock, flags);
849
850 del_timer(&host->timer);
851
852 mrq = host->mrq;
853
d129bceb
PO		 854 /*
855 * The controller needs a reset of internal state machines
856 * upon error conditions.
857 */
858 if ((mrq->cmd->error != MMC_ERR_NONE) ||
859 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
860 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
645289dc
PO		 861
862 /* Some controllers need this kick or reset won't work here */
863 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
864 unsigned int clock;
865
866 /* This is to force an update */
867 clock = host->clock;
868 host->clock = 0;
869 sdhci_set_clock(host, clock);
870 }
871
872 /* Spec says we should do both at the same time, but Ricoh
873 controllers do not like that. */
d129bceb
PO		 874 sdhci_reset(host, SDHCI_RESET_CMD);
875 sdhci_reset(host, SDHCI_RESET_DATA);
876 }
877
878 host->mrq = NULL;
879 host->cmd = NULL;
880 host->data = NULL;
881
882 sdhci_deactivate_led(host);
883
5f25a66f 884 mmiowb();
d129bceb
PO		 885 spin_unlock_irqrestore(&host->lock, flags);
886
887 mmc_request_done(host->mmc, mrq);
888}
889
890static void sdhci_timeout_timer(unsigned long data)
891{
892 struct sdhci_host *host;
893 unsigned long flags;
894
895 host = (struct sdhci_host*)data;
896
897 spin_lock_irqsave(&host->lock, flags);
898
899 if (host->mrq) {
acf1da45
PO		 900 printk(KERN_ERR "%s: Timeout waiting for hardware "
901 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 902 sdhci_dumpregs(host);
903
904 if (host->data) {
905 host->data->error = MMC_ERR_TIMEOUT;
906 sdhci_finish_data(host);
907 } else {
908 if (host->cmd)
909 host->cmd->error = MMC_ERR_TIMEOUT;
910 else
911 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
912
913 tasklet_schedule(&host->finish_tasklet);
914 }
915 }
916
5f25a66f 917 mmiowb();
d129bceb
PO		 918 spin_unlock_irqrestore(&host->lock, flags);
919}
920
921/*****************************************************************************\
922 * *
923 * Interrupt handling *
924 * *
925\*****************************************************************************/
926
927static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
928{
929 BUG_ON(intmask == 0);
930
931 if (!host->cmd) {
932 printk(KERN_ERR "%s: Got command interrupt even though no "
933 "command operation was in progress.\n",
934 mmc_hostname(host->mmc));
d129bceb
PO		 935 sdhci_dumpregs(host);
936 return;
937 }
938
43b58b36
PO		 939 if (intmask & SDHCI_INT_TIMEOUT)
940 host->cmd->error = MMC_ERR_TIMEOUT;
941 else if (intmask & SDHCI_INT_CRC)
942 host->cmd->error = MMC_ERR_BADCRC;
943 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
944 host->cmd->error = MMC_ERR_FAILED;
945
946 if (host->cmd->error != MMC_ERR_NONE)
d129bceb 947 tasklet_schedule(&host->finish_tasklet);
43b58b36
PO		 948 else if (intmask & SDHCI_INT_RESPONSE)
949 sdhci_finish_command(host);
d129bceb
PO		 950}
951
952static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
953{
954 BUG_ON(intmask == 0);
955
956 if (!host->data) {
957 /*
958 * A data end interrupt is sent together with the response
959 * for the stop command.
960 */
961 if (intmask & SDHCI_INT_DATA_END)
962 return;
963
964 printk(KERN_ERR "%s: Got data interrupt even though no "
965 "data operation was in progress.\n",
966 mmc_hostname(host->mmc));
d129bceb
PO		 967 sdhci_dumpregs(host);
968
969 return;
970 }
971
972 if (intmask & SDHCI_INT_DATA_TIMEOUT)
973 host->data->error = MMC_ERR_TIMEOUT;
974 else if (intmask & SDHCI_INT_DATA_CRC)
975 host->data->error = MMC_ERR_BADCRC;
976 else if (intmask & SDHCI_INT_DATA_END_BIT)
977 host->data->error = MMC_ERR_FAILED;
978
979 if (host->data->error != MMC_ERR_NONE)
980 sdhci_finish_data(host);
981 else {
a406f5a3 982 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 983 sdhci_transfer_pio(host);
984
6ba736a1
PO		 985 /*
986 * We currently don't do anything fancy with DMA
987 * boundaries, but as we can't disable the feature
988 * we need to at least restart the transfer.
989 */
990 if (intmask & SDHCI_INT_DMA_END)
991 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
992 host->ioaddr + SDHCI_DMA_ADDRESS);
993
d129bceb
PO		 994 if (intmask & SDHCI_INT_DATA_END)
995 sdhci_finish_data(host);
996 }
997}
998
7d12e780 999static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1000{
1001 irqreturn_t result;
1002 struct sdhci_host* host = dev_id;
1003 u32 intmask;
1004
1005 spin_lock(&host->lock);
1006
1007 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1008
62df67a5 1009 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1010 result = IRQ_NONE;
1011 goto out;
1012 }
1013
1014 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1015
3192a28f
PO		 1016 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1017 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1018 host->ioaddr + SDHCI_INT_STATUS);
d129bceb 1019 tasklet_schedule(&host->card_tasklet);
3192a28f 1020 }
d129bceb 1021
3192a28f 1022 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1023
3192a28f 1024 if (intmask & SDHCI_INT_CMD_MASK) {
d129bceb
PO		 1025 writel(intmask & SDHCI_INT_CMD_MASK,
1026 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1027 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1028 }
1029
1030 if (intmask & SDHCI_INT_DATA_MASK) {
d129bceb
PO		 1031 writel(intmask & SDHCI_INT_DATA_MASK,
1032 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1033 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1034 }
1035
1036 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1037
964f9ce2
PO		 1038 intmask &= ~SDHCI_INT_ERROR;
1039
d129bceb 1040 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1041 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1042 mmc_hostname(host->mmc));
3192a28f 1043 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
d129bceb
PO		 1044 }
1045
9d26a5d3 1046 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f
PO		 1047
1048 if (intmask) {
acf1da45 1049 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1050 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1051 sdhci_dumpregs(host);
1052
d129bceb 1053 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1054 }
d129bceb
PO		 1055
1056 result = IRQ_HANDLED;
1057
5f25a66f 1058 mmiowb();
d129bceb
PO		 1059out:
1060 spin_unlock(&host->lock);
1061
1062 return result;
1063}
1064
1065/*****************************************************************************\
1066 * *
1067 * Suspend/resume *
1068 * *
1069\*****************************************************************************/
1070
1071#ifdef CONFIG_PM
1072
1073static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1074{
1075 struct sdhci_chip *chip;
1076 int i, ret;
1077
1078 chip = pci_get_drvdata(pdev);
1079 if (!chip)
1080 return 0;
1081
1082 DBG("Suspending...\n");
1083
1084 for (i = 0;i < chip->num_slots;i++) {
1085 if (!chip->hosts[i])
1086 continue;
1087 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1088 if (ret) {
1089 for (i--;i >= 0;i--)
1090 mmc_resume_host(chip->hosts[i]->mmc);
1091 return ret;
1092 }
1093 }
1094
1095 pci_save_state(pdev);
1096 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
a715dfc7
PO		 1097
1098 for (i = 0;i < chip->num_slots;i++) {
1099 if (!chip->hosts[i])
1100 continue;
1101 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1102 }
1103
d129bceb
PO		 1104 pci_disable_device(pdev);
1105 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1106
1107 return 0;
1108}
1109
1110static int sdhci_resume (struct pci_dev *pdev)
1111{
1112 struct sdhci_chip *chip;
1113 int i, ret;
1114
1115 chip = pci_get_drvdata(pdev);
1116 if (!chip)
1117 return 0;
1118
1119 DBG("Resuming...\n");
1120
1121 pci_set_power_state(pdev, PCI_D0);
1122 pci_restore_state(pdev);
df1c4b7b
PO		 1123 ret = pci_enable_device(pdev);
1124 if (ret)
1125 return ret;
d129bceb
PO		 1126
1127 for (i = 0;i < chip->num_slots;i++) {
1128 if (!chip->hosts[i])
1129 continue;
1130 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1131 pci_set_master(pdev);
a715dfc7
PO		 1132 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1133 IRQF_SHARED, chip->hosts[i]->slot_descr,
1134 chip->hosts[i]);
1135 if (ret)
1136 return ret;
d129bceb 1137 sdhci_init(chip->hosts[i]);
5f25a66f 1138 mmiowb();
d129bceb
PO		 1139 ret = mmc_resume_host(chip->hosts[i]->mmc);
1140 if (ret)
1141 return ret;
1142 }
1143
1144 return 0;
1145}
1146
1147#else /* CONFIG_PM */
1148
1149#define sdhci_suspend NULL
1150#define sdhci_resume NULL
1151
1152#endif /* CONFIG_PM */
1153
1154/*****************************************************************************\
1155 * *
1156 * Device probing/removal *
1157 * *
1158\*****************************************************************************/
1159
1160static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1161{
1162 int ret;
4a965505 1163 unsigned int version;
d129bceb
PO		 1164 struct sdhci_chip *chip;
1165 struct mmc_host *mmc;
1166 struct sdhci_host *host;
1167
1168 u8 first_bar;
1169 unsigned int caps;
1170
1171 chip = pci_get_drvdata(pdev);
1172 BUG_ON(!chip);
1173
1174 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1175 if (ret)
1176 return ret;
1177
1178 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1179
1180 if (first_bar > 5) {
1181 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1182 return -ENODEV;
1183 }
1184
1185 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1186 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1187 return -ENODEV;
1188 }
1189
1190 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
a98087cf
PO		 1191 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1192 "You may experience problems.\n");
d129bceb
PO		 1193 }
1194
67435274
PO		 1195 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1196 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1197 return -ENODEV;
1198 }
1199
1200 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1201 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1202 return -ENODEV;
1203 }
1204
d129bceb
PO		 1205 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1206 if (!mmc)
1207 return -ENOMEM;
1208
1209 host = mmc_priv(mmc);
1210 host->mmc = mmc;
1211
8a4da143
PO		 1212 host->chip = chip;
1213 chip->hosts[slot] = host;
1214
d129bceb
PO		 1215 host->bar = first_bar + slot;
1216
1217 host->addr = pci_resource_start(pdev, host->bar);
1218 host->irq = pdev->irq;
1219
1220 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1221
1222 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1223
1224 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1225 if (ret)
1226 goto free;
1227
1228 host->ioaddr = ioremap_nocache(host->addr,
1229 pci_resource_len(pdev, host->bar));
1230 if (!host->ioaddr) {
1231 ret = -ENOMEM;
1232 goto release;
1233 }
1234
d96649ed
PO		 1235 sdhci_reset(host, SDHCI_RESET_ALL);
1236
4a965505
PO		 1237 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1238 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1239 if (version != 0) {
1240 printk(KERN_ERR "%s: Unknown controller version (%d). "
8b1b2185 1241 "You may experience problems.\n", host->slot_descr,
4a965505 1242 version);
4a965505
PO		 1243 }
1244
d129bceb
PO		 1245 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1246
67435274
PO		 1247 if (debug_nodma)
1248 DBG("DMA forced off\n");
1249 else if (debug_forcedma) {
1250 DBG("DMA forced on\n");
1251 host->flags |= SDHCI_USE_DMA;
98608076
PO		 1252 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1253 host->flags |= SDHCI_USE_DMA;
1254 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
67435274
PO		 1255 DBG("Controller doesn't have DMA interface\n");
1256 else if (!(caps & SDHCI_CAN_DO_DMA))
1257 DBG("Controller doesn't have DMA capability\n");
1258 else
d129bceb
PO		 1259 host->flags |= SDHCI_USE_DMA;
1260
1261 if (host->flags & SDHCI_USE_DMA) {
1262 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1263 printk(KERN_WARNING "%s: No suitable DMA available. "
1264 "Falling back to PIO.\n", host->slot_descr);
1265 host->flags &= ~SDHCI_USE_DMA;
1266 }
1267 }
1268
1269 if (host->flags & SDHCI_USE_DMA)
1270 pci_set_master(pdev);
1271 else /* XXX: Hack to get MMC layer to avoid highmem */
1272 pdev->dma_mask = 0;
1273
8ef1a143
PO		 1274 host->max_clk =
1275 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1276 if (host->max_clk == 0) {
1277 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1278 "frequency.\n", host->slot_descr);
1279 ret = -ENODEV;
1280 goto unmap;
1281 }
d129bceb
PO		 1282 host->max_clk *= 1000000;
1283
1c8cde92
PO		 1284 host->timeout_clk =
1285 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1286 if (host->timeout_clk == 0) {
1287 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1288 "frequency.\n", host->slot_descr);
1289 ret = -ENODEV;
1290 goto unmap;
1291 }
1292 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1293 host->timeout_clk *= 1000;
d129bceb
PO		 1294
1295 /*
1296 * Set host parameters.
1297 */
1298 mmc->ops = &sdhci_ops;
1299 mmc->f_min = host->max_clk / 256;
1300 mmc->f_max = host->max_clk;
42431acb 1301 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
d129bceb 1302
cd9277c0
PO		 1303 if (caps & SDHCI_CAN_DO_HISPD)
1304 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1305
146ad66e
PO		 1306 mmc->ocr_avail = 0;
1307 if (caps & SDHCI_CAN_VDD_330)
1308 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1309 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1310 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1311 if (caps & SDHCI_CAN_VDD_180)
55556da0 1312 mmc->ocr_avail |= MMC_VDD_165_195;
146ad66e
PO		 1313
1314 if (mmc->ocr_avail == 0) {
1315 printk(KERN_ERR "%s: Hardware doesn't report any "
1316 "support voltages.\n", host->slot_descr);
1317 ret = -ENODEV;
1318 goto unmap;
1319 }
1320
d129bceb
PO		 1321 spin_lock_init(&host->lock);
1322
1323 /*
1324 * Maximum number of segments. Hardware cannot do scatter lists.
1325 */
1326 if (host->flags & SDHCI_USE_DMA)
1327 mmc->max_hw_segs = 1;
1328 else
1329 mmc->max_hw_segs = 16;
1330 mmc->max_phys_segs = 16;
1331
1332 /*
bab76961 1333 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1334 * size (512KiB).
d129bceb 1335 */
55db890a 1336 mmc->max_req_size = 524288;
d129bceb
PO		 1337
1338 /*
1339 * Maximum segment size. Could be one segment with the maximum number
55db890a 1340 * of bytes.
d129bceb 1341 */
55db890a 1342 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1343
fe4a3c7a
PO		 1344 /*
1345 * Maximum block size. This varies from controller to controller and
1346 * is specified in the capabilities register.
1347 */
1348 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1349 if (mmc->max_blk_size >= 3) {
03f8590d 1350 printk(KERN_WARNING "%s: Invalid maximum block size, assuming 512\n",
fe4a3c7a 1351 host->slot_descr);
03f8590d
DV		 1352 mmc->max_blk_size = 512;
1353 } else
1354 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 1355
55db890a
PO		 1356 /*
1357 * Maximum block count.
1358 */
1359 mmc->max_blk_count = 65535;
1360
d129bceb
PO		 1361 /*
1362 * Init tasklets.
1363 */
1364 tasklet_init(&host->card_tasklet,
1365 sdhci_tasklet_card, (unsigned long)host);
1366 tasklet_init(&host->finish_tasklet,
1367 sdhci_tasklet_finish, (unsigned long)host);
1368
e4cad1b5 1369 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1370
dace1453 1371 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
d129bceb
PO		 1372 host->slot_descr, host);
1373 if (ret)
8ef1a143 1374 goto untasklet;
d129bceb
PO		 1375
1376 sdhci_init(host);
1377
1378#ifdef CONFIG_MMC_DEBUG
1379 sdhci_dumpregs(host);
1380#endif
1381
5f25a66f
PO		 1382 mmiowb();
1383
d129bceb
PO		 1384 mmc_add_host(mmc);
1385
1386 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1387 host->addr, host->irq,
1388 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1389
1390 return 0;
1391
8ef1a143 1392untasklet:
d129bceb
PO		 1393 tasklet_kill(&host->card_tasklet);
1394 tasklet_kill(&host->finish_tasklet);
8ef1a143 1395unmap:
d129bceb
PO		 1396 iounmap(host->ioaddr);
1397release:
1398 pci_release_region(pdev, host->bar);
1399free:
1400 mmc_free_host(mmc);
1401
1402 return ret;
1403}
1404
1405static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1406{
1407 struct sdhci_chip *chip;
1408 struct mmc_host *mmc;
1409 struct sdhci_host *host;
1410
1411 chip = pci_get_drvdata(pdev);
1412 host = chip->hosts[slot];
1413 mmc = host->mmc;
1414
1415 chip->hosts[slot] = NULL;
1416
1417 mmc_remove_host(mmc);
1418
1419 sdhci_reset(host, SDHCI_RESET_ALL);
1420
1421 free_irq(host->irq, host);
1422
1423 del_timer_sync(&host->timer);
1424
1425 tasklet_kill(&host->card_tasklet);
1426 tasklet_kill(&host->finish_tasklet);
1427
1428 iounmap(host->ioaddr);
1429
1430 pci_release_region(pdev, host->bar);
1431
1432 mmc_free_host(mmc);
1433}
1434
1435static int __devinit sdhci_probe(struct pci_dev *pdev,
1436 const struct pci_device_id *ent)
1437{
1438 int ret, i;
51f82bc0 1439 u8 slots, rev;
d129bceb
PO		 1440 struct sdhci_chip *chip;
1441
1442 BUG_ON(pdev == NULL);
1443 BUG_ON(ent == NULL);
1444
51f82bc0
PO		 1445 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1446
1447 printk(KERN_INFO DRIVER_NAME
1448 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1449 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1450 (int)rev);
d129bceb
PO		 1451
1452 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1453 if (ret)
1454 return ret;
1455
1456 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1457 DBG("found %d slot(s)\n", slots);
1458 if (slots == 0)
1459 return -ENODEV;
1460
1461 ret = pci_enable_device(pdev);
1462 if (ret)
1463 return ret;
1464
1465 chip = kzalloc(sizeof(struct sdhci_chip) +
1466 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1467 if (!chip) {
1468 ret = -ENOMEM;
1469 goto err;
1470 }
1471
1472 chip->pdev = pdev;
df673b22
PO		 1473 chip->quirks = ent->driver_data;
1474
1475 if (debug_quirks)
1476 chip->quirks = debug_quirks;
d129bceb
PO		 1477
1478 chip->num_slots = slots;
1479 pci_set_drvdata(pdev, chip);
1480
1481 for (i = 0;i < slots;i++) {
1482 ret = sdhci_probe_slot(pdev, i);
1483 if (ret) {
1484 for (i--;i >= 0;i--)
1485 sdhci_remove_slot(pdev, i);
1486 goto free;
1487 }
1488 }
1489
1490 return 0;
1491
1492free:
1493 pci_set_drvdata(pdev, NULL);
1494 kfree(chip);
1495
1496err:
1497 pci_disable_device(pdev);
1498 return ret;
1499}
1500
1501static void __devexit sdhci_remove(struct pci_dev *pdev)
1502{
1503 int i;
1504 struct sdhci_chip *chip;
1505
1506 chip = pci_get_drvdata(pdev);
1507
1508 if (chip) {
1509 for (i = 0;i < chip->num_slots;i++)
1510 sdhci_remove_slot(pdev, i);
1511
1512 pci_set_drvdata(pdev, NULL);
1513
1514 kfree(chip);
1515 }
1516
1517 pci_disable_device(pdev);
1518}
1519
1520static struct pci_driver sdhci_driver = {
1521 .name = DRIVER_NAME,
1522 .id_table = pci_ids,
1523 .probe = sdhci_probe,
1524 .remove = __devexit_p(sdhci_remove),
1525 .suspend = sdhci_suspend,
1526 .resume = sdhci_resume,
1527};
1528
1529/*****************************************************************************\
1530 * *
1531 * Driver init/exit *
1532 * *
1533\*****************************************************************************/
1534
1535static int __init sdhci_drv_init(void)
1536{
1537 printk(KERN_INFO DRIVER_NAME
52fbf9c9 1538 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 1539 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1540
1541 return pci_register_driver(&sdhci_driver);
1542}
1543
1544static void __exit sdhci_drv_exit(void)
1545{
1546 DBG("Exiting\n");
1547
1548 pci_unregister_driver(&sdhci_driver);
1549}
1550
1551module_init(sdhci_drv_init);
1552module_exit(sdhci_drv_exit);
1553
67435274
PO		 1554module_param(debug_nodma, uint, 0444);
1555module_param(debug_forcedma, uint, 0444);
df673b22 1556module_param(debug_quirks, uint, 0444);
67435274 1557
d129bceb
PO		 1558MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1559MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
d129bceb 1560MODULE_LICENSE("GPL");
67435274
PO		 1561
1562MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1563MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
df673b22 1564MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux 6.x block layer and io_uring tree(s)