[linux-2.6-block.git] / drivers / mmc / host / sdhci-tegra.c

/*
 * Copyright (C) 2010 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/delay.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/reset.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/gpio/consumer.h>

#include "sdhci-pltfm.h"

/* Tegra SDHOST controller vendor register definitions */
#define SDHCI_TEGRA_VENDOR_CLOCK_CTRL			0x100
#define SDHCI_CLOCK_CTRL_TAP_MASK			0x00ff0000
#define SDHCI_CLOCK_CTRL_TAP_SHIFT			16
#define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE		BIT(5)
#define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE		BIT(3)
#define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE	BIT(2)

#define SDHCI_TEGRA_VENDOR_MISC_CTRL		0x120
#define SDHCI_MISC_CTRL_ENABLE_SDR104		0x8
#define SDHCI_MISC_CTRL_ENABLE_SDR50		0x10
#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300	0x20
#define SDHCI_MISC_CTRL_ENABLE_DDR50		0x200

#define SDHCI_TEGRA_AUTO_CAL_CONFIG		0x1e4
#define SDHCI_AUTO_CAL_START			BIT(31)
#define SDHCI_AUTO_CAL_ENABLE			BIT(29)

#define NVQUIRK_FORCE_SDHCI_SPEC_200	BIT(0)
#define NVQUIRK_ENABLE_BLOCK_GAP_DET	BIT(1)
#define NVQUIRK_ENABLE_SDHCI_SPEC_300	BIT(2)
#define NVQUIRK_ENABLE_SDR50		BIT(3)
#define NVQUIRK_ENABLE_SDR104		BIT(4)
#define NVQUIRK_ENABLE_DDR50		BIT(5)
#define NVQUIRK_HAS_PADCALIB		BIT(6)

struct sdhci_tegra_soc_data {
	const struct sdhci_pltfm_data *pdata;
	u32 nvquirks;
};

struct sdhci_tegra {
	const struct sdhci_tegra_soc_data *soc_data;
	struct gpio_desc *power_gpio;
	bool ddr_signaling;
	bool pad_calib_required;

	struct reset_control *rst;
};

static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
			(reg == SDHCI_HOST_VERSION))) {
		/* Erratum: Version register is invalid in HW. */
		return SDHCI_SPEC_200;
	}

	return readw(host->ioaddr + reg);
}

static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	switch (reg) {
	case SDHCI_TRANSFER_MODE:
		/*
		 * Postpone this write, we must do it together with a
		 * command write that is down below.
		 */
		pltfm_host->xfer_mode_shadow = val;
		return;
	case SDHCI_COMMAND:
		writel((val << 16) | pltfm_host->xfer_mode_shadow,
			host->ioaddr + SDHCI_TRANSFER_MODE);
		return;
	}

	writew(val, host->ioaddr + reg);
}

static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	/* Seems like we're getting spurious timeout and crc errors, so
	 * disable signalling of them. In case of real errors software
	 * timers should take care of eventually detecting them.
	 */
	if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
		val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);

	writel(val, host->ioaddr + reg);

	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
			(reg == SDHCI_INT_ENABLE))) {
		/* Erratum: Must enable block gap interrupt detection */
		u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
		if (val & SDHCI_INT_CARD_INT)
			gap_ctrl |= 0x8;
		else
			gap_ctrl &= ~0x8;
		writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	}
}

static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
{
	return mmc_gpio_get_ro(host->mmc);
}

static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	u32 misc_ctrl, clk_ctrl;

	sdhci_reset(host, mask);

	if (!(mask & SDHCI_RESET_ALL))
		return;

	misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
	clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);

	misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 |
		       SDHCI_MISC_CTRL_ENABLE_SDR50 |
		       SDHCI_MISC_CTRL_ENABLE_DDR50 |
		       SDHCI_MISC_CTRL_ENABLE_SDR104);

	clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;

	/*
	 * If the board does not define a regulator for the SDHCI
	 * IO voltage, then don't advertise support for UHS modes
	 * even if the device supports it because the IO voltage
	 * cannot be configured.
	 */
	if (!IS_ERR(host->mmc->supply.vqmmc)) {
		/* Erratum: Enable SDHCI spec v3.00 support */
		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
			misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
		/* Advertise UHS modes as supported by host */
		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
			misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
		if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
			misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
		if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
			misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
		if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50)
			clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
	}

	sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
	sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);

	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
		tegra_host->pad_calib_required = true;

	tegra_host->ddr_signaling = false;
}

static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
{
	u32 val;

	mdelay(1);

	val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
	val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
	sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG);
}

static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
	unsigned long host_clk;

	if (!clock)
		return sdhci_set_clock(host, clock);

	host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
	clk_set_rate(pltfm_host->clk, host_clk);
	host->max_clk = clk_get_rate(pltfm_host->clk);

	sdhci_set_clock(host, clock);

	if (tegra_host->pad_calib_required) {
		tegra_sdhci_pad_autocalib(host);
		tegra_host->pad_calib_required = false;
	}
}

static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
					  unsigned timing)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);

	if (timing == MMC_TIMING_UHS_DDR50)
		tegra_host->ddr_signaling = true;

	return sdhci_set_uhs_signaling(host, timing);
}

static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	/*
	 * DDR modes require the host to run at double the card frequency, so
	 * the maximum rate we can support is half of the module input clock.
	 */
	return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2;
}

static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
{
	u32 reg;

	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
	reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
	reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
	sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
}

static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
{
	unsigned int min, max;

	/*
	 * Start search for minimum tap value at 10, as smaller values are
	 * may wrongly be reported as working but fail at higher speeds,
	 * according to the TRM.
	 */
	min = 10;
	while (min < 255) {
		tegra_sdhci_set_tap(host, min);
		if (!mmc_send_tuning(host->mmc, opcode, NULL))
			break;
		min++;
	}

	/* Find the maximum tap value that still passes. */
	max = min + 1;
	while (max < 255) {
		tegra_sdhci_set_tap(host, max);
		if (mmc_send_tuning(host->mmc, opcode, NULL)) {
			max--;
			break;
		}
		max++;
	}

	/* The TRM states the ideal tap value is at 75% in the passing range. */
	tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));

	return mmc_send_tuning(host->mmc, opcode, NULL);
}

static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
		tegra_host->pad_calib_required = true;
}

static const struct sdhci_ops tegra_sdhci_ops = {
	.get_ro     = tegra_sdhci_get_ro,
	.read_w     = tegra_sdhci_readw,
	.write_l    = tegra_sdhci_writel,
	.set_clock  = tegra_sdhci_set_clock,
	.set_bus_width = sdhci_set_bus_width,
	.reset      = tegra_sdhci_reset,
	.platform_execute_tuning = tegra_sdhci_execute_tuning,
	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
	.voltage_switch = tegra_sdhci_voltage_switch,
	.get_max_clock = tegra_sdhci_get_max_clock,
};

static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops  = &tegra_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
	.pdata = &sdhci_tegra20_pdata,
	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
		    NVQUIRK_ENABLE_BLOCK_GAP_DET,
};

static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
	.ops  = &tegra_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
	.pdata = &sdhci_tegra30_pdata,
	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
		    NVQUIRK_ENABLE_SDR50 |
		    NVQUIRK_ENABLE_SDR104 |
		    NVQUIRK_HAS_PADCALIB,
};

static const struct sdhci_ops tegra114_sdhci_ops = {
	.get_ro     = tegra_sdhci_get_ro,
	.read_w     = tegra_sdhci_readw,
	.write_w    = tegra_sdhci_writew,
	.write_l    = tegra_sdhci_writel,
	.set_clock  = tegra_sdhci_set_clock,
	.set_bus_width = sdhci_set_bus_width,
	.reset      = tegra_sdhci_reset,
	.platform_execute_tuning = tegra_sdhci_execute_tuning,
	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
	.voltage_switch = tegra_sdhci_voltage_switch,
	.get_max_clock = tegra_sdhci_get_max_clock,
};

static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
	.ops  = &tegra114_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
	.pdata = &sdhci_tegra114_pdata,
};

static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
		   /*
		    * The TRM states that the SD/MMC controller found on
		    * Tegra124 can address 34 bits (the maximum supported by
		    * the Tegra memory controller), but tests show that DMA
		    * to or from above 4 GiB doesn't work. This is possibly
		    * caused by missing programming, though it's not obvious
		    * what sequence is required. Mark 64-bit DMA broken for
		    * now to fix this for existing users (e.g. Nyan boards).
		    */
		   SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
	.ops  = &tegra114_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
	.pdata = &sdhci_tegra124_pdata,
};

static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
	.ops  = &tegra114_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
	.pdata = &sdhci_tegra210_pdata,
};

static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
		   /* SDHCI controllers on Tegra186 support 40-bit addressing.
		    * IOVA addresses are 48-bit wide on Tegra186.
		    * With 64-bit dma mask used for SDHCI, accesses can
		    * be broken. Disable 64-bit dma, which would fall back
		    * to 32-bit dma mask. Ideally 40-bit dma mask would work,
		    * But it is not supported as of now.
		    */
		   SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
	.ops  = &tegra114_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra186 = {
	.pdata = &sdhci_tegra186_pdata,
};

static const struct of_device_id sdhci_tegra_dt_match[] = {
	{ .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
	{ .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
	{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
	{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
	{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
	{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
	{}
};
MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);

static int sdhci_tegra_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	const struct sdhci_tegra_soc_data *soc_data;
	struct sdhci_host *host;
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_tegra *tegra_host;
	struct clk *clk;
	int rc;

	match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
	if (!match)
		return -EINVAL;
	soc_data = match->data;

	host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
	if (IS_ERR(host))
		return PTR_ERR(host);
	pltfm_host = sdhci_priv(host);

	tegra_host = sdhci_pltfm_priv(pltfm_host);
	tegra_host->ddr_signaling = false;
	tegra_host->pad_calib_required = false;
	tegra_host->soc_data = soc_data;

	rc = mmc_of_parse(host->mmc);
	if (rc)
		goto err_parse_dt;

	if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
		host->mmc->caps |= MMC_CAP_1_8V_DDR;

	tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
							 GPIOD_OUT_HIGH);
	if (IS_ERR(tegra_host->power_gpio)) {
		rc = PTR_ERR(tegra_host->power_gpio);
		goto err_power_req;
	}

	clk = devm_clk_get(mmc_dev(host->mmc), NULL);
	if (IS_ERR(clk)) {
		dev_err(mmc_dev(host->mmc), "clk err\n");
		rc = PTR_ERR(clk);
		goto err_clk_get;
	}
	clk_prepare_enable(clk);
	pltfm_host->clk = clk;

	tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
							   "sdhci");
	if (IS_ERR(tegra_host->rst)) {
		rc = PTR_ERR(tegra_host->rst);
		dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
		goto err_rst_get;
	}

	rc = reset_control_assert(tegra_host->rst);
	if (rc)
		goto err_rst_get;

	usleep_range(2000, 4000);

	rc = reset_control_deassert(tegra_host->rst);
	if (rc)
		goto err_rst_get;

	usleep_range(2000, 4000);

	rc = sdhci_add_host(host);
	if (rc)
		goto err_add_host;

	return 0;

err_add_host:
	reset_control_assert(tegra_host->rst);
err_rst_get:
	clk_disable_unprepare(pltfm_host->clk);
err_clk_get:
err_power_req:
err_parse_dt:
	sdhci_pltfm_free(pdev);
	return rc;
}

static int sdhci_tegra_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);

	sdhci_remove_host(host, 0);

	reset_control_assert(tegra_host->rst);
	usleep_range(2000, 4000);
	clk_disable_unprepare(pltfm_host->clk);

	sdhci_pltfm_free(pdev);

	return 0;
}

static struct platform_driver sdhci_tegra_driver = {
	.driver		= {
		.name	= "sdhci-tegra",
		.of_match_table = sdhci_tegra_dt_match,
		.pm	= &sdhci_pltfm_pmops,
	},
	.probe		= sdhci_tegra_probe,
	.remove		= sdhci_tegra_remove,
};

module_platform_driver(sdhci_tegra_driver);

MODULE_DESCRIPTION("SDHCI driver for Tegra");
MODULE_AUTHOR("Google, Inc.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
03d2bfc8 OJ	1	/*
	2	* Copyright (C) 2010 Google, Inc.
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	*/
	14
e5c63d91	15	#include <linux/delay.h>
03d2bfc8	16	#include <linux/err.h>
96547f5d	17	#include <linux/module.h>
03d2bfc8 OJ	18	#include <linux/init.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/clk.h>
	21	#include <linux/io.h>
55cd65e4	22	#include <linux/of.h>
3e44a1a7	23	#include <linux/of_device.h>
20567be9	24	#include <linux/reset.h>
03d2bfc8 OJ	25	#include <linux/mmc/card.h>
03d2bfc8 OJ	26	#include <linux/mmc/host.h>
c3c2384c	27	#include <linux/mmc/mmc.h>
0aacd23f	28	#include <linux/mmc/slot-gpio.h>
2391b340	29	#include <linux/gpio/consumer.h>
03d2bfc8	30
03d2bfc8 OJ	31	#include "sdhci-pltfm.h"
03d2bfc8 OJ	32
ca5879d3	33	/* Tegra SDHOST controller vendor register definitions */
74cd42bc	34	#define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100
c3c2384c LS	35	#define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000
	36	#define SDHCI_CLOCK_CTRL_TAP_SHIFT 16
	37	#define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5)
74cd42bc LS	38	#define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3)
	39	#define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2)
	40
ca5879d3	41	#define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
3145351a AB	42	#define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
3145351a AB	43	#define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
ca5879d3	44	#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
3145351a	45	#define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
ca5879d3	46
e5c63d91 LS	47	#define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4
	48	#define SDHCI_AUTO_CAL_START BIT(31)
	49	#define SDHCI_AUTO_CAL_ENABLE BIT(29)
	50
3e44a1a7 SW	51	#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
3e44a1a7 SW	52	#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
ca5879d3	53	#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
7ad2ed1d LS	54	#define NVQUIRK_ENABLE_SDR50 BIT(3)
	55	#define NVQUIRK_ENABLE_SDR104 BIT(4)
	56	#define NVQUIRK_ENABLE_DDR50 BIT(5)
e5c63d91	57	#define NVQUIRK_HAS_PADCALIB BIT(6)
3e44a1a7 SW	58
3e44a1a7 SW	59	struct sdhci_tegra_soc_data {
1db5eebf	60	const struct sdhci_pltfm_data *pdata;
3e44a1a7 SW	61	u32 nvquirks;
	62	};
	63
	64	struct sdhci_tegra {
3e44a1a7	65	const struct sdhci_tegra_soc_data *soc_data;
2391b340	66	struct gpio_desc *power_gpio;
a8e326a9	67	bool ddr_signaling;
e5c63d91	68	bool pad_calib_required;
20567be9 TR	69
20567be9 TR	70	struct reset_control *rst;
3e44a1a7 SW	71	};
3e44a1a7 SW	72
03d2bfc8 OJ	73	static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
03d2bfc8 OJ	74	{
3e44a1a7	75	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0734e79c	76	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
3e44a1a7 SW	77	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	78
	79	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
	80	(reg == SDHCI_HOST_VERSION))) {
03d2bfc8 OJ	81	/* Erratum: Version register is invalid in HW. */
	82	return SDHCI_SPEC_200;
	83	}
	84
	85	return readw(host->ioaddr + reg);
	86	}
	87
352ee868 PK	88	static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	89	{
	90	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
352ee868	91
01df7ecd RK	92	switch (reg) {
	93	case SDHCI_TRANSFER_MODE:
	94	/*
	95	* Postpone this write, we must do it together with a
	96	* command write that is down below.
	97	*/
	98	pltfm_host->xfer_mode_shadow = val;
	99	return;
	100	case SDHCI_COMMAND:
	101	writel((val << 16) \| pltfm_host->xfer_mode_shadow,
	102	host->ioaddr + SDHCI_TRANSFER_MODE);
	103	return;
352ee868 PK	104	}
	105
	106	writew(val, host->ioaddr + reg);
	107	}
	108
03d2bfc8 OJ	109	static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
03d2bfc8 OJ	110	{
3e44a1a7	111	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0734e79c	112	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
3e44a1a7 SW	113	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
3e44a1a7 SW	114
03d2bfc8 OJ	115	/* Seems like we're getting spurious timeout and crc errors, so
	116	* disable signalling of them. In case of real errors software
	117	* timers should take care of eventually detecting them.
	118	*/
	119	if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
	120	val &= ~(SDHCI_INT_TIMEOUT\|SDHCI_INT_CRC);
	121
	122	writel(val, host->ioaddr + reg);
	123
3e44a1a7 SW	124	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
3e44a1a7 SW	125	(reg == SDHCI_INT_ENABLE))) {
03d2bfc8 OJ	126	/* Erratum: Must enable block gap interrupt detection */
	127	u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	128	if (val & SDHCI_INT_CARD_INT)
	129	gap_ctrl \|= 0x8;
	130	else
	131	gap_ctrl &= ~0x8;
	132	writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	133	}
	134	}
	135
3e44a1a7	136	static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
03d2bfc8	137	{
0aacd23f	138	return mmc_gpio_get_ro(host->mmc);
03d2bfc8 OJ	139	}
03d2bfc8 OJ	140
03231f9b	141	static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
ca5879d3 PK	142	{
ca5879d3 PK	143	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0734e79c	144	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
ca5879d3	145	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
74cd42bc	146	u32 misc_ctrl, clk_ctrl;
ca5879d3	147
03231f9b RK	148	sdhci_reset(host, mask);
03231f9b RK	149
ca5879d3 PK	150	if (!(mask & SDHCI_RESET_ALL))
	151	return;
	152
1b84def8	153	misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
74cd42bc	154	clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
4f6aa326 JH	155
	156	misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 \|
	157	SDHCI_MISC_CTRL_ENABLE_SDR50 \|
	158	SDHCI_MISC_CTRL_ENABLE_DDR50 \|
	159	SDHCI_MISC_CTRL_ENABLE_SDR104);
	160
74cd42bc	161	clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
4f6aa326 JH	162
	163	/*
	164	* If the board does not define a regulator for the SDHCI
	165	* IO voltage, then don't advertise support for UHS modes
	166	* even if the device supports it because the IO voltage
	167	* cannot be configured.
	168	*/
	169	if (!IS_ERR(host->mmc->supply.vqmmc)) {
	170	/* Erratum: Enable SDHCI spec v3.00 support */
	171	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
	172	misc_ctrl \|= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
	173	/* Advertise UHS modes as supported by host */
	174	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
	175	misc_ctrl \|= SDHCI_MISC_CTRL_ENABLE_SDR50;
	176	if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
	177	misc_ctrl \|= SDHCI_MISC_CTRL_ENABLE_DDR50;
	178	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
	179	misc_ctrl \|= SDHCI_MISC_CTRL_ENABLE_SDR104;
	180	if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50)
	181	clk_ctrl \|= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
	182	}
	183
	184	sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
74cd42bc LS	185	sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
74cd42bc LS	186
e5c63d91 LS	187	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
	188	tegra_host->pad_calib_required = true;
	189
a8e326a9	190	tegra_host->ddr_signaling = false;
ca5879d3 PK	191	}
ca5879d3 PK	192
e5c63d91 LS	193	static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
	194	{
	195	u32 val;
	196
	197	mdelay(1);
	198
	199	val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
	200	val \|= SDHCI_AUTO_CAL_ENABLE \| SDHCI_AUTO_CAL_START;
	201	sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG);
	202	}
	203
a8e326a9 LS	204	static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
	205	{
	206	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0734e79c	207	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
a8e326a9 LS	208	unsigned long host_clk;
	209
	210	if (!clock)
3491b690	211	return sdhci_set_clock(host, clock);
a8e326a9 LS	212
	213	host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
	214	clk_set_rate(pltfm_host->clk, host_clk);
	215	host->max_clk = clk_get_rate(pltfm_host->clk);
	216
e5c63d91 LS	217	sdhci_set_clock(host, clock);
	218
	219	if (tegra_host->pad_calib_required) {
	220	tegra_sdhci_pad_autocalib(host);
	221	tegra_host->pad_calib_required = false;
	222	}
a8e326a9 LS	223	}
	224
	225	static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
	226	unsigned timing)
	227	{
	228	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
0734e79c	229	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
a8e326a9 LS	230
	231	if (timing == MMC_TIMING_UHS_DDR50)
	232	tegra_host->ddr_signaling = true;
	233
	234	return sdhci_set_uhs_signaling(host, timing);
	235	}
	236
	237	static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
	238	{
	239	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	240
	241	/*
	242	* DDR modes require the host to run at double the card frequency, so
	243	* the maximum rate we can support is half of the module input clock.
	244	*/
	245	return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2;
	246	}
	247
c3c2384c LS	248	static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
	249	{
	250	u32 reg;
	251
	252	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
	253	reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
	254	reg \|= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
	255	sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
	256	}
	257
	258	static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
	259	{
	260	unsigned int min, max;
	261
	262	/*
	263	* Start search for minimum tap value at 10, as smaller values are
	264	* may wrongly be reported as working but fail at higher speeds,
	265	* according to the TRM.
	266	*/
	267	min = 10;
	268	while (min < 255) {
	269	tegra_sdhci_set_tap(host, min);
	270	if (!mmc_send_tuning(host->mmc, opcode, NULL))
	271	break;
	272	min++;
	273	}
	274
	275	/* Find the maximum tap value that still passes. */
	276	max = min + 1;
	277	while (max < 255) {
	278	tegra_sdhci_set_tap(host, max);
	279	if (mmc_send_tuning(host->mmc, opcode, NULL)) {
	280	max--;
	281	break;
	282	}
	283	max++;
	284	}
	285
	286	/* The TRM states the ideal tap value is at 75% in the passing range. */
	287	tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
	288
	289	return mmc_send_tuning(host->mmc, opcode, NULL);
	290	}
	291
e5c63d91 LS	292	static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
	293	{
	294	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	295	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
	296	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	297
	298	if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
	299	tegra_host->pad_calib_required = true;
	300	}
	301
c915568d	302	static const struct sdhci_ops tegra_sdhci_ops = {
85d6509d	303	.get_ro = tegra_sdhci_get_ro,
85d6509d SG	304	.read_w = tegra_sdhci_readw,
85d6509d SG	305	.write_l = tegra_sdhci_writel,
a8e326a9	306	.set_clock = tegra_sdhci_set_clock,
14b04c6a	307	.set_bus_width = sdhci_set_bus_width,
03231f9b	308	.reset = tegra_sdhci_reset,
c3c2384c	309	.platform_execute_tuning = tegra_sdhci_execute_tuning,
a8e326a9	310	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
e5c63d91	311	.voltage_switch = tegra_sdhci_voltage_switch,
a8e326a9	312	.get_max_clock = tegra_sdhci_get_max_clock,
85d6509d SG	313	};
85d6509d SG	314
1db5eebf	315	static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
3e44a1a7 SW	316	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	317	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	318	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	319	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	320	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
3e44a1a7 SW	321	.ops = &tegra_sdhci_ops,
	322	};
	323
d49d19c2	324	static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
3e44a1a7 SW	325	.pdata = &sdhci_tegra20_pdata,
	326	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 \|
	327	NVQUIRK_ENABLE_BLOCK_GAP_DET,
	328	};
3e44a1a7	329
1db5eebf	330	static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
85d6509d	331	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
3e44a1a7	332	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
85d6509d SG	333	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
85d6509d SG	334	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	335	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	336	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
a8e326a9	337	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
85d6509d SG	338	.ops = &tegra_sdhci_ops,
85d6509d SG	339	};
03d2bfc8	340
d49d19c2	341	static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
3e44a1a7	342	.pdata = &sdhci_tegra30_pdata,
3145351a	343	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 \|
7ad2ed1d	344	NVQUIRK_ENABLE_SDR50 \|
e5c63d91 LS	345	NVQUIRK_ENABLE_SDR104 \|
e5c63d91 LS	346	NVQUIRK_HAS_PADCALIB,
3e44a1a7	347	};
3e44a1a7	348
01df7ecd RK	349	static const struct sdhci_ops tegra114_sdhci_ops = {
	350	.get_ro = tegra_sdhci_get_ro,
	351	.read_w = tegra_sdhci_readw,
	352	.write_w = tegra_sdhci_writew,
	353	.write_l = tegra_sdhci_writel,
a8e326a9	354	.set_clock = tegra_sdhci_set_clock,
14b04c6a	355	.set_bus_width = sdhci_set_bus_width,
01df7ecd	356	.reset = tegra_sdhci_reset,
c3c2384c	357	.platform_execute_tuning = tegra_sdhci_execute_tuning,
a8e326a9	358	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
e5c63d91	359	.voltage_switch = tegra_sdhci_voltage_switch,
a8e326a9	360	.get_max_clock = tegra_sdhci_get_max_clock,
01df7ecd RK	361	};
01df7ecd RK	362
1db5eebf	363	static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
5ebf2552 RK	364	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	365	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
	366	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	367	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	368	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	369	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
a8e326a9	370	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
01df7ecd	371	.ops = &tegra114_sdhci_ops,
5ebf2552 RK	372	};
5ebf2552 RK	373
d49d19c2	374	static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
5ebf2552	375	.pdata = &sdhci_tegra114_pdata,
7bf037d6 JH	376	};
7bf037d6 JH	377
4ae12588 TR	378	static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
	379	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	380	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
	381	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	382	SDHCI_QUIRK_NO_HISPD_BIT \|
	383	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
	384	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	385	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN \|
	386	/*
	387	* The TRM states that the SD/MMC controller found on
	388	* Tegra124 can address 34 bits (the maximum supported by
	389	* the Tegra memory controller), but tests show that DMA
	390	* to or from above 4 GiB doesn't work. This is possibly
	391	* caused by missing programming, though it's not obvious
	392	* what sequence is required. Mark 64-bit DMA broken for
	393	* now to fix this for existing users (e.g. Nyan boards).
	394	*/
	395	SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
	396	.ops = &tegra114_sdhci_ops,
	397	};
	398
	399	static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
	400	.pdata = &sdhci_tegra124_pdata,
	401	};
	402
b5a84ecf TR	403	static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
	404	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	405	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
	406	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	407	SDHCI_QUIRK_NO_HISPD_BIT \|
a8e326a9 LS	408	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
	409	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	410	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
b5a84ecf TR	411	.ops = &tegra114_sdhci_ops,
	412	};
	413
	414	static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
	415	.pdata = &sdhci_tegra210_pdata,
b5a84ecf TR	416	};
b5a84ecf TR	417
4346b7c7 TR	418	static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
	419	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	420	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
	421	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	422	SDHCI_QUIRK_NO_HISPD_BIT \|
	423	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
	424	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
68481a7e KR	425	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN \|
	426	/* SDHCI controllers on Tegra186 support 40-bit addressing.
	427	* IOVA addresses are 48-bit wide on Tegra186.
	428	* With 64-bit dma mask used for SDHCI, accesses can
	429	* be broken. Disable 64-bit dma, which would fall back
	430	* to 32-bit dma mask. Ideally 40-bit dma mask would work,
	431	* But it is not supported as of now.
	432	*/
	433	SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
4346b7c7 TR	434	.ops = &tegra114_sdhci_ops,
	435	};
	436
	437	static const struct sdhci_tegra_soc_data soc_data_tegra186 = {
	438	.pdata = &sdhci_tegra186_pdata,
	439	};
	440
498d83e7	441	static const struct of_device_id sdhci_tegra_dt_match[] = {
4346b7c7	442	{ .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
b5a84ecf	443	{ .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
4ae12588	444	{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
5ebf2552	445	{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
3e44a1a7	446	{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
3e44a1a7	447	{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
275173b2 GL	448	{}
275173b2 GL	449	};
e4404fab	450	MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
275173b2	451
c3be1efd	452	static int sdhci_tegra_probe(struct platform_device *pdev)
03d2bfc8	453	{
3e44a1a7 SW	454	const struct of_device_id *match;
	455	const struct sdhci_tegra_soc_data *soc_data;
	456	struct sdhci_host *host;
85d6509d	457	struct sdhci_pltfm_host *pltfm_host;
3e44a1a7	458	struct sdhci_tegra *tegra_host;
03d2bfc8 OJ	459	struct clk *clk;
	460	int rc;
	461
3e44a1a7	462	match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
b37f9d98 JL	463	if (!match)
	464	return -EINVAL;
	465	soc_data = match->data;
3e44a1a7	466
0734e79c	467	host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
85d6509d SG	468	if (IS_ERR(host))
85d6509d SG	469	return PTR_ERR(host);
85d6509d SG	470	pltfm_host = sdhci_priv(host);
85d6509d SG	471
0734e79c	472	tegra_host = sdhci_pltfm_priv(pltfm_host);
a8e326a9	473	tegra_host->ddr_signaling = false;
e5c63d91	474	tegra_host->pad_calib_required = false;
3e44a1a7	475	tegra_host->soc_data = soc_data;
275173b2	476
2391b340	477	rc = mmc_of_parse(host->mmc);
47caa84f SB	478	if (rc)
47caa84f SB	479	goto err_parse_dt;
0e786102	480
7ad2ed1d	481	if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
c3c2384c LS	482	host->mmc->caps \|= MMC_CAP_1_8V_DDR;
c3c2384c LS	483
2391b340 MJ	484	tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
	485	GPIOD_OUT_HIGH);
	486	if (IS_ERR(tegra_host->power_gpio)) {
	487	rc = PTR_ERR(tegra_host->power_gpio);
	488	goto err_power_req;
03d2bfc8 OJ	489	}
03d2bfc8 OJ	490
e4f79d9c	491	clk = devm_clk_get(mmc_dev(host->mmc), NULL);
03d2bfc8 OJ	492	if (IS_ERR(clk)) {
	493	dev_err(mmc_dev(host->mmc), "clk err\n");
	494	rc = PTR_ERR(clk);
85d6509d	495	goto err_clk_get;
03d2bfc8	496	}
1e674bc6	497	clk_prepare_enable(clk);
03d2bfc8 OJ	498	pltfm_host->clk = clk;
03d2bfc8 OJ	499
2cd6c49d PZ	500	tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
2cd6c49d PZ	501	"sdhci");
20567be9 TR	502	if (IS_ERR(tegra_host->rst)) {
	503	rc = PTR_ERR(tegra_host->rst);
	504	dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
	505	goto err_rst_get;
	506	}
	507
	508	rc = reset_control_assert(tegra_host->rst);
	509	if (rc)
	510	goto err_rst_get;
	511
	512	usleep_range(2000, 4000);
	513
	514	rc = reset_control_deassert(tegra_host->rst);
	515	if (rc)
	516	goto err_rst_get;
	517
	518	usleep_range(2000, 4000);
	519
85d6509d SG	520	rc = sdhci_add_host(host);
	521	if (rc)
	522	goto err_add_host;
	523
03d2bfc8 OJ	524	return 0;
03d2bfc8 OJ	525
85d6509d	526	err_add_host:
20567be9 TR	527	reset_control_assert(tegra_host->rst);
20567be9 TR	528	err_rst_get:
1e674bc6	529	clk_disable_unprepare(pltfm_host->clk);
85d6509d	530	err_clk_get:
85d6509d	531	err_power_req:
47caa84f	532	err_parse_dt:
85d6509d	533	sdhci_pltfm_free(pdev);
03d2bfc8 OJ	534	return rc;
	535	}
	536
20567be9 TR	537	static int sdhci_tegra_remove(struct platform_device *pdev)
	538	{
	539	struct sdhci_host *host = platform_get_drvdata(pdev);
	540	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	541	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
	542
	543	sdhci_remove_host(host, 0);
	544
	545	reset_control_assert(tegra_host->rst);
	546	usleep_range(2000, 4000);
	547	clk_disable_unprepare(pltfm_host->clk);
	548
	549	sdhci_pltfm_free(pdev);
	550
	551	return 0;
	552	}
	553
85d6509d SG	554	static struct platform_driver sdhci_tegra_driver = {
	555	.driver = {
	556	.name = "sdhci-tegra",
275173b2	557	.of_match_table = sdhci_tegra_dt_match,
fa243f64	558	.pm = &sdhci_pltfm_pmops,
85d6509d SG	559	},
85d6509d SG	560	.probe = sdhci_tegra_probe,
20567be9	561	.remove = sdhci_tegra_remove,
03d2bfc8 OJ	562	};
03d2bfc8 OJ	563
d1f81a64	564	module_platform_driver(sdhci_tegra_driver);
85d6509d SG	565
85d6509d SG	566	MODULE_DESCRIPTION("SDHCI driver for Tegra");
3e44a1a7	567	MODULE_AUTHOR("Google, Inc.");
85d6509d	568	MODULE_LICENSE("GPL v2");