[linux-2.6-block.git] / drivers / mmc / host / sdhci-tegra.c

/*
 * Copyright (C) 2010 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/gpio.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/slot-gpio.h>

#include "sdhci-pltfm.h"

/* Tegra SDHOST controller vendor register definitions */
#define SDHCI_TEGRA_VENDOR_MISC_CTRL		0x120
#define SDHCI_MISC_CTRL_ENABLE_SDR104		0x8
#define SDHCI_MISC_CTRL_ENABLE_SDR50		0x10
#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300	0x20
#define SDHCI_MISC_CTRL_ENABLE_DDR50		0x200

#define NVQUIRK_FORCE_SDHCI_SPEC_200	BIT(0)
#define NVQUIRK_ENABLE_BLOCK_GAP_DET	BIT(1)
#define NVQUIRK_ENABLE_SDHCI_SPEC_300	BIT(2)
#define NVQUIRK_DISABLE_SDR50		BIT(3)
#define NVQUIRK_DISABLE_SDR104		BIT(4)
#define NVQUIRK_DISABLE_DDR50		BIT(5)

struct sdhci_tegra_soc_data {
	const struct sdhci_pltfm_data *pdata;
	u32 nvquirks;
};

struct sdhci_tegra {
	const struct sdhci_tegra_soc_data *soc_data;
	int power_gpio;
};

static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
			(reg == SDHCI_HOST_VERSION))) {
		/* Erratum: Version register is invalid in HW. */
		return SDHCI_SPEC_200;
	}

	return readw(host->ioaddr + reg);
}

static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	/* Seems like we're getting spurious timeout and crc errors, so
	 * disable signalling of them. In case of real errors software
	 * timers should take care of eventually detecting them.
	 */
	if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
		val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);

	writel(val, host->ioaddr + reg);

	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
			(reg == SDHCI_INT_ENABLE))) {
		/* Erratum: Must enable block gap interrupt detection */
		u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
		if (val & SDHCI_INT_CARD_INT)
			gap_ctrl |= 0x8;
		else
			gap_ctrl &= ~0x8;
		writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	}
}

static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
{
	return mmc_gpio_get_ro(host->mmc);
}

static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	u32 misc_ctrl;

	sdhci_reset(host, mask);

	if (!(mask & SDHCI_RESET_ALL))
		return;

	misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
	/* Erratum: Enable SDHCI spec v3.00 support */
	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
		misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
	/* Don't advertise UHS modes which aren't supported yet */
	if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50)
		misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50;
	if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50)
		misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50;
	if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104)
		misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104;
	sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
}

static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
{
	u32 ctrl;

	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
	    (bus_width == MMC_BUS_WIDTH_8)) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
		ctrl |= SDHCI_CTRL_8BITBUS;
	} else {
		ctrl &= ~SDHCI_CTRL_8BITBUS;
		if (bus_width == MMC_BUS_WIDTH_4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}

static const struct sdhci_ops tegra_sdhci_ops = {
	.get_ro     = tegra_sdhci_get_ro,
	.read_w     = tegra_sdhci_readw,
	.write_l    = tegra_sdhci_writel,
	.set_clock  = sdhci_set_clock,
	.set_bus_width = tegra_sdhci_set_bus_width,
	.reset      = tegra_sdhci_reset,
	.set_uhs_signaling = sdhci_set_uhs_signaling,
	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
};

static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops  = &tegra_sdhci_ops,
};

static struct sdhci_tegra_soc_data soc_data_tegra20 = {
	.pdata = &sdhci_tegra20_pdata,
	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
		    NVQUIRK_ENABLE_BLOCK_GAP_DET,
};

static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops  = &tegra_sdhci_ops,
};

static struct sdhci_tegra_soc_data soc_data_tegra30 = {
	.pdata = &sdhci_tegra30_pdata,
	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
		    NVQUIRK_DISABLE_SDR50 |
		    NVQUIRK_DISABLE_SDR104,
};

static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops  = &tegra_sdhci_ops,
};

static struct sdhci_tegra_soc_data soc_data_tegra114 = {
	.pdata = &sdhci_tegra114_pdata,
	.nvquirks = NVQUIRK_DISABLE_SDR50 |
		    NVQUIRK_DISABLE_DDR50 |
		    NVQUIRK_DISABLE_SDR104,
};

static const struct of_device_id sdhci_tegra_dt_match[] = {
	{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 },
	{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
	{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
	{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
	{}
};
MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);

static int sdhci_tegra_parse_dt(struct device *dev)
{
	struct device_node *np = dev->of_node;
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;

	tegra_host->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
	return mmc_of_parse(host->mmc);
}

static int sdhci_tegra_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	const struct sdhci_tegra_soc_data *soc_data;
	struct sdhci_host *host;
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_tegra *tegra_host;
	struct clk *clk;
	int rc;

	match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
	if (!match)
		return -EINVAL;
	soc_data = match->data;

	host = sdhci_pltfm_init(pdev, soc_data->pdata, 0);
	if (IS_ERR(host))
		return PTR_ERR(host);
	pltfm_host = sdhci_priv(host);

	tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
	if (!tegra_host) {
		dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
		rc = -ENOMEM;
		goto err_alloc_tegra_host;
	}
	tegra_host->soc_data = soc_data;
	pltfm_host->priv = tegra_host;

	rc = sdhci_tegra_parse_dt(&pdev->dev);
	if (rc)
		goto err_parse_dt;

	if (gpio_is_valid(tegra_host->power_gpio)) {
		rc = gpio_request(tegra_host->power_gpio, "sdhci_power");
		if (rc) {
			dev_err(mmc_dev(host->mmc),
				"failed to allocate power gpio\n");
			goto err_power_req;
		}
		gpio_direction_output(tegra_host->power_gpio, 1);
	}

	clk = clk_get(mmc_dev(host->mmc), NULL);
	if (IS_ERR(clk)) {
		dev_err(mmc_dev(host->mmc), "clk err\n");
		rc = PTR_ERR(clk);
		goto err_clk_get;
	}
	clk_prepare_enable(clk);
	pltfm_host->clk = clk;

	rc = sdhci_add_host(host);
	if (rc)
		goto err_add_host;

	return 0;

err_add_host:
	clk_disable_unprepare(pltfm_host->clk);
	clk_put(pltfm_host->clk);
err_clk_get:
	if (gpio_is_valid(tegra_host->power_gpio))
		gpio_free(tegra_host->power_gpio);
err_power_req:
err_parse_dt:
err_alloc_tegra_host:
	sdhci_pltfm_free(pdev);
	return rc;
}

static int sdhci_tegra_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);

	sdhci_remove_host(host, dead);

	if (gpio_is_valid(tegra_host->power_gpio))
		gpio_free(tegra_host->power_gpio);

	clk_disable_unprepare(pltfm_host->clk);
	clk_put(pltfm_host->clk);

	sdhci_pltfm_free(pdev);

	return 0;
}

static struct platform_driver sdhci_tegra_driver = {
	.driver		= {
		.name	= "sdhci-tegra",
		.of_match_table = sdhci_tegra_dt_match,
		.pm	= SDHCI_PLTFM_PMOPS,
	},
	.probe		= sdhci_tegra_probe,
	.remove		= sdhci_tegra_remove,
};

module_platform_driver(sdhci_tegra_driver);

MODULE_DESCRIPTION("SDHCI driver for Tegra");
MODULE_AUTHOR("Google, Inc.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
03d2bfc8 OJ	1	/*
	2	* Copyright (C) 2010 Google, Inc.
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	*/
	14
	15	#include <linux/err.h>
96547f5d	16	#include <linux/module.h>
03d2bfc8 OJ	17	#include <linux/init.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/clk.h>
	20	#include <linux/io.h>
55cd65e4	21	#include <linux/of.h>
3e44a1a7	22	#include <linux/of_device.h>
275173b2	23	#include <linux/of_gpio.h>
03d2bfc8 OJ	24	#include <linux/gpio.h>
	25	#include <linux/mmc/card.h>
	26	#include <linux/mmc/host.h>
0aacd23f	27	#include <linux/mmc/slot-gpio.h>
03d2bfc8	28
03d2bfc8 OJ	29	#include "sdhci-pltfm.h"
03d2bfc8 OJ	30
ca5879d3 PK	31	/* Tegra SDHOST controller vendor register definitions */
ca5879d3 PK	32	#define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
3145351a AB	33	#define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
3145351a AB	34	#define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
ca5879d3	35	#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
3145351a	36	#define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
ca5879d3	37
3e44a1a7 SW	38	#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
3e44a1a7 SW	39	#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
ca5879d3	40	#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
3145351a AB	41	#define NVQUIRK_DISABLE_SDR50 BIT(3)
	42	#define NVQUIRK_DISABLE_SDR104 BIT(4)
	43	#define NVQUIRK_DISABLE_DDR50 BIT(5)
3e44a1a7 SW	44
3e44a1a7 SW	45	struct sdhci_tegra_soc_data {
1db5eebf	46	const struct sdhci_pltfm_data *pdata;
3e44a1a7 SW	47	u32 nvquirks;
	48	};
	49
	50	struct sdhci_tegra {
3e44a1a7	51	const struct sdhci_tegra_soc_data *soc_data;
0e786102	52	int power_gpio;
3e44a1a7 SW	53	};
3e44a1a7 SW	54
03d2bfc8 OJ	55	static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
03d2bfc8 OJ	56	{
3e44a1a7 SW	57	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	58	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	59	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	60
	61	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
	62	(reg == SDHCI_HOST_VERSION))) {
03d2bfc8 OJ	63	/* Erratum: Version register is invalid in HW. */
	64	return SDHCI_SPEC_200;
	65	}
	66
	67	return readw(host->ioaddr + reg);
	68	}
	69
	70	static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	71	{
3e44a1a7 SW	72	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	73	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	74	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	75
03d2bfc8 OJ	76	/* Seems like we're getting spurious timeout and crc errors, so
	77	* disable signalling of them. In case of real errors software
	78	* timers should take care of eventually detecting them.
	79	*/
	80	if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
	81	val &= ~(SDHCI_INT_TIMEOUT\|SDHCI_INT_CRC);
	82
	83	writel(val, host->ioaddr + reg);
	84
3e44a1a7 SW	85	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
3e44a1a7 SW	86	(reg == SDHCI_INT_ENABLE))) {
03d2bfc8 OJ	87	/* Erratum: Must enable block gap interrupt detection */
	88	u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	89	if (val & SDHCI_INT_CARD_INT)
	90	gap_ctrl \|= 0x8;
	91	else
	92	gap_ctrl &= ~0x8;
	93	writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	94	}
	95	}
	96
3e44a1a7	97	static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
03d2bfc8	98	{
0aacd23f	99	return mmc_gpio_get_ro(host->mmc);
03d2bfc8 OJ	100	}
03d2bfc8 OJ	101
03231f9b	102	static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
ca5879d3 PK	103	{
	104	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	105	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	106	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
3145351a	107	u32 misc_ctrl;
ca5879d3	108
03231f9b RK	109	sdhci_reset(host, mask);
03231f9b RK	110
ca5879d3 PK	111	if (!(mask & SDHCI_RESET_ALL))
	112	return;
	113
3145351a	114	misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
ca5879d3	115	/* Erratum: Enable SDHCI spec v3.00 support */
3145351a	116	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
ca5879d3	117	misc_ctrl \|= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
3145351a AB	118	/* Don't advertise UHS modes which aren't supported yet */
	119	if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50)
	120	misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50;
	121	if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50)
	122	misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50;
	123	if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104)
	124	misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104;
	125	sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
ca5879d3 PK	126	}
ca5879d3 PK	127
2317f56c	128	static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
03d2bfc8	129	{
03d2bfc8 OJ	130	u32 ctrl;
03d2bfc8 OJ	131
03d2bfc8	132	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
0aacd23f JL	133	if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
0aacd23f JL	134	(bus_width == MMC_BUS_WIDTH_8)) {
03d2bfc8 OJ	135	ctrl &= ~SDHCI_CTRL_4BITBUS;
	136	ctrl \|= SDHCI_CTRL_8BITBUS;
	137	} else {
	138	ctrl &= ~SDHCI_CTRL_8BITBUS;
	139	if (bus_width == MMC_BUS_WIDTH_4)
	140	ctrl \|= SDHCI_CTRL_4BITBUS;
	141	else
	142	ctrl &= ~SDHCI_CTRL_4BITBUS;
	143	}
	144	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
03d2bfc8 OJ	145	}
03d2bfc8 OJ	146
c915568d	147	static const struct sdhci_ops tegra_sdhci_ops = {
85d6509d	148	.get_ro = tegra_sdhci_get_ro,
85d6509d SG	149	.read_w = tegra_sdhci_readw,
85d6509d SG	150	.write_l = tegra_sdhci_writel,
1771059c	151	.set_clock = sdhci_set_clock,
2317f56c	152	.set_bus_width = tegra_sdhci_set_bus_width,
03231f9b	153	.reset = tegra_sdhci_reset,
96d7b78c	154	.set_uhs_signaling = sdhci_set_uhs_signaling,
f9260355	155	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
85d6509d SG	156	};
85d6509d SG	157
1db5eebf	158	static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
3e44a1a7 SW	159	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	160	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	161	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	162	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	163	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
3e44a1a7 SW	164	.ops = &tegra_sdhci_ops,
	165	};
	166
	167	static struct sdhci_tegra_soc_data soc_data_tegra20 = {
	168	.pdata = &sdhci_tegra20_pdata,
	169	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 \|
	170	NVQUIRK_ENABLE_BLOCK_GAP_DET,
	171	};
3e44a1a7	172
1db5eebf	173	static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
85d6509d	174	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
3e44a1a7	175	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
85d6509d SG	176	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
85d6509d SG	177	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	178	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	179	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
85d6509d SG	180	.ops = &tegra_sdhci_ops,
85d6509d SG	181	};
03d2bfc8	182
3e44a1a7 SW	183	static struct sdhci_tegra_soc_data soc_data_tegra30 = {
3e44a1a7 SW	184	.pdata = &sdhci_tegra30_pdata,
3145351a AB	185	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 \|
	186	NVQUIRK_DISABLE_SDR50 \|
	187	NVQUIRK_DISABLE_SDR104,
3e44a1a7	188	};
3e44a1a7	189
1db5eebf	190	static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
5ebf2552 RK	191	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	192	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
	193	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	194	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	195	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	196	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
5ebf2552 RK	197	.ops = &tegra_sdhci_ops,
	198	};
	199
	200	static struct sdhci_tegra_soc_data soc_data_tegra114 = {
	201	.pdata = &sdhci_tegra114_pdata,
3145351a AB	202	.nvquirks = NVQUIRK_DISABLE_SDR50 \|
	203	NVQUIRK_DISABLE_DDR50 \|
	204	NVQUIRK_DISABLE_SDR104,
5ebf2552 RK	205	};
5ebf2552 RK	206
498d83e7	207	static const struct of_device_id sdhci_tegra_dt_match[] = {
67debea3	208	{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 },
5ebf2552	209	{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
3e44a1a7	210	{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
3e44a1a7	211	{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
275173b2 GL	212	{}
275173b2 GL	213	};
e4404fab	214	MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
275173b2	215
47caa84f	216	static int sdhci_tegra_parse_dt(struct device *dev)
275173b2	217	{
0e786102	218	struct device_node *np = dev->of_node;
0aacd23f JL	219	struct sdhci_host *host = dev_get_drvdata(dev);
	220	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	221	struct sdhci_tegra *tegra_host = pltfm_host->priv;
275173b2	222
0e786102	223	tegra_host->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
47caa84f	224	return mmc_of_parse(host->mmc);
275173b2 GL	225	}
275173b2 GL	226
c3be1efd	227	static int sdhci_tegra_probe(struct platform_device *pdev)
03d2bfc8	228	{
3e44a1a7 SW	229	const struct of_device_id *match;
	230	const struct sdhci_tegra_soc_data *soc_data;
	231	struct sdhci_host *host;
85d6509d	232	struct sdhci_pltfm_host *pltfm_host;
3e44a1a7	233	struct sdhci_tegra *tegra_host;
03d2bfc8 OJ	234	struct clk *clk;
	235	int rc;
	236
3e44a1a7	237	match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
b37f9d98 JL	238	if (!match)
	239	return -EINVAL;
	240	soc_data = match->data;
3e44a1a7	241
0e748234	242	host = sdhci_pltfm_init(pdev, soc_data->pdata, 0);
85d6509d SG	243	if (IS_ERR(host))
85d6509d SG	244	return PTR_ERR(host);
85d6509d SG	245	pltfm_host = sdhci_priv(host);
85d6509d SG	246
3e44a1a7 SW	247	tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
	248	if (!tegra_host) {
	249	dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
	250	rc = -ENOMEM;
0e786102	251	goto err_alloc_tegra_host;
3e44a1a7	252	}
3e44a1a7	253	tegra_host->soc_data = soc_data;
3e44a1a7	254	pltfm_host->priv = tegra_host;
275173b2	255
47caa84f SB	256	rc = sdhci_tegra_parse_dt(&pdev->dev);
	257	if (rc)
	258	goto err_parse_dt;
0e786102 SW	259
	260	if (gpio_is_valid(tegra_host->power_gpio)) {
	261	rc = gpio_request(tegra_host->power_gpio, "sdhci_power");
03d2bfc8 OJ	262	if (rc) {
	263	dev_err(mmc_dev(host->mmc),
	264	"failed to allocate power gpio\n");
85d6509d	265	goto err_power_req;
03d2bfc8	266	}
0e786102	267	gpio_direction_output(tegra_host->power_gpio, 1);
03d2bfc8 OJ	268	}
03d2bfc8 OJ	269
03d2bfc8 OJ	270	clk = clk_get(mmc_dev(host->mmc), NULL);
	271	if (IS_ERR(clk)) {
	272	dev_err(mmc_dev(host->mmc), "clk err\n");
	273	rc = PTR_ERR(clk);
85d6509d	274	goto err_clk_get;
03d2bfc8	275	}
1e674bc6	276	clk_prepare_enable(clk);
03d2bfc8 OJ	277	pltfm_host->clk = clk;
03d2bfc8 OJ	278
85d6509d SG	279	rc = sdhci_add_host(host);
	280	if (rc)
	281	goto err_add_host;
	282
03d2bfc8 OJ	283	return 0;
03d2bfc8 OJ	284
85d6509d	285	err_add_host:
1e674bc6	286	clk_disable_unprepare(pltfm_host->clk);
85d6509d SG	287	clk_put(pltfm_host->clk);
85d6509d SG	288	err_clk_get:
0e786102 SW	289	if (gpio_is_valid(tegra_host->power_gpio))
0e786102 SW	290	gpio_free(tegra_host->power_gpio);
85d6509d	291	err_power_req:
47caa84f	292	err_parse_dt:
0e786102	293	err_alloc_tegra_host:
85d6509d	294	sdhci_pltfm_free(pdev);
03d2bfc8 OJ	295	return rc;
	296	}
	297
6e0ee714	298	static int sdhci_tegra_remove(struct platform_device *pdev)
03d2bfc8	299	{
85d6509d	300	struct sdhci_host *host = platform_get_drvdata(pdev);
03d2bfc8	301	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
3e44a1a7	302	struct sdhci_tegra *tegra_host = pltfm_host->priv;
85d6509d SG	303	int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
	304
	305	sdhci_remove_host(host, dead);
03d2bfc8	306
0e786102 SW	307	if (gpio_is_valid(tegra_host->power_gpio))
0e786102 SW	308	gpio_free(tegra_host->power_gpio);
03d2bfc8	309
1e674bc6	310	clk_disable_unprepare(pltfm_host->clk);
03d2bfc8	311	clk_put(pltfm_host->clk);
85d6509d SG	312
	313	sdhci_pltfm_free(pdev);
	314
	315	return 0;
03d2bfc8 OJ	316	}
03d2bfc8 OJ	317
85d6509d SG	318	static struct platform_driver sdhci_tegra_driver = {
	319	.driver = {
	320	.name = "sdhci-tegra",
275173b2	321	.of_match_table = sdhci_tegra_dt_match,
29495aa0	322	.pm = SDHCI_PLTFM_PMOPS,
85d6509d SG	323	},
85d6509d SG	324	.probe = sdhci_tegra_probe,
0433c143	325	.remove = sdhci_tegra_remove,
03d2bfc8 OJ	326	};
03d2bfc8 OJ	327
d1f81a64	328	module_platform_driver(sdhci_tegra_driver);
85d6509d SG	329
85d6509d SG	330	MODULE_DESCRIPTION("SDHCI driver for Tegra");
3e44a1a7	331	MODULE_AUTHOR("Google, Inc.");
85d6509d	332	MODULE_LICENSE("GPL v2");