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mmc: sdhci-sprd: fixed incorrect clock divider
[linux-2.6-block.git] / drivers / mmc / host / sdhci-sprd.c
CommitLineData
fb8bd90f
CZ		 1// SPDX-License-Identifier: GPL-2.0
2//
3// Secure Digital Host Controller
4//
5// Copyright (C) 2018 Spreadtrum, Inc.
6// Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
7
8#include <linux/delay.h>
9#include <linux/dma-mapping.h>
10#include <linux/highmem.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/of_gpio.h>
29ca763f 15#include <linux/pinctrl/consumer.h>
fb8bd90f
CZ		 16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/regulator/consumer.h>
19#include <linux/slab.h>
20
21#include "sdhci-pltfm.h"
22
23/* SDHCI_ARGUMENT2 register high 16bit */
24#define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16)
25
87a395c2
BW		 26#define SDHCI_SPRD_REG_32_DLL_CFG 0x200
27#define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
28#define SDHCI_SPRD_DLL_EN BIT(21)
29#define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16)
30#define SDHCI_SPRD_DLL_INIT_COUNT 0xc00
31#define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3
32
5f2f4e0d
BW		 33#define SDHCI_SPRD_REG_32_DLL_DLY 0x204
34
fb8bd90f
CZ		 35#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208
36#define SDHCIBSPRD_IT_WR_DLY_INV BIT(5)
37#define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13)
38#define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21)
39#define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29)
40
41#define SDHCI_SPRD_REG_32_BUSY_POSI 0x250
42#define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25)
43#define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24)
44
45#define SDHCI_SPRD_REG_DEBOUNCE 0x28C
46#define SDHCI_SPRD_BIT_DLL_BAK BIT(0)
47#define SDHCI_SPRD_BIT_DLL_VAL BIT(1)
48
49#define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B
50
51/* SDHCI_HOST_CONTROL2 */
52#define SDHCI_SPRD_CTRL_HS200 0x0005
53#define SDHCI_SPRD_CTRL_HS400 0x0006
494c11e1 54#define SDHCI_SPRD_CTRL_HS400ES 0x0007
fb8bd90f
CZ		 55
56/*
57 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
58 * reserved, and only used on Spreadtrum's design, the hardware cannot work
59 * if this bit is cleared.
60 * 1 : normal work
61 * 0 : hardware reset
62 */
63#define SDHCI_HW_RESET_CARD BIT(3)
64
65#define SDHCI_SPRD_MAX_CUR 0xFFFFFF
66#define SDHCI_SPRD_CLK_MAX_DIV 1023
67
68#define SDHCI_SPRD_CLK_DEF_RATE 26000000
87a395c2 69#define SDHCI_SPRD_PHY_DLL_CLK 52000000
fb8bd90f
CZ		 70
71struct sdhci_sprd_host {
72 u32 version;
73 struct clk *clk_sdio;
74 struct clk *clk_enable;
ebd88a38 75 struct clk *clk_2x_enable;
29ca763f
BW		 76 struct pinctrl *pinctrl;
77 struct pinctrl_state *pins_uhs;
78 struct pinctrl_state *pins_default;
fb8bd90f
CZ		 79 u32 base_rate;
80 int flags; /* backup of host attribute */
5f2f4e0d
BW		 81 u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
82};
83
84struct sdhci_sprd_phy_cfg {
85 const char *property;
86 u8 timing;
87};
88
89static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
90 { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
91 { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
92 { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
93 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
94 { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
95 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
96 { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
97 { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
98 { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
fb8bd90f
CZ		 99};
100
101#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
102
103static void sdhci_sprd_init_config(struct sdhci_host *host)
104{
105 u16 val;
106
107 /* set dll backup mode */
108 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
109 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
110 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
111}
112
113static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
114{
115 if (unlikely(reg == SDHCI_MAX_CURRENT))
116 return SDHCI_SPRD_MAX_CUR;
117
118 return readl_relaxed(host->ioaddr + reg);
119}
120
121static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
122{
123 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
124 if (unlikely(reg == SDHCI_MAX_CURRENT))
125 return;
126
127 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
128 val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
129
130 writel_relaxed(val, host->ioaddr + reg);
131}
132
133static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
134{
135 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
136 if (unlikely(reg == SDHCI_BLOCK_COUNT))
137 return;
138
139 writew_relaxed(val, host->ioaddr + reg);
140}
141
142static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
143{
144 /*
145 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
146 * standard specification, sdhci_reset() write this register directly
147 * without checking other reserved bits, that will clear BIT(3) which
148 * is defined as hardware reset on Spreadtrum's platform and clearing
149 * it by mistake will lead the card not work. So here we need to work
150 * around it.
151 */
152 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
153 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
154 val |= SDHCI_HW_RESET_CARD;
155 }
156
157 writeb_relaxed(val, host->ioaddr + reg);
158}
159
160static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
161{
162 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
163
164 ctrl &= ~SDHCI_CLOCK_CARD_EN;
165 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
166}
167
494c11e1
BW		 168static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
169{
170 u16 ctrl;
171
172 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
173 ctrl |= SDHCI_CLOCK_CARD_EN;
174 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
175}
176
fb8bd90f
CZ		 177static inline void
178sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
179{
180 u32 dll_dly_offset;
181
182 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
183 if (en)
184 dll_dly_offset |= mask;
185 else
186 dll_dly_offset &= ~mask;
187 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
188}
189
190static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
191{
192 u32 div;
193
194 /* select 2x clock source */
195 if (base_clk <= clk * 2)
196 return 0;
197
198 div = (u32) (base_clk / (clk * 2));
199
200 if ((base_clk / div) > (clk * 2))
201 div++;
202
203 if (div > SDHCI_SPRD_CLK_MAX_DIV)
204 div = SDHCI_SPRD_CLK_MAX_DIV;
205
206 if (div % 2)
207 div = (div + 1) / 2;
208 else
209 div = div / 2;
210
211 return div;
212}
213
214static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
215 unsigned int clk)
216{
217 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
218 u32 div, val, mask;
219
efdaf275 220 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
fb8bd90f 221
efdaf275
CZ		 222 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
223 div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
224 sdhci_enable_clk(host, div);
fb8bd90f
CZ		 225
226 /* enable auto gate sdhc_enable_auto_gate */
227 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
228 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN |
229 SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
230 if (mask != (val & mask)) {
231 val |= mask;
232 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
233 }
234}
235
87a395c2
BW		 236static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
237{
238 u32 tmp;
239
240 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
241 tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
242 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
243 /* wait 1ms */
244 usleep_range(1000, 1250);
245
246 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
247 tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
248 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
249 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
250 /* wait 1ms */
251 usleep_range(1000, 1250);
252
253 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
254 tmp |= SDHCI_SPRD_DLL_EN;
255 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
256 /* wait 1ms */
257 usleep_range(1000, 1250);
258}
259
fb8bd90f
CZ		 260static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
261{
87a395c2 262 bool en = false, clk_changed = false;
fb8bd90f
CZ		 263
264 if (clock == 0) {
265 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
266 } else if (clock != host->clock) {
267 sdhci_sprd_sd_clk_off(host);
268 _sdhci_sprd_set_clock(host, clock);
269
270 if (clock <= 400000)
271 en = true;
272 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
273 SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
87a395c2 274 clk_changed = true;
fb8bd90f
CZ		 275 } else {
276 _sdhci_sprd_set_clock(host, clock);
277 }
87a395c2
BW		 278
279 /*
280 * According to the Spreadtrum SD host specification, when we changed
281 * the clock to be more than 52M, we should enable the PHY DLL which
282 * is used to track the clock frequency to make the clock work more
283 * stable. Otherwise deviation may occur of the higher clock.
284 */
285 if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
286 sdhci_sprd_enable_phy_dll(host);
fb8bd90f
CZ		 287}
288
289static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
290{
291 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
292
293 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
294}
295
296static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
297{
298 return 400000;
299}
300
301static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
302 unsigned int timing)
303{
5f2f4e0d
BW		 304 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
305 struct mmc_host *mmc = host->mmc;
306 u32 *p = sprd_host->phy_delay;
fb8bd90f
CZ		 307 u16 ctrl_2;
308
309 if (timing == host->timing)
310 return;
311
312 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
313 /* Select Bus Speed Mode for host */
314 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
315 switch (timing) {
316 case MMC_TIMING_UHS_SDR12:
317 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
318 break;
319 case MMC_TIMING_MMC_HS:
320 case MMC_TIMING_SD_HS:
321 case MMC_TIMING_UHS_SDR25:
322 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
323 break;
324 case MMC_TIMING_UHS_SDR50:
325 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
326 break;
327 case MMC_TIMING_UHS_SDR104:
328 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
329 break;
330 case MMC_TIMING_UHS_DDR50:
331 case MMC_TIMING_MMC_DDR52:
332 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
333 break;
334 case MMC_TIMING_MMC_HS200:
335 ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
336 break;
337 case MMC_TIMING_MMC_HS400:
338 ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
339 break;
340 default:
341 break;
342 }
343
344 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
5f2f4e0d
BW		 345
346 if (!mmc->ios.enhanced_strobe)
347 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
fb8bd90f
CZ		 348}
349
350static void sdhci_sprd_hw_reset(struct sdhci_host *host)
351{
352 int val;
353
354 /*
355 * Note: don't use sdhci_writeb() API here since it is redirected to
356 * sdhci_sprd_writeb() in which we have a workaround for
357 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
358 * not be cleared.
359 */
360 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
361 val &= ~SDHCI_HW_RESET_CARD;
362 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
363 /* wait for 10 us */
364 usleep_range(10, 20);
365
366 val |= SDHCI_HW_RESET_CARD;
367 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
368 usleep_range(300, 500);
369}
370
7486831d
BW		 371static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
372{
373 /* The Spredtrum controller actual maximum timeout count is 1 << 31 */
374 return 1 << 31;
375}
376
fb8bd90f
CZ		 377static struct sdhci_ops sdhci_sprd_ops = {
378 .read_l = sdhci_sprd_readl,
379 .write_l = sdhci_sprd_writel,
380 .write_b = sdhci_sprd_writeb,
381 .set_clock = sdhci_sprd_set_clock,
382 .get_max_clock = sdhci_sprd_get_max_clock,
383 .get_min_clock = sdhci_sprd_get_min_clock,
384 .set_bus_width = sdhci_set_bus_width,
385 .reset = sdhci_reset,
386 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
387 .hw_reset = sdhci_sprd_hw_reset,
7486831d 388 .get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
fb8bd90f
CZ		 389};
390
391static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
392{
393 struct sdhci_host *host = mmc_priv(mmc);
394 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
395
396 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
397
398 /*
399 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit
400 * block count register which doesn't support stuff bits of
401 * CMD23 argument on Spreadtrum's sd host controller.
402 */
403 if (host->version >= SDHCI_SPEC_410 &&
404 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
405 (host->flags & SDHCI_AUTO_CMD23))
406 host->flags &= ~SDHCI_AUTO_CMD23;
407
408 sdhci_request(mmc, mrq);
409}
410
eef9e0a6
BW		 411static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
412{
29ca763f
BW		 413 struct sdhci_host *host = mmc_priv(mmc);
414 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
eef9e0a6
BW		 415 int ret;
416
417 if (!IS_ERR(mmc->supply.vqmmc)) {
418 ret = mmc_regulator_set_vqmmc(mmc, ios);
419 if (ret) {
420 pr_err("%s: Switching signalling voltage failed\n",
421 mmc_hostname(mmc));
422 return ret;
423 }
424 }
425
29ca763f
BW		 426 if (IS_ERR(sprd_host->pinctrl))
427 return 0;
428
429 switch (ios->signal_voltage) {
430 case MMC_SIGNAL_VOLTAGE_180:
431 ret = pinctrl_select_state(sprd_host->pinctrl,
432 sprd_host->pins_uhs);
433 if (ret) {
434 pr_err("%s: failed to select uhs pin state\n",
435 mmc_hostname(mmc));
436 return ret;
437 }
438 break;
439
440 default:
441 /* fall-through */
442 case MMC_SIGNAL_VOLTAGE_330:
443 ret = pinctrl_select_state(sprd_host->pinctrl,
444 sprd_host->pins_default);
445 if (ret) {
446 pr_err("%s: failed to select default pin state\n",
447 mmc_hostname(mmc));
448 return ret;
449 }
450 break;
451 }
452
453 /* Wait for 300 ~ 500 us for pin state stable */
454 usleep_range(300, 500);
455 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
456
eef9e0a6
BW		 457 return 0;
458}
459
494c11e1
BW		 460static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
461 struct mmc_ios *ios)
462{
463 struct sdhci_host *host = mmc_priv(mmc);
5f2f4e0d
BW		 464 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
465 u32 *p = sprd_host->phy_delay;
494c11e1
BW		 466 u16 ctrl_2;
467
468 if (!ios->enhanced_strobe)
469 return;
470
471 sdhci_sprd_sd_clk_off(host);
472
473 /* Set HS400 enhanced strobe mode */
474 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
475 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
476 ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
477 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
478
479 sdhci_sprd_sd_clk_on(host);
5f2f4e0d
BW		 480
481 /* Set the PHY DLL delay value for HS400 enhanced strobe mode */
482 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
483 SDHCI_SPRD_REG_32_DLL_DLY);
484}
485
486static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
487 struct device_node *np)
488{
489 u32 *p = sprd_host->phy_delay;
490 int ret, i, index;
491 u32 val[4];
492
493 for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
494 ret = of_property_read_u32_array(np,
495 sdhci_sprd_phy_cfgs[i].property, val, 4);
496 if (ret)
497 continue;
498
499 index = sdhci_sprd_phy_cfgs[i].timing;
500 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
501 }
494c11e1
BW		 502}
503
fb8bd90f
CZ		 504static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
505 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
506 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
507 SDHCI_QUIRK2_USE_32BIT_BLK_CNT,
508 .ops = &sdhci_sprd_ops,
509};
510
511static int sdhci_sprd_probe(struct platform_device *pdev)
512{
513 struct sdhci_host *host;
514 struct sdhci_sprd_host *sprd_host;
515 struct clk *clk;
516 int ret = 0;
517
518 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
519 if (IS_ERR(host))
520 return PTR_ERR(host);
521
522 host->dma_mask = DMA_BIT_MASK(64);
523 pdev->dev.dma_mask = &host->dma_mask;
524 host->mmc_host_ops.request = sdhci_sprd_request;
494c11e1
BW		 525 host->mmc_host_ops.hs400_enhanced_strobe =
526 sdhci_sprd_hs400_enhanced_strobe;
eef9e0a6
BW		 527 /*
528 * We can not use the standard ops to change and detect the voltage
529 * signal for Spreadtrum SD host controller, since our voltage regulator
530 * for I/O is fixed in hardware, that means we do not need control
531 * the standard SD host controller to change the I/O voltage.
532 */
533 host->mmc_host_ops.start_signal_voltage_switch =
534 sdhci_sprd_voltage_switch;
fb8bd90f
CZ		 535
536 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
537 MMC_CAP_ERASE | MMC_CAP_CMD23;
538 ret = mmc_of_parse(host->mmc);
539 if (ret)
540 goto pltfm_free;
541
542 sprd_host = TO_SPRD_HOST(host);
5f2f4e0d 543 sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
fb8bd90f 544
29ca763f
BW		 545 sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
546 if (!IS_ERR(sprd_host->pinctrl)) {
547 sprd_host->pins_uhs =
548 pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
549 if (IS_ERR(sprd_host->pins_uhs)) {
550 ret = PTR_ERR(sprd_host->pins_uhs);
551 goto pltfm_free;
552 }
553
554 sprd_host->pins_default =
555 pinctrl_lookup_state(sprd_host->pinctrl, "default");
556 if (IS_ERR(sprd_host->pins_default)) {
557 ret = PTR_ERR(sprd_host->pins_default);
558 goto pltfm_free;
559 }
560 }
561
fb8bd90f
CZ		 562 clk = devm_clk_get(&pdev->dev, "sdio");
563 if (IS_ERR(clk)) {
564 ret = PTR_ERR(clk);
565 goto pltfm_free;
566 }
567 sprd_host->clk_sdio = clk;
568 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
569 if (!sprd_host->base_rate)
570 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
571
572 clk = devm_clk_get(&pdev->dev, "enable");
573 if (IS_ERR(clk)) {
574 ret = PTR_ERR(clk);
575 goto pltfm_free;
576 }
577 sprd_host->clk_enable = clk;
578
ebd88a38
BW		 579 clk = devm_clk_get(&pdev->dev, "2x_enable");
580 if (!IS_ERR(clk))
581 sprd_host->clk_2x_enable = clk;
582
fb8bd90f
CZ		 583 ret = clk_prepare_enable(sprd_host->clk_sdio);
584 if (ret)
585 goto pltfm_free;
586
1d94717d 587 ret = clk_prepare_enable(sprd_host->clk_enable);
fb8bd90f
CZ		 588 if (ret)
589 goto clk_disable;
590
ebd88a38
BW		 591 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
592 if (ret)
593 goto clk_disable2;
594
fb8bd90f
CZ		 595 sdhci_sprd_init_config(host);
596 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
597 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
598 SDHCI_VENDOR_VER_SHIFT);
599
600 pm_runtime_get_noresume(&pdev->dev);
601 pm_runtime_set_active(&pdev->dev);
602 pm_runtime_enable(&pdev->dev);
603 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
604 pm_runtime_use_autosuspend(&pdev->dev);
605 pm_suspend_ignore_children(&pdev->dev, 1);
606
607 sdhci_enable_v4_mode(host);
608
609 ret = sdhci_setup_host(host);
610 if (ret)
611 goto pm_runtime_disable;
612
613 sprd_host->flags = host->flags;
614
615 ret = __sdhci_add_host(host);
616 if (ret)
617 goto err_cleanup_host;
618
619 pm_runtime_mark_last_busy(&pdev->dev);
620 pm_runtime_put_autosuspend(&pdev->dev);
621
622 return 0;
623
624err_cleanup_host:
625 sdhci_cleanup_host(host);
626
627pm_runtime_disable:
fc62113b 628 pm_runtime_put_noidle(&pdev->dev);
fb8bd90f
CZ		 629 pm_runtime_disable(&pdev->dev);
630 pm_runtime_set_suspended(&pdev->dev);
631
ebd88a38
BW		 632 clk_disable_unprepare(sprd_host->clk_2x_enable);
633
634clk_disable2:
fb8bd90f
CZ		 635 clk_disable_unprepare(sprd_host->clk_enable);
636
637clk_disable:
638 clk_disable_unprepare(sprd_host->clk_sdio);
639
640pltfm_free:
641 sdhci_pltfm_free(pdev);
642 return ret;
643}
644
645static int sdhci_sprd_remove(struct platform_device *pdev)
646{
647 struct sdhci_host *host = platform_get_drvdata(pdev);
648 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
649 struct mmc_host *mmc = host->mmc;
650
651 mmc_remove_host(mmc);
652 clk_disable_unprepare(sprd_host->clk_sdio);
653 clk_disable_unprepare(sprd_host->clk_enable);
ebd88a38 654 clk_disable_unprepare(sprd_host->clk_2x_enable);
fb8bd90f
CZ		 655
656 mmc_free_host(mmc);
657
658 return 0;
659}
660
661static const struct of_device_id sdhci_sprd_of_match[] = {
662 { .compatible = "sprd,sdhci-r11", },
663 { }
664};
665MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
666
667#ifdef CONFIG_PM
668static int sdhci_sprd_runtime_suspend(struct device *dev)
669{
670 struct sdhci_host *host = dev_get_drvdata(dev);
671 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
672
673 sdhci_runtime_suspend_host(host);
674
675 clk_disable_unprepare(sprd_host->clk_sdio);
676 clk_disable_unprepare(sprd_host->clk_enable);
ebd88a38 677 clk_disable_unprepare(sprd_host->clk_2x_enable);
fb8bd90f
CZ		 678
679 return 0;
680}
681
682static int sdhci_sprd_runtime_resume(struct device *dev)
683{
684 struct sdhci_host *host = dev_get_drvdata(dev);
685 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
686 int ret;
687
ebd88a38 688 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
fb8bd90f
CZ		 689 if (ret)
690 return ret;
691
ebd88a38
BW		 692 ret = clk_prepare_enable(sprd_host->clk_enable);
693 if (ret)
694 goto clk_2x_disable;
695
fb8bd90f 696 ret = clk_prepare_enable(sprd_host->clk_sdio);
ebd88a38
BW		 697 if (ret)
698 goto clk_disable;
fb8bd90f 699
c6303c5d 700 sdhci_runtime_resume_host(host, 1);
fb8bd90f 701 return 0;
ebd88a38
BW		 702
703clk_disable:
704 clk_disable_unprepare(sprd_host->clk_enable);
705
706clk_2x_disable:
707 clk_disable_unprepare(sprd_host->clk_2x_enable);
708
709 return ret;
fb8bd90f
CZ		 710}
711#endif
712
713static const struct dev_pm_ops sdhci_sprd_pm_ops = {
714 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
715 pm_runtime_force_resume)
716 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
717 sdhci_sprd_runtime_resume, NULL)
718};
719
720static struct platform_driver sdhci_sprd_driver = {
721 .probe = sdhci_sprd_probe,
722 .remove = sdhci_sprd_remove,
723 .driver = {
724 .name = "sdhci_sprd_r11",
725 .of_match_table = of_match_ptr(sdhci_sprd_of_match),
726 .pm = &sdhci_sprd_pm_ops,
727 },
728};
729module_platform_driver(sdhci_sprd_driver);
730
731MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
732MODULE_LICENSE("GPL v2");
733MODULE_ALIAS("platform:sdhci-sprd-r11");
Linux 6.x block layer and io_uring tree(s)