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0d1bb41a BD |
1 | /* linux/drivers/mmc/host/sdhci-s3c.c |
2 | * | |
3 | * Copyright 2008 Openmoko Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * SDHCI (HSMMC) support for Samsung SoC | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
017210d1 | 15 | #include <linux/spinlock.h> |
0d1bb41a BD |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/platform_device.h> | |
cc014f3e | 19 | #include <linux/platform_data/mmc-sdhci-s3c.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
0d1bb41a BD |
21 | #include <linux/clk.h> |
22 | #include <linux/io.h> | |
17866e14 | 23 | #include <linux/gpio.h> |
55156d24 | 24 | #include <linux/module.h> |
d5e9c02c MB |
25 | #include <linux/of.h> |
26 | #include <linux/of_gpio.h> | |
27 | #include <linux/pm.h> | |
9f4e8151 | 28 | #include <linux/pm_runtime.h> |
0d1bb41a BD |
29 | |
30 | #include <linux/mmc/host.h> | |
31 | ||
0d1bb41a BD |
32 | #include "sdhci.h" |
33 | ||
34 | #define MAX_BUS_CLK (4) | |
35 | ||
57f83245 JC |
36 | #define S3C_SDHCI_CONTROL2 (0x80) |
37 | #define S3C_SDHCI_CONTROL3 (0x84) | |
38 | #define S3C64XX_SDHCI_CONTROL4 (0x8C) | |
39 | ||
e64aae82 JC |
40 | #define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31) |
41 | #define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30) | |
42 | #define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29) | |
43 | #define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28) | |
57f83245 JC |
44 | |
45 | #define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) | |
46 | #define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) | |
47 | #define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) | |
48 | ||
49 | #define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) | |
50 | #define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16) | |
51 | #define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) | |
52 | ||
e64aae82 JC |
53 | #define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15) |
54 | #define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14) | |
55 | #define S3C_SDHCI_CTRL2_SDCDSEL BIT(13) | |
56 | #define S3C_SDHCI_CTRL2_SDSIGPC BIT(12) | |
57 | #define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11) | |
57f83245 JC |
58 | |
59 | #define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9) | |
60 | #define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9) | |
61 | #define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9) | |
62 | #define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9) | |
63 | #define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9) | |
64 | #define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9) | |
65 | ||
e64aae82 JC |
66 | #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8) |
67 | #define S3C_SDHCI_CTRL2_RWAITMODE BIT(7) | |
68 | #define S3C_SDHCI_CTRL2_DISBUFRD BIT(6) | |
69 | ||
57f83245 JC |
70 | #define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4) |
71 | #define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4) | |
e64aae82 JC |
72 | #define S3C_SDHCI_CTRL2_PWRSYNC BIT(3) |
73 | #define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1) | |
74 | #define S3C_SDHCI_CTRL2_HWINITFIN BIT(0) | |
57f83245 | 75 | |
e64aae82 JC |
76 | #define S3C_SDHCI_CTRL3_FCSEL3 BIT(31) |
77 | #define S3C_SDHCI_CTRL3_FCSEL2 BIT(23) | |
78 | #define S3C_SDHCI_CTRL3_FCSEL1 BIT(15) | |
79 | #define S3C_SDHCI_CTRL3_FCSEL0 BIT(7) | |
57f83245 JC |
80 | |
81 | #define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24) | |
82 | #define S3C_SDHCI_CTRL3_FIA3_SHIFT (24) | |
83 | #define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24) | |
84 | ||
85 | #define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16) | |
86 | #define S3C_SDHCI_CTRL3_FIA2_SHIFT (16) | |
87 | #define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16) | |
88 | ||
89 | #define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8) | |
90 | #define S3C_SDHCI_CTRL3_FIA1_SHIFT (8) | |
91 | #define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8) | |
92 | ||
93 | #define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0) | |
94 | #define S3C_SDHCI_CTRL3_FIA0_SHIFT (0) | |
95 | #define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0) | |
96 | ||
97 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16) | |
98 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16) | |
99 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16) | |
100 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16) | |
101 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16) | |
102 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16) | |
103 | ||
104 | #define S3C64XX_SDHCI_CONTROL4_BUSY (1) | |
105 | ||
0d1bb41a BD |
106 | /** |
107 | * struct sdhci_s3c - S3C SDHCI instance | |
108 | * @host: The SDHCI host created | |
109 | * @pdev: The platform device we where created from. | |
110 | * @ioarea: The resource created when we claimed the IO area. | |
111 | * @pdata: The platform data for this controller. | |
112 | * @cur_clk: The index of the current bus clock. | |
113 | * @clk_io: The clock for the internal bus interface. | |
114 | * @clk_bus: The clocks that are available for the SD/MMC bus clock. | |
115 | */ | |
116 | struct sdhci_s3c { | |
117 | struct sdhci_host *host; | |
118 | struct platform_device *pdev; | |
119 | struct resource *ioarea; | |
120 | struct s3c_sdhci_platdata *pdata; | |
3ac147fa | 121 | int cur_clk; |
17866e14 MS |
122 | int ext_cd_irq; |
123 | int ext_cd_gpio; | |
0d1bb41a BD |
124 | |
125 | struct clk *clk_io; | |
126 | struct clk *clk_bus[MAX_BUS_CLK]; | |
6eb28bdc | 127 | unsigned long clk_rates[MAX_BUS_CLK]; |
1771059c RK |
128 | |
129 | bool no_divider; | |
0d1bb41a BD |
130 | }; |
131 | ||
3119936a TA |
132 | /** |
133 | * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data | |
134 | * @sdhci_quirks: sdhci host specific quirks. | |
135 | * | |
136 | * Specifies platform specific configuration of sdhci controller. | |
137 | * Note: A structure for driver specific platform data is used for future | |
138 | * expansion of its usage. | |
139 | */ | |
140 | struct sdhci_s3c_drv_data { | |
141 | unsigned int sdhci_quirks; | |
1771059c | 142 | bool no_divider; |
3119936a TA |
143 | }; |
144 | ||
0d1bb41a BD |
145 | static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) |
146 | { | |
147 | return sdhci_priv(host); | |
148 | } | |
149 | ||
0d1bb41a BD |
150 | /** |
151 | * sdhci_s3c_get_max_clk - callback to get maximum clock frequency. | |
152 | * @host: The SDHCI host instance. | |
153 | * | |
154 | * Callback to return the maximum clock rate acheivable by the controller. | |
155 | */ | |
156 | static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host) | |
157 | { | |
158 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
159 | unsigned long rate, max = 0; |
160 | int src; | |
0d1bb41a | 161 | |
222a13c5 TF |
162 | for (src = 0; src < MAX_BUS_CLK; src++) { |
163 | rate = ourhost->clk_rates[src]; | |
0d1bb41a BD |
164 | if (rate > max) |
165 | max = rate; | |
166 | } | |
167 | ||
168 | return max; | |
169 | } | |
170 | ||
0d1bb41a BD |
171 | /** |
172 | * sdhci_s3c_consider_clock - consider one the bus clocks for current setting | |
173 | * @ourhost: Our SDHCI instance. | |
174 | * @src: The source clock index. | |
175 | * @wanted: The clock frequency wanted. | |
176 | */ | |
177 | static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, | |
178 | unsigned int src, | |
179 | unsigned int wanted) | |
180 | { | |
181 | unsigned long rate; | |
182 | struct clk *clksrc = ourhost->clk_bus[src]; | |
8880a4a5 | 183 | int shift; |
0d1bb41a | 184 | |
8f4b78d9 | 185 | if (IS_ERR(clksrc)) |
0d1bb41a BD |
186 | return UINT_MAX; |
187 | ||
253e0a7c | 188 | /* |
3119936a TA |
189 | * If controller uses a non-standard clock division, find the best clock |
190 | * speed possible with selected clock source and skip the division. | |
253e0a7c | 191 | */ |
1771059c | 192 | if (ourhost->no_divider) { |
253e0a7c JS |
193 | rate = clk_round_rate(clksrc, wanted); |
194 | return wanted - rate; | |
195 | } | |
196 | ||
6eb28bdc | 197 | rate = ourhost->clk_rates[src]; |
0d1bb41a | 198 | |
22003000 | 199 | for (shift = 0; shift <= 8; ++shift) { |
8880a4a5 | 200 | if ((rate >> shift) <= wanted) |
0d1bb41a BD |
201 | break; |
202 | } | |
22003000 TF |
203 | |
204 | if (shift > 8) { | |
205 | dev_dbg(&ourhost->pdev->dev, | |
206 | "clk %d: rate %ld, min rate %lu > wanted %u\n", | |
207 | src, rate, rate / 256, wanted); | |
208 | return UINT_MAX; | |
209 | } | |
0d1bb41a BD |
210 | |
211 | dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n", | |
8880a4a5 | 212 | src, rate, wanted, rate >> shift); |
0d1bb41a | 213 | |
8880a4a5 | 214 | return wanted - (rate >> shift); |
0d1bb41a BD |
215 | } |
216 | ||
217 | /** | |
218 | * sdhci_s3c_set_clock - callback on clock change | |
219 | * @host: The SDHCI host being changed | |
220 | * @clock: The clock rate being requested. | |
221 | * | |
222 | * When the card's clock is going to be changed, look at the new frequency | |
223 | * and find the best clock source to go with it. | |
224 | */ | |
225 | static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) | |
226 | { | |
227 | struct sdhci_s3c *ourhost = to_s3c(host); | |
228 | unsigned int best = UINT_MAX; | |
229 | unsigned int delta; | |
230 | int best_src = 0; | |
231 | int src; | |
232 | u32 ctrl; | |
233 | ||
1650d0c7 RK |
234 | host->mmc->actual_clock = 0; |
235 | ||
0d1bb41a | 236 | /* don't bother if the clock is going off. */ |
1771059c RK |
237 | if (clock == 0) { |
238 | sdhci_set_clock(host, clock); | |
0d1bb41a | 239 | return; |
1771059c | 240 | } |
0d1bb41a BD |
241 | |
242 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
243 | delta = sdhci_s3c_consider_clock(ourhost, src, clock); | |
244 | if (delta < best) { | |
245 | best = delta; | |
246 | best_src = src; | |
247 | } | |
248 | } | |
249 | ||
250 | dev_dbg(&ourhost->pdev->dev, | |
251 | "selected source %d, clock %d, delta %d\n", | |
252 | best_src, clock, best); | |
253 | ||
254 | /* select the new clock source */ | |
0d1bb41a BD |
255 | if (ourhost->cur_clk != best_src) { |
256 | struct clk *clk = ourhost->clk_bus[best_src]; | |
257 | ||
0f310a05 | 258 | clk_prepare_enable(clk); |
3ac147fa TF |
259 | if (ourhost->cur_clk >= 0) |
260 | clk_disable_unprepare( | |
261 | ourhost->clk_bus[ourhost->cur_clk]); | |
0d1bb41a BD |
262 | |
263 | ourhost->cur_clk = best_src; | |
6eb28bdc | 264 | host->max_clk = ourhost->clk_rates[best_src]; |
0d1bb41a BD |
265 | } |
266 | ||
3ac147fa TF |
267 | /* turn clock off to card before changing clock source */ |
268 | writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
269 | ||
270 | ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
271 | ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; | |
272 | ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; | |
273 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); | |
274 | ||
6fe47179 TA |
275 | /* reprogram default hardware configuration */ |
276 | writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, | |
277 | host->ioaddr + S3C64XX_SDHCI_CONTROL4); | |
278 | ||
279 | ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
280 | ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | | |
281 | S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | | |
282 | S3C_SDHCI_CTRL2_ENFBCLKRX | | |
283 | S3C_SDHCI_CTRL2_DFCNT_NONE | | |
284 | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); | |
285 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); | |
286 | ||
287 | /* reconfigure the controller for new clock rate */ | |
288 | ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); | |
289 | if (clock < 25 * 1000000) | |
290 | ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); | |
291 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); | |
1771059c RK |
292 | |
293 | sdhci_set_clock(host, clock); | |
0d1bb41a BD |
294 | } |
295 | ||
ce5f036b MS |
296 | /** |
297 | * sdhci_s3c_get_min_clock - callback to get minimal supported clock value | |
298 | * @host: The SDHCI host being queried | |
299 | * | |
300 | * To init mmc host properly a minimal clock value is needed. For high system | |
301 | * bus clock's values the standard formula gives values out of allowed range. | |
302 | * The clock still can be set to lower values, if clock source other then | |
303 | * system bus is selected. | |
304 | */ | |
305 | static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host) | |
306 | { | |
307 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 | 308 | unsigned long rate, min = ULONG_MAX; |
ce5f036b MS |
309 | int src; |
310 | ||
311 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
222a13c5 TF |
312 | rate = ourhost->clk_rates[src] / 256; |
313 | if (!rate) | |
ce5f036b | 314 | continue; |
222a13c5 TF |
315 | if (rate < min) |
316 | min = rate; | |
ce5f036b | 317 | } |
222a13c5 | 318 | |
ce5f036b MS |
319 | return min; |
320 | } | |
321 | ||
253e0a7c JS |
322 | /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/ |
323 | static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host) | |
324 | { | |
325 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
326 | unsigned long rate, max = 0; |
327 | int src; | |
328 | ||
329 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
330 | struct clk *clk; | |
331 | ||
332 | clk = ourhost->clk_bus[src]; | |
333 | if (IS_ERR(clk)) | |
334 | continue; | |
335 | ||
336 | rate = clk_round_rate(clk, ULONG_MAX); | |
337 | if (rate > max) | |
338 | max = rate; | |
339 | } | |
253e0a7c | 340 | |
222a13c5 | 341 | return max; |
253e0a7c JS |
342 | } |
343 | ||
344 | /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */ | |
345 | static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host) | |
346 | { | |
347 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
348 | unsigned long rate, min = ULONG_MAX; |
349 | int src; | |
253e0a7c | 350 | |
222a13c5 TF |
351 | for (src = 0; src < MAX_BUS_CLK; src++) { |
352 | struct clk *clk; | |
353 | ||
354 | clk = ourhost->clk_bus[src]; | |
355 | if (IS_ERR(clk)) | |
356 | continue; | |
357 | ||
358 | rate = clk_round_rate(clk, 0); | |
359 | if (rate < min) | |
360 | min = rate; | |
361 | } | |
362 | ||
363 | return min; | |
253e0a7c JS |
364 | } |
365 | ||
366 | /* sdhci_cmu_set_clock - callback on clock change.*/ | |
367 | static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) | |
368 | { | |
369 | struct sdhci_s3c *ourhost = to_s3c(host); | |
2ad0b249 | 370 | struct device *dev = &ourhost->pdev->dev; |
3119936a TA |
371 | unsigned long timeout; |
372 | u16 clk = 0; | |
cd0cfdd2 | 373 | int ret; |
253e0a7c | 374 | |
1650d0c7 RK |
375 | host->mmc->actual_clock = 0; |
376 | ||
7ef2a5e2 JC |
377 | /* If the clock is going off, set to 0 at clock control register */ |
378 | if (clock == 0) { | |
379 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | |
253e0a7c | 380 | return; |
7ef2a5e2 | 381 | } |
253e0a7c JS |
382 | |
383 | sdhci_s3c_set_clock(host, clock); | |
384 | ||
017210d1 PO |
385 | /* Reset SD Clock Enable */ |
386 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
387 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
388 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
389 | ||
cd0cfdd2 MB |
390 | ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); |
391 | if (ret != 0) { | |
392 | dev_err(dev, "%s: failed to set clock rate %uHz\n", | |
393 | mmc_hostname(host->mmc), clock); | |
394 | return; | |
395 | } | |
253e0a7c | 396 | |
3119936a TA |
397 | clk = SDHCI_CLOCK_INT_EN; |
398 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
399 | ||
400 | /* Wait max 20 ms */ | |
401 | timeout = 20; | |
402 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) | |
403 | & SDHCI_CLOCK_INT_STABLE)) { | |
404 | if (timeout == 0) { | |
2ad0b249 JH |
405 | dev_err(dev, "%s: Internal clock never stabilised.\n", |
406 | mmc_hostname(host->mmc)); | |
3119936a TA |
407 | return; |
408 | } | |
409 | timeout--; | |
410 | mdelay(1); | |
411 | } | |
412 | ||
413 | clk |= SDHCI_CLOCK_CARD_EN; | |
414 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
253e0a7c JS |
415 | } |
416 | ||
0d1bb41a BD |
417 | static struct sdhci_ops sdhci_s3c_ops = { |
418 | .get_max_clock = sdhci_s3c_get_max_clk, | |
0d1bb41a | 419 | .set_clock = sdhci_s3c_set_clock, |
ce5f036b | 420 | .get_min_clock = sdhci_s3c_get_min_clock, |
5b7f5eaf | 421 | .set_bus_width = sdhci_set_bus_width, |
03231f9b | 422 | .reset = sdhci_reset, |
96d7b78c | 423 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
0d1bb41a BD |
424 | }; |
425 | ||
cd1b00eb | 426 | #ifdef CONFIG_OF |
c3be1efd | 427 | static int sdhci_s3c_parse_dt(struct device *dev, |
cd1b00eb TA |
428 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) |
429 | { | |
430 | struct device_node *node = dev->of_node; | |
cd1b00eb | 431 | u32 max_width; |
cd1b00eb TA |
432 | |
433 | /* if the bus-width property is not specified, assume width as 1 */ | |
434 | if (of_property_read_u32(node, "bus-width", &max_width)) | |
435 | max_width = 1; | |
436 | pdata->max_width = max_width; | |
437 | ||
cd1b00eb | 438 | /* get the card detection method */ |
ab5023ef | 439 | if (of_get_property(node, "broken-cd", NULL)) { |
cd1b00eb | 440 | pdata->cd_type = S3C_SDHCI_CD_NONE; |
e19499ae | 441 | return 0; |
cd1b00eb TA |
442 | } |
443 | ||
ab5023ef | 444 | if (of_get_property(node, "non-removable", NULL)) { |
cd1b00eb | 445 | pdata->cd_type = S3C_SDHCI_CD_PERMANENT; |
e19499ae | 446 | return 0; |
cd1b00eb TA |
447 | } |
448 | ||
11bc9381 | 449 | if (of_get_named_gpio(node, "cd-gpios", 0)) |
b96efccb | 450 | return 0; |
cd1b00eb | 451 | |
e19499ae TA |
452 | /* assuming internal card detect that will be configured by pinctrl */ |
453 | pdata->cd_type = S3C_SDHCI_CD_INTERNAL; | |
cd1b00eb | 454 | return 0; |
cd1b00eb TA |
455 | } |
456 | #else | |
c3be1efd | 457 | static int sdhci_s3c_parse_dt(struct device *dev, |
cd1b00eb TA |
458 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) |
459 | { | |
460 | return -EINVAL; | |
461 | } | |
462 | #endif | |
463 | ||
464 | static const struct of_device_id sdhci_s3c_dt_match[]; | |
465 | ||
3119936a TA |
466 | static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data( |
467 | struct platform_device *pdev) | |
468 | { | |
cd1b00eb TA |
469 | #ifdef CONFIG_OF |
470 | if (pdev->dev.of_node) { | |
471 | const struct of_device_id *match; | |
472 | match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node); | |
473 | return (struct sdhci_s3c_drv_data *)match->data; | |
474 | } | |
475 | #endif | |
3119936a TA |
476 | return (struct sdhci_s3c_drv_data *) |
477 | platform_get_device_id(pdev)->driver_data; | |
478 | } | |
479 | ||
c3be1efd | 480 | static int sdhci_s3c_probe(struct platform_device *pdev) |
0d1bb41a | 481 | { |
1d4dc338 | 482 | struct s3c_sdhci_platdata *pdata; |
3119936a | 483 | struct sdhci_s3c_drv_data *drv_data; |
0d1bb41a BD |
484 | struct device *dev = &pdev->dev; |
485 | struct sdhci_host *host; | |
486 | struct sdhci_s3c *sc; | |
487 | struct resource *res; | |
488 | int ret, irq, ptr, clks; | |
489 | ||
cd1b00eb | 490 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
0d1bb41a BD |
491 | dev_err(dev, "no device data specified\n"); |
492 | return -ENOENT; | |
493 | } | |
494 | ||
495 | irq = platform_get_irq(pdev, 0); | |
496 | if (irq < 0) { | |
497 | dev_err(dev, "no irq specified\n"); | |
498 | return irq; | |
499 | } | |
500 | ||
0d1bb41a BD |
501 | host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); |
502 | if (IS_ERR(host)) { | |
503 | dev_err(dev, "sdhci_alloc_host() failed\n"); | |
504 | return PTR_ERR(host); | |
505 | } | |
cd1b00eb | 506 | sc = sdhci_priv(host); |
0d1bb41a | 507 | |
1d4dc338 TA |
508 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
509 | if (!pdata) { | |
510 | ret = -ENOMEM; | |
b1b8fea9 | 511 | goto err_pdata_io_clk; |
cd1b00eb TA |
512 | } |
513 | ||
514 | if (pdev->dev.of_node) { | |
515 | ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata); | |
516 | if (ret) | |
b1b8fea9 | 517 | goto err_pdata_io_clk; |
cd1b00eb TA |
518 | } else { |
519 | memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); | |
520 | sc->ext_cd_gpio = -1; /* invalid gpio number */ | |
1d4dc338 | 521 | } |
1d4dc338 | 522 | |
3119936a | 523 | drv_data = sdhci_s3c_get_driver_data(pdev); |
0d1bb41a BD |
524 | |
525 | sc->host = host; | |
526 | sc->pdev = pdev; | |
527 | sc->pdata = pdata; | |
3ac147fa | 528 | sc->cur_clk = -1; |
0d1bb41a BD |
529 | |
530 | platform_set_drvdata(pdev, host); | |
531 | ||
3aaf7ba7 | 532 | sc->clk_io = devm_clk_get(dev, "hsmmc"); |
0d1bb41a BD |
533 | if (IS_ERR(sc->clk_io)) { |
534 | dev_err(dev, "failed to get io clock\n"); | |
535 | ret = PTR_ERR(sc->clk_io); | |
b1b8fea9 | 536 | goto err_pdata_io_clk; |
0d1bb41a BD |
537 | } |
538 | ||
539 | /* enable the local io clock and keep it running for the moment. */ | |
0f310a05 | 540 | clk_prepare_enable(sc->clk_io); |
0d1bb41a BD |
541 | |
542 | for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { | |
4346b6d9 | 543 | char name[14]; |
0d1bb41a | 544 | |
4346b6d9 | 545 | snprintf(name, 14, "mmc_busclk.%d", ptr); |
8f4b78d9 TF |
546 | sc->clk_bus[ptr] = devm_clk_get(dev, name); |
547 | if (IS_ERR(sc->clk_bus[ptr])) | |
0d1bb41a | 548 | continue; |
0d1bb41a BD |
549 | |
550 | clks++; | |
6eb28bdc TF |
551 | sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]); |
552 | ||
0d1bb41a | 553 | dev_info(dev, "clock source %d: %s (%ld Hz)\n", |
6eb28bdc | 554 | ptr, name, sc->clk_rates[ptr]); |
0d1bb41a BD |
555 | } |
556 | ||
557 | if (clks == 0) { | |
558 | dev_err(dev, "failed to find any bus clocks\n"); | |
559 | ret = -ENOENT; | |
560 | goto err_no_busclks; | |
561 | } | |
562 | ||
9bda6da7 | 563 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a3e2cd7f TR |
564 | host->ioaddr = devm_ioremap_resource(&pdev->dev, res); |
565 | if (IS_ERR(host->ioaddr)) { | |
566 | ret = PTR_ERR(host->ioaddr); | |
0d1bb41a BD |
567 | goto err_req_regs; |
568 | } | |
569 | ||
570 | /* Ensure we have minimal gpio selected CMD/CLK/Detect */ | |
571 | if (pdata->cfg_gpio) | |
572 | pdata->cfg_gpio(pdev, pdata->max_width); | |
573 | ||
574 | host->hw_name = "samsung-hsmmc"; | |
575 | host->ops = &sdhci_s3c_ops; | |
576 | host->quirks = 0; | |
285e244f | 577 | host->quirks2 = 0; |
0d1bb41a BD |
578 | host->irq = irq; |
579 | ||
580 | /* Setup quirks for the controller */ | |
b2e75eff | 581 | host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; |
a1d56460 | 582 | host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; |
1771059c | 583 | if (drv_data) { |
3119936a | 584 | host->quirks |= drv_data->sdhci_quirks; |
1771059c RK |
585 | sc->no_divider = drv_data->no_divider; |
586 | } | |
0d1bb41a BD |
587 | |
588 | #ifndef CONFIG_MMC_SDHCI_S3C_DMA | |
589 | ||
590 | /* we currently see overruns on errors, so disable the SDMA | |
591 | * support as well. */ | |
592 | host->quirks |= SDHCI_QUIRK_BROKEN_DMA; | |
593 | ||
594 | #endif /* CONFIG_MMC_SDHCI_S3C_DMA */ | |
595 | ||
596 | /* It seems we do not get an DATA transfer complete on non-busy | |
597 | * transfers, not sure if this is a problem with this specific | |
598 | * SDHCI block, or a missing configuration that needs to be set. */ | |
599 | host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ; | |
600 | ||
732f0e31 KP |
601 | /* This host supports the Auto CMD12 */ |
602 | host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; | |
603 | ||
7199e2b6 JC |
604 | /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */ |
605 | host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC; | |
606 | ||
17866e14 MS |
607 | if (pdata->cd_type == S3C_SDHCI_CD_NONE || |
608 | pdata->cd_type == S3C_SDHCI_CD_PERMANENT) | |
609 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
610 | ||
611 | if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT) | |
612 | host->mmc->caps = MMC_CAP_NONREMOVABLE; | |
613 | ||
0d22c770 TA |
614 | switch (pdata->max_width) { |
615 | case 8: | |
616 | host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
617 | case 4: | |
618 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; | |
619 | break; | |
620 | } | |
621 | ||
fa1773cc SL |
622 | if (pdata->pm_caps) |
623 | host->mmc->pm_caps |= pdata->pm_caps; | |
624 | ||
0d1bb41a BD |
625 | host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR | |
626 | SDHCI_QUIRK_32BIT_DMA_SIZE); | |
627 | ||
3fe42e07 HL |
628 | /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ |
629 | host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; | |
630 | ||
253e0a7c JS |
631 | /* |
632 | * If controller does not have internal clock divider, | |
633 | * we can use overriding functions instead of default. | |
634 | */ | |
1771059c | 635 | if (sc->no_divider) { |
253e0a7c JS |
636 | sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; |
637 | sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; | |
638 | sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; | |
639 | } | |
640 | ||
b3824f2c JS |
641 | /* It supports additional host capabilities if needed */ |
642 | if (pdata->host_caps) | |
643 | host->mmc->caps |= pdata->host_caps; | |
644 | ||
c1c4b66d JC |
645 | if (pdata->host_caps2) |
646 | host->mmc->caps2 |= pdata->host_caps2; | |
647 | ||
9f4e8151 MB |
648 | pm_runtime_enable(&pdev->dev); |
649 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); | |
650 | pm_runtime_use_autosuspend(&pdev->dev); | |
651 | pm_suspend_ignore_children(&pdev->dev, 1); | |
652 | ||
f8e3260c UH |
653 | ret = mmc_of_parse(host->mmc); |
654 | if (ret) | |
655 | goto err_req_regs; | |
11bc9381 | 656 | |
0d1bb41a | 657 | ret = sdhci_add_host(host); |
fb8617e1 | 658 | if (ret) |
9bda6da7 | 659 | goto err_req_regs; |
0d1bb41a | 660 | |
162d6f98 | 661 | #ifdef CONFIG_PM |
0aa55c23 SJ |
662 | if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) |
663 | clk_disable_unprepare(sc->clk_io); | |
2abeb5c5 | 664 | #endif |
0d1bb41a BD |
665 | return 0; |
666 | ||
0d1bb41a | 667 | err_req_regs: |
221414db BZ |
668 | pm_runtime_disable(&pdev->dev); |
669 | ||
0d1bb41a | 670 | err_no_busclks: |
0f310a05 | 671 | clk_disable_unprepare(sc->clk_io); |
0d1bb41a | 672 | |
b1b8fea9 | 673 | err_pdata_io_clk: |
0d1bb41a BD |
674 | sdhci_free_host(host); |
675 | ||
676 | return ret; | |
677 | } | |
678 | ||
6e0ee714 | 679 | static int sdhci_s3c_remove(struct platform_device *pdev) |
0d1bb41a | 680 | { |
9d51a6b2 MS |
681 | struct sdhci_host *host = platform_get_drvdata(pdev); |
682 | struct sdhci_s3c *sc = sdhci_priv(host); | |
17866e14 MS |
683 | |
684 | if (sc->ext_cd_irq) | |
685 | free_irq(sc->ext_cd_irq, sc); | |
686 | ||
162d6f98 | 687 | #ifdef CONFIG_PM |
11bc9381 | 688 | if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL) |
0aa55c23 | 689 | clk_prepare_enable(sc->clk_io); |
2abeb5c5 | 690 | #endif |
9d51a6b2 MS |
691 | sdhci_remove_host(host, 1); |
692 | ||
387a8cbd | 693 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
9f4e8151 MB |
694 | pm_runtime_disable(&pdev->dev); |
695 | ||
0f310a05 | 696 | clk_disable_unprepare(sc->clk_io); |
9d51a6b2 | 697 | |
9d51a6b2 | 698 | sdhci_free_host(host); |
9d51a6b2 | 699 | |
0d1bb41a BD |
700 | return 0; |
701 | } | |
702 | ||
d5e9c02c | 703 | #ifdef CONFIG_PM_SLEEP |
29495aa0 | 704 | static int sdhci_s3c_suspend(struct device *dev) |
0d1bb41a | 705 | { |
29495aa0 | 706 | struct sdhci_host *host = dev_get_drvdata(dev); |
0d1bb41a | 707 | |
d38dcad4 AH |
708 | if (host->tuning_mode != SDHCI_TUNING_MODE_3) |
709 | mmc_retune_needed(host->mmc); | |
710 | ||
29495aa0 | 711 | return sdhci_suspend_host(host); |
0d1bb41a BD |
712 | } |
713 | ||
29495aa0 | 714 | static int sdhci_s3c_resume(struct device *dev) |
0d1bb41a | 715 | { |
29495aa0 | 716 | struct sdhci_host *host = dev_get_drvdata(dev); |
0d1bb41a | 717 | |
65d13516 | 718 | return sdhci_resume_host(host); |
0d1bb41a | 719 | } |
d5e9c02c | 720 | #endif |
0d1bb41a | 721 | |
162d6f98 | 722 | #ifdef CONFIG_PM |
9f4e8151 MB |
723 | static int sdhci_s3c_runtime_suspend(struct device *dev) |
724 | { | |
725 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2abeb5c5 CK |
726 | struct sdhci_s3c *ourhost = to_s3c(host); |
727 | struct clk *busclk = ourhost->clk_io; | |
728 | int ret; | |
729 | ||
730 | ret = sdhci_runtime_suspend_host(host); | |
9f4e8151 | 731 | |
d38dcad4 AH |
732 | if (host->tuning_mode != SDHCI_TUNING_MODE_3) |
733 | mmc_retune_needed(host->mmc); | |
734 | ||
3ac147fa TF |
735 | if (ourhost->cur_clk >= 0) |
736 | clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]); | |
0f310a05 | 737 | clk_disable_unprepare(busclk); |
2abeb5c5 | 738 | return ret; |
9f4e8151 MB |
739 | } |
740 | ||
741 | static int sdhci_s3c_runtime_resume(struct device *dev) | |
742 | { | |
743 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2abeb5c5 CK |
744 | struct sdhci_s3c *ourhost = to_s3c(host); |
745 | struct clk *busclk = ourhost->clk_io; | |
746 | int ret; | |
9f4e8151 | 747 | |
0f310a05 | 748 | clk_prepare_enable(busclk); |
3ac147fa TF |
749 | if (ourhost->cur_clk >= 0) |
750 | clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]); | |
2abeb5c5 CK |
751 | ret = sdhci_runtime_resume_host(host); |
752 | return ret; | |
9f4e8151 MB |
753 | } |
754 | #endif | |
755 | ||
29495aa0 | 756 | static const struct dev_pm_ops sdhci_s3c_pmops = { |
d5e9c02c | 757 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume) |
9f4e8151 MB |
758 | SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume, |
759 | NULL) | |
29495aa0 ML |
760 | }; |
761 | ||
4d0aa491 | 762 | static const struct platform_device_id sdhci_s3c_driver_ids[] = { |
3119936a TA |
763 | { |
764 | .name = "s3c-sdhci", | |
765 | .driver_data = (kernel_ulong_t)NULL, | |
3119936a TA |
766 | }, |
767 | { } | |
768 | }; | |
769 | MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids); | |
770 | ||
cd1b00eb | 771 | #ifdef CONFIG_OF |
3a8e9cad MS |
772 | static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { |
773 | .no_divider = true, | |
774 | }; | |
775 | ||
cd1b00eb TA |
776 | static const struct of_device_id sdhci_s3c_dt_match[] = { |
777 | { .compatible = "samsung,s3c6410-sdhci", }, | |
778 | { .compatible = "samsung,exynos4210-sdhci", | |
3a8e9cad | 779 | .data = &exynos4_sdhci_drv_data }, |
cd1b00eb TA |
780 | {}, |
781 | }; | |
782 | MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match); | |
783 | #endif | |
784 | ||
0d1bb41a BD |
785 | static struct platform_driver sdhci_s3c_driver = { |
786 | .probe = sdhci_s3c_probe, | |
0433c143 | 787 | .remove = sdhci_s3c_remove, |
3119936a | 788 | .id_table = sdhci_s3c_driver_ids, |
0d1bb41a | 789 | .driver = { |
0d1bb41a | 790 | .name = "s3c-sdhci", |
cd1b00eb | 791 | .of_match_table = of_match_ptr(sdhci_s3c_dt_match), |
6b3a194b | 792 | .pm = &sdhci_s3c_pmops, |
0d1bb41a BD |
793 | }, |
794 | }; | |
795 | ||
d1f81a64 | 796 | module_platform_driver(sdhci_s3c_driver); |
0d1bb41a BD |
797 | |
798 | MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue"); | |
799 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
800 | MODULE_LICENSE("GPL v2"); | |
801 | MODULE_ALIAS("platform:s3c-sdhci"); |