[linux-2.6-block.git] / drivers / mmc / host / sdhci-pxav3.c

/*
 * Copyright (C) 2010 Marvell International Ltd.
 *		Zhangfei Gao <zhangfei.gao@marvell.com>
 *		Kevin Wang <dwang4@marvell.com>
 *		Mingwei Wang <mwwang@marvell.com>
 *		Philip Rakity <prakity@marvell.com>
 *		Mark Brown <markb@marvell.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/platform_data/pxa_sdhci.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>

#include "sdhci.h"
#include "sdhci-pltfm.h"

#define SD_CLOCK_BURST_SIZE_SETUP		0x10A
#define SDCLK_SEL	0x100
#define SDCLK_DELAY_SHIFT	9
#define SDCLK_DELAY_MASK	0x1f

#define SD_CFG_FIFO_PARAM       0x100
#define SDCFG_GEN_PAD_CLK_ON	(1<<6)
#define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
#define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24

#define SD_SPI_MODE          0x108
#define SD_CE_ATA_1          0x10C

#define SD_CE_ATA_2          0x10E
#define SDCE_MISC_INT		(1<<2)
#define SDCE_MISC_INT_EN	(1<<1)

static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
{
	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;

	if (mask == SDHCI_RESET_ALL) {
		/*
		 * tune timing of read data/command when crc error happen
		 * no performance impact
		 */
		if (pdata && 0 != pdata->clk_delay_cycles) {
			u16 tmp;

			tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
			tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
				<< SDCLK_DELAY_SHIFT;
			tmp |= SDCLK_SEL;
			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
		}
	}
}

#define MAX_WAIT_COUNT 5
static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;
	u16 tmp;
	int count;

	if (pxa->power_mode == MMC_POWER_UP
			&& power_mode == MMC_POWER_ON) {

		dev_dbg(mmc_dev(host->mmc),
				"%s: slot->power_mode = %d,"
				"ios->power_mode = %d\n",
				__func__,
				pxa->power_mode,
				power_mode);

		/* set we want notice of when 74 clocks are sent */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT_EN;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);

		/* start sending the 74 clocks */
		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
		tmp |= SDCFG_GEN_PAD_CLK_ON;
		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);

		/* slowest speed is about 100KHz or 10usec per clock */
		udelay(740);
		count = 0;

		while (count++ < MAX_WAIT_COUNT) {
			if ((readw(host->ioaddr + SD_CE_ATA_2)
						& SDCE_MISC_INT) == 0)
				break;
			udelay(10);
		}

		if (count == MAX_WAIT_COUNT)
			dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");

		/* clear the interrupt bit if posted */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);
	}
	pxa->power_mode = power_mode;
}

static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
{
	u16 ctrl_2;

	/*
	 * Set V18_EN -- UHS modes do not work without this.
	 * does not change signaling voltage
	 */
	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/* Select Bus Speed Mode for host */
	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	switch (uhs) {
	case MMC_TIMING_UHS_SDR12:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
		break;
	case MMC_TIMING_UHS_SDR25:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
		break;
	case MMC_TIMING_UHS_SDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_SDR104:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_DDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
		break;
	}

	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	dev_dbg(mmc_dev(host->mmc),
		"%s uhs = %d, ctrl_2 = %04X\n",
		__func__, uhs, ctrl_2);

	return 0;
}

static struct sdhci_ops pxav3_sdhci_ops = {
	.platform_reset_exit = pxav3_set_private_registers,
	.set_uhs_signaling = pxav3_set_uhs_signaling,
	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
};

#ifdef CONFIG_OF
static const struct of_device_id sdhci_pxav3_of_match[] = {
	{
		.compatible = "mrvl,pxav3-mmc",
	},
	{},
};
MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);

static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	struct sdhci_pxa_platdata *pdata;
	struct device_node *np = dev->of_node;
	u32 bus_width;
	u32 clk_delay_cycles;

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	if (of_find_property(np, "non-removable", NULL))
		pdata->flags |= PXA_FLAG_CARD_PERMANENT;

	of_property_read_u32(np, "bus-width", &bus_width);
	if (bus_width == 8)
		pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;

	of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
	if (clk_delay_cycles > 0)
		pdata->clk_delay_cycles = clk_delay_cycles;

	return pdata;
}
#else
static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	return NULL;
}
#endif

static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
{
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	struct device *dev = &pdev->dev;
	struct sdhci_host *host = NULL;
	struct sdhci_pxa *pxa = NULL;
	const struct of_device_id *match;

	int ret;
	struct clk *clk;

	pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
	if (!pxa)
		return -ENOMEM;

	host = sdhci_pltfm_init(pdev, NULL);
	if (IS_ERR(host)) {
		kfree(pxa);
		return PTR_ERR(host);
	}
	pltfm_host = sdhci_priv(host);
	pltfm_host->priv = pxa;

	clk = clk_get(dev, "PXA-SDHCLK");
	if (IS_ERR(clk)) {
		dev_err(dev, "failed to get io clock\n");
		ret = PTR_ERR(clk);
		goto err_clk_get;
	}
	pltfm_host->clk = clk;
	clk_enable(clk);

	host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
		| SDHCI_QUIRK_32BIT_ADMA_SIZE;

	/* enable 1/8V DDR capable */
	host->mmc->caps |= MMC_CAP_1_8V_DDR;

	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
	if (match)
		pdata = pxav3_get_mmc_pdata(dev);

	if (pdata) {
		if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
			/* on-chip device */
			host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
			host->mmc->caps |= MMC_CAP_NONREMOVABLE;
		}

		/* If slot design supports 8 bit data, indicate this to MMC. */
		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
			host->mmc->caps |= MMC_CAP_8_BIT_DATA;

		if (pdata->quirks)
			host->quirks |= pdata->quirks;
		if (pdata->host_caps)
			host->mmc->caps |= pdata->host_caps;
		if (pdata->pm_caps)
			host->mmc->pm_caps |= pdata->pm_caps;
	}

	host->ops = &pxav3_sdhci_ops;

	ret = sdhci_add_host(host);
	if (ret) {
		dev_err(&pdev->dev, "failed to add host\n");
		goto err_add_host;
	}

	platform_set_drvdata(pdev, host);

	return 0;

err_add_host:
	clk_disable(clk);
	clk_put(clk);
err_clk_get:
	sdhci_pltfm_free(pdev);
	kfree(pxa);
	return ret;
}

static int __devexit sdhci_pxav3_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = pltfm_host->priv;

	sdhci_remove_host(host, 1);

	clk_disable(pltfm_host->clk);
	clk_put(pltfm_host->clk);
	sdhci_pltfm_free(pdev);
	kfree(pxa);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static struct platform_driver sdhci_pxav3_driver = {
	.driver		= {
		.name	= "sdhci-pxav3",
#ifdef CONFIG_OF
		.of_match_table = sdhci_pxav3_of_match,
#endif
		.owner	= THIS_MODULE,
		.pm	= SDHCI_PLTFM_PMOPS,
	},
	.probe		= sdhci_pxav3_probe,
	.remove		= __devexit_p(sdhci_pxav3_remove),
};

module_platform_driver(sdhci_pxav3_driver);

MODULE_DESCRIPTION("SDHCI driver for pxav3");
MODULE_AUTHOR("Marvell International Ltd.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a702c8ab ZG	1	/*
	2	* Copyright (C) 2010 Marvell International Ltd.
	3	* Zhangfei Gao <zhangfei.gao@marvell.com>
	4	* Kevin Wang <dwang4@marvell.com>
	5	* Mingwei Wang <mwwang@marvell.com>
	6	* Philip Rakity <prakity@marvell.com>
	7	* Mark Brown <markb@marvell.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19	#include <linux/err.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/clk.h>
	23	#include <linux/io.h>
	24	#include <linux/gpio.h>
	25	#include <linux/mmc/card.h>
	26	#include <linux/mmc/host.h>
bfed345e	27	#include <linux/platform_data/pxa_sdhci.h>
a702c8ab ZG	28	#include <linux/slab.h>
a702c8ab ZG	29	#include <linux/delay.h>
88b47679	30	#include <linux/module.h>
b650352d CB	31	#include <linux/of.h>
	32	#include <linux/of_device.h>
	33
a702c8ab ZG	34	#include "sdhci.h"
	35	#include "sdhci-pltfm.h"
	36
	37	#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
	38	#define SDCLK_SEL 0x100
	39	#define SDCLK_DELAY_SHIFT 9
	40	#define SDCLK_DELAY_MASK 0x1f
	41
	42	#define SD_CFG_FIFO_PARAM 0x100
	43	#define SDCFG_GEN_PAD_CLK_ON (1<<6)
	44	#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
	45	#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
	46
	47	#define SD_SPI_MODE 0x108
	48	#define SD_CE_ATA_1 0x10C
	49
	50	#define SD_CE_ATA_2 0x10E
	51	#define SDCE_MISC_INT (1<<2)
	52	#define SDCE_MISC_INT_EN (1<<1)
	53
	54	static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
	55	{
	56	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	57	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	58
	59	if (mask == SDHCI_RESET_ALL) {
	60	/*
	61	* tune timing of read data/command when crc error happen
	62	* no performance impact
	63	*/
	64	if (pdata && 0 != pdata->clk_delay_cycles) {
	65	u16 tmp;
	66
	67	tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	68	tmp \|= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
	69	<< SDCLK_DELAY_SHIFT;
	70	tmp \|= SDCLK_SEL;
	71	writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	72	}
	73	}
	74	}
	75
	76	#define MAX_WAIT_COUNT 5
	77	static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
	78	{
	79	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	80	struct sdhci_pxa *pxa = pltfm_host->priv;
	81	u16 tmp;
	82	int count;
	83
	84	if (pxa->power_mode == MMC_POWER_UP
	85	&& power_mode == MMC_POWER_ON) {
	86
	87	dev_dbg(mmc_dev(host->mmc),
	88	"%s: slot->power_mode = %d,"
	89	"ios->power_mode = %d\n",
	90	__func__,
	91	pxa->power_mode,
	92	power_mode);
	93
	94	/* set we want notice of when 74 clocks are sent */
	95	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	96	tmp \|= SDCE_MISC_INT_EN;
	97	writew(tmp, host->ioaddr + SD_CE_ATA_2);
98
99	/* start sending the 74 clocks */
100	tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
101	tmp \|= SDCFG_GEN_PAD_CLK_ON;
102	writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
103
104	/* slowest speed is about 100KHz or 10usec per clock */
105	udelay(740);
106	count = 0;
107
108	while (count++ < MAX_WAIT_COUNT) {
109	if ((readw(host->ioaddr + SD_CE_ATA_2)
110	& SDCE_MISC_INT) == 0)
111	break;
112	udelay(10);
113	}
114
115	if (count == MAX_WAIT_COUNT)
116	dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
117
118	/* clear the interrupt bit if posted */
119	tmp = readw(host->ioaddr + SD_CE_ATA_2);
120	tmp \|= SDCE_MISC_INT;
121	writew(tmp, host->ioaddr + SD_CE_ATA_2);
122	}
123	pxa->power_mode = power_mode;
124	}
125
126	static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
127	{
128	u16 ctrl_2;
129
130	/*
131	* Set V18_EN -- UHS modes do not work without this.
132	* does not change signaling voltage
133	*/
134	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
135
136	/* Select Bus Speed Mode for host */
137	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
138	switch (uhs) {
139	case MMC_TIMING_UHS_SDR12:
140	ctrl_2 \|= SDHCI_CTRL_UHS_SDR12;
141	break;
142	case MMC_TIMING_UHS_SDR25:
143	ctrl_2 \|= SDHCI_CTRL_UHS_SDR25;
144	break;
145	case MMC_TIMING_UHS_SDR50:
146	ctrl_2 \|= SDHCI_CTRL_UHS_SDR50 \| SDHCI_CTRL_VDD_180;
147	break;
148	case MMC_TIMING_UHS_SDR104:
149	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104 \| SDHCI_CTRL_VDD_180;
150	break;
151	case MMC_TIMING_UHS_DDR50:
152	ctrl_2 \|= SDHCI_CTRL_UHS_DDR50 \| SDHCI_CTRL_VDD_180;
153	break;
154	}
155
156	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
157	dev_dbg(mmc_dev(host->mmc),
158	"%s uhs = %d, ctrl_2 = %04X\n",
159	__func__, uhs, ctrl_2);
160
161	return 0;
162	}
163
164	static struct sdhci_ops pxav3_sdhci_ops = {
165	.platform_reset_exit = pxav3_set_private_registers,
166	.set_uhs_signaling = pxav3_set_uhs_signaling,
167	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
168	};
169
b650352d CB	170	#ifdef CONFIG_OF
	171	static const struct of_device_id sdhci_pxav3_of_match[] = {
	172	{
	173	.compatible = "mrvl,pxav3-mmc",
	174	},
	175	{},
	176	};
	177	MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
	178
	179	static struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	180	{
	181	struct sdhci_pxa_platdata *pdata;
	182	struct device_node *np = dev->of_node;
	183	u32 bus_width;
	184	u32 clk_delay_cycles;
	185
	186	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	187	if (!pdata)
	188	return NULL;
	189
	190	if (of_find_property(np, "non-removable", NULL))
	191	pdata->flags \|= PXA_FLAG_CARD_PERMANENT;
	192
	193	of_property_read_u32(np, "bus-width", &bus_width);
	194	if (bus_width == 8)
	195	pdata->flags \|= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
	196
	197	of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
	198	if (clk_delay_cycles > 0)
	199	pdata->clk_delay_cycles = clk_delay_cycles;
	200
	201	return pdata;
	202	}
	203	#else
	204	static inline struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	205	{
	206	return NULL;
	207	}
	208	#endif
	209
a702c8ab ZG	210	static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
	211	{
	212	struct sdhci_pltfm_host *pltfm_host;
	213	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	214	struct device *dev = &pdev->dev;
	215	struct sdhci_host *host = NULL;
	216	struct sdhci_pxa *pxa = NULL;
b650352d CB	217	const struct of_device_id *match;
b650352d CB	218
a702c8ab ZG	219	int ret;
	220	struct clk *clk;
	221
	222	pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
	223	if (!pxa)
	224	return -ENOMEM;
	225
	226	host = sdhci_pltfm_init(pdev, NULL);
	227	if (IS_ERR(host)) {
	228	kfree(pxa);
	229	return PTR_ERR(host);
	230	}
	231	pltfm_host = sdhci_priv(host);
	232	pltfm_host->priv = pxa;
	233
	234	clk = clk_get(dev, "PXA-SDHCLK");
	235	if (IS_ERR(clk)) {
	236	dev_err(dev, "failed to get io clock\n");
	237	ret = PTR_ERR(clk);
	238	goto err_clk_get;
	239	}
	240	pltfm_host->clk = clk;
	241	clk_enable(clk);
	242
	243	host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
606a15e4 PR	244	\| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
606a15e4 PR	245	\| SDHCI_QUIRK_32BIT_ADMA_SIZE;
a702c8ab ZG	246
	247	/* enable 1/8V DDR capable */
	248	host->mmc->caps \|= MMC_CAP_1_8V_DDR;
	249
b650352d CB	250	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
	251	if (match)
	252	pdata = pxav3_get_mmc_pdata(dev);
	253
a702c8ab ZG	254	if (pdata) {
	255	if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
	256	/* on-chip device */
	257	host->quirks \|= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
	258	host->mmc->caps \|= MMC_CAP_NONREMOVABLE;
	259	}
	260
	261	/* If slot design supports 8 bit data, indicate this to MMC. */
	262	if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
	263	host->mmc->caps \|= MMC_CAP_8_BIT_DATA;
	264
	265	if (pdata->quirks)
	266	host->quirks \|= pdata->quirks;
	267	if (pdata->host_caps)
	268	host->mmc->caps \|= pdata->host_caps;
	269	if (pdata->pm_caps)
	270	host->mmc->pm_caps \|= pdata->pm_caps;
	271	}
	272
	273	host->ops = &pxav3_sdhci_ops;
	274
	275	ret = sdhci_add_host(host);
	276	if (ret) {
	277	dev_err(&pdev->dev, "failed to add host\n");
	278	goto err_add_host;
	279	}
	280
	281	platform_set_drvdata(pdev, host);
	282
	283	return 0;
	284
	285	err_add_host:
	286	clk_disable(clk);
	287	clk_put(clk);
	288	err_clk_get:
	289	sdhci_pltfm_free(pdev);
	290	kfree(pxa);
	291	return ret;
	292	}
	293
	294	static int __devexit sdhci_pxav3_remove(struct platform_device *pdev)
	295	{
	296	struct sdhci_host *host = platform_get_drvdata(pdev);
	297	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	298	struct sdhci_pxa *pxa = pltfm_host->priv;
	299
	300	sdhci_remove_host(host, 1);
	301
	302	clk_disable(pltfm_host->clk);
	303	clk_put(pltfm_host->clk);
	304	sdhci_pltfm_free(pdev);
	305	kfree(pxa);
	306
	307	platform_set_drvdata(pdev, NULL);
	308
	309	return 0;
	310	}
	311
	312	static struct platform_driver sdhci_pxav3_driver = {
	313	.driver = {
	314	.name = "sdhci-pxav3",
b650352d CB	315	#ifdef CONFIG_OF
	316	.of_match_table = sdhci_pxav3_of_match,
	317	#endif
a702c8ab	318	.owner = THIS_MODULE,
29495aa0	319	.pm = SDHCI_PLTFM_PMOPS,
a702c8ab ZG	320	},
	321	.probe = sdhci_pxav3_probe,
	322	.remove = __devexit_p(sdhci_pxav3_remove),
a702c8ab	323	};
a702c8ab	324
d1f81a64	325	module_platform_driver(sdhci_pxav3_driver);
a702c8ab ZG	326
	327	MODULE_DESCRIPTION("SDHCI driver for pxav3");
	328	MODULE_AUTHOR("Marvell International Ltd.");
	329	MODULE_LICENSE("GPL v2");
	330