[linux-2.6-block.git] / drivers / mmc / host / sdhci-pxav3.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2010 Marvell International Ltd.
 *		Zhangfei Gao <zhangfei.gao@marvell.com>
 *		Kevin Wang <dwang4@marvell.com>
 *		Mingwei Wang <mwwang@marvell.com>
 *		Philip Rakity <prakity@marvell.com>
 *		Mark Brown <markb@marvell.com>
 */
#include <linux/err.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/platform_data/pxa_sdhci.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/mbus.h>

#include "sdhci.h"
#include "sdhci-pltfm.h"

#define PXAV3_RPM_DELAY_MS     50

#define SD_CLOCK_BURST_SIZE_SETUP		0x10A
#define SDCLK_SEL	0x100
#define SDCLK_DELAY_SHIFT	9
#define SDCLK_DELAY_MASK	0x1f

#define SD_CFG_FIFO_PARAM       0x100
#define SDCFG_GEN_PAD_CLK_ON	(1<<6)
#define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
#define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24

#define SD_SPI_MODE          0x108
#define SD_CE_ATA_1          0x10C

#define SD_CE_ATA_2          0x10E
#define SDCE_MISC_INT		(1<<2)
#define SDCE_MISC_INT_EN	(1<<1)

struct sdhci_pxa {
	struct clk *clk_core;
	struct clk *clk_io;
	u8	power_mode;
	void __iomem *sdio3_conf_reg;
};

/*
 * These registers are relative to the second register region, for the
 * MBus bridge.
 */
#define SDHCI_WINDOW_CTRL(i)	(0x80 + ((i) << 3))
#define SDHCI_WINDOW_BASE(i)	(0x84 + ((i) << 3))
#define SDHCI_MAX_WIN_NUM	8

/*
 * Fields below belong to SDIO3 Configuration Register (third register
 * region for the Armada 38x flavor)
 */

#define SDIO3_CONF_CLK_INV	BIT(0)
#define SDIO3_CONF_SD_FB_CLK	BIT(2)

static int mv_conf_mbus_windows(struct platform_device *pdev,
				const struct mbus_dram_target_info *dram)
{
	int i;
	void __iomem *regs;
	struct resource *res;

	if (!dram) {
		dev_err(&pdev->dev, "no mbus dram info\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		dev_err(&pdev->dev, "cannot get mbus registers\n");
		return -EINVAL;
	}

	regs = ioremap(res->start, resource_size(res));
	if (!regs) {
		dev_err(&pdev->dev, "cannot map mbus registers\n");
		return -ENOMEM;
	}

	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
		writel(0, regs + SDHCI_WINDOW_CTRL(i));
		writel(0, regs + SDHCI_WINDOW_BASE(i));
	}

	for (i = 0; i < dram->num_cs; i++) {
		const struct mbus_dram_window *cs = dram->cs + i;

		/* Write size, attributes and target id to control register */
		writel(((cs->size - 1) & 0xffff0000) |
			(cs->mbus_attr << 8) |
			(dram->mbus_dram_target_id << 4) | 1,
			regs + SDHCI_WINDOW_CTRL(i));
		/* Write base address to base register */
		writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
	}

	iounmap(regs);

	return 0;
}

static int armada_38x_quirks(struct platform_device *pdev,
			     struct sdhci_host *host)
{
	struct device_node *np = pdev->dev.of_node;
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
	struct resource *res;

	host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
	host->quirks |= SDHCI_QUIRK_MISSING_CAPS;

	host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
					   "conf-sdio3");
	if (res) {
		pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(pxa->sdio3_conf_reg))
			return PTR_ERR(pxa->sdio3_conf_reg);
	} else {
		/*
		 * According to erratum 'FE-2946959' both SDR50 and DDR50
		 * modes require specific clock adjustments in SDIO3
		 * Configuration register, if the adjustment is not done,
		 * remove them from the capabilities.
		 */
		host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);

		dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n");
	}

	/*
	 * According to erratum 'ERR-7878951' Armada 38x SDHCI
	 * controller has different capabilities than the ones shown
	 * in its registers
	 */
	if (of_property_read_bool(np, "no-1-8-v")) {
		host->caps &= ~SDHCI_CAN_VDD_180;
		host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
	} else {
		host->caps &= ~SDHCI_CAN_VDD_330;
	}
	host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);

	return 0;
}

static void pxav3_reset(struct sdhci_host *host, u8 mask)
{
	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;

	sdhci_reset(host, mask);

	if (mask == SDHCI_RESET_ALL) {
		/*
		 * tune timing of read data/command when crc error happen
		 * no performance impact
		 */
		if (pdata && 0 != pdata->clk_delay_cycles) {
			u16 tmp;

			tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
			tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
				<< SDCLK_DELAY_SHIFT;
			tmp |= SDCLK_SEL;
			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
		}
	}
}

#define MAX_WAIT_COUNT 5
static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
	u16 tmp;
	int count;

	if (pxa->power_mode == MMC_POWER_UP
			&& power_mode == MMC_POWER_ON) {

		dev_dbg(mmc_dev(host->mmc),
				"%s: slot->power_mode = %d,"
				"ios->power_mode = %d\n",
				__func__,
				pxa->power_mode,
				power_mode);

		/* set we want notice of when 74 clocks are sent */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT_EN;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);

		/* start sending the 74 clocks */
		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
		tmp |= SDCFG_GEN_PAD_CLK_ON;
		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);

		/* slowest speed is about 100KHz or 10usec per clock */
		udelay(740);
		count = 0;

		while (count++ < MAX_WAIT_COUNT) {
			if ((readw(host->ioaddr + SD_CE_ATA_2)
						& SDCE_MISC_INT) == 0)
				break;
			udelay(10);
		}

		if (count == MAX_WAIT_COUNT)
			dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");

		/* clear the interrupt bit if posted */
		tmp = readw(host->ioaddr + SD_CE_ATA_2);
		tmp |= SDCE_MISC_INT;
		writew(tmp, host->ioaddr + SD_CE_ATA_2);
	}
	pxa->power_mode = power_mode;
}

static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
	u16 ctrl_2;

	/*
	 * Set V18_EN -- UHS modes do not work without this.
	 * does not change signaling voltage
	 */
	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/* Select Bus Speed Mode for host */
	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	switch (uhs) {
	case MMC_TIMING_UHS_SDR12:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
		break;
	case MMC_TIMING_UHS_SDR25:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
		break;
	case MMC_TIMING_UHS_SDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_UHS_SDR104:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
		break;
	case MMC_TIMING_MMC_DDR52:
	case MMC_TIMING_UHS_DDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
		break;
	}

	/*
	 * Update SDIO3 Configuration register according to erratum
	 * FE-2946959
	 */
	if (pxa->sdio3_conf_reg) {
		u8 reg_val  = readb(pxa->sdio3_conf_reg);

		if (uhs == MMC_TIMING_UHS_SDR50 ||
		    uhs == MMC_TIMING_UHS_DDR50) {
			reg_val &= ~SDIO3_CONF_CLK_INV;
			reg_val |= SDIO3_CONF_SD_FB_CLK;
		} else if (uhs == MMC_TIMING_MMC_HS) {
			reg_val &= ~SDIO3_CONF_CLK_INV;
			reg_val &= ~SDIO3_CONF_SD_FB_CLK;
		} else {
			reg_val |= SDIO3_CONF_CLK_INV;
			reg_val &= ~SDIO3_CONF_SD_FB_CLK;
		}
		writeb(reg_val, pxa->sdio3_conf_reg);
	}

	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	dev_dbg(mmc_dev(host->mmc),
		"%s uhs = %d, ctrl_2 = %04X\n",
		__func__, uhs, ctrl_2);
}

static void pxav3_set_power(struct sdhci_host *host, unsigned char mode,
			    unsigned short vdd)
{
	struct mmc_host *mmc = host->mmc;
	u8 pwr = host->pwr;

	sdhci_set_power_noreg(host, mode, vdd);

	if (host->pwr == pwr)
		return;

	if (host->pwr == 0)
		vdd = 0;

	if (!IS_ERR(mmc->supply.vmmc))
		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
}

static const struct sdhci_ops pxav3_sdhci_ops = {
	.set_clock = sdhci_set_clock,
	.set_power = pxav3_set_power,
	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
	.set_bus_width = sdhci_set_bus_width,
	.reset = pxav3_reset,
	.set_uhs_signaling = pxav3_set_uhs_signaling,
};

static const struct sdhci_pltfm_data sdhci_pxav3_pdata = {
	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
		| SDHCI_QUIRK_32BIT_ADMA_SIZE
		| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops = &pxav3_sdhci_ops,
};

#ifdef CONFIG_OF
static const struct of_device_id sdhci_pxav3_of_match[] = {
	{
		.compatible = "mrvl,pxav3-mmc",
	},
	{
		.compatible = "marvell,armada-380-sdhci",
	},
	{},
};
MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);

static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	struct sdhci_pxa_platdata *pdata;
	struct device_node *np = dev->of_node;
	u32 clk_delay_cycles;

	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;

	if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
				  &clk_delay_cycles))
		pdata->clk_delay_cycles = clk_delay_cycles;

	return pdata;
}
#else
static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
{
	return NULL;
}
#endif

static int sdhci_pxav3_probe(struct platform_device *pdev)
{
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	struct device *dev = &pdev->dev;
	struct device_node *np = pdev->dev.of_node;
	struct sdhci_host *host = NULL;
	struct sdhci_pxa *pxa = NULL;
	const struct of_device_id *match;
	int ret;

	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, sizeof(*pxa));
	if (IS_ERR(host))
		return PTR_ERR(host);

	pltfm_host = sdhci_priv(host);
	pxa = sdhci_pltfm_priv(pltfm_host);

	pxa->clk_io = devm_clk_get(dev, "io");
	if (IS_ERR(pxa->clk_io))
		pxa->clk_io = devm_clk_get(dev, NULL);
	if (IS_ERR(pxa->clk_io)) {
		dev_err(dev, "failed to get io clock\n");
		ret = PTR_ERR(pxa->clk_io);
		goto err_clk_get;
	}
	pltfm_host->clk = pxa->clk_io;
	clk_prepare_enable(pxa->clk_io);

	pxa->clk_core = devm_clk_get(dev, "core");
	if (!IS_ERR(pxa->clk_core))
		clk_prepare_enable(pxa->clk_core);

	/* enable 1/8V DDR capable */
	host->mmc->caps |= MMC_CAP_1_8V_DDR;

	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
		ret = armada_38x_quirks(pdev, host);
		if (ret < 0)
			goto err_mbus_win;
		ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
		if (ret < 0)
			goto err_mbus_win;
	}

	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
	if (match) {
		ret = mmc_of_parse(host->mmc);
		if (ret)
			goto err_of_parse;
		sdhci_get_of_property(pdev);
		pdata = pxav3_get_mmc_pdata(dev);
		pdev->dev.platform_data = pdata;
	} else if (pdata) {
		/* on-chip device */
		if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
			host->mmc->caps |= MMC_CAP_NONREMOVABLE;

		/* If slot design supports 8 bit data, indicate this to MMC. */
		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
			host->mmc->caps |= MMC_CAP_8_BIT_DATA;

		if (pdata->quirks)
			host->quirks |= pdata->quirks;
		if (pdata->quirks2)
			host->quirks2 |= pdata->quirks2;
		if (pdata->host_caps)
			host->mmc->caps |= pdata->host_caps;
		if (pdata->host_caps2)
			host->mmc->caps2 |= pdata->host_caps2;
		if (pdata->pm_caps)
			host->mmc->pm_caps |= pdata->pm_caps;
	}

	pm_runtime_get_noresume(&pdev->dev);
	pm_runtime_set_active(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_enable(&pdev->dev);
	pm_suspend_ignore_children(&pdev->dev, 1);

	ret = sdhci_add_host(host);
	if (ret)
		goto err_add_host;

	if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)
		device_init_wakeup(&pdev->dev, 1);

	pm_runtime_put_autosuspend(&pdev->dev);

	return 0;

err_add_host:
	pm_runtime_disable(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);
err_of_parse:
err_mbus_win:
	clk_disable_unprepare(pxa->clk_io);
	clk_disable_unprepare(pxa->clk_core);
err_clk_get:
	sdhci_pltfm_free(pdev);
	return ret;
}

static int sdhci_pxav3_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);

	pm_runtime_get_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);

	sdhci_remove_host(host, 1);

	clk_disable_unprepare(pxa->clk_io);
	clk_disable_unprepare(pxa->clk_core);

	sdhci_pltfm_free(pdev);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int sdhci_pxav3_suspend(struct device *dev)
{
	int ret;
	struct sdhci_host *host = dev_get_drvdata(dev);

	pm_runtime_get_sync(dev);
	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
		mmc_retune_needed(host->mmc);
	ret = sdhci_suspend_host(host);
	pm_runtime_mark_last_busy(dev);
	pm_runtime_put_autosuspend(dev);

	return ret;
}

static int sdhci_pxav3_resume(struct device *dev)
{
	int ret;
	struct sdhci_host *host = dev_get_drvdata(dev);

	pm_runtime_get_sync(dev);
	ret = sdhci_resume_host(host);
	pm_runtime_mark_last_busy(dev);
	pm_runtime_put_autosuspend(dev);

	return ret;
}
#endif

#ifdef CONFIG_PM
static int sdhci_pxav3_runtime_suspend(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
	int ret;

	ret = sdhci_runtime_suspend_host(host);
	if (ret)
		return ret;

	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
		mmc_retune_needed(host->mmc);

	clk_disable_unprepare(pxa->clk_io);
	if (!IS_ERR(pxa->clk_core))
		clk_disable_unprepare(pxa->clk_core);

	return 0;
}

static int sdhci_pxav3_runtime_resume(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);

	clk_prepare_enable(pxa->clk_io);
	if (!IS_ERR(pxa->clk_core))
		clk_prepare_enable(pxa->clk_core);

	return sdhci_runtime_resume_host(host);
}
#endif

static const struct dev_pm_ops sdhci_pxav3_pmops = {
	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
		sdhci_pxav3_runtime_resume, NULL)
};

static struct platform_driver sdhci_pxav3_driver = {
	.driver		= {
		.name	= "sdhci-pxav3",
		.of_match_table = of_match_ptr(sdhci_pxav3_of_match),
		.pm	= &sdhci_pxav3_pmops,
	},
	.probe		= sdhci_pxav3_probe,
	.remove		= sdhci_pxav3_remove,
};

module_platform_driver(sdhci_pxav3_driver);

MODULE_DESCRIPTION("SDHCI driver for pxav3");
MODULE_AUTHOR("Marvell International Ltd.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9c92ab61	1	// SPDX-License-Identifier: GPL-2.0-only
a702c8ab ZG	2	/*
	3	* Copyright (C) 2010 Marvell International Ltd.
	4	* Zhangfei Gao <zhangfei.gao@marvell.com>
	5	* Kevin Wang <dwang4@marvell.com>
	6	* Mingwei Wang <mwwang@marvell.com>
	7	* Philip Rakity <prakity@marvell.com>
	8	* Mark Brown <markb@marvell.com>
a702c8ab ZG	9	*/
	10	#include <linux/err.h>
	11	#include <linux/init.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/clk.h>
	14	#include <linux/io.h>
a702c8ab ZG	15	#include <linux/mmc/card.h>
a702c8ab ZG	16	#include <linux/mmc/host.h>
bfed345e	17	#include <linux/platform_data/pxa_sdhci.h>
a702c8ab ZG	18	#include <linux/slab.h>
a702c8ab ZG	19	#include <linux/delay.h>
88b47679	20	#include <linux/module.h>
b650352d CB	21	#include <linux/of.h>
b650352d CB	22	#include <linux/of_device.h>
bb691ae4 KL	23	#include <linux/pm.h>
bb691ae4 KL	24	#include <linux/pm_runtime.h>
5491ce3f	25	#include <linux/mbus.h>
b650352d	26
a702c8ab ZG	27	#include "sdhci.h"
	28	#include "sdhci-pltfm.h"
	29
bb691ae4 KL	30	#define PXAV3_RPM_DELAY_MS 50
bb691ae4 KL	31
a702c8ab ZG	32	#define SD_CLOCK_BURST_SIZE_SETUP 0x10A
	33	#define SDCLK_SEL 0x100
	34	#define SDCLK_DELAY_SHIFT 9
	35	#define SDCLK_DELAY_MASK 0x1f
	36
	37	#define SD_CFG_FIFO_PARAM 0x100
	38	#define SDCFG_GEN_PAD_CLK_ON (1<<6)
	39	#define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF
	40	#define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24
	41
	42	#define SD_SPI_MODE 0x108
	43	#define SD_CE_ATA_1 0x10C
	44
	45	#define SD_CE_ATA_2 0x10E
	46	#define SDCE_MISC_INT (1<<2)
	47	#define SDCE_MISC_INT_EN (1<<1)
	48
cc9571e8	49	struct sdhci_pxa {
8afdc9cc	50	struct clk *clk_core;
8c96a7a3	51	struct clk *clk_io;
cc9571e8	52	u8 power_mode;
1140011e	53	void __iomem *sdio3_conf_reg;
cc9571e8 SH	54	};
cc9571e8 SH	55
5491ce3f MW	56	/*
	57	* These registers are relative to the second register region, for the
	58	* MBus bridge.
	59	*/
	60	#define SDHCI_WINDOW_CTRL(i) (0x80 + ((i) << 3))
	61	#define SDHCI_WINDOW_BASE(i) (0x84 + ((i) << 3))
	62	#define SDHCI_MAX_WIN_NUM 8
	63
1140011e MW	64	/*
	65	* Fields below belong to SDIO3 Configuration Register (third register
	66	* region for the Armada 38x flavor)
	67	*/
	68
	69	#define SDIO3_CONF_CLK_INV BIT(0)
	70	#define SDIO3_CONF_SD_FB_CLK BIT(2)
	71
5491ce3f MW	72	static int mv_conf_mbus_windows(struct platform_device *pdev,
	73	const struct mbus_dram_target_info *dram)
	74	{
	75	int i;
	76	void __iomem *regs;
	77	struct resource *res;
	78
	79	if (!dram) {
	80	dev_err(&pdev->dev, "no mbus dram info\n");
	81	return -EINVAL;
	82	}
	83
	84	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	85	if (!res) {
	86	dev_err(&pdev->dev, "cannot get mbus registers\n");
	87	return -EINVAL;
	88	}
	89
	90	regs = ioremap(res->start, resource_size(res));
	91	if (!regs) {
	92	dev_err(&pdev->dev, "cannot map mbus registers\n");
	93	return -ENOMEM;
	94	}
	95
	96	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
	97	writel(0, regs + SDHCI_WINDOW_CTRL(i));
	98	writel(0, regs + SDHCI_WINDOW_BASE(i));
	99	}
	100
	101	for (i = 0; i < dram->num_cs; i++) {
	102	const struct mbus_dram_window *cs = dram->cs + i;
	103
	104	/* Write size, attributes and target id to control register */
	105	writel(((cs->size - 1) & 0xffff0000) \|
	106	(cs->mbus_attr << 8) \|
	107	(dram->mbus_dram_target_id << 4) \| 1,
	108	regs + SDHCI_WINDOW_CTRL(i));
	109	/* Write base address to base register */
	110	writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
	111	}
	112
	113	iounmap(regs);
	114
	115	return 0;
	116	}
	117
a39128bc MW	118	static int armada_38x_quirks(struct platform_device *pdev,
a39128bc MW	119	struct sdhci_host *host)
d4b803c5	120	{
a39128bc	121	struct device_node *np = pdev->dev.of_node;
1140011e	122	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
f599da40	123	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
1140011e	124	struct resource *res;
a39128bc	125
5de76bfc	126	host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
d4b803c5	127	host->quirks \|= SDHCI_QUIRK_MISSING_CAPS;
0ca33b4a RK	128
	129	host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
	130	host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
	131
1140011e MW	132	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
	133	"conf-sdio3");
	134	if (res) {
	135	pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
	136	if (IS_ERR(pxa->sdio3_conf_reg))
	137	return PTR_ERR(pxa->sdio3_conf_reg);
	138	} else {
	139	/*
	140	* According to erratum 'FE-2946959' both SDR50 and DDR50
	141	* modes require specific clock adjustments in SDIO3
	142	* Configuration register, if the adjustment is not done,
	143	* remove them from the capabilities.
	144	*/
1140011e MW	145	host->caps1 &= ~(SDHCI_SUPPORT_SDR50 \| SDHCI_SUPPORT_DDR50);
	146
	147	dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n");
	148	}
a39128bc MW	149
	150	/*
	151	* According to erratum 'ERR-7878951' Armada 38x SDHCI
	152	* controller has different capabilities than the ones shown
	153	* in its registers
	154	*/
a39128bc MW	155	if (of_property_read_bool(np, "no-1-8-v")) {
	156	host->caps &= ~SDHCI_CAN_VDD_180;
	157	host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
	158	} else {
	159	host->caps &= ~SDHCI_CAN_VDD_330;
	160	}
	161	host->caps1 &= ~(SDHCI_SUPPORT_SDR104 \| SDHCI_USE_SDR50_TUNING);
	162
d4b803c5 GC	163	return 0;
	164	}
	165
03231f9b	166	static void pxav3_reset(struct sdhci_host *host, u8 mask)
a702c8ab ZG	167	{
	168	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
	169	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	170
03231f9b RK	171	sdhci_reset(host, mask);
03231f9b RK	172
a702c8ab ZG	173	if (mask == SDHCI_RESET_ALL) {
	174	/*
	175	* tune timing of read data/command when crc error happen
	176	* no performance impact
	177	*/
	178	if (pdata && 0 != pdata->clk_delay_cycles) {
	179	u16 tmp;
	180
	181	tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	182	tmp \|= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
	183	<< SDCLK_DELAY_SHIFT;
	184	tmp \|= SDCLK_SEL;
	185	writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
	186	}
	187	}
	188	}
	189
	190	#define MAX_WAIT_COUNT 5
	191	static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
	192	{
	193	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
f599da40	194	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
a702c8ab ZG	195	u16 tmp;
	196	int count;
	197
	198	if (pxa->power_mode == MMC_POWER_UP
	199	&& power_mode == MMC_POWER_ON) {
	200
	201	dev_dbg(mmc_dev(host->mmc),
	202	"%s: slot->power_mode = %d,"
	203	"ios->power_mode = %d\n",
	204	__func__,
	205	pxa->power_mode,
	206	power_mode);
	207
	208	/* set we want notice of when 74 clocks are sent */
	209	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	210	tmp \|= SDCE_MISC_INT_EN;
	211	writew(tmp, host->ioaddr + SD_CE_ATA_2);
	212
	213	/* start sending the 74 clocks */
	214	tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
	215	tmp \|= SDCFG_GEN_PAD_CLK_ON;
	216	writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
	217
	218	/* slowest speed is about 100KHz or 10usec per clock */
	219	udelay(740);
	220	count = 0;
	221
	222	while (count++ < MAX_WAIT_COUNT) {
	223	if ((readw(host->ioaddr + SD_CE_ATA_2)
	224	& SDCE_MISC_INT) == 0)
	225	break;
	226	udelay(10);
	227	}
	228
	229	if (count == MAX_WAIT_COUNT)
	230	dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
	231
	232	/* clear the interrupt bit if posted */
	233	tmp = readw(host->ioaddr + SD_CE_ATA_2);
	234	tmp \|= SDCE_MISC_INT;
	235	writew(tmp, host->ioaddr + SD_CE_ATA_2);
	236	}
	237	pxa->power_mode = power_mode;
	238	}
	239
13e64501	240	static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
a702c8ab	241	{
1140011e	242	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
f599da40	243	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
a702c8ab ZG	244	u16 ctrl_2;
	245
	246	/*
	247	* Set V18_EN -- UHS modes do not work without this.
	248	* does not change signaling voltage
	249	*/
	250	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	251
	252	/* Select Bus Speed Mode for host */
	253	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	254	switch (uhs) {
	255	case MMC_TIMING_UHS_SDR12:
	256	ctrl_2 \|= SDHCI_CTRL_UHS_SDR12;
	257	break;
	258	case MMC_TIMING_UHS_SDR25:
	259	ctrl_2 \|= SDHCI_CTRL_UHS_SDR25;
	260	break;
	261	case MMC_TIMING_UHS_SDR50:
	262	ctrl_2 \|= SDHCI_CTRL_UHS_SDR50 \| SDHCI_CTRL_VDD_180;
	263	break;
	264	case MMC_TIMING_UHS_SDR104:
	265	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104 \| SDHCI_CTRL_VDD_180;
	266	break;
668e84b2	267	case MMC_TIMING_MMC_DDR52:
a702c8ab ZG	268	case MMC_TIMING_UHS_DDR50:
	269	ctrl_2 \|= SDHCI_CTRL_UHS_DDR50 \| SDHCI_CTRL_VDD_180;
	270	break;
	271	}
	272
1140011e MW	273	/*
	274	* Update SDIO3 Configuration register according to erratum
	275	* FE-2946959
	276	*/
	277	if (pxa->sdio3_conf_reg) {
	278	u8 reg_val = readb(pxa->sdio3_conf_reg);
	279
	280	if (uhs == MMC_TIMING_UHS_SDR50 \|\|
	281	uhs == MMC_TIMING_UHS_DDR50) {
	282	reg_val &= ~SDIO3_CONF_CLK_INV;
	283	reg_val \|= SDIO3_CONF_SD_FB_CLK;
fa796414 NH	284	} else if (uhs == MMC_TIMING_MMC_HS) {
	285	reg_val &= ~SDIO3_CONF_CLK_INV;
	286	reg_val &= ~SDIO3_CONF_SD_FB_CLK;
1140011e MW	287	} else {
	288	reg_val \|= SDIO3_CONF_CLK_INV;
	289	reg_val &= ~SDIO3_CONF_SD_FB_CLK;
	290	}
	291	writeb(reg_val, pxa->sdio3_conf_reg);
	292	}
	293
a702c8ab ZG	294	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	295	dev_dbg(mmc_dev(host->mmc),
	296	"%s uhs = %d, ctrl_2 = %04X\n",
	297	__func__, uhs, ctrl_2);
a702c8ab ZG	298	}
a702c8ab ZG	299
1dceb041 AH	300	static void pxav3_set_power(struct sdhci_host *host, unsigned char mode,
	301	unsigned short vdd)
	302	{
	303	struct mmc_host *mmc = host->mmc;
	304	u8 pwr = host->pwr;
	305
606d3131	306	sdhci_set_power_noreg(host, mode, vdd);
1dceb041 AH	307
	308	if (host->pwr == pwr)
	309	return;
	310
	311	if (host->pwr == 0)
	312	vdd = 0;
	313
d1e4f74f	314	if (!IS_ERR(mmc->supply.vmmc))
1dceb041	315	mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1dceb041 AH	316	}
1dceb041 AH	317
c915568d	318	static const struct sdhci_ops pxav3_sdhci_ops = {
1771059c	319	.set_clock = sdhci_set_clock,
1dceb041	320	.set_power = pxav3_set_power,
a702c8ab	321	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
d005d943	322	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
2317f56c	323	.set_bus_width = sdhci_set_bus_width,
03231f9b	324	.reset = pxav3_reset,
b3153765	325	.set_uhs_signaling = pxav3_set_uhs_signaling,
a702c8ab ZG	326	};
a702c8ab ZG	327
d35ade8f	328	static const struct sdhci_pltfm_data sdhci_pxav3_pdata = {
e065162a	329	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
73b7afb9 KL	330	\| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
	331	\| SDHCI_QUIRK_32BIT_ADMA_SIZE
	332	\| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	333	.ops = &pxav3_sdhci_ops,
	334	};
	335
b650352d CB	336	#ifdef CONFIG_OF
	337	static const struct of_device_id sdhci_pxav3_of_match[] = {
	338	{
	339	.compatible = "mrvl,pxav3-mmc",
	340	},
5491ce3f MW	341	{
	342	.compatible = "marvell,armada-380-sdhci",
	343	},
b650352d CB	344	{},
	345	};
	346	MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
	347
	348	static struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	349	{
	350	struct sdhci_pxa_platdata *pdata;
	351	struct device_node *np = dev->of_node;
b650352d CB	352	u32 clk_delay_cycles;
	353
	354	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	355	if (!pdata)
	356	return NULL;
	357
14460dba JZ	358	if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
14460dba JZ	359	&clk_delay_cycles))
b650352d CB	360	pdata->clk_delay_cycles = clk_delay_cycles;
	361
	362	return pdata;
	363	}
	364	#else
	365	static inline struct sdhci_pxa_platdata pxav3_get_mmc_pdata(struct device dev)
	366	{
	367	return NULL;
	368	}
	369	#endif
	370
c3be1efd	371	static int sdhci_pxav3_probe(struct platform_device *pdev)
a702c8ab ZG	372	{
	373	struct sdhci_pltfm_host *pltfm_host;
	374	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
	375	struct device *dev = &pdev->dev;
5491ce3f	376	struct device_node *np = pdev->dev.of_node;
a702c8ab ZG	377	struct sdhci_host *host = NULL;
a702c8ab ZG	378	struct sdhci_pxa *pxa = NULL;
b650352d	379	const struct of_device_id *match;
a702c8ab	380	int ret;
a702c8ab	381
f599da40	382	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, sizeof(*pxa));
3df5b281	383	if (IS_ERR(host))
a702c8ab	384	return PTR_ERR(host);
5491ce3f	385
a702c8ab	386	pltfm_host = sdhci_priv(host);
f599da40	387	pxa = sdhci_pltfm_priv(pltfm_host);
a702c8ab	388
01ae1070 SH	389	pxa->clk_io = devm_clk_get(dev, "io");
	390	if (IS_ERR(pxa->clk_io))
	391	pxa->clk_io = devm_clk_get(dev, NULL);
8c96a7a3	392	if (IS_ERR(pxa->clk_io)) {
a702c8ab	393	dev_err(dev, "failed to get io clock\n");
8c96a7a3	394	ret = PTR_ERR(pxa->clk_io);
a702c8ab ZG	395	goto err_clk_get;
a702c8ab ZG	396	}
8c96a7a3 SH	397	pltfm_host->clk = pxa->clk_io;
8c96a7a3 SH	398	clk_prepare_enable(pxa->clk_io);
a702c8ab	399
8afdc9cc SH	400	pxa->clk_core = devm_clk_get(dev, "core");
	401	if (!IS_ERR(pxa->clk_core))
	402	clk_prepare_enable(pxa->clk_core);
	403
a39128bc MW	404	/* enable 1/8V DDR capable */
	405	host->mmc->caps \|= MMC_CAP_1_8V_DDR;
	406
aa8165f9	407	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
a39128bc	408	ret = armada_38x_quirks(pdev, host);
d4b803c5	409	if (ret < 0)
2162d9f4	410	goto err_mbus_win;
aa8165f9 TP	411	ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
	412	if (ret < 0)
	413	goto err_mbus_win;
	414	}
	415
b650352d	416	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
943647f6	417	if (match) {
d2cf6071 SB	418	ret = mmc_of_parse(host->mmc);
	419	if (ret)
	420	goto err_of_parse;
943647f6	421	sdhci_get_of_property(pdev);
b650352d	422	pdata = pxav3_get_mmc_pdata(dev);
9cd76049	423	pdev->dev.platform_data = pdata;
943647f6	424	} else if (pdata) {
c844a46f KL	425	/* on-chip device */
c844a46f KL	426	if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
a702c8ab	427	host->mmc->caps \|= MMC_CAP_NONREMOVABLE;
a702c8ab ZG	428
	429	/* If slot design supports 8 bit data, indicate this to MMC. */
	430	if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
	431	host->mmc->caps \|= MMC_CAP_8_BIT_DATA;
	432
	433	if (pdata->quirks)
	434	host->quirks \|= pdata->quirks;
7c52d7bb KL	435	if (pdata->quirks2)
7c52d7bb KL	436	host->quirks2 \|= pdata->quirks2;
a702c8ab ZG	437	if (pdata->host_caps)
a702c8ab ZG	438	host->mmc->caps \|= pdata->host_caps;
8f63795c CB	439	if (pdata->host_caps2)
8f63795c CB	440	host->mmc->caps2 \|= pdata->host_caps2;
a702c8ab ZG	441	if (pdata->pm_caps)
	442	host->mmc->pm_caps \|= pdata->pm_caps;
	443	}
	444
62cf983a JZ	445	pm_runtime_get_noresume(&pdev->dev);
62cf983a JZ	446	pm_runtime_set_active(&pdev->dev);
bb691ae4 KL	447	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
bb691ae4 KL	448	pm_runtime_use_autosuspend(&pdev->dev);
62cf983a	449	pm_runtime_enable(&pdev->dev);
bb691ae4	450	pm_suspend_ignore_children(&pdev->dev, 1);
bb691ae4	451
a702c8ab	452	ret = sdhci_add_host(host);
fb8617e1	453	if (ret)
a702c8ab	454	goto err_add_host;
a702c8ab	455
83dc9fec	456	if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)
740b7a44	457	device_init_wakeup(&pdev->dev, 1);
740b7a44	458
bb691ae4 KL	459	pm_runtime_put_autosuspend(&pdev->dev);
bb691ae4 KL	460
a702c8ab ZG	461	return 0;
	462
	463	err_add_host:
0dcaa249	464	pm_runtime_disable(&pdev->dev);
62cf983a	465	pm_runtime_put_noidle(&pdev->dev);
87d2163d	466	err_of_parse:
aa8165f9	467	err_mbus_win:
8c96a7a3	468	clk_disable_unprepare(pxa->clk_io);
c25d9e1b	469	clk_disable_unprepare(pxa->clk_core);
a702c8ab ZG	470	err_clk_get:
a702c8ab ZG	471	sdhci_pltfm_free(pdev);
a702c8ab ZG	472	return ret;
	473	}
	474
6e0ee714	475	static int sdhci_pxav3_remove(struct platform_device *pdev)
a702c8ab ZG	476	{
	477	struct sdhci_host *host = platform_get_drvdata(pdev);
	478	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
f599da40	479	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
a702c8ab	480
bb691ae4	481	pm_runtime_get_sync(&pdev->dev);
bb691ae4	482	pm_runtime_disable(&pdev->dev);
20f1f2d7 JZ	483	pm_runtime_put_noidle(&pdev->dev);
	484
	485	sdhci_remove_host(host, 1);
a702c8ab	486
8c96a7a3	487	clk_disable_unprepare(pxa->clk_io);
c25d9e1b	488	clk_disable_unprepare(pxa->clk_core);
8f63795c	489
a702c8ab	490	sdhci_pltfm_free(pdev);
a702c8ab	491
a702c8ab ZG	492	return 0;
	493	}
	494
bb691ae4 KL	495	#ifdef CONFIG_PM_SLEEP
	496	static int sdhci_pxav3_suspend(struct device *dev)
	497	{
	498	int ret;
	499	struct sdhci_host *host = dev_get_drvdata(dev);
	500
	501	pm_runtime_get_sync(dev);
d38dcad4 AH	502	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
d38dcad4 AH	503	mmc_retune_needed(host->mmc);
bb691ae4 KL	504	ret = sdhci_suspend_host(host);
	505	pm_runtime_mark_last_busy(dev);
	506	pm_runtime_put_autosuspend(dev);
	507
	508	return ret;
	509	}
	510
	511	static int sdhci_pxav3_resume(struct device *dev)
	512	{
	513	int ret;
	514	struct sdhci_host *host = dev_get_drvdata(dev);
	515
	516	pm_runtime_get_sync(dev);
	517	ret = sdhci_resume_host(host);
	518	pm_runtime_mark_last_busy(dev);
	519	pm_runtime_put_autosuspend(dev);
	520
	521	return ret;
	522	}
	523	#endif
	524
162d6f98	525	#ifdef CONFIG_PM
bb691ae4 KL	526	static int sdhci_pxav3_runtime_suspend(struct device *dev)
	527	{
	528	struct sdhci_host *host = dev_get_drvdata(dev);
	529	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
f599da40	530	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
3bb10f60	531	int ret;
bb691ae4	532
3bb10f60 JZ	533	ret = sdhci_runtime_suspend_host(host);
	534	if (ret)
	535	return ret;
bb691ae4	536
d38dcad4 AH	537	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
	538	mmc_retune_needed(host->mmc);
	539
8c96a7a3	540	clk_disable_unprepare(pxa->clk_io);
8afdc9cc SH	541	if (!IS_ERR(pxa->clk_core))
8afdc9cc SH	542	clk_disable_unprepare(pxa->clk_core);
bb691ae4 KL	543
	544	return 0;
	545	}
	546
	547	static int sdhci_pxav3_runtime_resume(struct device *dev)
	548	{
	549	struct sdhci_host *host = dev_get_drvdata(dev);
	550	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
f599da40	551	struct sdhci_pxa *pxa = sdhci_pltfm_priv(pltfm_host);
bb691ae4	552
8c96a7a3	553	clk_prepare_enable(pxa->clk_io);
8afdc9cc SH	554	if (!IS_ERR(pxa->clk_core))
8afdc9cc SH	555	clk_prepare_enable(pxa->clk_core);
bb691ae4	556
3bb10f60	557	return sdhci_runtime_resume_host(host);
bb691ae4 KL	558	}
	559	#endif
	560
bb691ae4 KL	561	static const struct dev_pm_ops sdhci_pxav3_pmops = {
	562	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
	563	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
	564	sdhci_pxav3_runtime_resume, NULL)
	565	};
	566
a702c8ab ZG	567	static struct platform_driver sdhci_pxav3_driver = {
	568	.driver = {
	569	.name = "sdhci-pxav3",
59d22309	570	.of_match_table = of_match_ptr(sdhci_pxav3_of_match),
a81ce772	571	.pm = &sdhci_pxav3_pmops,
a702c8ab ZG	572	},
a702c8ab ZG	573	.probe = sdhci_pxav3_probe,
0433c143	574	.remove = sdhci_pxav3_remove,
a702c8ab	575	};
a702c8ab	576
d1f81a64	577	module_platform_driver(sdhci_pxav3_driver);
a702c8ab ZG	578
	579	MODULE_DESCRIPTION("SDHCI driver for pxav3");
	580	MODULE_AUTHOR("Marvell International Ltd.");
	581	MODULE_LICENSE("GPL v2");
	582