[linux-2.6-block.git] / drivers / mmc / host / sdhci-pltfm.h

/*
 * Copyright 2010 MontaVista Software, LLC.
 *
 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _DRIVERS_MMC_SDHCI_PLTFM_H
#define _DRIVERS_MMC_SDHCI_PLTFM_H

#include <linux/clk.h>
#include <linux/platform_device.h>
#include "sdhci.h"

struct sdhci_pltfm_data {
	const struct sdhci_ops *ops;
	unsigned int quirks;
	unsigned int quirks2;
};

struct sdhci_pltfm_host {
	struct clk *clk;

	/* migrate from sdhci_of_host */
	unsigned int clock;
	u16 xfer_mode_shadow;

	unsigned long private[0] ____cacheline_aligned;
};

#ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
/*
 * These accessors are designed for big endian hosts doing I/O to
 * little endian controllers incorporating a 32-bit hardware byte swapper.
 */
static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg)
{
	return in_be32(host->ioaddr + reg);
}

static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg)
{
	return in_be16(host->ioaddr + (reg ^ 0x2));
}

static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg)
{
	return in_8(host->ioaddr + (reg ^ 0x3));
}

static inline void sdhci_be32bs_writel(struct sdhci_host *host,
				       u32 val, int reg)
{
	out_be32(host->ioaddr + reg, val);
}

static inline void sdhci_be32bs_writew(struct sdhci_host *host,
				       u16 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	int base = reg & ~0x3;
	int shift = (reg & 0x2) * 8;

	switch (reg) {
	case SDHCI_TRANSFER_MODE:
		/*
		 * Postpone this write, we must do it together with a
		 * command write that is down below.
		 */
		pltfm_host->xfer_mode_shadow = val;
		return;
	case SDHCI_COMMAND:
		sdhci_be32bs_writel(host,
				    val << 16 | pltfm_host->xfer_mode_shadow,
				    SDHCI_TRANSFER_MODE);
		return;
	}
	clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
}

static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
{
	int base = reg & ~0x3;
	int shift = (reg & 0x3) * 8;

	clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
}
#endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */

void sdhci_get_property(struct platform_device *pdev);

static inline void sdhci_get_of_property(struct platform_device *pdev)
{
	return sdhci_get_property(pdev);
}

extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
					  const struct sdhci_pltfm_data *pdata,
					  size_t priv_size);
extern void sdhci_pltfm_free(struct platform_device *pdev);

extern int sdhci_pltfm_register(struct platform_device *pdev,
				const struct sdhci_pltfm_data *pdata,
				size_t priv_size);
extern int sdhci_pltfm_unregister(struct platform_device *pdev);

extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host);

static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host)
{
	return host->private;
}

int sdhci_pltfm_suspend(struct device *dev);
int sdhci_pltfm_resume(struct device *dev);
extern const struct dev_pm_ops sdhci_pltfm_pmops;

#endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */
Commit	Line	Data
515033f9 AV	1	/*
	2	* Copyright 2010 MontaVista Software, LLC.
	3	*
	4	* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#ifndef _DRIVERS_MMC_SDHCI_PLTFM_H
	12	#define _DRIVERS_MMC_SDHCI_PLTFM_H
	13
4b711cb1	14	#include <linux/clk.h>
85d6509d	15	#include <linux/platform_device.h>
f0de8369	16	#include "sdhci.h"
20b1597b	17
94cc6a86	18	struct sdhci_pltfm_data {
ad1df8c2	19	const struct sdhci_ops *ops;
94cc6a86	20	unsigned int quirks;
ad82ab65	21	unsigned int quirks2;
94cc6a86 SG	22	};
94cc6a86 SG	23
4b711cb1 WS	24	struct sdhci_pltfm_host {
4b711cb1 WS	25	struct clk *clk;
e307148f SG	26
	27	/* migrate from sdhci_of_host */
	28	unsigned int clock;
	29	u16 xfer_mode_shadow;
0e748234 CD	30
0e748234 CD	31	unsigned long private[0] ____cacheline_aligned;
4b711cb1 WS	32	};
4b711cb1 WS	33
38576af1	34	#ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
f0de8369 SG	35	/*
	36	* These accessors are designed for big endian hosts doing I/O to
	37	* little endian controllers incorporating a 32-bit hardware byte swapper.
	38	*/
	39	static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg)
	40	{
	41	return in_be32(host->ioaddr + reg);
	42	}
	43
	44	static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg)
	45	{
	46	return in_be16(host->ioaddr + (reg ^ 0x2));
	47	}
	48
	49	static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg)
	50	{
	51	return in_8(host->ioaddr + (reg ^ 0x3));
	52	}
	53
	54	static inline void sdhci_be32bs_writel(struct sdhci_host *host,
	55	u32 val, int reg)
	56	{
	57	out_be32(host->ioaddr + reg, val);
	58	}
	59
	60	static inline void sdhci_be32bs_writew(struct sdhci_host *host,
	61	u16 val, int reg)
	62	{
	63	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	64	int base = reg & ~0x3;
	65	int shift = (reg & 0x2) * 8;
	66
	67	switch (reg) {
	68	case SDHCI_TRANSFER_MODE:
	69	/*
	70	* Postpone this write, we must do it together with a
	71	* command write that is down below.
	72	*/
	73	pltfm_host->xfer_mode_shadow = val;
	74	return;
	75	case SDHCI_COMMAND:
	76	sdhci_be32bs_writel(host,
	77	val << 16 \| pltfm_host->xfer_mode_shadow,
	78	SDHCI_TRANSFER_MODE);
	79	return;
	80	}
	81	clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
	82	}
	83
	84	static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
	85	{
	86	int base = reg & ~0x3;
	87	int shift = (reg & 0x3) * 8;
	88
	89	clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
	90	}
	91	#endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */
38576af1	92
8199d312 AH	93	void sdhci_get_property(struct platform_device *pdev);
	94
	95	static inline void sdhci_get_of_property(struct platform_device *pdev)
	96	{
	97	return sdhci_get_property(pdev);
	98	}
38576af1	99
85d6509d	100	extern struct sdhci_host sdhci_pltfm_init(struct platform_device pdev,
0e748234 CD	101	const struct sdhci_pltfm_data *pdata,
0e748234 CD	102	size_t priv_size);
85d6509d SG	103	extern void sdhci_pltfm_free(struct platform_device *pdev);
	104
	105	extern int sdhci_pltfm_register(struct platform_device *pdev,
0e748234 CD	106	const struct sdhci_pltfm_data *pdata,
0e748234 CD	107	size_t priv_size);
85d6509d SG	108	extern int sdhci_pltfm_unregister(struct platform_device *pdev);
85d6509d SG	109
d005d943 LPC	110	extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host);
d005d943 LPC	111
0e748234 CD	112	static inline void sdhci_pltfm_priv(struct sdhci_pltfm_host host)
0e748234 CD	113	{
178b0fa0	114	return host->private;
0e748234 CD	115	}
0e748234 CD	116
83a7b32a MY	117	int sdhci_pltfm_suspend(struct device *dev);
83a7b32a MY	118	int sdhci_pltfm_resume(struct device *dev);
29495aa0	119	extern const struct dev_pm_ops sdhci_pltfm_pmops;
20b1597b	120
515033f9	121	#endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */