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mmc: sdhci-acpi: Add a HID and UID for a SD Card host controller
[linux-2.6-block.git] / drivers / mmc / host / sdhci-pci.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
88b47679 17#include <linux/module.h>
b8c86fc5
PO		 18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
ccc92c23 21#include <linux/device.h>
b8c86fc5 22#include <linux/mmc/host.h>
b177bc91
AP		 23#include <linux/scatterlist.h>
24#include <linux/io.h>
0f201655 25#include <linux/gpio.h>
66fd8ad5 26#include <linux/pm_runtime.h>
52c506f0 27#include <linux/mmc/sdhci-pci-data.h>
b8c86fc5
PO		 28
29#include "sdhci.h"
522624f9 30#include "sdhci-pci.h"
01acf691 31#include "sdhci-pci-o2micro.h"
22606405
PO		 32
33/*****************************************************************************\
34 * *
35 * Hardware specific quirk handling *
36 * *
37\*****************************************************************************/
38
39static int ricoh_probe(struct sdhci_pci_chip *chip)
40{
c99436fb
CB		 41 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
42 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 43 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 44 return 0;
45}
46
47static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
48{
49 slot->host->caps =
50 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
51 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 52
ccc92c23
ML		 53 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
54 & SDHCI_CLOCK_BASE_MASK) |
55
56 SDHCI_TIMEOUT_CLK_UNIT |
57 SDHCI_CAN_VDD_330 |
1a1f1f04 58 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 59 SDHCI_CAN_DO_SDMA;
60 return 0;
61}
62
63static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
64{
65 /* Apply a delay to allow controller to settle */
66 /* Otherwise it becomes confused if card state changed
67 during suspend */
68 msleep(500);
22606405
PO		 69 return 0;
70}
71
72static const struct sdhci_pci_fixes sdhci_ricoh = {
73 .probe = ricoh_probe,
84938294
VK		 74 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
75 SDHCI_QUIRK_FORCE_DMA |
76 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 77};
78
ccc92c23
ML		 79static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
80 .probe_slot = ricoh_mmc_probe_slot,
81 .resume = ricoh_mmc_resume,
82 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
83 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
84 SDHCI_QUIRK_NO_CARD_NO_RESET |
85 SDHCI_QUIRK_MISSING_CAPS
86};
87
22606405
PO		 88static const struct sdhci_pci_fixes sdhci_ene_712 = {
89 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
90 SDHCI_QUIRK_BROKEN_DMA,
91};
92
93static const struct sdhci_pci_fixes sdhci_ene_714 = {
94 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
95 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
96 SDHCI_QUIRK_BROKEN_DMA,
97};
98
99static const struct sdhci_pci_fixes sdhci_cafe = {
100 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 101 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 102 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 103 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 104};
105
43e968ce
DB		 106static const struct sdhci_pci_fixes sdhci_intel_qrk = {
107 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
108};
109
68077b02
ML		 110static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
111{
112 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
113 return 0;
114}
115
f9ee3eab
AC		 116/*
117 * ADMA operation is disabled for Moorestown platform due to
118 * hardware bugs.
119 */
35ac6f08 120static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 121{
122 /*
35ac6f08
JP		 123 * slots number is fixed here for MRST as SDIO3/5 are never used and
124 * have hardware bugs.
f9ee3eab
AC		 125 */
126 chip->num_slots = 1;
127 return 0;
128}
129
296e0b03
AS		 130static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
131{
132 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
133 return 0;
134}
135
66fd8ad5
AH		 136#ifdef CONFIG_PM_RUNTIME
137
c5e027a4 138static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 139{
140 struct sdhci_pci_slot *slot = dev_id;
141 struct sdhci_host *host = slot->host;
142
143 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
144 return IRQ_HANDLED;
145}
146
c5e027a4 147static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 148{
c5e027a4 149 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 150
151 slot->cd_gpio = -EINVAL;
152 slot->cd_irq = -EINVAL;
153
c5e027a4
AH		 154 if (!gpio_is_valid(gpio))
155 return;
156
66fd8ad5
AH		 157 err = gpio_request(gpio, "sd_cd");
158 if (err < 0)
159 goto out;
160
161 err = gpio_direction_input(gpio);
162 if (err < 0)
163 goto out_free;
164
165 irq = gpio_to_irq(gpio);
166 if (irq < 0)
167 goto out_free;
168
c5e027a4 169 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 170 IRQF_TRIGGER_FALLING, "sd_cd", slot);
171 if (err)
172 goto out_free;
173
174 slot->cd_gpio = gpio;
175 slot->cd_irq = irq;
66fd8ad5 176
c5e027a4 177 return;
66fd8ad5
AH		 178
179out_free:
180 gpio_free(gpio);
181out:
182 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 183}
184
c5e027a4 185static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 186{
187 if (slot->cd_irq >= 0)
188 free_irq(slot->cd_irq, slot);
c5e027a4
AH		 189 if (gpio_is_valid(slot->cd_gpio))
190 gpio_free(slot->cd_gpio);
66fd8ad5
AH		 191}
192
193#else
194
c5e027a4
AH		 195static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
196{
197}
198
199static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
200{
201}
66fd8ad5
AH		 202
203#endif
204
0d013bcf
AH		 205static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
206{
66fd8ad5 207 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
da721cf7
AH		 208 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
209 MMC_CAP2_HC_ERASE_SZ;
0d013bcf
AH		 210 return 0;
211}
212
93933508
AH		 213static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
214{
012e4671 215 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 216 return 0;
217}
218
f9ee3eab
AC		 219static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
220 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 221 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 222};
223
35ac6f08 224static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 225 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 226 .probe = mrst_hc_probe,
f9ee3eab
AC		 227};
228
29229052
XS		 229static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
230 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 231 .allow_runtime_pm = true,
77a0122e 232 .own_cd_for_runtime_pm = true,
29229052
XS		 233};
234
0d013bcf
AH		 235static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
236 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 237 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 238 .allow_runtime_pm = true,
93933508 239 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 240};
241
242static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 243 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 244 .allow_runtime_pm = true,
0d013bcf 245 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 246};
247
296e0b03
AS		 248static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
249 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
250 .probe_slot = pch_hc_probe_slot,
251};
252
c9faff6c
AH		 253static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
254{
255 u8 reg;
256
257 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
258 reg |= 0x10;
259 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
260 /* For eMMC, minimum is 1us but give it 9us for good measure */
261 udelay(9);
262 reg &= ~0x10;
263 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
264 /* For eMMC, minimum is 200us but give it 300us for good measure */
265 usleep_range(300, 1000);
266}
267
728ef3d1
AH		 268static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
269{
c9faff6c 270 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
f25c3372 271 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR;
728ef3d1 272 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
c9faff6c 273 slot->hw_reset = sdhci_pci_int_hw_reset;
728ef3d1
AH		 274 return 0;
275}
276
277static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
278{
279 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
280 return 0;
281}
282
283static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
284 .allow_runtime_pm = true,
285 .probe_slot = byt_emmc_probe_slot,
d61b5946 286 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 287};
288
289static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
b7574bad
GY		 290 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
291 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 292 .allow_runtime_pm = true,
293 .probe_slot = byt_sdio_probe_slot,
294};
295
296static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
b7574bad
GY		 297 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
298 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
7396e318 299 .allow_runtime_pm = true,
77a0122e 300 .own_cd_for_runtime_pm = true,
728ef3d1
AH		 301};
302
8776a165
DC		 303/* Define Host controllers for Intel Merrifield platform */
304#define INTEL_MRFL_EMMC_0 0
305#define INTEL_MRFL_EMMC_1 1
306
307static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
308{
309 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
310 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
311 /* SD support is not ready yet */
312 return -ENODEV;
313
314 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
315 MMC_CAP_1_8V_DDR;
316
317 return 0;
318}
319
320static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
321 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 322 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
323 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
f1b55a55 324 .allow_runtime_pm = true,
8776a165
DC		 325 .probe_slot = intel_mrfl_mmc_probe_slot,
326};
327
26daa1ed
JL		 328/* O2Micro extra registers */
329#define O2_SD_LOCK_WP 0xD3
330#define O2_SD_MULTI_VCC3V 0xEE
331#define O2_SD_CLKREQ 0xEC
332#define O2_SD_CAPS 0xE0
333#define O2_SD_ADMA1 0xE2
334#define O2_SD_ADMA2 0xE7
335#define O2_SD_INF_MOD 0xF1
336
45211e21
PO		 337static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
338{
339 u8 scratch;
340 int ret;
341
342 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
343 if (ret)
344 return ret;
345
346 /*
347 * Turn PMOS on [bit 0], set over current detection to 2.4 V
348 * [bit 1:2] and enable over current debouncing [bit 6].
349 */
350 if (on)
351 scratch |= 0x47;
352 else
353 scratch &= ~0x47;
354
355 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
356 if (ret)
357 return ret;
358
359 return 0;
360}
361
362static int jmicron_probe(struct sdhci_pci_chip *chip)
363{
364 int ret;
8f230f45 365 u16 mmcdev = 0;
45211e21 366
93fc48c7
PO		 367 if (chip->pdev->revision == 0) {
368 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
369 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 370 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 371 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 372 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 373 }
374
4489428a
PO		 375 /*
376 * JMicron chips can have two interfaces to the same hardware
377 * in order to work around limitations in Microsoft's driver.
378 * We need to make sure we only bind to one of them.
379 *
380 * This code assumes two things:
381 *
382 * 1. The PCI code adds subfunctions in order.
383 *
384 * 2. The MMC interface has a lower subfunction number
385 * than the SD interface.
386 */
8f230f45
TI		 387 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
388 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
389 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
390 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
391
392 if (mmcdev) {
4489428a
PO		 393 struct pci_dev *sd_dev;
394
395 sd_dev = NULL;
396 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 397 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 398 if ((PCI_SLOT(chip->pdev->devfn) ==
399 PCI_SLOT(sd_dev->devfn)) &&
400 (chip->pdev->bus == sd_dev->bus))
401 break;
402 }
403
404 if (sd_dev) {
405 pci_dev_put(sd_dev);
406 dev_info(&chip->pdev->dev, "Refusing to bind to "
407 "secondary interface.\n");
408 return -ENODEV;
409 }
410 }
411
45211e21
PO		 412 /*
413 * JMicron chips need a bit of a nudge to enable the power
414 * output pins.
415 */
416 ret = jmicron_pmos(chip, 1);
417 if (ret) {
418 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
419 return ret;
420 }
421
82b0e23a
TI		 422 /* quirk for unsable RO-detection on JM388 chips */
423 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
424 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
425 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
426
45211e21
PO		 427 return 0;
428}
429
4489428a
PO		 430static void jmicron_enable_mmc(struct sdhci_host *host, int on)
431{
432 u8 scratch;
433
434 scratch = readb(host->ioaddr + 0xC0);
435
436 if (on)
437 scratch |= 0x01;
438 else
439 scratch &= ~0x01;
440
441 writeb(scratch, host->ioaddr + 0xC0);
442}
443
444static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
445{
2134a922
PO		 446 if (slot->chip->pdev->revision == 0) {
447 u16 version;
448
449 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
450 version = (version & SDHCI_VENDOR_VER_MASK) >>
451 SDHCI_VENDOR_VER_SHIFT;
452
453 /*
454 * Older versions of the chip have lots of nasty glitches
455 * in the ADMA engine. It's best just to avoid it
456 * completely.
457 */
458 if (version < 0xAC)
459 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
460 }
461
8f230f45
TI		 462 /* JM388 MMC doesn't support 1.8V while SD supports it */
463 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
464 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
465 MMC_VDD_29_30 | MMC_VDD_30_31 |
466 MMC_VDD_165_195; /* allow 1.8V */
467 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
468 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
469 }
470
4489428a
PO		 471 /*
472 * The secondary interface requires a bit set to get the
473 * interrupts.
474 */
8f230f45
TI		 475 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
476 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 477 jmicron_enable_mmc(slot->host, 1);
478
d75c1084
TI		 479 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
480
4489428a
PO		 481 return 0;
482}
483
1e72859e 484static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 485{
1e72859e
PO		 486 if (dead)
487 return;
488
8f230f45
TI		 489 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
490 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 491 jmicron_enable_mmc(slot->host, 0);
492}
493
29495aa0 494static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a
PO		 495{
496 int i;
497
8f230f45
TI		 498 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
499 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 500 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 501 jmicron_enable_mmc(chip->slots[i]->host, 0);
502 }
503
504 return 0;
505}
506
45211e21
PO		 507static int jmicron_resume(struct sdhci_pci_chip *chip)
508{
4489428a
PO		 509 int ret, i;
510
8f230f45
TI		 511 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
512 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 513 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 514 jmicron_enable_mmc(chip->slots[i]->host, 1);
515 }
45211e21
PO		 516
517 ret = jmicron_pmos(chip, 1);
518 if (ret) {
519 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
520 return ret;
521 }
522
523 return 0;
524}
525
26daa1ed 526static const struct sdhci_pci_fixes sdhci_o2 = {
01acf691
AL		 527 .probe = sdhci_pci_o2_probe,
528 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
529 .probe_slot = sdhci_pci_o2_probe_slot,
530 .resume = sdhci_pci_o2_resume,
26daa1ed
JL		 531};
532
22606405 533static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 534 .probe = jmicron_probe,
535
4489428a
PO		 536 .probe_slot = jmicron_probe_slot,
537 .remove_slot = jmicron_remove_slot,
538
539 .suspend = jmicron_suspend,
45211e21 540 .resume = jmicron_resume,
22606405
PO		 541};
542
a7a6186c
NP		 543/* SysKonnect CardBus2SDIO extra registers */
544#define SYSKT_CTRL 0x200
545#define SYSKT_RDFIFO_STAT 0x204
546#define SYSKT_WRFIFO_STAT 0x208
547#define SYSKT_POWER_DATA 0x20c
548#define SYSKT_POWER_330 0xef
549#define SYSKT_POWER_300 0xf8
550#define SYSKT_POWER_184 0xcc
551#define SYSKT_POWER_CMD 0x20d
552#define SYSKT_POWER_START (1 << 7)
553#define SYSKT_POWER_STATUS 0x20e
554#define SYSKT_POWER_STATUS_OK (1 << 0)
555#define SYSKT_BOARD_REV 0x210
556#define SYSKT_CHIP_REV 0x211
557#define SYSKT_CONF_DATA 0x212
558#define SYSKT_CONF_DATA_1V8 (1 << 2)
559#define SYSKT_CONF_DATA_2V5 (1 << 1)
560#define SYSKT_CONF_DATA_3V3 (1 << 0)
561
562static int syskt_probe(struct sdhci_pci_chip *chip)
563{
564 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
565 chip->pdev->class &= ~0x0000FF;
566 chip->pdev->class |= PCI_SDHCI_IFDMA;
567 }
568 return 0;
569}
570
571static int syskt_probe_slot(struct sdhci_pci_slot *slot)
572{
573 int tm, ps;
574
575 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
576 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
577 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
578 "board rev %d.%d, chip rev %d.%d\n",
579 board_rev >> 4, board_rev & 0xf,
580 chip_rev >> 4, chip_rev & 0xf);
581 if (chip_rev >= 0x20)
582 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
583
584 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
585 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
586 udelay(50);
587 tm = 10; /* Wait max 1 ms */
588 do {
589 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
590 if (ps & SYSKT_POWER_STATUS_OK)
591 break;
592 udelay(100);
593 } while (--tm);
594 if (!tm) {
595 dev_err(&slot->chip->pdev->dev,
596 "power regulator never stabilized");
597 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
598 return -ENODEV;
599 }
600
601 return 0;
602}
603
604static const struct sdhci_pci_fixes sdhci_syskt = {
605 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
606 .probe = syskt_probe,
607 .probe_slot = syskt_probe_slot,
608};
609
557b0697
HW		 610static int via_probe(struct sdhci_pci_chip *chip)
611{
612 if (chip->pdev->revision == 0x10)
613 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
614
615 return 0;
616}
617
618static const struct sdhci_pci_fixes sdhci_via = {
619 .probe = via_probe,
620};
621
9107ebbf
MC		 622static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
623{
624 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
625 return 0;
626}
627
628static const struct sdhci_pci_fixes sdhci_rtsx = {
629 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
630 SDHCI_QUIRK2_BROKEN_DDR50,
631 .probe_slot = rtsx_probe_slot,
632};
633
9647f84d 634static const struct pci_device_id pci_ids[] = {
b8c86fc5
PO		 635 {
636 .vendor = PCI_VENDOR_ID_RICOH,
637 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 638 .subvendor = PCI_ANY_ID,
b8c86fc5 639 .subdevice = PCI_ANY_ID,
22606405 640 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 641 },
642
ccc92c23
ML		 643 {
644 .vendor = PCI_VENDOR_ID_RICOH,
645 .device = 0x843,
646 .subvendor = PCI_ANY_ID,
647 .subdevice = PCI_ANY_ID,
648 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
649 },
650
568133eb
PC		 651 {
652 .vendor = PCI_VENDOR_ID_RICOH,
653 .device = 0xe822,
654 .subvendor = PCI_ANY_ID,
655 .subdevice = PCI_ANY_ID,
656 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
657 },
658
5fd11c07
MI		 659 {
660 .vendor = PCI_VENDOR_ID_RICOH,
661 .device = 0xe823,
662 .subvendor = PCI_ANY_ID,
663 .subdevice = PCI_ANY_ID,
664 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
665 },
666
b8c86fc5
PO		 667 {
668 .vendor = PCI_VENDOR_ID_ENE,
669 .device = PCI_DEVICE_ID_ENE_CB712_SD,
670 .subvendor = PCI_ANY_ID,
671 .subdevice = PCI_ANY_ID,
22606405 672 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 673 },
674
675 {
676 .vendor = PCI_VENDOR_ID_ENE,
677 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
678 .subvendor = PCI_ANY_ID,
679 .subdevice = PCI_ANY_ID,
22606405 680 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 681 },
682
683 {
684 .vendor = PCI_VENDOR_ID_ENE,
685 .device = PCI_DEVICE_ID_ENE_CB714_SD,
686 .subvendor = PCI_ANY_ID,
687 .subdevice = PCI_ANY_ID,
22606405 688 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 689 },
690
691 {
692 .vendor = PCI_VENDOR_ID_ENE,
693 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
694 .subvendor = PCI_ANY_ID,
695 .subdevice = PCI_ANY_ID,
22606405 696 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 697 },
698
699 {
700 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 701 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 702 .subvendor = PCI_ANY_ID,
703 .subdevice = PCI_ANY_ID,
22606405 704 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 705 },
706
707 {
708 .vendor = PCI_VENDOR_ID_JMICRON,
709 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
710 .subvendor = PCI_ANY_ID,
711 .subdevice = PCI_ANY_ID,
22606405 712 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 713 },
714
4489428a
PO		 715 {
716 .vendor = PCI_VENDOR_ID_JMICRON,
717 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
718 .subvendor = PCI_ANY_ID,
719 .subdevice = PCI_ANY_ID,
720 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 721 },
722
723 {
724 .vendor = PCI_VENDOR_ID_JMICRON,
725 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
726 .subvendor = PCI_ANY_ID,
727 .subdevice = PCI_ANY_ID,
728 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
729 },
730
731 {
732 .vendor = PCI_VENDOR_ID_JMICRON,
733 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
734 .subvendor = PCI_ANY_ID,
735 .subdevice = PCI_ANY_ID,
736 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 737 },
738
a7a6186c
NP		 739 {
740 .vendor = PCI_VENDOR_ID_SYSKONNECT,
741 .device = 0x8000,
742 .subvendor = PCI_ANY_ID,
743 .subdevice = PCI_ANY_ID,
744 .driver_data = (kernel_ulong_t)&sdhci_syskt,
745 },
746
557b0697
HW		 747 {
748 .vendor = PCI_VENDOR_ID_VIA,
749 .device = 0x95d0,
750 .subvendor = PCI_ANY_ID,
751 .subdevice = PCI_ANY_ID,
752 .driver_data = (kernel_ulong_t)&sdhci_via,
9107ebbf
MC		 753 },
754
755 {
756 .vendor = PCI_VENDOR_ID_REALTEK,
757 .device = 0x5250,
758 .subvendor = PCI_ANY_ID,
759 .subdevice = PCI_ANY_ID,
760 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
557b0697
HW		 761 },
762
43e968ce
DB		 763 {
764 .vendor = PCI_VENDOR_ID_INTEL,
765 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
766 .subvendor = PCI_ANY_ID,
767 .subdevice = PCI_ANY_ID,
768 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
769 },
770
29229052
XS		 771 {
772 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 773 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
774 .subvendor = PCI_ANY_ID,
775 .subdevice = PCI_ANY_ID,
776 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
777 },
778
779 {
780 .vendor = PCI_VENDOR_ID_INTEL,
781 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
782 .subvendor = PCI_ANY_ID,
783 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 784 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
785 },
786
787 {
788 .vendor = PCI_VENDOR_ID_INTEL,
789 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
790 .subvendor = PCI_ANY_ID,
791 .subdevice = PCI_ANY_ID,
792 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 793 },
794
795 {
796 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 797 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
798 .subvendor = PCI_ANY_ID,
799 .subdevice = PCI_ANY_ID,
800 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
801 },
802
803 {
804 .vendor = PCI_VENDOR_ID_INTEL,
805 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
806 .subvendor = PCI_ANY_ID,
807 .subdevice = PCI_ANY_ID,
0d013bcf 808 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 809 },
810
811 {
812 .vendor = PCI_VENDOR_ID_INTEL,
813 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
814 .subvendor = PCI_ANY_ID,
815 .subdevice = PCI_ANY_ID,
0d013bcf 816 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 817 },
818
819 {
820 .vendor = PCI_VENDOR_ID_INTEL,
821 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
822 .subvendor = PCI_ANY_ID,
823 .subdevice = PCI_ANY_ID,
0d013bcf 824 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 825 },
826
827 {
828 .vendor = PCI_VENDOR_ID_INTEL,
829 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
830 .subvendor = PCI_ANY_ID,
831 .subdevice = PCI_ANY_ID,
0d013bcf 832 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 833 },
834
296e0b03
AS		 835 {
836 .vendor = PCI_VENDOR_ID_INTEL,
837 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
838 .subvendor = PCI_ANY_ID,
839 .subdevice = PCI_ANY_ID,
840 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
841 },
842
843 {
844 .vendor = PCI_VENDOR_ID_INTEL,
845 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
846 .subvendor = PCI_ANY_ID,
847 .subdevice = PCI_ANY_ID,
848 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
849 },
850
728ef3d1
AH		 851 {
852 .vendor = PCI_VENDOR_ID_INTEL,
853 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
854 .subvendor = PCI_ANY_ID,
855 .subdevice = PCI_ANY_ID,
856 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
857 },
858
859 {
860 .vendor = PCI_VENDOR_ID_INTEL,
861 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
862 .subvendor = PCI_ANY_ID,
863 .subdevice = PCI_ANY_ID,
864 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
865 },
866
867 {
868 .vendor = PCI_VENDOR_ID_INTEL,
869 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
870 .subvendor = PCI_ANY_ID,
871 .subdevice = PCI_ANY_ID,
872 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
873 },
874
30d025c0
AH		 875 {
876 .vendor = PCI_VENDOR_ID_INTEL,
877 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
878 .subvendor = PCI_ANY_ID,
879 .subdevice = PCI_ANY_ID,
880 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
881 },
882
066173b6
AC		 883 {
884 .vendor = PCI_VENDOR_ID_INTEL,
885 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
886 .subvendor = PCI_ANY_ID,
887 .subdevice = PCI_ANY_ID,
888 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
889 },
890
891 {
892 .vendor = PCI_VENDOR_ID_INTEL,
893 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
894 .subvendor = PCI_ANY_ID,
895 .subdevice = PCI_ANY_ID,
896 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
897 },
898
899 {
900 .vendor = PCI_VENDOR_ID_INTEL,
901 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
902 .subvendor = PCI_ANY_ID,
903 .subdevice = PCI_ANY_ID,
904 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
905 },
d052068a
EE		 906
907 {
908 .vendor = PCI_VENDOR_ID_INTEL,
909 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
910 .subvendor = PCI_ANY_ID,
911 .subdevice = PCI_ANY_ID,
912 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
913 },
914
915 {
916 .vendor = PCI_VENDOR_ID_INTEL,
917 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
918 .subvendor = PCI_ANY_ID,
919 .subdevice = PCI_ANY_ID,
920 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
921 },
922
923 {
924 .vendor = PCI_VENDOR_ID_INTEL,
925 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
926 .subvendor = PCI_ANY_ID,
927 .subdevice = PCI_ANY_ID,
928 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
929 },
930
931 {
932 .vendor = PCI_VENDOR_ID_INTEL,
933 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
934 .subvendor = PCI_ANY_ID,
935 .subdevice = PCI_ANY_ID,
936 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
937 },
938
939 {
940 .vendor = PCI_VENDOR_ID_INTEL,
941 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
942 .subvendor = PCI_ANY_ID,
943 .subdevice = PCI_ANY_ID,
944 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
945 },
946
8776a165
DC		 947 {
948 .vendor = PCI_VENDOR_ID_INTEL,
949 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
950 .subvendor = PCI_ANY_ID,
951 .subdevice = PCI_ANY_ID,
952 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
953 },
26daa1ed
JL		 954 {
955 .vendor = PCI_VENDOR_ID_O2,
956 .device = PCI_DEVICE_ID_O2_8120,
957 .subvendor = PCI_ANY_ID,
958 .subdevice = PCI_ANY_ID,
959 .driver_data = (kernel_ulong_t)&sdhci_o2,
960 },
961
962 {
963 .vendor = PCI_VENDOR_ID_O2,
964 .device = PCI_DEVICE_ID_O2_8220,
965 .subvendor = PCI_ANY_ID,
966 .subdevice = PCI_ANY_ID,
967 .driver_data = (kernel_ulong_t)&sdhci_o2,
968 },
969
970 {
971 .vendor = PCI_VENDOR_ID_O2,
972 .device = PCI_DEVICE_ID_O2_8221,
973 .subvendor = PCI_ANY_ID,
974 .subdevice = PCI_ANY_ID,
975 .driver_data = (kernel_ulong_t)&sdhci_o2,
976 },
977
978 {
979 .vendor = PCI_VENDOR_ID_O2,
980 .device = PCI_DEVICE_ID_O2_8320,
981 .subvendor = PCI_ANY_ID,
982 .subdevice = PCI_ANY_ID,
983 .driver_data = (kernel_ulong_t)&sdhci_o2,
984 },
985
986 {
987 .vendor = PCI_VENDOR_ID_O2,
988 .device = PCI_DEVICE_ID_O2_8321,
989 .subvendor = PCI_ANY_ID,
990 .subdevice = PCI_ANY_ID,
991 .driver_data = (kernel_ulong_t)&sdhci_o2,
992 },
993
01acf691
AL		 994 {
995 .vendor = PCI_VENDOR_ID_O2,
996 .device = PCI_DEVICE_ID_O2_FUJIN2,
997 .subvendor = PCI_ANY_ID,
998 .subdevice = PCI_ANY_ID,
999 .driver_data = (kernel_ulong_t)&sdhci_o2,
1000 },
1001
1002 {
1003 .vendor = PCI_VENDOR_ID_O2,
1004 .device = PCI_DEVICE_ID_O2_SDS0,
1005 .subvendor = PCI_ANY_ID,
1006 .subdevice = PCI_ANY_ID,
1007 .driver_data = (kernel_ulong_t)&sdhci_o2,
1008 },
1009
1010 {
1011 .vendor = PCI_VENDOR_ID_O2,
1012 .device = PCI_DEVICE_ID_O2_SDS1,
1013 .subvendor = PCI_ANY_ID,
1014 .subdevice = PCI_ANY_ID,
1015 .driver_data = (kernel_ulong_t)&sdhci_o2,
1016 },
1017
1018 {
1019 .vendor = PCI_VENDOR_ID_O2,
1020 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1021 .subvendor = PCI_ANY_ID,
1022 .subdevice = PCI_ANY_ID,
1023 .driver_data = (kernel_ulong_t)&sdhci_o2,
1024 },
1025
1026 {
1027 .vendor = PCI_VENDOR_ID_O2,
1028 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1029 .subvendor = PCI_ANY_ID,
1030 .subdevice = PCI_ANY_ID,
1031 .driver_data = (kernel_ulong_t)&sdhci_o2,
1032 },
1033
b8c86fc5
PO		 1034 { /* Generic SD host controller */
1035 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1036 },
1037
1038 { /* end: all zeroes */ },
1039};
1040
1041MODULE_DEVICE_TABLE(pci, pci_ids);
1042
b8c86fc5
PO		 1043/*****************************************************************************\
1044 * *
1045 * SDHCI core callbacks *
1046 * *
1047\*****************************************************************************/
1048
1049static int sdhci_pci_enable_dma(struct sdhci_host *host)
1050{
1051 struct sdhci_pci_slot *slot;
1052 struct pci_dev *pdev;
1053 int ret;
1054
1055 slot = sdhci_priv(host);
1056 pdev = slot->chip->pdev;
1057
1058 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1059 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1060 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1061 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1062 "doesn't fully claim to support it.\n");
1063 }
1064
284901a9 1065 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b8c86fc5
PO		 1066 if (ret)
1067 return ret;
1068
1069 pci_set_master(pdev);
1070
1071 return 0;
1072}
1073
2317f56c 1074static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
68077b02
ML		 1075{
1076 u8 ctrl;
1077
1078 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1079
1080 switch (width) {
1081 case MMC_BUS_WIDTH_8:
1082 ctrl |= SDHCI_CTRL_8BITBUS;
1083 ctrl &= ~SDHCI_CTRL_4BITBUS;
1084 break;
1085 case MMC_BUS_WIDTH_4:
1086 ctrl |= SDHCI_CTRL_4BITBUS;
1087 ctrl &= ~SDHCI_CTRL_8BITBUS;
1088 break;
1089 default:
1090 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1091 break;
1092 }
1093
1094 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
68077b02
ML		 1095}
1096
c9faff6c 1097static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1098{
1099 struct sdhci_pci_slot *slot = sdhci_priv(host);
1100 int rst_n_gpio = slot->rst_n_gpio;
1101
1102 if (!gpio_is_valid(rst_n_gpio))
1103 return;
1104 gpio_set_value_cansleep(rst_n_gpio, 0);
1105 /* For eMMC, minimum is 1us but give it 10us for good measure */
1106 udelay(10);
1107 gpio_set_value_cansleep(rst_n_gpio, 1);
1108 /* For eMMC, minimum is 200us but give it 300us for good measure */
1109 usleep_range(300, 1000);
1110}
1111
c9faff6c
AH		 1112static void sdhci_pci_hw_reset(struct sdhci_host *host)
1113{
1114 struct sdhci_pci_slot *slot = sdhci_priv(host);
1115
1116 if (slot->hw_reset)
1117 slot->hw_reset(host);
1118}
1119
c915568d 1120static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1121 .set_clock = sdhci_set_clock,
b8c86fc5 1122 .enable_dma = sdhci_pci_enable_dma,
2317f56c 1123 .set_bus_width = sdhci_pci_set_bus_width,
03231f9b 1124 .reset = sdhci_reset,
96d7b78c 1125 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1126 .hw_reset = sdhci_pci_hw_reset,
b8c86fc5
PO		 1127};
1128
1129/*****************************************************************************\
1130 * *
1131 * Suspend/resume *
1132 * *
1133\*****************************************************************************/
1134
1135#ifdef CONFIG_PM
1136
29495aa0 1137static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1138{
29495aa0 1139 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1140 struct sdhci_pci_chip *chip;
1141 struct sdhci_pci_slot *slot;
5f619704 1142 mmc_pm_flag_t slot_pm_flags;
2f4cbb3d 1143 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 1144 int i, ret;
1145
1146 chip = pci_get_drvdata(pdev);
1147 if (!chip)
1148 return 0;
1149
b177bc91 1150 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1151 slot = chip->slots[i];
1152 if (!slot)
1153 continue;
1154
29495aa0 1155 ret = sdhci_suspend_host(slot->host);
b8c86fc5 1156
b678b91f
AL		 1157 if (ret)
1158 goto err_pci_suspend;
2f4cbb3d 1159
5f619704
DD		 1160 slot_pm_flags = slot->host->mmc->pm_flags;
1161 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1162 sdhci_enable_irq_wakeups(slot->host);
1163
1164 pm_flags |= slot_pm_flags;
b8c86fc5
PO		 1165 }
1166
4489428a 1167 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1168 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1169 if (ret)
1170 goto err_pci_suspend;
4489428a
PO		 1171 }
1172
2f4cbb3d 1173 if (pm_flags & MMC_PM_KEEP_POWER) {
6b91f2d4
CD		 1174 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1175 device_init_wakeup(dev, true);
1176 else
1177 device_init_wakeup(dev, false);
1178 } else
1179 device_init_wakeup(dev, false);
b8c86fc5
PO		 1180
1181 return 0;
b678b91f
AL		 1182
1183err_pci_suspend:
1184 while (--i >= 0)
1185 sdhci_resume_host(chip->slots[i]->host);
1186 return ret;
b8c86fc5
PO		 1187}
1188
29495aa0 1189static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1190{
29495aa0 1191 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1192 struct sdhci_pci_chip *chip;
1193 struct sdhci_pci_slot *slot;
1194 int i, ret;
1195
1196 chip = pci_get_drvdata(pdev);
1197 if (!chip)
1198 return 0;
1199
45211e21
PO		 1200 if (chip->fixes && chip->fixes->resume) {
1201 ret = chip->fixes->resume(chip);
1202 if (ret)
1203 return ret;
1204 }
1205
b177bc91 1206 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1207 slot = chip->slots[i];
1208 if (!slot)
1209 continue;
1210
1211 ret = sdhci_resume_host(slot->host);
1212 if (ret)
1213 return ret;
1214 }
1215
1216 return 0;
1217}
1218
1219#else /* CONFIG_PM */
1220
1221#define sdhci_pci_suspend NULL
1222#define sdhci_pci_resume NULL
1223
1224#endif /* CONFIG_PM */
1225
66fd8ad5
AH		 1226#ifdef CONFIG_PM_RUNTIME
1227
1228static int sdhci_pci_runtime_suspend(struct device *dev)
1229{
1230 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1231 struct sdhci_pci_chip *chip;
1232 struct sdhci_pci_slot *slot;
66fd8ad5
AH		 1233 int i, ret;
1234
1235 chip = pci_get_drvdata(pdev);
1236 if (!chip)
1237 return 0;
1238
1239 for (i = 0; i < chip->num_slots; i++) {
1240 slot = chip->slots[i];
1241 if (!slot)
1242 continue;
1243
1244 ret = sdhci_runtime_suspend_host(slot->host);
1245
b678b91f
AL		 1246 if (ret)
1247 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1248 }
1249
1250 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1251 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1252 if (ret)
1253 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1254 }
1255
1256 return 0;
b678b91f
AL		 1257
1258err_pci_runtime_suspend:
1259 while (--i >= 0)
1260 sdhci_runtime_resume_host(chip->slots[i]->host);
1261 return ret;
66fd8ad5
AH		 1262}
1263
1264static int sdhci_pci_runtime_resume(struct device *dev)
1265{
1266 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1267 struct sdhci_pci_chip *chip;
1268 struct sdhci_pci_slot *slot;
1269 int i, ret;
1270
1271 chip = pci_get_drvdata(pdev);
1272 if (!chip)
1273 return 0;
1274
1275 if (chip->fixes && chip->fixes->resume) {
1276 ret = chip->fixes->resume(chip);
1277 if (ret)
1278 return ret;
1279 }
1280
1281 for (i = 0; i < chip->num_slots; i++) {
1282 slot = chip->slots[i];
1283 if (!slot)
1284 continue;
1285
1286 ret = sdhci_runtime_resume_host(slot->host);
1287 if (ret)
1288 return ret;
1289 }
1290
1291 return 0;
1292}
1293
1294static int sdhci_pci_runtime_idle(struct device *dev)
1295{
1296 return 0;
1297}
1298
66fd8ad5
AH		 1299#endif
1300
1301static const struct dev_pm_ops sdhci_pci_pm_ops = {
29495aa0
ML		 1302 .suspend = sdhci_pci_suspend,
1303 .resume = sdhci_pci_resume,
f3a92b1a
PG		 1304 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1305 sdhci_pci_runtime_resume, sdhci_pci_runtime_idle)
66fd8ad5
AH		 1306};
1307
b8c86fc5
PO		 1308/*****************************************************************************\
1309 * *
1310 * Device probing/removal *
1311 * *
1312\*****************************************************************************/
1313
c3be1efd 1314static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1315 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1316 int slotno)
b8c86fc5
PO		 1317{
1318 struct sdhci_pci_slot *slot;
1319 struct sdhci_host *host;
52c506f0 1320 int ret, bar = first_bar + slotno;
b8c86fc5
PO		 1321
1322 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1323 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1324 return ERR_PTR(-ENODEV);
1325 }
1326
90b3e6c5 1327 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1328 dev_err(&pdev->dev, "Invalid iomem size. You may "
1329 "experience problems.\n");
1330 }
1331
1332 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1333 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1334 return ERR_PTR(-ENODEV);
1335 }
1336
1337 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1338 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1339 return ERR_PTR(-ENODEV);
1340 }
1341
1342 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1343 if (IS_ERR(host)) {
c60a32cd 1344 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1345 return ERR_CAST(host);
b8c86fc5
PO		 1346 }
1347
1348 slot = sdhci_priv(host);
1349
1350 slot->chip = chip;
1351 slot->host = host;
1352 slot->pci_bar = bar;
0f201655 1353 slot->rst_n_gpio = -EINVAL;
c5e027a4 1354 slot->cd_gpio = -EINVAL;
b8c86fc5 1355
52c506f0
AH		 1356 /* Retrieve platform data if there is any */
1357 if (*sdhci_pci_get_data)
1358 slot->data = sdhci_pci_get_data(pdev, slotno);
1359
1360 if (slot->data) {
1361 if (slot->data->setup) {
1362 ret = slot->data->setup(slot->data);
1363 if (ret) {
1364 dev_err(&pdev->dev, "platform setup failed\n");
1365 goto free;
1366 }
1367 }
c5e027a4
AH		 1368 slot->rst_n_gpio = slot->data->rst_n_gpio;
1369 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1370 }
1371
b8c86fc5
PO		 1372 host->hw_name = "PCI";
1373 host->ops = &sdhci_pci_ops;
1374 host->quirks = chip->quirks;
f3c55a7b 1375 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1376
1377 host->irq = pdev->irq;
1378
1379 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1380 if (ret) {
1381 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1382 goto cleanup;
b8c86fc5
PO		 1383 }
1384
092f82ed 1385 host->ioaddr = pci_ioremap_bar(pdev, bar);
b8c86fc5
PO		 1386 if (!host->ioaddr) {
1387 dev_err(&pdev->dev, "failed to remap registers\n");
9fdcdbb0 1388 ret = -ENOMEM;
b8c86fc5
PO		 1389 goto release;
1390 }
1391
4489428a
PO		 1392 if (chip->fixes && chip->fixes->probe_slot) {
1393 ret = chip->fixes->probe_slot(slot);
1394 if (ret)
1395 goto unmap;
1396 }
1397
c5e027a4
AH		 1398 if (gpio_is_valid(slot->rst_n_gpio)) {
1399 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1400 gpio_direction_output(slot->rst_n_gpio, 1);
1401 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1402 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1403 } else {
1404 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1405 slot->rst_n_gpio = -EINVAL;
1406 }
1407 }
1408
2f4cbb3d 1409 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
eed222ac 1410 host->mmc->slotno = slotno;
a08b17be 1411 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1412
b8c86fc5
PO		 1413 ret = sdhci_add_host(host);
1414 if (ret)
4489428a 1415 goto remove;
b8c86fc5 1416
c5e027a4
AH		 1417 sdhci_pci_add_own_cd(slot);
1418
77a0122e
AH		 1419 /*
1420 * Check if the chip needs a separate GPIO for card detect to wake up
1421 * from runtime suspend. If it is not there, don't allow runtime PM.
1422 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1423 */
945be38c
AH		 1424 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1425 !gpio_is_valid(slot->cd_gpio))
77a0122e
AH		 1426 chip->allow_runtime_pm = false;
1427
b8c86fc5
PO		 1428 return slot;
1429
4489428a 1430remove:
c5e027a4
AH		 1431 if (gpio_is_valid(slot->rst_n_gpio))
1432 gpio_free(slot->rst_n_gpio);
1433
4489428a 1434 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1435 chip->fixes->remove_slot(slot, 0);
4489428a 1436
b8c86fc5
PO		 1437unmap:
1438 iounmap(host->ioaddr);
1439
1440release:
1441 pci_release_region(pdev, bar);
c60a32cd 1442
52c506f0
AH		 1443cleanup:
1444 if (slot->data && slot->data->cleanup)
1445 slot->data->cleanup(slot->data);
1446
c60a32cd 1447free:
b8c86fc5
PO		 1448 sdhci_free_host(host);
1449
1450 return ERR_PTR(ret);
1451}
1452
1453static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1454{
1e72859e
PO		 1455 int dead;
1456 u32 scratch;
1457
c5e027a4
AH		 1458 sdhci_pci_remove_own_cd(slot);
1459
1e72859e
PO		 1460 dead = 0;
1461 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1462 if (scratch == (u32)-1)
1463 dead = 1;
1464
1465 sdhci_remove_host(slot->host, dead);
4489428a 1466
c5e027a4
AH		 1467 if (gpio_is_valid(slot->rst_n_gpio))
1468 gpio_free(slot->rst_n_gpio);
1469
4489428a 1470 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1471 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1472
52c506f0
AH		 1473 if (slot->data && slot->data->cleanup)
1474 slot->data->cleanup(slot->data);
1475
b8c86fc5 1476 pci_release_region(slot->chip->pdev, slot->pci_bar);
4489428a 1477
b8c86fc5
PO		 1478 sdhci_free_host(slot->host);
1479}
1480
c3be1efd 1481static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5
AH		 1482{
1483 pm_runtime_put_noidle(dev);
1484 pm_runtime_allow(dev);
1485 pm_runtime_set_autosuspend_delay(dev, 50);
1486 pm_runtime_use_autosuspend(dev);
1487 pm_suspend_ignore_children(dev, 1);
1488}
1489
6e0ee714 1490static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 1491{
1492 pm_runtime_forbid(dev);
1493 pm_runtime_get_noresume(dev);
1494}
1495
c3be1efd 1496static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 1497 const struct pci_device_id *ent)
1498{
1499 struct sdhci_pci_chip *chip;
1500 struct sdhci_pci_slot *slot;
1501
cf5e23e1 1502 u8 slots, first_bar;
b8c86fc5
PO		 1503 int ret, i;
1504
1505 BUG_ON(pdev == NULL);
1506 BUG_ON(ent == NULL);
1507
b8c86fc5 1508 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1509 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1510
1511 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1512 if (ret)
1513 return ret;
1514
1515 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1516 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1517 if (slots == 0)
1518 return -ENODEV;
1519
1520 BUG_ON(slots > MAX_SLOTS);
1521
1522 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1523 if (ret)
1524 return ret;
1525
1526 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1527
1528 if (first_bar > 5) {
1529 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1530 return -ENODEV;
1531 }
1532
1533 ret = pci_enable_device(pdev);
1534 if (ret)
1535 return ret;
1536
1537 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1538 if (!chip) {
1539 ret = -ENOMEM;
1540 goto err;
1541 }
1542
1543 chip->pdev = pdev;
b177bc91 1544 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1545 if (chip->fixes) {
22606405 1546 chip->quirks = chip->fixes->quirks;
f3c55a7b 1547 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 1548 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1549 }
b8c86fc5
PO		 1550 chip->num_slots = slots;
1551
1552 pci_set_drvdata(pdev, chip);
1553
22606405
PO		 1554 if (chip->fixes && chip->fixes->probe) {
1555 ret = chip->fixes->probe(chip);
1556 if (ret)
1557 goto free;
1558 }
1559
225d85fe
AC		 1560 slots = chip->num_slots; /* Quirk may have changed this */
1561
b177bc91 1562 for (i = 0; i < slots; i++) {
52c506f0 1563 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 1564 if (IS_ERR(slot)) {
b177bc91 1565 for (i--; i >= 0; i--)
b8c86fc5
PO		 1566 sdhci_pci_remove_slot(chip->slots[i]);
1567 ret = PTR_ERR(slot);
1568 goto free;
1569 }
1570
1571 chip->slots[i] = slot;
1572 }
1573
c43fd774
AH		 1574 if (chip->allow_runtime_pm)
1575 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 1576
b8c86fc5
PO		 1577 return 0;
1578
1579free:
1580 pci_set_drvdata(pdev, NULL);
1581 kfree(chip);
1582
1583err:
1584 pci_disable_device(pdev);
1585 return ret;
1586}
1587
6e0ee714 1588static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 1589{
1590 int i;
1591 struct sdhci_pci_chip *chip;
1592
1593 chip = pci_get_drvdata(pdev);
1594
1595 if (chip) {
c43fd774
AH		 1596 if (chip->allow_runtime_pm)
1597 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1598
b177bc91 1599 for (i = 0; i < chip->num_slots; i++)
b8c86fc5
PO		 1600 sdhci_pci_remove_slot(chip->slots[i]);
1601
1602 pci_set_drvdata(pdev, NULL);
1603 kfree(chip);
1604 }
1605
1606 pci_disable_device(pdev);
1607}
1608
1609static struct pci_driver sdhci_driver = {
b177bc91 1610 .name = "sdhci-pci",
b8c86fc5 1611 .id_table = pci_ids,
b177bc91 1612 .probe = sdhci_pci_probe,
0433c143 1613 .remove = sdhci_pci_remove,
66fd8ad5
AH		 1614 .driver = {
1615 .pm = &sdhci_pci_pm_ops
1616 },
b8c86fc5
PO		 1617};
1618
acc69646 1619module_pci_driver(sdhci_driver);
b8c86fc5 1620
32710e8f 1621MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1622MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1623MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)