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mmc: dw_mmc-pltfm: Remove superflous #else condition on CONFIG_PM_SLEEP
[linux-2.6-block.git] / drivers / mmc / host / sdhci-pci.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
88b47679 17#include <linux/module.h>
b8c86fc5
PO		 18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
ccc92c23 21#include <linux/device.h>
b8c86fc5 22#include <linux/mmc/host.h>
b177bc91
AP		 23#include <linux/scatterlist.h>
24#include <linux/io.h>
0f201655 25#include <linux/gpio.h>
66fd8ad5 26#include <linux/pm_runtime.h>
52c506f0 27#include <linux/mmc/sdhci-pci-data.h>
b8c86fc5
PO		 28
29#include "sdhci.h"
522624f9 30#include "sdhci-pci.h"
01acf691 31#include "sdhci-pci-o2micro.h"
22606405
PO		 32
33/*****************************************************************************\
34 * *
35 * Hardware specific quirk handling *
36 * *
37\*****************************************************************************/
38
39static int ricoh_probe(struct sdhci_pci_chip *chip)
40{
c99436fb
CB		 41 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
42 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 43 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 44 return 0;
45}
46
47static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
48{
49 slot->host->caps =
50 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
51 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 52
ccc92c23
ML		 53 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
54 & SDHCI_CLOCK_BASE_MASK) |
55
56 SDHCI_TIMEOUT_CLK_UNIT |
57 SDHCI_CAN_VDD_330 |
1a1f1f04 58 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 59 SDHCI_CAN_DO_SDMA;
60 return 0;
61}
62
63static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
64{
65 /* Apply a delay to allow controller to settle */
66 /* Otherwise it becomes confused if card state changed
67 during suspend */
68 msleep(500);
22606405
PO		 69 return 0;
70}
71
72static const struct sdhci_pci_fixes sdhci_ricoh = {
73 .probe = ricoh_probe,
84938294
VK		 74 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
75 SDHCI_QUIRK_FORCE_DMA |
76 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 77};
78
ccc92c23
ML		 79static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
80 .probe_slot = ricoh_mmc_probe_slot,
81 .resume = ricoh_mmc_resume,
82 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
83 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
84 SDHCI_QUIRK_NO_CARD_NO_RESET |
85 SDHCI_QUIRK_MISSING_CAPS
86};
87
22606405
PO		 88static const struct sdhci_pci_fixes sdhci_ene_712 = {
89 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
90 SDHCI_QUIRK_BROKEN_DMA,
91};
92
93static const struct sdhci_pci_fixes sdhci_ene_714 = {
94 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
95 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
96 SDHCI_QUIRK_BROKEN_DMA,
97};
98
99static const struct sdhci_pci_fixes sdhci_cafe = {
100 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 101 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 102 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 103 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 104};
105
43e968ce
DB		 106static const struct sdhci_pci_fixes sdhci_intel_qrk = {
107 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
108};
109
68077b02
ML		 110static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
111{
112 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
113 return 0;
114}
115
f9ee3eab
AC		 116/*
117 * ADMA operation is disabled for Moorestown platform due to
118 * hardware bugs.
119 */
35ac6f08 120static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 121{
122 /*
35ac6f08
JP		 123 * slots number is fixed here for MRST as SDIO3/5 are never used and
124 * have hardware bugs.
f9ee3eab
AC		 125 */
126 chip->num_slots = 1;
127 return 0;
128}
129
296e0b03
AS		 130static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
131{
132 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
133 return 0;
134}
135
66fd8ad5
AH		 136#ifdef CONFIG_PM_RUNTIME
137
c5e027a4 138static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 139{
140 struct sdhci_pci_slot *slot = dev_id;
141 struct sdhci_host *host = slot->host;
142
143 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
144 return IRQ_HANDLED;
145}
146
c5e027a4 147static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 148{
c5e027a4 149 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 150
151 slot->cd_gpio = -EINVAL;
152 slot->cd_irq = -EINVAL;
153
c5e027a4
AH		 154 if (!gpio_is_valid(gpio))
155 return;
156
66fd8ad5
AH		 157 err = gpio_request(gpio, "sd_cd");
158 if (err < 0)
159 goto out;
160
161 err = gpio_direction_input(gpio);
162 if (err < 0)
163 goto out_free;
164
165 irq = gpio_to_irq(gpio);
166 if (irq < 0)
167 goto out_free;
168
c5e027a4 169 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 170 IRQF_TRIGGER_FALLING, "sd_cd", slot);
171 if (err)
172 goto out_free;
173
174 slot->cd_gpio = gpio;
175 slot->cd_irq = irq;
66fd8ad5 176
c5e027a4 177 return;
66fd8ad5
AH		 178
179out_free:
180 gpio_free(gpio);
181out:
182 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 183}
184
c5e027a4 185static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 186{
187 if (slot->cd_irq >= 0)
188 free_irq(slot->cd_irq, slot);
c5e027a4
AH		 189 if (gpio_is_valid(slot->cd_gpio))
190 gpio_free(slot->cd_gpio);
66fd8ad5
AH		 191}
192
193#else
194
c5e027a4
AH		 195static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
196{
197}
198
199static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
200{
201}
66fd8ad5
AH		 202
203#endif
204
0d013bcf
AH		 205static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
206{
66fd8ad5 207 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
da721cf7
AH		 208 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
209 MMC_CAP2_HC_ERASE_SZ;
0d013bcf
AH		 210 return 0;
211}
212
93933508
AH		 213static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
214{
012e4671 215 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 216 return 0;
217}
218
f9ee3eab
AC		 219static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
220 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 221 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 222};
223
35ac6f08 224static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 225 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 226 .probe = mrst_hc_probe,
f9ee3eab
AC		 227};
228
29229052
XS		 229static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
230 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 231 .allow_runtime_pm = true,
77a0122e 232 .own_cd_for_runtime_pm = true,
29229052
XS		 233};
234
0d013bcf
AH		 235static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
236 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 237 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 238 .allow_runtime_pm = true,
93933508 239 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 240};
241
242static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 243 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 244 .allow_runtime_pm = true,
0d013bcf 245 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 246};
247
296e0b03
AS		 248static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
249 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
250 .probe_slot = pch_hc_probe_slot,
251};
252
c9faff6c
AH		 253static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
254{
255 u8 reg;
256
257 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
258 reg |= 0x10;
259 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
260 /* For eMMC, minimum is 1us but give it 9us for good measure */
261 udelay(9);
262 reg &= ~0x10;
263 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
264 /* For eMMC, minimum is 200us but give it 300us for good measure */
265 usleep_range(300, 1000);
266}
267
728ef3d1
AH		 268static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
269{
c9faff6c 270 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
f25c3372 271 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR;
728ef3d1 272 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
c9faff6c 273 slot->hw_reset = sdhci_pci_int_hw_reset;
728ef3d1
AH		 274 return 0;
275}
276
277static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
278{
279 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
280 return 0;
281}
282
283static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
284 .allow_runtime_pm = true,
285 .probe_slot = byt_emmc_probe_slot,
d61b5946 286 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 287};
288
289static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
290 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
291 .allow_runtime_pm = true,
292 .probe_slot = byt_sdio_probe_slot,
293};
294
295static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
7396e318
AH		 296 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON,
297 .allow_runtime_pm = true,
77a0122e 298 .own_cd_for_runtime_pm = true,
728ef3d1
AH		 299};
300
8776a165
DC		 301/* Define Host controllers for Intel Merrifield platform */
302#define INTEL_MRFL_EMMC_0 0
303#define INTEL_MRFL_EMMC_1 1
304
305static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
306{
307 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
308 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
309 /* SD support is not ready yet */
310 return -ENODEV;
311
312 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
313 MMC_CAP_1_8V_DDR;
314
315 return 0;
316}
317
318static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
319 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
390145f9 320 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200,
8776a165
DC		 321 .probe_slot = intel_mrfl_mmc_probe_slot,
322};
323
26daa1ed
JL		 324/* O2Micro extra registers */
325#define O2_SD_LOCK_WP 0xD3
326#define O2_SD_MULTI_VCC3V 0xEE
327#define O2_SD_CLKREQ 0xEC
328#define O2_SD_CAPS 0xE0
329#define O2_SD_ADMA1 0xE2
330#define O2_SD_ADMA2 0xE7
331#define O2_SD_INF_MOD 0xF1
332
45211e21
PO		 333static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
334{
335 u8 scratch;
336 int ret;
337
338 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
339 if (ret)
340 return ret;
341
342 /*
343 * Turn PMOS on [bit 0], set over current detection to 2.4 V
344 * [bit 1:2] and enable over current debouncing [bit 6].
345 */
346 if (on)
347 scratch |= 0x47;
348 else
349 scratch &= ~0x47;
350
351 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
352 if (ret)
353 return ret;
354
355 return 0;
356}
357
358static int jmicron_probe(struct sdhci_pci_chip *chip)
359{
360 int ret;
8f230f45 361 u16 mmcdev = 0;
45211e21 362
93fc48c7
PO		 363 if (chip->pdev->revision == 0) {
364 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
365 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 366 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 367 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 368 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 369 }
370
4489428a
PO		 371 /*
372 * JMicron chips can have two interfaces to the same hardware
373 * in order to work around limitations in Microsoft's driver.
374 * We need to make sure we only bind to one of them.
375 *
376 * This code assumes two things:
377 *
378 * 1. The PCI code adds subfunctions in order.
379 *
380 * 2. The MMC interface has a lower subfunction number
381 * than the SD interface.
382 */
8f230f45
TI		 383 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
384 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
385 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
386 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
387
388 if (mmcdev) {
4489428a
PO		 389 struct pci_dev *sd_dev;
390
391 sd_dev = NULL;
392 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 393 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 394 if ((PCI_SLOT(chip->pdev->devfn) ==
395 PCI_SLOT(sd_dev->devfn)) &&
396 (chip->pdev->bus == sd_dev->bus))
397 break;
398 }
399
400 if (sd_dev) {
401 pci_dev_put(sd_dev);
402 dev_info(&chip->pdev->dev, "Refusing to bind to "
403 "secondary interface.\n");
404 return -ENODEV;
405 }
406 }
407
45211e21
PO		 408 /*
409 * JMicron chips need a bit of a nudge to enable the power
410 * output pins.
411 */
412 ret = jmicron_pmos(chip, 1);
413 if (ret) {
414 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
415 return ret;
416 }
417
82b0e23a
TI		 418 /* quirk for unsable RO-detection on JM388 chips */
419 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
420 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
421 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
422
45211e21
PO		 423 return 0;
424}
425
4489428a
PO		 426static void jmicron_enable_mmc(struct sdhci_host *host, int on)
427{
428 u8 scratch;
429
430 scratch = readb(host->ioaddr + 0xC0);
431
432 if (on)
433 scratch |= 0x01;
434 else
435 scratch &= ~0x01;
436
437 writeb(scratch, host->ioaddr + 0xC0);
438}
439
440static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
441{
2134a922
PO		 442 if (slot->chip->pdev->revision == 0) {
443 u16 version;
444
445 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
446 version = (version & SDHCI_VENDOR_VER_MASK) >>
447 SDHCI_VENDOR_VER_SHIFT;
448
449 /*
450 * Older versions of the chip have lots of nasty glitches
451 * in the ADMA engine. It's best just to avoid it
452 * completely.
453 */
454 if (version < 0xAC)
455 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
456 }
457
8f230f45
TI		 458 /* JM388 MMC doesn't support 1.8V while SD supports it */
459 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
460 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
461 MMC_VDD_29_30 | MMC_VDD_30_31 |
462 MMC_VDD_165_195; /* allow 1.8V */
463 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
464 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
465 }
466
4489428a
PO		 467 /*
468 * The secondary interface requires a bit set to get the
469 * interrupts.
470 */
8f230f45
TI		 471 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
472 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 473 jmicron_enable_mmc(slot->host, 1);
474
d75c1084
TI		 475 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
476
4489428a
PO		 477 return 0;
478}
479
1e72859e 480static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 481{
1e72859e
PO		 482 if (dead)
483 return;
484
8f230f45
TI		 485 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
486 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 487 jmicron_enable_mmc(slot->host, 0);
488}
489
29495aa0 490static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a
PO		 491{
492 int i;
493
8f230f45
TI		 494 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
495 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 496 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 497 jmicron_enable_mmc(chip->slots[i]->host, 0);
498 }
499
500 return 0;
501}
502
45211e21
PO		 503static int jmicron_resume(struct sdhci_pci_chip *chip)
504{
4489428a
PO		 505 int ret, i;
506
8f230f45
TI		 507 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
508 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 509 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 510 jmicron_enable_mmc(chip->slots[i]->host, 1);
511 }
45211e21
PO		 512
513 ret = jmicron_pmos(chip, 1);
514 if (ret) {
515 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
516 return ret;
517 }
518
519 return 0;
520}
521
26daa1ed 522static const struct sdhci_pci_fixes sdhci_o2 = {
01acf691
AL		 523 .probe = sdhci_pci_o2_probe,
524 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
525 .probe_slot = sdhci_pci_o2_probe_slot,
526 .resume = sdhci_pci_o2_resume,
26daa1ed
JL		 527};
528
22606405 529static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 530 .probe = jmicron_probe,
531
4489428a
PO		 532 .probe_slot = jmicron_probe_slot,
533 .remove_slot = jmicron_remove_slot,
534
535 .suspend = jmicron_suspend,
45211e21 536 .resume = jmicron_resume,
22606405
PO		 537};
538
a7a6186c
NP		 539/* SysKonnect CardBus2SDIO extra registers */
540#define SYSKT_CTRL 0x200
541#define SYSKT_RDFIFO_STAT 0x204
542#define SYSKT_WRFIFO_STAT 0x208
543#define SYSKT_POWER_DATA 0x20c
544#define SYSKT_POWER_330 0xef
545#define SYSKT_POWER_300 0xf8
546#define SYSKT_POWER_184 0xcc
547#define SYSKT_POWER_CMD 0x20d
548#define SYSKT_POWER_START (1 << 7)
549#define SYSKT_POWER_STATUS 0x20e
550#define SYSKT_POWER_STATUS_OK (1 << 0)
551#define SYSKT_BOARD_REV 0x210
552#define SYSKT_CHIP_REV 0x211
553#define SYSKT_CONF_DATA 0x212
554#define SYSKT_CONF_DATA_1V8 (1 << 2)
555#define SYSKT_CONF_DATA_2V5 (1 << 1)
556#define SYSKT_CONF_DATA_3V3 (1 << 0)
557
558static int syskt_probe(struct sdhci_pci_chip *chip)
559{
560 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
561 chip->pdev->class &= ~0x0000FF;
562 chip->pdev->class |= PCI_SDHCI_IFDMA;
563 }
564 return 0;
565}
566
567static int syskt_probe_slot(struct sdhci_pci_slot *slot)
568{
569 int tm, ps;
570
571 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
572 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
573 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
574 "board rev %d.%d, chip rev %d.%d\n",
575 board_rev >> 4, board_rev & 0xf,
576 chip_rev >> 4, chip_rev & 0xf);
577 if (chip_rev >= 0x20)
578 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
579
580 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
581 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
582 udelay(50);
583 tm = 10; /* Wait max 1 ms */
584 do {
585 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
586 if (ps & SYSKT_POWER_STATUS_OK)
587 break;
588 udelay(100);
589 } while (--tm);
590 if (!tm) {
591 dev_err(&slot->chip->pdev->dev,
592 "power regulator never stabilized");
593 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
594 return -ENODEV;
595 }
596
597 return 0;
598}
599
600static const struct sdhci_pci_fixes sdhci_syskt = {
601 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
602 .probe = syskt_probe,
603 .probe_slot = syskt_probe_slot,
604};
605
557b0697
HW		 606static int via_probe(struct sdhci_pci_chip *chip)
607{
608 if (chip->pdev->revision == 0x10)
609 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
610
611 return 0;
612}
613
614static const struct sdhci_pci_fixes sdhci_via = {
615 .probe = via_probe,
616};
617
9107ebbf
MC		 618static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
619{
620 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
621 return 0;
622}
623
624static const struct sdhci_pci_fixes sdhci_rtsx = {
625 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
626 SDHCI_QUIRK2_BROKEN_DDR50,
627 .probe_slot = rtsx_probe_slot,
628};
629
9647f84d 630static const struct pci_device_id pci_ids[] = {
b8c86fc5
PO		 631 {
632 .vendor = PCI_VENDOR_ID_RICOH,
633 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 634 .subvendor = PCI_ANY_ID,
b8c86fc5 635 .subdevice = PCI_ANY_ID,
22606405 636 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 637 },
638
ccc92c23
ML		 639 {
640 .vendor = PCI_VENDOR_ID_RICOH,
641 .device = 0x843,
642 .subvendor = PCI_ANY_ID,
643 .subdevice = PCI_ANY_ID,
644 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
645 },
646
568133eb
PC		 647 {
648 .vendor = PCI_VENDOR_ID_RICOH,
649 .device = 0xe822,
650 .subvendor = PCI_ANY_ID,
651 .subdevice = PCI_ANY_ID,
652 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
653 },
654
5fd11c07
MI		 655 {
656 .vendor = PCI_VENDOR_ID_RICOH,
657 .device = 0xe823,
658 .subvendor = PCI_ANY_ID,
659 .subdevice = PCI_ANY_ID,
660 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
661 },
662
b8c86fc5
PO		 663 {
664 .vendor = PCI_VENDOR_ID_ENE,
665 .device = PCI_DEVICE_ID_ENE_CB712_SD,
666 .subvendor = PCI_ANY_ID,
667 .subdevice = PCI_ANY_ID,
22606405 668 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 669 },
670
671 {
672 .vendor = PCI_VENDOR_ID_ENE,
673 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
674 .subvendor = PCI_ANY_ID,
675 .subdevice = PCI_ANY_ID,
22606405 676 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 677 },
678
679 {
680 .vendor = PCI_VENDOR_ID_ENE,
681 .device = PCI_DEVICE_ID_ENE_CB714_SD,
682 .subvendor = PCI_ANY_ID,
683 .subdevice = PCI_ANY_ID,
22606405 684 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 685 },
686
687 {
688 .vendor = PCI_VENDOR_ID_ENE,
689 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
690 .subvendor = PCI_ANY_ID,
691 .subdevice = PCI_ANY_ID,
22606405 692 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 693 },
694
695 {
696 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 697 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 698 .subvendor = PCI_ANY_ID,
699 .subdevice = PCI_ANY_ID,
22606405 700 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 701 },
702
703 {
704 .vendor = PCI_VENDOR_ID_JMICRON,
705 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
706 .subvendor = PCI_ANY_ID,
707 .subdevice = PCI_ANY_ID,
22606405 708 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 709 },
710
4489428a
PO		 711 {
712 .vendor = PCI_VENDOR_ID_JMICRON,
713 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
714 .subvendor = PCI_ANY_ID,
715 .subdevice = PCI_ANY_ID,
716 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 717 },
718
719 {
720 .vendor = PCI_VENDOR_ID_JMICRON,
721 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
722 .subvendor = PCI_ANY_ID,
723 .subdevice = PCI_ANY_ID,
724 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
725 },
726
727 {
728 .vendor = PCI_VENDOR_ID_JMICRON,
729 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
730 .subvendor = PCI_ANY_ID,
731 .subdevice = PCI_ANY_ID,
732 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 733 },
734
a7a6186c
NP		 735 {
736 .vendor = PCI_VENDOR_ID_SYSKONNECT,
737 .device = 0x8000,
738 .subvendor = PCI_ANY_ID,
739 .subdevice = PCI_ANY_ID,
740 .driver_data = (kernel_ulong_t)&sdhci_syskt,
741 },
742
557b0697
HW		 743 {
744 .vendor = PCI_VENDOR_ID_VIA,
745 .device = 0x95d0,
746 .subvendor = PCI_ANY_ID,
747 .subdevice = PCI_ANY_ID,
748 .driver_data = (kernel_ulong_t)&sdhci_via,
9107ebbf
MC		 749 },
750
751 {
752 .vendor = PCI_VENDOR_ID_REALTEK,
753 .device = 0x5250,
754 .subvendor = PCI_ANY_ID,
755 .subdevice = PCI_ANY_ID,
756 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
557b0697
HW		 757 },
758
43e968ce
DB		 759 {
760 .vendor = PCI_VENDOR_ID_INTEL,
761 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
762 .subvendor = PCI_ANY_ID,
763 .subdevice = PCI_ANY_ID,
764 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
765 },
766
29229052
XS		 767 {
768 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 769 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
770 .subvendor = PCI_ANY_ID,
771 .subdevice = PCI_ANY_ID,
772 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
773 },
774
775 {
776 .vendor = PCI_VENDOR_ID_INTEL,
777 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
778 .subvendor = PCI_ANY_ID,
779 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 780 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
781 },
782
783 {
784 .vendor = PCI_VENDOR_ID_INTEL,
785 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
786 .subvendor = PCI_ANY_ID,
787 .subdevice = PCI_ANY_ID,
788 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 789 },
790
791 {
792 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 793 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
794 .subvendor = PCI_ANY_ID,
795 .subdevice = PCI_ANY_ID,
796 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
797 },
798
799 {
800 .vendor = PCI_VENDOR_ID_INTEL,
801 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
802 .subvendor = PCI_ANY_ID,
803 .subdevice = PCI_ANY_ID,
0d013bcf 804 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 805 },
806
807 {
808 .vendor = PCI_VENDOR_ID_INTEL,
809 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
810 .subvendor = PCI_ANY_ID,
811 .subdevice = PCI_ANY_ID,
0d013bcf 812 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 813 },
814
815 {
816 .vendor = PCI_VENDOR_ID_INTEL,
817 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
818 .subvendor = PCI_ANY_ID,
819 .subdevice = PCI_ANY_ID,
0d013bcf 820 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 821 },
822
823 {
824 .vendor = PCI_VENDOR_ID_INTEL,
825 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
826 .subvendor = PCI_ANY_ID,
827 .subdevice = PCI_ANY_ID,
0d013bcf 828 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 829 },
830
296e0b03
AS		 831 {
832 .vendor = PCI_VENDOR_ID_INTEL,
833 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
834 .subvendor = PCI_ANY_ID,
835 .subdevice = PCI_ANY_ID,
836 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
837 },
838
839 {
840 .vendor = PCI_VENDOR_ID_INTEL,
841 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
842 .subvendor = PCI_ANY_ID,
843 .subdevice = PCI_ANY_ID,
844 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
845 },
846
728ef3d1
AH		 847 {
848 .vendor = PCI_VENDOR_ID_INTEL,
849 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
850 .subvendor = PCI_ANY_ID,
851 .subdevice = PCI_ANY_ID,
852 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
853 },
854
855 {
856 .vendor = PCI_VENDOR_ID_INTEL,
857 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
858 .subvendor = PCI_ANY_ID,
859 .subdevice = PCI_ANY_ID,
860 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
861 },
862
863 {
864 .vendor = PCI_VENDOR_ID_INTEL,
865 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
866 .subvendor = PCI_ANY_ID,
867 .subdevice = PCI_ANY_ID,
868 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
869 },
870
30d025c0
AH		 871 {
872 .vendor = PCI_VENDOR_ID_INTEL,
873 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
874 .subvendor = PCI_ANY_ID,
875 .subdevice = PCI_ANY_ID,
876 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
877 },
878
d052068a
EE		 879
880 {
881 .vendor = PCI_VENDOR_ID_INTEL,
882 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
883 .subvendor = PCI_ANY_ID,
884 .subdevice = PCI_ANY_ID,
885 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
886 },
887
888 {
889 .vendor = PCI_VENDOR_ID_INTEL,
890 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
891 .subvendor = PCI_ANY_ID,
892 .subdevice = PCI_ANY_ID,
893 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
894 },
895
896 {
897 .vendor = PCI_VENDOR_ID_INTEL,
898 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
899 .subvendor = PCI_ANY_ID,
900 .subdevice = PCI_ANY_ID,
901 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
902 },
903
904 {
905 .vendor = PCI_VENDOR_ID_INTEL,
906 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
907 .subvendor = PCI_ANY_ID,
908 .subdevice = PCI_ANY_ID,
909 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
910 },
911
912 {
913 .vendor = PCI_VENDOR_ID_INTEL,
914 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
915 .subvendor = PCI_ANY_ID,
916 .subdevice = PCI_ANY_ID,
917 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
918 },
919
8776a165
DC		 920 {
921 .vendor = PCI_VENDOR_ID_INTEL,
922 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
923 .subvendor = PCI_ANY_ID,
924 .subdevice = PCI_ANY_ID,
925 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
926 },
26daa1ed
JL		 927 {
928 .vendor = PCI_VENDOR_ID_O2,
929 .device = PCI_DEVICE_ID_O2_8120,
930 .subvendor = PCI_ANY_ID,
931 .subdevice = PCI_ANY_ID,
932 .driver_data = (kernel_ulong_t)&sdhci_o2,
933 },
934
935 {
936 .vendor = PCI_VENDOR_ID_O2,
937 .device = PCI_DEVICE_ID_O2_8220,
938 .subvendor = PCI_ANY_ID,
939 .subdevice = PCI_ANY_ID,
940 .driver_data = (kernel_ulong_t)&sdhci_o2,
941 },
942
943 {
944 .vendor = PCI_VENDOR_ID_O2,
945 .device = PCI_DEVICE_ID_O2_8221,
946 .subvendor = PCI_ANY_ID,
947 .subdevice = PCI_ANY_ID,
948 .driver_data = (kernel_ulong_t)&sdhci_o2,
949 },
950
951 {
952 .vendor = PCI_VENDOR_ID_O2,
953 .device = PCI_DEVICE_ID_O2_8320,
954 .subvendor = PCI_ANY_ID,
955 .subdevice = PCI_ANY_ID,
956 .driver_data = (kernel_ulong_t)&sdhci_o2,
957 },
958
959 {
960 .vendor = PCI_VENDOR_ID_O2,
961 .device = PCI_DEVICE_ID_O2_8321,
962 .subvendor = PCI_ANY_ID,
963 .subdevice = PCI_ANY_ID,
964 .driver_data = (kernel_ulong_t)&sdhci_o2,
965 },
966
01acf691
AL		 967 {
968 .vendor = PCI_VENDOR_ID_O2,
969 .device = PCI_DEVICE_ID_O2_FUJIN2,
970 .subvendor = PCI_ANY_ID,
971 .subdevice = PCI_ANY_ID,
972 .driver_data = (kernel_ulong_t)&sdhci_o2,
973 },
974
975 {
976 .vendor = PCI_VENDOR_ID_O2,
977 .device = PCI_DEVICE_ID_O2_SDS0,
978 .subvendor = PCI_ANY_ID,
979 .subdevice = PCI_ANY_ID,
980 .driver_data = (kernel_ulong_t)&sdhci_o2,
981 },
982
983 {
984 .vendor = PCI_VENDOR_ID_O2,
985 .device = PCI_DEVICE_ID_O2_SDS1,
986 .subvendor = PCI_ANY_ID,
987 .subdevice = PCI_ANY_ID,
988 .driver_data = (kernel_ulong_t)&sdhci_o2,
989 },
990
991 {
992 .vendor = PCI_VENDOR_ID_O2,
993 .device = PCI_DEVICE_ID_O2_SEABIRD0,
994 .subvendor = PCI_ANY_ID,
995 .subdevice = PCI_ANY_ID,
996 .driver_data = (kernel_ulong_t)&sdhci_o2,
997 },
998
999 {
1000 .vendor = PCI_VENDOR_ID_O2,
1001 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1002 .subvendor = PCI_ANY_ID,
1003 .subdevice = PCI_ANY_ID,
1004 .driver_data = (kernel_ulong_t)&sdhci_o2,
1005 },
1006
b8c86fc5
PO		 1007 { /* Generic SD host controller */
1008 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1009 },
1010
1011 { /* end: all zeroes */ },
1012};
1013
1014MODULE_DEVICE_TABLE(pci, pci_ids);
1015
b8c86fc5
PO		 1016/*****************************************************************************\
1017 * *
1018 * SDHCI core callbacks *
1019 * *
1020\*****************************************************************************/
1021
1022static int sdhci_pci_enable_dma(struct sdhci_host *host)
1023{
1024 struct sdhci_pci_slot *slot;
1025 struct pci_dev *pdev;
1026 int ret;
1027
1028 slot = sdhci_priv(host);
1029 pdev = slot->chip->pdev;
1030
1031 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1032 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1033 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1034 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1035 "doesn't fully claim to support it.\n");
1036 }
1037
284901a9 1038 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b8c86fc5
PO		 1039 if (ret)
1040 return ret;
1041
1042 pci_set_master(pdev);
1043
1044 return 0;
1045}
1046
2317f56c 1047static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
68077b02
ML		 1048{
1049 u8 ctrl;
1050
1051 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1052
1053 switch (width) {
1054 case MMC_BUS_WIDTH_8:
1055 ctrl |= SDHCI_CTRL_8BITBUS;
1056 ctrl &= ~SDHCI_CTRL_4BITBUS;
1057 break;
1058 case MMC_BUS_WIDTH_4:
1059 ctrl |= SDHCI_CTRL_4BITBUS;
1060 ctrl &= ~SDHCI_CTRL_8BITBUS;
1061 break;
1062 default:
1063 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1064 break;
1065 }
1066
1067 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
68077b02
ML		 1068}
1069
c9faff6c 1070static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1071{
1072 struct sdhci_pci_slot *slot = sdhci_priv(host);
1073 int rst_n_gpio = slot->rst_n_gpio;
1074
1075 if (!gpio_is_valid(rst_n_gpio))
1076 return;
1077 gpio_set_value_cansleep(rst_n_gpio, 0);
1078 /* For eMMC, minimum is 1us but give it 10us for good measure */
1079 udelay(10);
1080 gpio_set_value_cansleep(rst_n_gpio, 1);
1081 /* For eMMC, minimum is 200us but give it 300us for good measure */
1082 usleep_range(300, 1000);
1083}
1084
c9faff6c
AH		 1085static void sdhci_pci_hw_reset(struct sdhci_host *host)
1086{
1087 struct sdhci_pci_slot *slot = sdhci_priv(host);
1088
1089 if (slot->hw_reset)
1090 slot->hw_reset(host);
1091}
1092
c915568d 1093static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1094 .set_clock = sdhci_set_clock,
b8c86fc5 1095 .enable_dma = sdhci_pci_enable_dma,
2317f56c 1096 .set_bus_width = sdhci_pci_set_bus_width,
03231f9b 1097 .reset = sdhci_reset,
96d7b78c 1098 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1099 .hw_reset = sdhci_pci_hw_reset,
b8c86fc5
PO		 1100};
1101
1102/*****************************************************************************\
1103 * *
1104 * Suspend/resume *
1105 * *
1106\*****************************************************************************/
1107
1108#ifdef CONFIG_PM
1109
29495aa0 1110static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1111{
29495aa0 1112 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1113 struct sdhci_pci_chip *chip;
1114 struct sdhci_pci_slot *slot;
5f619704 1115 mmc_pm_flag_t slot_pm_flags;
2f4cbb3d 1116 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 1117 int i, ret;
1118
1119 chip = pci_get_drvdata(pdev);
1120 if (!chip)
1121 return 0;
1122
b177bc91 1123 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1124 slot = chip->slots[i];
1125 if (!slot)
1126 continue;
1127
29495aa0 1128 ret = sdhci_suspend_host(slot->host);
b8c86fc5 1129
b678b91f
AL		 1130 if (ret)
1131 goto err_pci_suspend;
2f4cbb3d 1132
5f619704
DD		 1133 slot_pm_flags = slot->host->mmc->pm_flags;
1134 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1135 sdhci_enable_irq_wakeups(slot->host);
1136
1137 pm_flags |= slot_pm_flags;
b8c86fc5
PO		 1138 }
1139
4489428a 1140 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1141 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1142 if (ret)
1143 goto err_pci_suspend;
4489428a
PO		 1144 }
1145
2f4cbb3d 1146 if (pm_flags & MMC_PM_KEEP_POWER) {
6b91f2d4
CD		 1147 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1148 device_init_wakeup(dev, true);
1149 else
1150 device_init_wakeup(dev, false);
1151 } else
1152 device_init_wakeup(dev, false);
b8c86fc5
PO		 1153
1154 return 0;
b678b91f
AL		 1155
1156err_pci_suspend:
1157 while (--i >= 0)
1158 sdhci_resume_host(chip->slots[i]->host);
1159 return ret;
b8c86fc5
PO		 1160}
1161
29495aa0 1162static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1163{
29495aa0 1164 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1165 struct sdhci_pci_chip *chip;
1166 struct sdhci_pci_slot *slot;
1167 int i, ret;
1168
1169 chip = pci_get_drvdata(pdev);
1170 if (!chip)
1171 return 0;
1172
45211e21
PO		 1173 if (chip->fixes && chip->fixes->resume) {
1174 ret = chip->fixes->resume(chip);
1175 if (ret)
1176 return ret;
1177 }
1178
b177bc91 1179 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1180 slot = chip->slots[i];
1181 if (!slot)
1182 continue;
1183
1184 ret = sdhci_resume_host(slot->host);
1185 if (ret)
1186 return ret;
1187 }
1188
1189 return 0;
1190}
1191
1192#else /* CONFIG_PM */
1193
1194#define sdhci_pci_suspend NULL
1195#define sdhci_pci_resume NULL
1196
1197#endif /* CONFIG_PM */
1198
66fd8ad5
AH		 1199#ifdef CONFIG_PM_RUNTIME
1200
1201static int sdhci_pci_runtime_suspend(struct device *dev)
1202{
1203 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1204 struct sdhci_pci_chip *chip;
1205 struct sdhci_pci_slot *slot;
66fd8ad5
AH		 1206 int i, ret;
1207
1208 chip = pci_get_drvdata(pdev);
1209 if (!chip)
1210 return 0;
1211
1212 for (i = 0; i < chip->num_slots; i++) {
1213 slot = chip->slots[i];
1214 if (!slot)
1215 continue;
1216
1217 ret = sdhci_runtime_suspend_host(slot->host);
1218
b678b91f
AL		 1219 if (ret)
1220 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1221 }
1222
1223 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1224 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1225 if (ret)
1226 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1227 }
1228
1229 return 0;
b678b91f
AL		 1230
1231err_pci_runtime_suspend:
1232 while (--i >= 0)
1233 sdhci_runtime_resume_host(chip->slots[i]->host);
1234 return ret;
66fd8ad5
AH		 1235}
1236
1237static int sdhci_pci_runtime_resume(struct device *dev)
1238{
1239 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1240 struct sdhci_pci_chip *chip;
1241 struct sdhci_pci_slot *slot;
1242 int i, ret;
1243
1244 chip = pci_get_drvdata(pdev);
1245 if (!chip)
1246 return 0;
1247
1248 if (chip->fixes && chip->fixes->resume) {
1249 ret = chip->fixes->resume(chip);
1250 if (ret)
1251 return ret;
1252 }
1253
1254 for (i = 0; i < chip->num_slots; i++) {
1255 slot = chip->slots[i];
1256 if (!slot)
1257 continue;
1258
1259 ret = sdhci_runtime_resume_host(slot->host);
1260 if (ret)
1261 return ret;
1262 }
1263
1264 return 0;
1265}
1266
1267static int sdhci_pci_runtime_idle(struct device *dev)
1268{
1269 return 0;
1270}
1271
1272#else
1273
1274#define sdhci_pci_runtime_suspend NULL
1275#define sdhci_pci_runtime_resume NULL
1276#define sdhci_pci_runtime_idle NULL
1277
1278#endif
1279
1280static const struct dev_pm_ops sdhci_pci_pm_ops = {
29495aa0
ML		 1281 .suspend = sdhci_pci_suspend,
1282 .resume = sdhci_pci_resume,
66fd8ad5
AH		 1283 .runtime_suspend = sdhci_pci_runtime_suspend,
1284 .runtime_resume = sdhci_pci_runtime_resume,
1285 .runtime_idle = sdhci_pci_runtime_idle,
1286};
1287
b8c86fc5
PO		 1288/*****************************************************************************\
1289 * *
1290 * Device probing/removal *
1291 * *
1292\*****************************************************************************/
1293
c3be1efd 1294static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1295 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1296 int slotno)
b8c86fc5
PO		 1297{
1298 struct sdhci_pci_slot *slot;
1299 struct sdhci_host *host;
52c506f0 1300 int ret, bar = first_bar + slotno;
b8c86fc5
PO		 1301
1302 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1303 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1304 return ERR_PTR(-ENODEV);
1305 }
1306
90b3e6c5 1307 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1308 dev_err(&pdev->dev, "Invalid iomem size. You may "
1309 "experience problems.\n");
1310 }
1311
1312 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1313 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1314 return ERR_PTR(-ENODEV);
1315 }
1316
1317 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1318 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1319 return ERR_PTR(-ENODEV);
1320 }
1321
1322 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1323 if (IS_ERR(host)) {
c60a32cd 1324 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1325 return ERR_CAST(host);
b8c86fc5
PO		 1326 }
1327
1328 slot = sdhci_priv(host);
1329
1330 slot->chip = chip;
1331 slot->host = host;
1332 slot->pci_bar = bar;
0f201655 1333 slot->rst_n_gpio = -EINVAL;
c5e027a4 1334 slot->cd_gpio = -EINVAL;
b8c86fc5 1335
52c506f0
AH		 1336 /* Retrieve platform data if there is any */
1337 if (*sdhci_pci_get_data)
1338 slot->data = sdhci_pci_get_data(pdev, slotno);
1339
1340 if (slot->data) {
1341 if (slot->data->setup) {
1342 ret = slot->data->setup(slot->data);
1343 if (ret) {
1344 dev_err(&pdev->dev, "platform setup failed\n");
1345 goto free;
1346 }
1347 }
c5e027a4
AH		 1348 slot->rst_n_gpio = slot->data->rst_n_gpio;
1349 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1350 }
1351
b8c86fc5
PO		 1352 host->hw_name = "PCI";
1353 host->ops = &sdhci_pci_ops;
1354 host->quirks = chip->quirks;
f3c55a7b 1355 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1356
1357 host->irq = pdev->irq;
1358
1359 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1360 if (ret) {
1361 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1362 goto cleanup;
b8c86fc5
PO		 1363 }
1364
092f82ed 1365 host->ioaddr = pci_ioremap_bar(pdev, bar);
b8c86fc5
PO		 1366 if (!host->ioaddr) {
1367 dev_err(&pdev->dev, "failed to remap registers\n");
9fdcdbb0 1368 ret = -ENOMEM;
b8c86fc5
PO		 1369 goto release;
1370 }
1371
4489428a
PO		 1372 if (chip->fixes && chip->fixes->probe_slot) {
1373 ret = chip->fixes->probe_slot(slot);
1374 if (ret)
1375 goto unmap;
1376 }
1377
c5e027a4
AH		 1378 if (gpio_is_valid(slot->rst_n_gpio)) {
1379 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1380 gpio_direction_output(slot->rst_n_gpio, 1);
1381 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1382 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1383 } else {
1384 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1385 slot->rst_n_gpio = -EINVAL;
1386 }
1387 }
1388
2f4cbb3d 1389 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
eed222ac 1390 host->mmc->slotno = slotno;
a08b17be 1391 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1392
b8c86fc5
PO		 1393 ret = sdhci_add_host(host);
1394 if (ret)
4489428a 1395 goto remove;
b8c86fc5 1396
c5e027a4
AH		 1397 sdhci_pci_add_own_cd(slot);
1398
77a0122e
AH		 1399 /*
1400 * Check if the chip needs a separate GPIO for card detect to wake up
1401 * from runtime suspend. If it is not there, don't allow runtime PM.
1402 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1403 */
945be38c
AH		 1404 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1405 !gpio_is_valid(slot->cd_gpio))
77a0122e
AH		 1406 chip->allow_runtime_pm = false;
1407
b8c86fc5
PO		 1408 return slot;
1409
4489428a 1410remove:
c5e027a4
AH		 1411 if (gpio_is_valid(slot->rst_n_gpio))
1412 gpio_free(slot->rst_n_gpio);
1413
4489428a 1414 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1415 chip->fixes->remove_slot(slot, 0);
4489428a 1416
b8c86fc5
PO		 1417unmap:
1418 iounmap(host->ioaddr);
1419
1420release:
1421 pci_release_region(pdev, bar);
c60a32cd 1422
52c506f0
AH		 1423cleanup:
1424 if (slot->data && slot->data->cleanup)
1425 slot->data->cleanup(slot->data);
1426
c60a32cd 1427free:
b8c86fc5
PO		 1428 sdhci_free_host(host);
1429
1430 return ERR_PTR(ret);
1431}
1432
1433static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1434{
1e72859e
PO		 1435 int dead;
1436 u32 scratch;
1437
c5e027a4
AH		 1438 sdhci_pci_remove_own_cd(slot);
1439
1e72859e
PO		 1440 dead = 0;
1441 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1442 if (scratch == (u32)-1)
1443 dead = 1;
1444
1445 sdhci_remove_host(slot->host, dead);
4489428a 1446
c5e027a4
AH		 1447 if (gpio_is_valid(slot->rst_n_gpio))
1448 gpio_free(slot->rst_n_gpio);
1449
4489428a 1450 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1451 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1452
52c506f0
AH		 1453 if (slot->data && slot->data->cleanup)
1454 slot->data->cleanup(slot->data);
1455
b8c86fc5 1456 pci_release_region(slot->chip->pdev, slot->pci_bar);
4489428a 1457
b8c86fc5
PO		 1458 sdhci_free_host(slot->host);
1459}
1460
c3be1efd 1461static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5
AH		 1462{
1463 pm_runtime_put_noidle(dev);
1464 pm_runtime_allow(dev);
1465 pm_runtime_set_autosuspend_delay(dev, 50);
1466 pm_runtime_use_autosuspend(dev);
1467 pm_suspend_ignore_children(dev, 1);
1468}
1469
6e0ee714 1470static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 1471{
1472 pm_runtime_forbid(dev);
1473 pm_runtime_get_noresume(dev);
1474}
1475
c3be1efd 1476static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 1477 const struct pci_device_id *ent)
1478{
1479 struct sdhci_pci_chip *chip;
1480 struct sdhci_pci_slot *slot;
1481
cf5e23e1 1482 u8 slots, first_bar;
b8c86fc5
PO		 1483 int ret, i;
1484
1485 BUG_ON(pdev == NULL);
1486 BUG_ON(ent == NULL);
1487
b8c86fc5 1488 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1489 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1490
1491 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1492 if (ret)
1493 return ret;
1494
1495 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1496 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1497 if (slots == 0)
1498 return -ENODEV;
1499
1500 BUG_ON(slots > MAX_SLOTS);
1501
1502 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1503 if (ret)
1504 return ret;
1505
1506 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1507
1508 if (first_bar > 5) {
1509 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1510 return -ENODEV;
1511 }
1512
1513 ret = pci_enable_device(pdev);
1514 if (ret)
1515 return ret;
1516
1517 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1518 if (!chip) {
1519 ret = -ENOMEM;
1520 goto err;
1521 }
1522
1523 chip->pdev = pdev;
b177bc91 1524 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1525 if (chip->fixes) {
22606405 1526 chip->quirks = chip->fixes->quirks;
f3c55a7b 1527 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 1528 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1529 }
b8c86fc5
PO		 1530 chip->num_slots = slots;
1531
1532 pci_set_drvdata(pdev, chip);
1533
22606405
PO		 1534 if (chip->fixes && chip->fixes->probe) {
1535 ret = chip->fixes->probe(chip);
1536 if (ret)
1537 goto free;
1538 }
1539
225d85fe
AC		 1540 slots = chip->num_slots; /* Quirk may have changed this */
1541
b177bc91 1542 for (i = 0; i < slots; i++) {
52c506f0 1543 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 1544 if (IS_ERR(slot)) {
b177bc91 1545 for (i--; i >= 0; i--)
b8c86fc5
PO		 1546 sdhci_pci_remove_slot(chip->slots[i]);
1547 ret = PTR_ERR(slot);
1548 goto free;
1549 }
1550
1551 chip->slots[i] = slot;
1552 }
1553
c43fd774
AH		 1554 if (chip->allow_runtime_pm)
1555 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 1556
b8c86fc5
PO		 1557 return 0;
1558
1559free:
1560 pci_set_drvdata(pdev, NULL);
1561 kfree(chip);
1562
1563err:
1564 pci_disable_device(pdev);
1565 return ret;
1566}
1567
6e0ee714 1568static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 1569{
1570 int i;
1571 struct sdhci_pci_chip *chip;
1572
1573 chip = pci_get_drvdata(pdev);
1574
1575 if (chip) {
c43fd774
AH		 1576 if (chip->allow_runtime_pm)
1577 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1578
b177bc91 1579 for (i = 0; i < chip->num_slots; i++)
b8c86fc5
PO		 1580 sdhci_pci_remove_slot(chip->slots[i]);
1581
1582 pci_set_drvdata(pdev, NULL);
1583 kfree(chip);
1584 }
1585
1586 pci_disable_device(pdev);
1587}
1588
1589static struct pci_driver sdhci_driver = {
b177bc91 1590 .name = "sdhci-pci",
b8c86fc5 1591 .id_table = pci_ids,
b177bc91 1592 .probe = sdhci_pci_probe,
0433c143 1593 .remove = sdhci_pci_remove,
66fd8ad5
AH		 1594 .driver = {
1595 .pm = &sdhci_pci_pm_ops
1596 },
b8c86fc5
PO		 1597};
1598
acc69646 1599module_pci_driver(sdhci_driver);
b8c86fc5 1600
32710e8f 1601MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1602MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1603MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)