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Merge branch 'for-linus' of git://git.kernel.dk/linux-block
[linux-2.6-block.git] / drivers / mmc / host / sdhci-pci.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
88b47679 17#include <linux/module.h>
b8c86fc5
PO		 18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
ccc92c23 21#include <linux/device.h>
b8c86fc5 22#include <linux/mmc/host.h>
e1bfad6d 23#include <linux/mmc/mmc.h>
b177bc91
AP		 24#include <linux/scatterlist.h>
25#include <linux/io.h>
0f201655 26#include <linux/gpio.h>
66fd8ad5 27#include <linux/pm_runtime.h>
ff59c520 28#include <linux/mmc/slot-gpio.h>
52c506f0 29#include <linux/mmc/sdhci-pci-data.h>
b8c86fc5
PO		 30
31#include "sdhci.h"
522624f9 32#include "sdhci-pci.h"
01acf691 33#include "sdhci-pci-o2micro.h"
22606405
PO		 34
35/*****************************************************************************\
36 * *
37 * Hardware specific quirk handling *
38 * *
39\*****************************************************************************/
40
41static int ricoh_probe(struct sdhci_pci_chip *chip)
42{
c99436fb
CB		 43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 46 return 0;
47}
48
49static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
50{
51 slot->host->caps =
52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
53 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 54
ccc92c23
ML		 55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
56 & SDHCI_CLOCK_BASE_MASK) |
57
58 SDHCI_TIMEOUT_CLK_UNIT |
59 SDHCI_CAN_VDD_330 |
1a1f1f04 60 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 61 SDHCI_CAN_DO_SDMA;
62 return 0;
63}
64
65static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
66{
67 /* Apply a delay to allow controller to settle */
68 /* Otherwise it becomes confused if card state changed
69 during suspend */
70 msleep(500);
22606405
PO		 71 return 0;
72}
73
74static const struct sdhci_pci_fixes sdhci_ricoh = {
75 .probe = ricoh_probe,
84938294
VK		 76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
77 SDHCI_QUIRK_FORCE_DMA |
78 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 79};
80
ccc92c23
ML		 81static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
82 .probe_slot = ricoh_mmc_probe_slot,
83 .resume = ricoh_mmc_resume,
84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
85 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
86 SDHCI_QUIRK_NO_CARD_NO_RESET |
87 SDHCI_QUIRK_MISSING_CAPS
88};
89
22606405
PO		 90static const struct sdhci_pci_fixes sdhci_ene_712 = {
91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
92 SDHCI_QUIRK_BROKEN_DMA,
93};
94
95static const struct sdhci_pci_fixes sdhci_ene_714 = {
96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
98 SDHCI_QUIRK_BROKEN_DMA,
99};
100
101static const struct sdhci_pci_fixes sdhci_cafe = {
102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 103 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 104 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 106};
107
43e968ce
DB		 108static const struct sdhci_pci_fixes sdhci_intel_qrk = {
109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
110};
111
68077b02
ML		 112static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
113{
114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
115 return 0;
116}
117
f9ee3eab
AC		 118/*
119 * ADMA operation is disabled for Moorestown platform due to
120 * hardware bugs.
121 */
35ac6f08 122static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 123{
124 /*
35ac6f08
JP		 125 * slots number is fixed here for MRST as SDIO3/5 are never used and
126 * have hardware bugs.
f9ee3eab
AC		 127 */
128 chip->num_slots = 1;
129 return 0;
130}
131
296e0b03
AS		 132static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
133{
134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
135 return 0;
136}
137
162d6f98 138#ifdef CONFIG_PM
66fd8ad5 139
c5e027a4 140static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 141{
142 struct sdhci_pci_slot *slot = dev_id;
143 struct sdhci_host *host = slot->host;
144
145 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
146 return IRQ_HANDLED;
147}
148
c5e027a4 149static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 150{
c5e027a4 151 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 152
153 slot->cd_gpio = -EINVAL;
154 slot->cd_irq = -EINVAL;
155
c5e027a4
AH		 156 if (!gpio_is_valid(gpio))
157 return;
158
66fd8ad5
AH		 159 err = gpio_request(gpio, "sd_cd");
160 if (err < 0)
161 goto out;
162
163 err = gpio_direction_input(gpio);
164 if (err < 0)
165 goto out_free;
166
167 irq = gpio_to_irq(gpio);
168 if (irq < 0)
169 goto out_free;
170
c5e027a4 171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 172 IRQF_TRIGGER_FALLING, "sd_cd", slot);
173 if (err)
174 goto out_free;
175
176 slot->cd_gpio = gpio;
177 slot->cd_irq = irq;
66fd8ad5 178
c5e027a4 179 return;
66fd8ad5
AH		 180
181out_free:
182 gpio_free(gpio);
183out:
184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 185}
186
c5e027a4 187static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 188{
189 if (slot->cd_irq >= 0)
190 free_irq(slot->cd_irq, slot);
c5e027a4
AH		 191 if (gpio_is_valid(slot->cd_gpio))
192 gpio_free(slot->cd_gpio);
66fd8ad5
AH		 193}
194
195#else
196
c5e027a4
AH		 197static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
198{
199}
200
201static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
202{
203}
66fd8ad5
AH		 204
205#endif
206
0d013bcf
AH		 207static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
208{
66fd8ad5 209 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
da721cf7
AH		 210 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
211 MMC_CAP2_HC_ERASE_SZ;
0d013bcf
AH		 212 return 0;
213}
214
93933508
AH		 215static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
216{
012e4671 217 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 218 return 0;
219}
220
f9ee3eab
AC		 221static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
222 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 223 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 224};
225
35ac6f08 226static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 227 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 228 .probe = mrst_hc_probe,
f9ee3eab
AC		 229};
230
29229052
XS		 231static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
232 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 233 .allow_runtime_pm = true,
77a0122e 234 .own_cd_for_runtime_pm = true,
29229052
XS		 235};
236
0d013bcf
AH		 237static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
238 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 239 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 240 .allow_runtime_pm = true,
93933508 241 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 242};
243
244static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 246 .allow_runtime_pm = true,
0d013bcf 247 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 248};
249
296e0b03
AS		 250static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
251 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
252 .probe_slot = pch_hc_probe_slot,
253};
254
c9faff6c
AH		 255static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
256{
257 u8 reg;
258
259 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
260 reg |= 0x10;
261 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
262 /* For eMMC, minimum is 1us but give it 9us for good measure */
263 udelay(9);
264 reg &= ~0x10;
265 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
266 /* For eMMC, minimum is 200us but give it 300us for good measure */
267 usleep_range(300, 1000);
268}
269
e1bfad6d
AH		 270static int spt_select_drive_strength(struct sdhci_host *host,
271 struct mmc_card *card,
272 unsigned int max_dtr,
273 int host_drv, int card_drv, int *drv_type)
274{
275 int drive_strength;
276
277 if (sdhci_pci_spt_drive_strength > 0)
278 drive_strength = sdhci_pci_spt_drive_strength & 0xf;
279 else
280 drive_strength = 1; /* 33-ohm */
281
282 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0)
283 drive_strength = 0; /* Default 50-ohm */
284
285 return drive_strength;
286}
287
288/* Try to read the drive strength from the card */
289static void spt_read_drive_strength(struct sdhci_host *host)
290{
291 u32 val, i, t;
292 u16 m;
293
294 if (sdhci_pci_spt_drive_strength)
295 return;
296
297 sdhci_pci_spt_drive_strength = -1;
298
299 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7;
300 if (m != 3 && m != 5)
301 return;
302 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
303 if (val & 0x3)
304 return;
305 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE);
306 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
307 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE);
308 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
309 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE);
310 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
311 sdhci_writel(host, 0, SDHCI_ARGUMENT);
312 sdhci_writew(host, 0x83b, SDHCI_COMMAND);
313 for (i = 0; i < 1000; i++) {
314 val = sdhci_readl(host, SDHCI_INT_STATUS);
315 if (val & 0xffff8000)
316 return;
317 if (val & 0x20)
318 break;
319 udelay(1);
320 }
321 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
322 if (!(val & 0x800))
323 return;
324 for (i = 0; i < 47; i++)
325 val = sdhci_readl(host, SDHCI_BUFFER);
326 t = val & 0xf00;
327 if (t != 0x200 && t != 0x300)
328 return;
329
330 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf);
331}
332
728ef3d1
AH		 333static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
334{
c9faff6c 335 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
6aab23a8
AH		 336 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
337 MMC_CAP_BUS_WIDTH_TEST |
338 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1 339 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
c9faff6c 340 slot->hw_reset = sdhci_pci_int_hw_reset;
a06586b6
AH		 341 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
342 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
e1bfad6d
AH		 343 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) {
344 spt_read_drive_strength(slot->host);
345 slot->select_drive_strength = spt_select_drive_strength;
346 }
728ef3d1
AH		 347 return 0;
348}
349
350static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
351{
6aab23a8
AH		 352 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
353 MMC_CAP_BUS_WIDTH_TEST |
354 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1
AH		 355 return 0;
356}
357
ff59c520
AH		 358static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
359{
6aab23a8
AH		 360 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
361 MMC_CAP_WAIT_WHILE_BUSY;
ff59c520
AH		 362 slot->cd_con_id = NULL;
363 slot->cd_idx = 0;
364 slot->cd_override_level = true;
365 return 0;
366}
367
728ef3d1
AH		 368static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
369 .allow_runtime_pm = true,
370 .probe_slot = byt_emmc_probe_slot,
db6e8cdf 371 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
e58e4a0d 372 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
b69587e2 373 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
e58e4a0d 374 SDHCI_QUIRK2_STOP_WITH_TC,
728ef3d1
AH		 375};
376
377static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
db6e8cdf 378 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 379 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
380 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 381 .allow_runtime_pm = true,
382 .probe_slot = byt_sdio_probe_slot,
383};
384
385static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
db6e8cdf 386 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad 387 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
e58e4a0d
AH		 388 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
389 SDHCI_QUIRK2_STOP_WITH_TC,
7396e318 390 .allow_runtime_pm = true,
77a0122e 391 .own_cd_for_runtime_pm = true,
ff59c520 392 .probe_slot = byt_sd_probe_slot,
728ef3d1
AH		 393};
394
8776a165
DC		 395/* Define Host controllers for Intel Merrifield platform */
396#define INTEL_MRFL_EMMC_0 0
397#define INTEL_MRFL_EMMC_1 1
398
399static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
400{
401 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
402 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
403 /* SD support is not ready yet */
404 return -ENODEV;
405
406 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
407 MMC_CAP_1_8V_DDR;
408
409 return 0;
410}
411
412static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
413 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 414 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
415 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
f1b55a55 416 .allow_runtime_pm = true,
8776a165
DC		 417 .probe_slot = intel_mrfl_mmc_probe_slot,
418};
419
26daa1ed
JL		 420/* O2Micro extra registers */
421#define O2_SD_LOCK_WP 0xD3
422#define O2_SD_MULTI_VCC3V 0xEE
423#define O2_SD_CLKREQ 0xEC
424#define O2_SD_CAPS 0xE0
425#define O2_SD_ADMA1 0xE2
426#define O2_SD_ADMA2 0xE7
427#define O2_SD_INF_MOD 0xF1
428
45211e21
PO		 429static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
430{
431 u8 scratch;
432 int ret;
433
434 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
435 if (ret)
436 return ret;
437
438 /*
439 * Turn PMOS on [bit 0], set over current detection to 2.4 V
440 * [bit 1:2] and enable over current debouncing [bit 6].
441 */
442 if (on)
443 scratch |= 0x47;
444 else
445 scratch &= ~0x47;
446
447 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
448 if (ret)
449 return ret;
450
451 return 0;
452}
453
454static int jmicron_probe(struct sdhci_pci_chip *chip)
455{
456 int ret;
8f230f45 457 u16 mmcdev = 0;
45211e21 458
93fc48c7
PO		 459 if (chip->pdev->revision == 0) {
460 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
461 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 462 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 463 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 464 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 465 }
466
4489428a
PO		 467 /*
468 * JMicron chips can have two interfaces to the same hardware
469 * in order to work around limitations in Microsoft's driver.
470 * We need to make sure we only bind to one of them.
471 *
472 * This code assumes two things:
473 *
474 * 1. The PCI code adds subfunctions in order.
475 *
476 * 2. The MMC interface has a lower subfunction number
477 * than the SD interface.
478 */
8f230f45
TI		 479 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
480 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
481 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
482 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
483
484 if (mmcdev) {
4489428a
PO		 485 struct pci_dev *sd_dev;
486
487 sd_dev = NULL;
488 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 489 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 490 if ((PCI_SLOT(chip->pdev->devfn) ==
491 PCI_SLOT(sd_dev->devfn)) &&
492 (chip->pdev->bus == sd_dev->bus))
493 break;
494 }
495
496 if (sd_dev) {
497 pci_dev_put(sd_dev);
498 dev_info(&chip->pdev->dev, "Refusing to bind to "
499 "secondary interface.\n");
500 return -ENODEV;
501 }
502 }
503
45211e21
PO		 504 /*
505 * JMicron chips need a bit of a nudge to enable the power
506 * output pins.
507 */
508 ret = jmicron_pmos(chip, 1);
509 if (ret) {
510 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
511 return ret;
512 }
513
82b0e23a
TI		 514 /* quirk for unsable RO-detection on JM388 chips */
515 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
516 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
517 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
518
45211e21
PO		 519 return 0;
520}
521
4489428a
PO		 522static void jmicron_enable_mmc(struct sdhci_host *host, int on)
523{
524 u8 scratch;
525
526 scratch = readb(host->ioaddr + 0xC0);
527
528 if (on)
529 scratch |= 0x01;
530 else
531 scratch &= ~0x01;
532
533 writeb(scratch, host->ioaddr + 0xC0);
534}
535
536static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
537{
2134a922
PO		 538 if (slot->chip->pdev->revision == 0) {
539 u16 version;
540
541 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
542 version = (version & SDHCI_VENDOR_VER_MASK) >>
543 SDHCI_VENDOR_VER_SHIFT;
544
545 /*
546 * Older versions of the chip have lots of nasty glitches
547 * in the ADMA engine. It's best just to avoid it
548 * completely.
549 */
550 if (version < 0xAC)
551 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
552 }
553
8f230f45
TI		 554 /* JM388 MMC doesn't support 1.8V while SD supports it */
555 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
556 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
557 MMC_VDD_29_30 | MMC_VDD_30_31 |
558 MMC_VDD_165_195; /* allow 1.8V */
559 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
560 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
561 }
562
4489428a
PO		 563 /*
564 * The secondary interface requires a bit set to get the
565 * interrupts.
566 */
8f230f45
TI		 567 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
568 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 569 jmicron_enable_mmc(slot->host, 1);
570
d75c1084
TI		 571 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
572
4489428a
PO		 573 return 0;
574}
575
1e72859e 576static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 577{
1e72859e
PO		 578 if (dead)
579 return;
580
8f230f45
TI		 581 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
582 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 583 jmicron_enable_mmc(slot->host, 0);
584}
585
29495aa0 586static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a
PO		 587{
588 int i;
589
8f230f45
TI		 590 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
591 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 592 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 593 jmicron_enable_mmc(chip->slots[i]->host, 0);
594 }
595
596 return 0;
597}
598
45211e21
PO		 599static int jmicron_resume(struct sdhci_pci_chip *chip)
600{
4489428a
PO		 601 int ret, i;
602
8f230f45
TI		 603 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
604 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 605 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 606 jmicron_enable_mmc(chip->slots[i]->host, 1);
607 }
45211e21
PO		 608
609 ret = jmicron_pmos(chip, 1);
610 if (ret) {
611 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
612 return ret;
613 }
614
615 return 0;
616}
617
26daa1ed 618static const struct sdhci_pci_fixes sdhci_o2 = {
01acf691
AL		 619 .probe = sdhci_pci_o2_probe,
620 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
621 .probe_slot = sdhci_pci_o2_probe_slot,
622 .resume = sdhci_pci_o2_resume,
26daa1ed
JL		 623};
624
22606405 625static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 626 .probe = jmicron_probe,
627
4489428a
PO		 628 .probe_slot = jmicron_probe_slot,
629 .remove_slot = jmicron_remove_slot,
630
631 .suspend = jmicron_suspend,
45211e21 632 .resume = jmicron_resume,
22606405
PO		 633};
634
a7a6186c
NP		 635/* SysKonnect CardBus2SDIO extra registers */
636#define SYSKT_CTRL 0x200
637#define SYSKT_RDFIFO_STAT 0x204
638#define SYSKT_WRFIFO_STAT 0x208
639#define SYSKT_POWER_DATA 0x20c
640#define SYSKT_POWER_330 0xef
641#define SYSKT_POWER_300 0xf8
642#define SYSKT_POWER_184 0xcc
643#define SYSKT_POWER_CMD 0x20d
644#define SYSKT_POWER_START (1 << 7)
645#define SYSKT_POWER_STATUS 0x20e
646#define SYSKT_POWER_STATUS_OK (1 << 0)
647#define SYSKT_BOARD_REV 0x210
648#define SYSKT_CHIP_REV 0x211
649#define SYSKT_CONF_DATA 0x212
650#define SYSKT_CONF_DATA_1V8 (1 << 2)
651#define SYSKT_CONF_DATA_2V5 (1 << 1)
652#define SYSKT_CONF_DATA_3V3 (1 << 0)
653
654static int syskt_probe(struct sdhci_pci_chip *chip)
655{
656 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
657 chip->pdev->class &= ~0x0000FF;
658 chip->pdev->class |= PCI_SDHCI_IFDMA;
659 }
660 return 0;
661}
662
663static int syskt_probe_slot(struct sdhci_pci_slot *slot)
664{
665 int tm, ps;
666
667 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
668 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
669 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
670 "board rev %d.%d, chip rev %d.%d\n",
671 board_rev >> 4, board_rev & 0xf,
672 chip_rev >> 4, chip_rev & 0xf);
673 if (chip_rev >= 0x20)
674 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
675
676 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
677 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
678 udelay(50);
679 tm = 10; /* Wait max 1 ms */
680 do {
681 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
682 if (ps & SYSKT_POWER_STATUS_OK)
683 break;
684 udelay(100);
685 } while (--tm);
686 if (!tm) {
687 dev_err(&slot->chip->pdev->dev,
688 "power regulator never stabilized");
689 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
690 return -ENODEV;
691 }
692
693 return 0;
694}
695
696static const struct sdhci_pci_fixes sdhci_syskt = {
697 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
698 .probe = syskt_probe,
699 .probe_slot = syskt_probe_slot,
700};
701
557b0697
HW		 702static int via_probe(struct sdhci_pci_chip *chip)
703{
704 if (chip->pdev->revision == 0x10)
705 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
706
707 return 0;
708}
709
710static const struct sdhci_pci_fixes sdhci_via = {
711 .probe = via_probe,
712};
713
9107ebbf
MC		 714static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
715{
716 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
717 return 0;
718}
719
720static const struct sdhci_pci_fixes sdhci_rtsx = {
721 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
e30b978f 722 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
9107ebbf
MC		 723 SDHCI_QUIRK2_BROKEN_DDR50,
724 .probe_slot = rtsx_probe_slot,
725};
726
b5e97d6e
VW		 727/*AMD chipset generation*/
728enum amd_chipset_gen {
729 AMD_CHIPSET_BEFORE_ML,
730 AMD_CHIPSET_CZ,
731 AMD_CHIPSET_NL,
732 AMD_CHIPSET_UNKNOWN,
733};
734
d44f88da
VW		 735static int amd_probe(struct sdhci_pci_chip *chip)
736{
737 struct pci_dev *smbus_dev;
b5e97d6e 738 enum amd_chipset_gen gen;
d44f88da
VW		 739
740 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
741 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
b5e97d6e
VW		 742 if (smbus_dev) {
743 gen = AMD_CHIPSET_BEFORE_ML;
744 } else {
745 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
746 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
747 if (smbus_dev) {
748 if (smbus_dev->revision < 0x51)
749 gen = AMD_CHIPSET_CZ;
750 else
751 gen = AMD_CHIPSET_NL;
752 } else {
753 gen = AMD_CHIPSET_UNKNOWN;
754 }
755 }
d44f88da 756
b5e97d6e 757 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) {
d44f88da 758 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
e765bfa2
VW		 759 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
760 }
d44f88da
VW		 761
762 return 0;
763}
764
765static const struct sdhci_pci_fixes sdhci_amd = {
766 .probe = amd_probe,
767};
768
9647f84d 769static const struct pci_device_id pci_ids[] = {
b8c86fc5
PO		 770 {
771 .vendor = PCI_VENDOR_ID_RICOH,
772 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 773 .subvendor = PCI_ANY_ID,
b8c86fc5 774 .subdevice = PCI_ANY_ID,
22606405 775 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 776 },
777
ccc92c23
ML		 778 {
779 .vendor = PCI_VENDOR_ID_RICOH,
780 .device = 0x843,
781 .subvendor = PCI_ANY_ID,
782 .subdevice = PCI_ANY_ID,
783 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
784 },
785
568133eb
PC		 786 {
787 .vendor = PCI_VENDOR_ID_RICOH,
788 .device = 0xe822,
789 .subvendor = PCI_ANY_ID,
790 .subdevice = PCI_ANY_ID,
791 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
792 },
793
5fd11c07
MI		 794 {
795 .vendor = PCI_VENDOR_ID_RICOH,
796 .device = 0xe823,
797 .subvendor = PCI_ANY_ID,
798 .subdevice = PCI_ANY_ID,
799 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
800 },
801
b8c86fc5
PO		 802 {
803 .vendor = PCI_VENDOR_ID_ENE,
804 .device = PCI_DEVICE_ID_ENE_CB712_SD,
805 .subvendor = PCI_ANY_ID,
806 .subdevice = PCI_ANY_ID,
22606405 807 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 808 },
809
810 {
811 .vendor = PCI_VENDOR_ID_ENE,
812 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
813 .subvendor = PCI_ANY_ID,
814 .subdevice = PCI_ANY_ID,
22606405 815 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 816 },
817
818 {
819 .vendor = PCI_VENDOR_ID_ENE,
820 .device = PCI_DEVICE_ID_ENE_CB714_SD,
821 .subvendor = PCI_ANY_ID,
822 .subdevice = PCI_ANY_ID,
22606405 823 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 824 },
825
826 {
827 .vendor = PCI_VENDOR_ID_ENE,
828 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
829 .subvendor = PCI_ANY_ID,
830 .subdevice = PCI_ANY_ID,
22606405 831 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 832 },
833
834 {
835 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 836 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 837 .subvendor = PCI_ANY_ID,
838 .subdevice = PCI_ANY_ID,
22606405 839 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 840 },
841
842 {
843 .vendor = PCI_VENDOR_ID_JMICRON,
844 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
845 .subvendor = PCI_ANY_ID,
846 .subdevice = PCI_ANY_ID,
22606405 847 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 848 },
849
4489428a
PO		 850 {
851 .vendor = PCI_VENDOR_ID_JMICRON,
852 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
853 .subvendor = PCI_ANY_ID,
854 .subdevice = PCI_ANY_ID,
855 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 856 },
857
858 {
859 .vendor = PCI_VENDOR_ID_JMICRON,
860 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
861 .subvendor = PCI_ANY_ID,
862 .subdevice = PCI_ANY_ID,
863 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
864 },
865
866 {
867 .vendor = PCI_VENDOR_ID_JMICRON,
868 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
869 .subvendor = PCI_ANY_ID,
870 .subdevice = PCI_ANY_ID,
871 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 872 },
873
a7a6186c
NP		 874 {
875 .vendor = PCI_VENDOR_ID_SYSKONNECT,
876 .device = 0x8000,
877 .subvendor = PCI_ANY_ID,
878 .subdevice = PCI_ANY_ID,
879 .driver_data = (kernel_ulong_t)&sdhci_syskt,
880 },
881
557b0697
HW		 882 {
883 .vendor = PCI_VENDOR_ID_VIA,
884 .device = 0x95d0,
885 .subvendor = PCI_ANY_ID,
886 .subdevice = PCI_ANY_ID,
887 .driver_data = (kernel_ulong_t)&sdhci_via,
9107ebbf
MC		 888 },
889
890 {
891 .vendor = PCI_VENDOR_ID_REALTEK,
892 .device = 0x5250,
893 .subvendor = PCI_ANY_ID,
894 .subdevice = PCI_ANY_ID,
895 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
557b0697
HW		 896 },
897
43e968ce
DB		 898 {
899 .vendor = PCI_VENDOR_ID_INTEL,
900 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
901 .subvendor = PCI_ANY_ID,
902 .subdevice = PCI_ANY_ID,
903 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
904 },
905
29229052
XS		 906 {
907 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 908 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
909 .subvendor = PCI_ANY_ID,
910 .subdevice = PCI_ANY_ID,
911 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
912 },
913
914 {
915 .vendor = PCI_VENDOR_ID_INTEL,
916 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
917 .subvendor = PCI_ANY_ID,
918 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 919 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
920 },
921
922 {
923 .vendor = PCI_VENDOR_ID_INTEL,
924 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
925 .subvendor = PCI_ANY_ID,
926 .subdevice = PCI_ANY_ID,
927 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 928 },
929
930 {
931 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 932 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
933 .subvendor = PCI_ANY_ID,
934 .subdevice = PCI_ANY_ID,
935 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
936 },
937
938 {
939 .vendor = PCI_VENDOR_ID_INTEL,
940 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
941 .subvendor = PCI_ANY_ID,
942 .subdevice = PCI_ANY_ID,
0d013bcf 943 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 944 },
945
946 {
947 .vendor = PCI_VENDOR_ID_INTEL,
948 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
949 .subvendor = PCI_ANY_ID,
950 .subdevice = PCI_ANY_ID,
0d013bcf 951 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 952 },
953
954 {
955 .vendor = PCI_VENDOR_ID_INTEL,
956 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
957 .subvendor = PCI_ANY_ID,
958 .subdevice = PCI_ANY_ID,
0d013bcf 959 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 960 },
961
962 {
963 .vendor = PCI_VENDOR_ID_INTEL,
964 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
965 .subvendor = PCI_ANY_ID,
966 .subdevice = PCI_ANY_ID,
0d013bcf 967 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 968 },
969
296e0b03
AS		 970 {
971 .vendor = PCI_VENDOR_ID_INTEL,
972 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
973 .subvendor = PCI_ANY_ID,
974 .subdevice = PCI_ANY_ID,
975 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
976 },
977
978 {
979 .vendor = PCI_VENDOR_ID_INTEL,
980 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
981 .subvendor = PCI_ANY_ID,
982 .subdevice = PCI_ANY_ID,
983 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
984 },
985
728ef3d1
AH		 986 {
987 .vendor = PCI_VENDOR_ID_INTEL,
988 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
989 .subvendor = PCI_ANY_ID,
990 .subdevice = PCI_ANY_ID,
991 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
992 },
993
994 {
995 .vendor = PCI_VENDOR_ID_INTEL,
996 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
997 .subvendor = PCI_ANY_ID,
998 .subdevice = PCI_ANY_ID,
999 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1000 },
1001
1002 {
1003 .vendor = PCI_VENDOR_ID_INTEL,
1004 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
1005 .subvendor = PCI_ANY_ID,
1006 .subdevice = PCI_ANY_ID,
1007 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1008 },
1009
30d025c0
AH		 1010 {
1011 .vendor = PCI_VENDOR_ID_INTEL,
1012 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
1013 .subvendor = PCI_ANY_ID,
1014 .subdevice = PCI_ANY_ID,
1015 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1016 },
1017
066173b6
AC		 1018 {
1019 .vendor = PCI_VENDOR_ID_INTEL,
1020 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
1021 .subvendor = PCI_ANY_ID,
1022 .subdevice = PCI_ANY_ID,
1023 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1024 },
1025
1026 {
1027 .vendor = PCI_VENDOR_ID_INTEL,
1028 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
1029 .subvendor = PCI_ANY_ID,
1030 .subdevice = PCI_ANY_ID,
1031 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1032 },
1033
1034 {
1035 .vendor = PCI_VENDOR_ID_INTEL,
1036 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
1037 .subvendor = PCI_ANY_ID,
1038 .subdevice = PCI_ANY_ID,
1039 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1040 },
d052068a
EE		 1041
1042 {
1043 .vendor = PCI_VENDOR_ID_INTEL,
1044 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
1045 .subvendor = PCI_ANY_ID,
1046 .subdevice = PCI_ANY_ID,
1047 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1048 },
1049
1050 {
1051 .vendor = PCI_VENDOR_ID_INTEL,
1052 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
1053 .subvendor = PCI_ANY_ID,
1054 .subdevice = PCI_ANY_ID,
1055 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1056 },
1057
1058 {
1059 .vendor = PCI_VENDOR_ID_INTEL,
1060 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
1061 .subvendor = PCI_ANY_ID,
1062 .subdevice = PCI_ANY_ID,
1063 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1064 },
1065
1066 {
1067 .vendor = PCI_VENDOR_ID_INTEL,
1068 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
1069 .subvendor = PCI_ANY_ID,
1070 .subdevice = PCI_ANY_ID,
1071 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1072 },
1073
1074 {
1075 .vendor = PCI_VENDOR_ID_INTEL,
1076 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
1077 .subvendor = PCI_ANY_ID,
1078 .subdevice = PCI_ANY_ID,
1079 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1080 },
1081
8776a165
DC		 1082 {
1083 .vendor = PCI_VENDOR_ID_INTEL,
1084 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
1085 .subvendor = PCI_ANY_ID,
1086 .subdevice = PCI_ANY_ID,
1087 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
1088 },
1f7f2652
AH		 1089
1090 {
1091 .vendor = PCI_VENDOR_ID_INTEL,
1092 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1093 .subvendor = PCI_ANY_ID,
1094 .subdevice = PCI_ANY_ID,
1095 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1096 },
1097
1098 {
1099 .vendor = PCI_VENDOR_ID_INTEL,
1100 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1101 .subvendor = PCI_ANY_ID,
1102 .subdevice = PCI_ANY_ID,
1103 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1104 },
1105
1106 {
1107 .vendor = PCI_VENDOR_ID_INTEL,
1108 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1109 .subvendor = PCI_ANY_ID,
1110 .subdevice = PCI_ANY_ID,
1111 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1112 },
1113
26daa1ed
JL		 1114 {
1115 .vendor = PCI_VENDOR_ID_O2,
1116 .device = PCI_DEVICE_ID_O2_8120,
1117 .subvendor = PCI_ANY_ID,
1118 .subdevice = PCI_ANY_ID,
1119 .driver_data = (kernel_ulong_t)&sdhci_o2,
1120 },
1121
1122 {
1123 .vendor = PCI_VENDOR_ID_O2,
1124 .device = PCI_DEVICE_ID_O2_8220,
1125 .subvendor = PCI_ANY_ID,
1126 .subdevice = PCI_ANY_ID,
1127 .driver_data = (kernel_ulong_t)&sdhci_o2,
1128 },
1129
1130 {
1131 .vendor = PCI_VENDOR_ID_O2,
1132 .device = PCI_DEVICE_ID_O2_8221,
1133 .subvendor = PCI_ANY_ID,
1134 .subdevice = PCI_ANY_ID,
1135 .driver_data = (kernel_ulong_t)&sdhci_o2,
1136 },
1137
1138 {
1139 .vendor = PCI_VENDOR_ID_O2,
1140 .device = PCI_DEVICE_ID_O2_8320,
1141 .subvendor = PCI_ANY_ID,
1142 .subdevice = PCI_ANY_ID,
1143 .driver_data = (kernel_ulong_t)&sdhci_o2,
1144 },
1145
1146 {
1147 .vendor = PCI_VENDOR_ID_O2,
1148 .device = PCI_DEVICE_ID_O2_8321,
1149 .subvendor = PCI_ANY_ID,
1150 .subdevice = PCI_ANY_ID,
1151 .driver_data = (kernel_ulong_t)&sdhci_o2,
1152 },
1153
01acf691
AL		 1154 {
1155 .vendor = PCI_VENDOR_ID_O2,
1156 .device = PCI_DEVICE_ID_O2_FUJIN2,
1157 .subvendor = PCI_ANY_ID,
1158 .subdevice = PCI_ANY_ID,
1159 .driver_data = (kernel_ulong_t)&sdhci_o2,
1160 },
1161
1162 {
1163 .vendor = PCI_VENDOR_ID_O2,
1164 .device = PCI_DEVICE_ID_O2_SDS0,
1165 .subvendor = PCI_ANY_ID,
1166 .subdevice = PCI_ANY_ID,
1167 .driver_data = (kernel_ulong_t)&sdhci_o2,
1168 },
1169
1170 {
1171 .vendor = PCI_VENDOR_ID_O2,
1172 .device = PCI_DEVICE_ID_O2_SDS1,
1173 .subvendor = PCI_ANY_ID,
1174 .subdevice = PCI_ANY_ID,
1175 .driver_data = (kernel_ulong_t)&sdhci_o2,
1176 },
1177
1178 {
1179 .vendor = PCI_VENDOR_ID_O2,
1180 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1181 .subvendor = PCI_ANY_ID,
1182 .subdevice = PCI_ANY_ID,
1183 .driver_data = (kernel_ulong_t)&sdhci_o2,
1184 },
1185
1186 {
1187 .vendor = PCI_VENDOR_ID_O2,
1188 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1189 .subvendor = PCI_ANY_ID,
1190 .subdevice = PCI_ANY_ID,
1191 .driver_data = (kernel_ulong_t)&sdhci_o2,
1192 },
d44f88da
VW		 1193 {
1194 .vendor = PCI_VENDOR_ID_AMD,
1195 .device = PCI_ANY_ID,
1196 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1197 .class_mask = 0xFFFF00,
1198 .subvendor = PCI_ANY_ID,
1199 .subdevice = PCI_ANY_ID,
1200 .driver_data = (kernel_ulong_t)&sdhci_amd,
1201 },
b8c86fc5
PO		 1202 { /* Generic SD host controller */
1203 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1204 },
1205
1206 { /* end: all zeroes */ },
1207};
1208
1209MODULE_DEVICE_TABLE(pci, pci_ids);
1210
b8c86fc5
PO		 1211/*****************************************************************************\
1212 * *
1213 * SDHCI core callbacks *
1214 * *
1215\*****************************************************************************/
1216
1217static int sdhci_pci_enable_dma(struct sdhci_host *host)
1218{
1219 struct sdhci_pci_slot *slot;
1220 struct pci_dev *pdev;
3828ecaa 1221 int ret = -1;
b8c86fc5
PO		 1222
1223 slot = sdhci_priv(host);
1224 pdev = slot->chip->pdev;
1225
1226 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1227 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1228 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1229 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1230 "doesn't fully claim to support it.\n");
1231 }
1232
3828ecaa
AH		 1233 if (host->flags & SDHCI_USE_64_BIT_DMA) {
1234 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) {
1235 host->flags &= ~SDHCI_USE_64_BIT_DMA;
1236 } else {
1237 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1238 if (ret)
1239 dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n");
1240 }
1241 }
1242 if (ret)
1243 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b8c86fc5
PO		 1244 if (ret)
1245 return ret;
1246
1247 pci_set_master(pdev);
1248
1249 return 0;
1250}
1251
2317f56c 1252static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
68077b02
ML		 1253{
1254 u8 ctrl;
1255
1256 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1257
1258 switch (width) {
1259 case MMC_BUS_WIDTH_8:
1260 ctrl |= SDHCI_CTRL_8BITBUS;
1261 ctrl &= ~SDHCI_CTRL_4BITBUS;
1262 break;
1263 case MMC_BUS_WIDTH_4:
1264 ctrl |= SDHCI_CTRL_4BITBUS;
1265 ctrl &= ~SDHCI_CTRL_8BITBUS;
1266 break;
1267 default:
1268 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1269 break;
1270 }
1271
1272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
68077b02
ML		 1273}
1274
c9faff6c 1275static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1276{
1277 struct sdhci_pci_slot *slot = sdhci_priv(host);
1278 int rst_n_gpio = slot->rst_n_gpio;
1279
1280 if (!gpio_is_valid(rst_n_gpio))
1281 return;
1282 gpio_set_value_cansleep(rst_n_gpio, 0);
1283 /* For eMMC, minimum is 1us but give it 10us for good measure */
1284 udelay(10);
1285 gpio_set_value_cansleep(rst_n_gpio, 1);
1286 /* For eMMC, minimum is 200us but give it 300us for good measure */
1287 usleep_range(300, 1000);
1288}
1289
c9faff6c
AH		 1290static void sdhci_pci_hw_reset(struct sdhci_host *host)
1291{
1292 struct sdhci_pci_slot *slot = sdhci_priv(host);
1293
1294 if (slot->hw_reset)
1295 slot->hw_reset(host);
1296}
1297
e1bfad6d
AH		 1298static int sdhci_pci_select_drive_strength(struct sdhci_host *host,
1299 struct mmc_card *card,
1300 unsigned int max_dtr, int host_drv,
1301 int card_drv, int *drv_type)
1302{
1303 struct sdhci_pci_slot *slot = sdhci_priv(host);
1304
1305 if (!slot->select_drive_strength)
1306 return 0;
1307
1308 return slot->select_drive_strength(host, card, max_dtr, host_drv,
1309 card_drv, drv_type);
1310}
1311
c915568d 1312static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1313 .set_clock = sdhci_set_clock,
b8c86fc5 1314 .enable_dma = sdhci_pci_enable_dma,
2317f56c 1315 .set_bus_width = sdhci_pci_set_bus_width,
03231f9b 1316 .reset = sdhci_reset,
96d7b78c 1317 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1318 .hw_reset = sdhci_pci_hw_reset,
e1bfad6d 1319 .select_drive_strength = sdhci_pci_select_drive_strength,
b8c86fc5
PO		 1320};
1321
1322/*****************************************************************************\
1323 * *
1324 * Suspend/resume *
1325 * *
1326\*****************************************************************************/
1327
1328#ifdef CONFIG_PM
1329
29495aa0 1330static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1331{
29495aa0 1332 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1333 struct sdhci_pci_chip *chip;
1334 struct sdhci_pci_slot *slot;
5f619704 1335 mmc_pm_flag_t slot_pm_flags;
2f4cbb3d 1336 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 1337 int i, ret;
1338
1339 chip = pci_get_drvdata(pdev);
1340 if (!chip)
1341 return 0;
1342
b177bc91 1343 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1344 slot = chip->slots[i];
1345 if (!slot)
1346 continue;
1347
29495aa0 1348 ret = sdhci_suspend_host(slot->host);
b8c86fc5 1349
b678b91f
AL		 1350 if (ret)
1351 goto err_pci_suspend;
2f4cbb3d 1352
5f619704
DD		 1353 slot_pm_flags = slot->host->mmc->pm_flags;
1354 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1355 sdhci_enable_irq_wakeups(slot->host);
1356
1357 pm_flags |= slot_pm_flags;
b8c86fc5
PO		 1358 }
1359
4489428a 1360 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1361 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1362 if (ret)
1363 goto err_pci_suspend;
4489428a
PO		 1364 }
1365
2f4cbb3d 1366 if (pm_flags & MMC_PM_KEEP_POWER) {
6b91f2d4
CD		 1367 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1368 device_init_wakeup(dev, true);
1369 else
1370 device_init_wakeup(dev, false);
1371 } else
1372 device_init_wakeup(dev, false);
b8c86fc5
PO		 1373
1374 return 0;
b678b91f
AL		 1375
1376err_pci_suspend:
1377 while (--i >= 0)
1378 sdhci_resume_host(chip->slots[i]->host);
1379 return ret;
b8c86fc5
PO		 1380}
1381
29495aa0 1382static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1383{
29495aa0 1384 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1385 struct sdhci_pci_chip *chip;
1386 struct sdhci_pci_slot *slot;
1387 int i, ret;
1388
1389 chip = pci_get_drvdata(pdev);
1390 if (!chip)
1391 return 0;
1392
45211e21
PO		 1393 if (chip->fixes && chip->fixes->resume) {
1394 ret = chip->fixes->resume(chip);
1395 if (ret)
1396 return ret;
1397 }
1398
b177bc91 1399 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1400 slot = chip->slots[i];
1401 if (!slot)
1402 continue;
1403
1404 ret = sdhci_resume_host(slot->host);
1405 if (ret)
1406 return ret;
1407 }
1408
1409 return 0;
1410}
1411
66fd8ad5
AH		 1412static int sdhci_pci_runtime_suspend(struct device *dev)
1413{
1414 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1415 struct sdhci_pci_chip *chip;
1416 struct sdhci_pci_slot *slot;
66fd8ad5
AH		 1417 int i, ret;
1418
1419 chip = pci_get_drvdata(pdev);
1420 if (!chip)
1421 return 0;
1422
1423 for (i = 0; i < chip->num_slots; i++) {
1424 slot = chip->slots[i];
1425 if (!slot)
1426 continue;
1427
1428 ret = sdhci_runtime_suspend_host(slot->host);
1429
b678b91f
AL		 1430 if (ret)
1431 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1432 }
1433
1434 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1435 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1436 if (ret)
1437 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1438 }
1439
1440 return 0;
b678b91f
AL		 1441
1442err_pci_runtime_suspend:
1443 while (--i >= 0)
1444 sdhci_runtime_resume_host(chip->slots[i]->host);
1445 return ret;
66fd8ad5
AH		 1446}
1447
1448static int sdhci_pci_runtime_resume(struct device *dev)
1449{
1450 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1451 struct sdhci_pci_chip *chip;
1452 struct sdhci_pci_slot *slot;
1453 int i, ret;
1454
1455 chip = pci_get_drvdata(pdev);
1456 if (!chip)
1457 return 0;
1458
1459 if (chip->fixes && chip->fixes->resume) {
1460 ret = chip->fixes->resume(chip);
1461 if (ret)
1462 return ret;
1463 }
1464
1465 for (i = 0; i < chip->num_slots; i++) {
1466 slot = chip->slots[i];
1467 if (!slot)
1468 continue;
1469
1470 ret = sdhci_runtime_resume_host(slot->host);
1471 if (ret)
1472 return ret;
1473 }
1474
1475 return 0;
1476}
1477
162d6f98
RW		 1478#else /* CONFIG_PM */
1479
1480#define sdhci_pci_suspend NULL
1481#define sdhci_pci_resume NULL
1482
1483#endif /* CONFIG_PM */
66fd8ad5
AH		 1484
1485static const struct dev_pm_ops sdhci_pci_pm_ops = {
29495aa0
ML		 1486 .suspend = sdhci_pci_suspend,
1487 .resume = sdhci_pci_resume,
f3a92b1a 1488 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
106276bb 1489 sdhci_pci_runtime_resume, NULL)
66fd8ad5
AH		 1490};
1491
b8c86fc5
PO		 1492/*****************************************************************************\
1493 * *
1494 * Device probing/removal *
1495 * *
1496\*****************************************************************************/
1497
c3be1efd 1498static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1499 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1500 int slotno)
b8c86fc5
PO		 1501{
1502 struct sdhci_pci_slot *slot;
1503 struct sdhci_host *host;
52c506f0 1504 int ret, bar = first_bar + slotno;
b8c86fc5
PO		 1505
1506 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1507 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1508 return ERR_PTR(-ENODEV);
1509 }
1510
90b3e6c5 1511 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1512 dev_err(&pdev->dev, "Invalid iomem size. You may "
1513 "experience problems.\n");
1514 }
1515
1516 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1517 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1518 return ERR_PTR(-ENODEV);
1519 }
1520
1521 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1522 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1523 return ERR_PTR(-ENODEV);
1524 }
1525
1526 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1527 if (IS_ERR(host)) {
c60a32cd 1528 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1529 return ERR_CAST(host);
b8c86fc5
PO		 1530 }
1531
1532 slot = sdhci_priv(host);
1533
1534 slot->chip = chip;
1535 slot->host = host;
1536 slot->pci_bar = bar;
0f201655 1537 slot->rst_n_gpio = -EINVAL;
c5e027a4 1538 slot->cd_gpio = -EINVAL;
ff59c520 1539 slot->cd_idx = -1;
b8c86fc5 1540
52c506f0
AH		 1541 /* Retrieve platform data if there is any */
1542 if (*sdhci_pci_get_data)
1543 slot->data = sdhci_pci_get_data(pdev, slotno);
1544
1545 if (slot->data) {
1546 if (slot->data->setup) {
1547 ret = slot->data->setup(slot->data);
1548 if (ret) {
1549 dev_err(&pdev->dev, "platform setup failed\n");
1550 goto free;
1551 }
1552 }
c5e027a4
AH		 1553 slot->rst_n_gpio = slot->data->rst_n_gpio;
1554 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1555 }
1556
b8c86fc5
PO		 1557 host->hw_name = "PCI";
1558 host->ops = &sdhci_pci_ops;
1559 host->quirks = chip->quirks;
f3c55a7b 1560 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1561
1562 host->irq = pdev->irq;
1563
1564 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1565 if (ret) {
1566 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1567 goto cleanup;
b8c86fc5
PO		 1568 }
1569
092f82ed 1570 host->ioaddr = pci_ioremap_bar(pdev, bar);
b8c86fc5
PO		 1571 if (!host->ioaddr) {
1572 dev_err(&pdev->dev, "failed to remap registers\n");
9fdcdbb0 1573 ret = -ENOMEM;
b8c86fc5
PO		 1574 goto release;
1575 }
1576
4489428a
PO		 1577 if (chip->fixes && chip->fixes->probe_slot) {
1578 ret = chip->fixes->probe_slot(slot);
1579 if (ret)
1580 goto unmap;
1581 }
1582
c5e027a4
AH		 1583 if (gpio_is_valid(slot->rst_n_gpio)) {
1584 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1585 gpio_direction_output(slot->rst_n_gpio, 1);
1586 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1587 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1588 } else {
1589 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1590 slot->rst_n_gpio = -EINVAL;
1591 }
1592 }
1593
2f4cbb3d 1594 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
eed222ac 1595 host->mmc->slotno = slotno;
a08b17be 1596 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1597
ff59c520
AH		 1598 if (slot->cd_idx >= 0 &&
1599 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1600 slot->cd_override_level, 0, NULL)) {
1601 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1602 slot->cd_idx = -1;
1603 }
1604
b8c86fc5
PO		 1605 ret = sdhci_add_host(host);
1606 if (ret)
4489428a 1607 goto remove;
b8c86fc5 1608
c5e027a4
AH		 1609 sdhci_pci_add_own_cd(slot);
1610
77a0122e
AH		 1611 /*
1612 * Check if the chip needs a separate GPIO for card detect to wake up
1613 * from runtime suspend. If it is not there, don't allow runtime PM.
1614 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1615 */
945be38c 1616 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
ff59c520 1617 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
77a0122e
AH		 1618 chip->allow_runtime_pm = false;
1619
b8c86fc5
PO		 1620 return slot;
1621
4489428a 1622remove:
c5e027a4
AH		 1623 if (gpio_is_valid(slot->rst_n_gpio))
1624 gpio_free(slot->rst_n_gpio);
1625
4489428a 1626 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1627 chip->fixes->remove_slot(slot, 0);
4489428a 1628
b8c86fc5
PO		 1629unmap:
1630 iounmap(host->ioaddr);
1631
1632release:
1633 pci_release_region(pdev, bar);
c60a32cd 1634
52c506f0
AH		 1635cleanup:
1636 if (slot->data && slot->data->cleanup)
1637 slot->data->cleanup(slot->data);
1638
c60a32cd 1639free:
b8c86fc5
PO		 1640 sdhci_free_host(host);
1641
1642 return ERR_PTR(ret);
1643}
1644
1645static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1646{
1e72859e
PO		 1647 int dead;
1648 u32 scratch;
1649
c5e027a4
AH		 1650 sdhci_pci_remove_own_cd(slot);
1651
1e72859e
PO		 1652 dead = 0;
1653 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1654 if (scratch == (u32)-1)
1655 dead = 1;
1656
1657 sdhci_remove_host(slot->host, dead);
4489428a 1658
c5e027a4
AH		 1659 if (gpio_is_valid(slot->rst_n_gpio))
1660 gpio_free(slot->rst_n_gpio);
1661
4489428a 1662 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1663 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1664
52c506f0
AH		 1665 if (slot->data && slot->data->cleanup)
1666 slot->data->cleanup(slot->data);
1667
b8c86fc5 1668 pci_release_region(slot->chip->pdev, slot->pci_bar);
4489428a 1669
b8c86fc5
PO		 1670 sdhci_free_host(slot->host);
1671}
1672
c3be1efd 1673static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5
AH		 1674{
1675 pm_runtime_put_noidle(dev);
1676 pm_runtime_allow(dev);
1677 pm_runtime_set_autosuspend_delay(dev, 50);
1678 pm_runtime_use_autosuspend(dev);
1679 pm_suspend_ignore_children(dev, 1);
1680}
1681
6e0ee714 1682static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 1683{
1684 pm_runtime_forbid(dev);
1685 pm_runtime_get_noresume(dev);
1686}
1687
c3be1efd 1688static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 1689 const struct pci_device_id *ent)
1690{
1691 struct sdhci_pci_chip *chip;
1692 struct sdhci_pci_slot *slot;
1693
cf5e23e1 1694 u8 slots, first_bar;
b8c86fc5
PO		 1695 int ret, i;
1696
1697 BUG_ON(pdev == NULL);
1698 BUG_ON(ent == NULL);
1699
b8c86fc5 1700 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1701 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1702
1703 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1704 if (ret)
1705 return ret;
1706
1707 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1708 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1709 if (slots == 0)
1710 return -ENODEV;
1711
1712 BUG_ON(slots > MAX_SLOTS);
1713
1714 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1715 if (ret)
1716 return ret;
1717
1718 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1719
1720 if (first_bar > 5) {
1721 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1722 return -ENODEV;
1723 }
1724
1725 ret = pci_enable_device(pdev);
1726 if (ret)
1727 return ret;
1728
1729 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1730 if (!chip) {
1731 ret = -ENOMEM;
1732 goto err;
1733 }
1734
1735 chip->pdev = pdev;
b177bc91 1736 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1737 if (chip->fixes) {
22606405 1738 chip->quirks = chip->fixes->quirks;
f3c55a7b 1739 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 1740 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1741 }
b8c86fc5
PO		 1742 chip->num_slots = slots;
1743
1744 pci_set_drvdata(pdev, chip);
1745
22606405
PO		 1746 if (chip->fixes && chip->fixes->probe) {
1747 ret = chip->fixes->probe(chip);
1748 if (ret)
1749 goto free;
1750 }
1751
225d85fe
AC		 1752 slots = chip->num_slots; /* Quirk may have changed this */
1753
b177bc91 1754 for (i = 0; i < slots; i++) {
52c506f0 1755 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 1756 if (IS_ERR(slot)) {
b177bc91 1757 for (i--; i >= 0; i--)
b8c86fc5
PO		 1758 sdhci_pci_remove_slot(chip->slots[i]);
1759 ret = PTR_ERR(slot);
1760 goto free;
1761 }
1762
1763 chip->slots[i] = slot;
1764 }
1765
c43fd774
AH		 1766 if (chip->allow_runtime_pm)
1767 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 1768
b8c86fc5
PO		 1769 return 0;
1770
1771free:
1772 pci_set_drvdata(pdev, NULL);
1773 kfree(chip);
1774
1775err:
1776 pci_disable_device(pdev);
1777 return ret;
1778}
1779
6e0ee714 1780static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 1781{
1782 int i;
1783 struct sdhci_pci_chip *chip;
1784
1785 chip = pci_get_drvdata(pdev);
1786
1787 if (chip) {
c43fd774
AH		 1788 if (chip->allow_runtime_pm)
1789 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1790
b177bc91 1791 for (i = 0; i < chip->num_slots; i++)
b8c86fc5
PO		 1792 sdhci_pci_remove_slot(chip->slots[i]);
1793
1794 pci_set_drvdata(pdev, NULL);
1795 kfree(chip);
1796 }
1797
1798 pci_disable_device(pdev);
1799}
1800
1801static struct pci_driver sdhci_driver = {
b177bc91 1802 .name = "sdhci-pci",
b8c86fc5 1803 .id_table = pci_ids,
b177bc91 1804 .probe = sdhci_pci_probe,
0433c143 1805 .remove = sdhci_pci_remove,
66fd8ad5
AH		 1806 .driver = {
1807 .pm = &sdhci_pci_pm_ops
1808 },
b8c86fc5
PO		 1809};
1810
acc69646 1811module_pci_driver(sdhci_driver);
b8c86fc5 1812
32710e8f 1813MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1814MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1815MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)