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mmc: sdhci-omap: Fix NULL pointer exception if regulator is not configured
[linux-2.6-block.git] / drivers / mmc / host / sdhci-omap.c
CommitLineData
6b1baefe 1// SPDX-License-Identifier: GPL-2.0-only
7d326930
KVA		 2/**
3 * SDHCI Controller driver for TI's OMAP SoCs
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7d326930
KVA		 7 */
8
9#include <linux/delay.h>
5da5e494 10#include <linux/mmc/mmc.h>
7d326930
KVA		 11#include <linux/mmc/slot-gpio.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/regulator/consumer.h>
8d20b2ea 18#include <linux/pinctrl/consumer.h>
212f4f8a 19#include <linux/sys_soc.h>
961de0a8 20#include <linux/thermal.h>
7d326930
KVA		 21
22#include "sdhci-pltfm.h"
23
24#define SDHCI_OMAP_CON 0x12c
25#define CON_DW8 BIT(5)
26#define CON_DMA_MASTER BIT(20)
27ceb7e0 27#define CON_DDR BIT(19)
20ea26a1
KVA		 28#define CON_CLKEXTFREE BIT(16)
29#define CON_PADEN BIT(15)
efde12b2 30#define CON_CTPL BIT(11)
7d326930
KVA		 31#define CON_INIT BIT(1)
32#define CON_OD BIT(0)
33
9fc2cd76
KVA		 34#define SDHCI_OMAP_DLL 0x0134
35#define DLL_SWT BIT(20)
36#define DLL_FORCE_SR_C_SHIFT 13
37#define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT)
38#define DLL_FORCE_VALUE BIT(12)
39#define DLL_CALIB BIT(1)
40
7d326930
KVA		 41#define SDHCI_OMAP_CMD 0x20c
42
20ea26a1
KVA		 43#define SDHCI_OMAP_PSTATE 0x0224
44#define PSTATE_DLEV_DAT0 BIT(20)
45#define PSTATE_DATI BIT(1)
46
7d326930
KVA		 47#define SDHCI_OMAP_HCTL 0x228
48#define HCTL_SDBP BIT(8)
49#define HCTL_SDVS_SHIFT 9
50#define HCTL_SDVS_MASK (0x7 << HCTL_SDVS_SHIFT)
51#define HCTL_SDVS_33 (0x7 << HCTL_SDVS_SHIFT)
52#define HCTL_SDVS_30 (0x6 << HCTL_SDVS_SHIFT)
53#define HCTL_SDVS_18 (0x5 << HCTL_SDVS_SHIFT)
54
55#define SDHCI_OMAP_SYSCTL 0x22c
56#define SYSCTL_CEN BIT(2)
57#define SYSCTL_CLKD_SHIFT 6
58#define SYSCTL_CLKD_MASK 0x3ff
59
60#define SDHCI_OMAP_STAT 0x230
61
62#define SDHCI_OMAP_IE 0x234
63#define INT_CC_EN BIT(0)
64
65#define SDHCI_OMAP_AC12 0x23c
66#define AC12_V1V8_SIGEN BIT(19)
9fc2cd76 67#define AC12_SCLK_SEL BIT(23)
7d326930
KVA		 68
69#define SDHCI_OMAP_CAPA 0x240
70#define CAPA_VS33 BIT(24)
71#define CAPA_VS30 BIT(25)
72#define CAPA_VS18 BIT(26)
73
9fc2cd76
KVA		 74#define SDHCI_OMAP_CAPA2 0x0244
75#define CAPA2_TSDR50 BIT(13)
76
7d326930
KVA		 77#define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */
78
79#define SYSCTL_CLKD_MAX 0x3FF
80
81#define IOV_1V8 1800000 /* 180000 uV */
82#define IOV_3V0 3000000 /* 300000 uV */
83#define IOV_3V3 3300000 /* 330000 uV */
84
9fc2cd76
KVA		 85#define MAX_PHASE_DELAY 0x7C
86
8d20b2ea
KVA		 87/* sdhci-omap controller flags */
88#define SDHCI_OMAP_REQUIRE_IODELAY BIT(0)
9e84a2e6 89#define SDHCI_OMAP_SPECIAL_RESET BIT(1)
8d20b2ea 90
7d326930
KVA		 91struct sdhci_omap_data {
92 u32 offset;
8d20b2ea 93 u8 flags;
7d326930
KVA		 94};
95
96struct sdhci_omap_host {
212f4f8a 97 char *version;
7d326930
KVA		 98 void __iomem *base;
99 struct device *dev;
100 struct regulator *pbias;
101 bool pbias_enabled;
102 struct sdhci_host *host;
103 u8 bus_mode;
104 u8 power_mode;
8d20b2ea
KVA		 105 u8 timing;
106 u8 flags;
107
108 struct pinctrl *pinctrl;
109 struct pinctrl_state **pinctrl_state;
5b0d6210 110 bool is_tuning;
ee0f3092
FA		 111 /* Omap specific context save */
112 u32 con;
113 u32 hctl;
114 u32 sysctl;
115 u32 capa;
7d326930
KVA		 116};
117
8d20b2ea
KVA		 118static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
119static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
120
7d326930
KVA		 121static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
122 unsigned int offset)
123{
124 return readl(host->base + offset);
125}
126
127static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
128 unsigned int offset, u32 data)
129{
130 writel(data, host->base + offset);
131}
132
133static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
134 bool power_on, unsigned int iov)
135{
136 int ret;
137 struct device *dev = omap_host->dev;
138
139 if (IS_ERR(omap_host->pbias))
140 return 0;
141
142 if (power_on) {
143 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
144 if (ret) {
145 dev_err(dev, "pbias set voltage failed\n");
146 return ret;
147 }
148
149 if (omap_host->pbias_enabled)
150 return 0;
151
152 ret = regulator_enable(omap_host->pbias);
153 if (ret) {
154 dev_err(dev, "pbias reg enable fail\n");
155 return ret;
156 }
157
158 omap_host->pbias_enabled = true;
159 } else {
160 if (!omap_host->pbias_enabled)
161 return 0;
162
163 ret = regulator_disable(omap_host->pbias);
164 if (ret) {
165 dev_err(dev, "pbias reg disable fail\n");
166 return ret;
167 }
168 omap_host->pbias_enabled = false;
169 }
170
171 return 0;
172}
173
174static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
175 unsigned int iov)
176{
177 int ret;
178 struct sdhci_host *host = omap_host->host;
179 struct mmc_host *mmc = host->mmc;
180
181 ret = sdhci_omap_set_pbias(omap_host, false, 0);
182 if (ret)
183 return ret;
184
185 if (!IS_ERR(mmc->supply.vqmmc)) {
186 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
187 if (ret) {
188 dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
189 return ret;
190 }
191 }
192
193 ret = sdhci_omap_set_pbias(omap_host, true, iov);
194 if (ret)
195 return ret;
196
197 return 0;
198}
199
200static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
201 unsigned char signal_voltage)
202{
203 u32 reg;
204 ktime_t timeout;
205
206 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
207 reg &= ~HCTL_SDVS_MASK;
208
209 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
210 reg |= HCTL_SDVS_33;
211 else
212 reg |= HCTL_SDVS_18;
213
214 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
215
216 reg |= HCTL_SDBP;
217 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
218
219 /* wait 1ms */
220 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
9f0ea0bd
AH		 221 while (1) {
222 bool timedout = ktime_after(ktime_get(), timeout);
223
224 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)
225 break;
226 if (WARN_ON(timedout))
7d326930
KVA		 227 return;
228 usleep_range(5, 10);
229 }
230}
231
efde12b2
KVA		 232static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
233{
234 struct sdhci_host *host = mmc_priv(mmc);
235 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
236 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
237 u32 reg;
238
239 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
240 if (enable)
241 reg |= (CON_CTPL | CON_CLKEXTFREE);
242 else
243 reg &= ~(CON_CTPL | CON_CLKEXTFREE);
244 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
245
246 sdhci_enable_sdio_irq(mmc, enable);
247}
248
9fc2cd76
KVA		 249static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
250 int count)
251{
252 int i;
253 u32 reg;
254
255 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
256 reg |= DLL_FORCE_VALUE;
257 reg &= ~DLL_FORCE_SR_C_MASK;
258 reg |= (count << DLL_FORCE_SR_C_SHIFT);
259 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
260
261 reg |= DLL_CALIB;
262 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
263 for (i = 0; i < 1000; i++) {
264 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
265 if (reg & DLL_CALIB)
266 break;
267 }
268 reg &= ~DLL_CALIB;
269 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
270}
271
272static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
273{
274 u32 reg;
275
276 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
277 reg &= ~AC12_SCLK_SEL;
278 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
279
280 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
281 reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
282 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
283}
284
285static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
286{
287 struct sdhci_host *host = mmc_priv(mmc);
288 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
289 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
961de0a8 290 struct thermal_zone_device *thermal_dev;
9fc2cd76
KVA		 291 struct device *dev = omap_host->dev;
292 struct mmc_ios *ios = &mmc->ios;
293 u32 start_window = 0, max_window = 0;
961de0a8 294 bool single_point_failure = false;
db2039fc 295 bool dcrc_was_enabled = false;
9fc2cd76
KVA		 296 u8 cur_match, prev_match = 0;
297 u32 length = 0, max_len = 0;
298 u32 phase_delay = 0;
961de0a8 299 int temperature;
9fc2cd76
KVA		 300 int ret = 0;
301 u32 reg;
961de0a8 302 int i;
9fc2cd76 303
9fc2cd76
KVA		 304 /* clock tuning is not needed for upto 52MHz */
305 if (ios->clock <= 52000000)
306 return 0;
307
308 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
309 if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
310 return 0;
311
961de0a8
FA		 312 thermal_dev = thermal_zone_get_zone_by_name("cpu_thermal");
313 if (IS_ERR(thermal_dev)) {
314 dev_err(dev, "Unable to get thermal zone for tuning\n");
315 return PTR_ERR(thermal_dev);
316 }
317
318 ret = thermal_zone_get_temp(thermal_dev, &temperature);
319 if (ret)
320 return ret;
321
9fc2cd76
KVA		 322 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
323 reg |= DLL_SWT;
324 sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
325
7d33c358
KVA		 326 /*
327 * OMAP5/DRA74X/DRA72x Errata i802:
328 * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
329 * during the tuning procedure. So disable it during the
330 * tuning procedure.
331 */
db2039fc
FA		 332 if (host->ier & SDHCI_INT_DATA_CRC) {
333 host->ier &= ~SDHCI_INT_DATA_CRC;
334 dcrc_was_enabled = true;
335 }
7d33c358 336
5b0d6210
FA		 337 omap_host->is_tuning = true;
338
961de0a8
FA		 339 /*
340 * Stage 1: Search for a maximum pass window ignoring any
341 * any single point failures. If the tuning value ends up
342 * near it, move away from it in stage 2 below
343 */
9fc2cd76
KVA		 344 while (phase_delay <= MAX_PHASE_DELAY) {
345 sdhci_omap_set_dll(omap_host, phase_delay);
346
347 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
348 if (cur_match) {
349 if (prev_match) {
350 length++;
961de0a8
FA		 351 } else if (single_point_failure) {
352 /* ignore single point failure */
353 length++;
9fc2cd76
KVA		 354 } else {
355 start_window = phase_delay;
356 length = 1;
357 }
961de0a8
FA		 358 } else {
359 single_point_failure = prev_match;
9fc2cd76
KVA		 360 }
361
362 if (length > max_len) {
363 max_window = start_window;
364 max_len = length;
365 }
366
367 prev_match = cur_match;
368 phase_delay += 4;
369 }
370
371 if (!max_len) {
372 dev_err(dev, "Unable to find match\n");
373 ret = -EIO;
374 goto tuning_error;
375 }
376
961de0a8
FA		 377 /*
378 * Assign tuning value as a ratio of maximum pass window based
379 * on temperature
380 */
381 if (temperature < -20000)
feb40824 382 phase_delay = min(max_window + 4 * (max_len - 1) - 24,
961de0a8
FA		 383 max_window +
384 DIV_ROUND_UP(13 * max_len, 16) * 4);
385 else if (temperature < 20000)
386 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
387 else if (temperature < 40000)
388 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
389 else if (temperature < 70000)
390 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
391 else if (temperature < 90000)
392 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
393 else if (temperature < 120000)
394 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
395 else
396 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
397
398 /*
399 * Stage 2: Search for a single point failure near the chosen tuning
400 * value in two steps. First in the +3 to +10 range and then in the
401 * +2 to -10 range. If found, move away from it in the appropriate
402 * direction by the appropriate amount depending on the temperature.
403 */
404 for (i = 3; i <= 10; i++) {
405 sdhci_omap_set_dll(omap_host, phase_delay + i);
406
407 if (mmc_send_tuning(mmc, opcode, NULL)) {
408 if (temperature < 10000)
409 phase_delay += i + 6;
410 else if (temperature < 20000)
411 phase_delay += i - 12;
412 else if (temperature < 70000)
413 phase_delay += i - 8;
414 else
415 phase_delay += i - 6;
416
417 goto single_failure_found;
418 }
419 }
420
421 for (i = 2; i >= -10; i--) {
422 sdhci_omap_set_dll(omap_host, phase_delay + i);
423
424 if (mmc_send_tuning(mmc, opcode, NULL)) {
425 if (temperature < 10000)
426 phase_delay += i + 12;
427 else if (temperature < 20000)
428 phase_delay += i + 8;
429 else if (temperature < 70000)
430 phase_delay += i + 8;
431 else if (temperature < 90000)
432 phase_delay += i + 10;
433 else
434 phase_delay += i + 12;
435
436 goto single_failure_found;
437 }
438 }
439
440single_failure_found:
9fc2cd76
KVA		 441 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
442 if (!(reg & AC12_SCLK_SEL)) {
443 ret = -EIO;
444 goto tuning_error;
445 }
446
9fc2cd76
KVA		 447 sdhci_omap_set_dll(omap_host, phase_delay);
448
5b0d6210
FA		 449 omap_host->is_tuning = false;
450
9fc2cd76
KVA		 451 goto ret;
452
453tuning_error:
5b0d6210 454 omap_host->is_tuning = false;
9fc2cd76
KVA		 455 dev_err(dev, "Tuning failed\n");
456 sdhci_omap_disable_tuning(omap_host);
457
458ret:
459 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
db2039fc
FA		 460 /* Reenable forbidden interrupt */
461 if (dcrc_was_enabled)
462 host->ier |= SDHCI_INT_DATA_CRC;
7d33c358
KVA		 463 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
464 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
9fc2cd76
KVA		 465 return ret;
466}
467
20ea26a1
KVA		 468static int sdhci_omap_card_busy(struct mmc_host *mmc)
469{
470 u32 reg, ac12;
471 int ret = false;
472 struct sdhci_host *host = mmc_priv(mmc);
473 struct sdhci_pltfm_host *pltfm_host;
474 struct sdhci_omap_host *omap_host;
475 u32 ier = host->ier;
476
477 pltfm_host = sdhci_priv(host);
478 omap_host = sdhci_pltfm_priv(pltfm_host);
479
480 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
481 ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
482 reg &= ~CON_CLKEXTFREE;
483 if (ac12 & AC12_V1V8_SIGEN)
484 reg |= CON_CLKEXTFREE;
485 reg |= CON_PADEN;
486 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
487
488 disable_irq(host->irq);
489 ier |= SDHCI_INT_CARD_INT;
490 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
491 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
492
493 /*
494 * Delay is required for PSTATE to correctly reflect
495 * DLEV/CLEV values after PADEN is set.
496 */
497 usleep_range(50, 100);
498 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
499 if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
500 ret = true;
501
502 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
503 reg &= ~(CON_CLKEXTFREE | CON_PADEN);
504 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
505
506 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
507 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
508 enable_irq(host->irq);
509
510 return ret;
511}
512
7d326930
KVA		 513static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
514 struct mmc_ios *ios)
515{
516 u32 reg;
517 int ret;
518 unsigned int iov;
519 struct sdhci_host *host = mmc_priv(mmc);
520 struct sdhci_pltfm_host *pltfm_host;
521 struct sdhci_omap_host *omap_host;
522 struct device *dev;
523
524 pltfm_host = sdhci_priv(host);
525 omap_host = sdhci_pltfm_priv(pltfm_host);
526 dev = omap_host->dev;
527
528 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
529 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
530 if (!(reg & CAPA_VS33))
531 return -EOPNOTSUPP;
532
533 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
534
535 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
536 reg &= ~AC12_V1V8_SIGEN;
537 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
538
539 iov = IOV_3V3;
540 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
541 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
542 if (!(reg & CAPA_VS18))
543 return -EOPNOTSUPP;
544
545 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
546
547 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
548 reg |= AC12_V1V8_SIGEN;
549 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
550
551 iov = IOV_1V8;
552 } else {
553 return -EOPNOTSUPP;
554 }
555
556 ret = sdhci_omap_enable_iov(omap_host, iov);
557 if (ret) {
558 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
559 return ret;
560 }
561
562 dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
563 return 0;
564}
565
8d20b2ea
KVA		 566static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
567{
568 int ret;
569 struct pinctrl_state *pinctrl_state;
570 struct device *dev = omap_host->dev;
571
572 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
573 return;
574
575 if (omap_host->timing == timing)
576 return;
577
578 sdhci_omap_stop_clock(omap_host);
579
580 pinctrl_state = omap_host->pinctrl_state[timing];
581 ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
582 if (ret) {
583 dev_err(dev, "failed to select pinctrl state\n");
584 return;
585 }
586
587 sdhci_omap_start_clock(omap_host);
588 omap_host->timing = timing;
589}
590
300df508
KVA		 591static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
592 u8 power_mode)
593{
9fc2cd76
KVA		 594 if (omap_host->bus_mode == MMC_POWER_OFF)
595 sdhci_omap_disable_tuning(omap_host);
300df508
KVA		 596 omap_host->power_mode = power_mode;
597}
598
7d326930
KVA		 599static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
600 unsigned int mode)
601{
602 u32 reg;
603
604 if (omap_host->bus_mode == mode)
605 return;
606
607 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
608 if (mode == MMC_BUSMODE_OPENDRAIN)
609 reg |= CON_OD;
610 else
611 reg &= ~CON_OD;
612 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
613
614 omap_host->bus_mode = mode;
615}
616
ddde0e7d 617static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
7d326930
KVA		 618{
619 struct sdhci_host *host = mmc_priv(mmc);
620 struct sdhci_pltfm_host *pltfm_host;
621 struct sdhci_omap_host *omap_host;
622
623 pltfm_host = sdhci_priv(host);
624 omap_host = sdhci_pltfm_priv(pltfm_host);
625
626 sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
8d20b2ea 627 sdhci_omap_set_timing(omap_host, ios->timing);
7d326930 628 sdhci_set_ios(mmc, ios);
300df508 629 sdhci_omap_set_power_mode(omap_host, ios->power_mode);
7d326930
KVA		 630}
631
632static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
633 unsigned int clock)
634{
635 u16 dsor;
636
637 dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
638 if (dsor > SYSCTL_CLKD_MAX)
639 dsor = SYSCTL_CLKD_MAX;
640
641 return dsor;
642}
643
644static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
645{
646 u32 reg;
647
648 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
649 reg |= SYSCTL_CEN;
650 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
651}
652
653static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
654{
655 u32 reg;
656
657 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
658 reg &= ~SYSCTL_CEN;
659 sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
660}
661
662static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
663{
664 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
665 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
666 unsigned long clkdiv;
667
668 sdhci_omap_stop_clock(omap_host);
669
670 if (!clock)
671 return;
672
673 clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
674 clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
675 sdhci_enable_clk(host, clkdiv);
676
677 sdhci_omap_start_clock(omap_host);
678}
679
ddde0e7d 680static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
7d326930
KVA		 681 unsigned short vdd)
682{
683 struct mmc_host *mmc = host->mmc;
684
8e0e7bd3
TL		 685 if (!IS_ERR(mmc->supply.vmmc))
686 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
7d326930
KVA		 687}
688
689static int sdhci_omap_enable_dma(struct sdhci_host *host)
690{
691 u32 reg;
692 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
693 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
694
695 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
195fadb7
CZ		 696 reg &= ~CON_DMA_MASTER;
697 /* Switch to DMA slave mode when using external DMA */
698 if (!host->use_external_dma)
699 reg |= CON_DMA_MASTER;
700
7d326930
KVA		 701 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
702
703 return 0;
704}
705
ddde0e7d 706static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
7d326930
KVA		 707{
708 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
709
710 return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
711}
712
713static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
714{
715 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
716 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
717 u32 reg;
718
719 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
720 if (width == MMC_BUS_WIDTH_8)
721 reg |= CON_DW8;
722 else
723 reg &= ~CON_DW8;
724 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
725
726 sdhci_set_bus_width(host, width);
727}
728
729static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
730{
731 u32 reg;
732 ktime_t timeout;
733 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
734 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
735
736 if (omap_host->power_mode == power_mode)
737 return;
738
739 if (power_mode != MMC_POWER_ON)
740 return;
741
742 disable_irq(host->irq);
743
744 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
745 reg |= CON_INIT;
746 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
747 sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
748
749 /* wait 1ms */
750 timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
9f0ea0bd
AH		 751 while (1) {
752 bool timedout = ktime_after(ktime_get(), timeout);
753
754 if (sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)
755 break;
756 if (WARN_ON(timedout))
7d326930
KVA		 757 return;
758 usleep_range(5, 10);
759 }
760
761 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
762 reg &= ~CON_INIT;
763 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
764 sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
765
766 enable_irq(host->irq);
7d326930
KVA		 767}
768
27ceb7e0
KVA		 769static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
770 unsigned int timing)
771{
772 u32 reg;
773 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
774 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
775
776 sdhci_omap_stop_clock(omap_host);
777
778 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
779 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
780 reg |= CON_DDR;
781 else
782 reg &= ~CON_DDR;
783 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
784
785 sdhci_set_uhs_signaling(host, timing);
786 sdhci_omap_start_clock(omap_host);
787}
788
9e84a2e6 789#define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
2198eeff 790static void sdhci_omap_reset(struct sdhci_host *host, u8 mask)
5b0d6210
FA		 791{
792 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
793 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
9e84a2e6
FA		 794 unsigned long limit = MMC_TIMEOUT_US;
795 unsigned long i = 0;
5b0d6210
FA		 796
797 /* Don't reset data lines during tuning operation */
798 if (omap_host->is_tuning)
799 mask &= ~SDHCI_RESET_DATA;
800
9e84a2e6
FA		 801 if (omap_host->flags & SDHCI_OMAP_SPECIAL_RESET) {
802 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
803 while ((!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) &&
804 (i++ < limit))
805 udelay(1);
806 i = 0;
807 while ((sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) &&
808 (i++ < limit))
809 udelay(1);
810
811 if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)
812 dev_err(mmc_dev(host->mmc),
813 "Timeout waiting on controller reset in %s\n",
814 __func__);
815 return;
816 }
817
5b0d6210
FA		 818 sdhci_reset(host, mask);
819}
820
5c41ea6d
FA		 821#define CMD_ERR_MASK (SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX |\
822 SDHCI_INT_TIMEOUT)
823#define CMD_MASK (CMD_ERR_MASK | SDHCI_INT_RESPONSE)
824
825static u32 sdhci_omap_irq(struct sdhci_host *host, u32 intmask)
826{
827 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
828 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
829
830 if (omap_host->is_tuning && host->cmd && !host->data_early &&
831 (intmask & CMD_ERR_MASK)) {
832
833 /*
834 * Since we are not resetting data lines during tuning
835 * operation, data error or data complete interrupts
836 * might still arrive. Mark this request as a failure
837 * but still wait for the data interrupt
838 */
839 if (intmask & SDHCI_INT_TIMEOUT)
840 host->cmd->error = -ETIMEDOUT;
841 else
842 host->cmd->error = -EILSEQ;
843
844 host->cmd = NULL;
845
846 /*
847 * Sometimes command error interrupts and command complete
848 * interrupt will arrive together. Clear all command related
849 * interrupts here.
850 */
851 sdhci_writel(host, intmask & CMD_MASK, SDHCI_INT_STATUS);
852 intmask &= ~CMD_MASK;
853 }
854
855 return intmask;
856}
857
5da5e494
FA		 858static void sdhci_omap_set_timeout(struct sdhci_host *host,
859 struct mmc_command *cmd)
860{
861 if (cmd->opcode == MMC_ERASE)
862 sdhci_set_data_timeout_irq(host, false);
863
864 __sdhci_set_timeout(host, cmd);
865}
866
7d326930
KVA		 867static struct sdhci_ops sdhci_omap_ops = {
868 .set_clock = sdhci_omap_set_clock,
869 .set_power = sdhci_omap_set_power,
870 .enable_dma = sdhci_omap_enable_dma,
871 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
872 .get_min_clock = sdhci_omap_get_min_clock,
873 .set_bus_width = sdhci_omap_set_bus_width,
874 .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
5b0d6210 875 .reset = sdhci_omap_reset,
27ceb7e0 876 .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
5c41ea6d 877 .irq = sdhci_omap_irq,
5da5e494 878 .set_timeout = sdhci_omap_set_timeout,
7d326930
KVA		 879};
880
881static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
882{
883 u32 reg;
884 int ret = 0;
885 struct device *dev = omap_host->dev;
886 struct regulator *vqmmc;
887
888 vqmmc = regulator_get(dev, "vqmmc");
889 if (IS_ERR(vqmmc)) {
890 ret = PTR_ERR(vqmmc);
891 goto reg_put;
892 }
893
894 /* voltage capabilities might be set by boot loader, clear it */
895 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
896 reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
897
898 if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
899 reg |= CAPA_VS33;
900 if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
901 reg |= CAPA_VS18;
902
903 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
904
905reg_put:
906 regulator_put(vqmmc);
907
908 return ret;
909}
910
911static const struct sdhci_pltfm_data sdhci_omap_pdata = {
912 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
913 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
914 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
915 SDHCI_QUIRK_NO_HISPD_BIT |
916 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
e0b2dbcf
KVA		 917 .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
918 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
25f80d86
KVA		 919 SDHCI_QUIRK2_RSP_136_HAS_CRC |
920 SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
7d326930
KVA		 921 .ops = &sdhci_omap_ops,
922};
923
6d75df75
KVA		 924static const struct sdhci_omap_data k2g_data = {
925 .offset = 0x200,
926};
927
d6fe4928
FA		 928static const struct sdhci_omap_data am335_data = {
929 .offset = 0x200,
9e84a2e6 930 .flags = SDHCI_OMAP_SPECIAL_RESET,
d6fe4928
FA		 931};
932
933static const struct sdhci_omap_data am437_data = {
934 .offset = 0x200,
9e84a2e6 935 .flags = SDHCI_OMAP_SPECIAL_RESET,
d6fe4928
FA		 936};
937
7d326930
KVA		 938static const struct sdhci_omap_data dra7_data = {
939 .offset = 0x200,
8d20b2ea 940 .flags = SDHCI_OMAP_REQUIRE_IODELAY,
7d326930
KVA		 941};
942
943static const struct of_device_id omap_sdhci_match[] = {
944 { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
6d75df75 945 { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
d6fe4928
FA		 946 { .compatible = "ti,am335-sdhci", .data = &am335_data },
947 { .compatible = "ti,am437-sdhci", .data = &am437_data },
7d326930
KVA		 948 {},
949};
950MODULE_DEVICE_TABLE(of, omap_sdhci_match);
951
8d20b2ea
KVA		 952static struct pinctrl_state
953*sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
954 u32 *caps, u32 capmask)
955{
956 struct device *dev = omap_host->dev;
212f4f8a 957 char *version = omap_host->version;
8d20b2ea 958 struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
212f4f8a 959 char str[20];
8d20b2ea
KVA		 960
961 if (!(*caps & capmask))
962 goto ret;
963
212f4f8a
KVA		 964 if (version) {
965 snprintf(str, 20, "%s-%s", mode, version);
966 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
967 }
968
969 if (IS_ERR(pinctrl_state))
970 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
971
8d20b2ea
KVA		 972 if (IS_ERR(pinctrl_state)) {
973 dev_err(dev, "no pinctrl state for %s mode", mode);
974 *caps &= ~capmask;
975 }
976
977ret:
978 return pinctrl_state;
979}
980
981static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
982 *omap_host)
983{
984 struct device *dev = omap_host->dev;
985 struct sdhci_host *host = omap_host->host;
986 struct mmc_host *mmc = host->mmc;
987 u32 *caps = &mmc->caps;
988 u32 *caps2 = &mmc->caps2;
989 struct pinctrl_state *state;
990 struct pinctrl_state **pinctrl_state;
991
992 if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
993 return 0;
994
a86854d0
KC		 995 pinctrl_state = devm_kcalloc(dev,
996 MMC_TIMING_MMC_HS200 + 1,
997 sizeof(*pinctrl_state),
998 GFP_KERNEL);
8d20b2ea
KVA		 999 if (!pinctrl_state)
1000 return -ENOMEM;
1001
1002 omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
1003 if (IS_ERR(omap_host->pinctrl)) {
1004 dev_err(dev, "Cannot get pinctrl\n");
1005 return PTR_ERR(omap_host->pinctrl);
1006 }
1007
1008 state = pinctrl_lookup_state(omap_host->pinctrl, "default");
1009 if (IS_ERR(state)) {
1010 dev_err(dev, "no pinctrl state for default mode\n");
1011 return PTR_ERR(state);
1012 }
1013 pinctrl_state[MMC_TIMING_LEGACY] = state;
1014
1015 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
1016 MMC_CAP_UHS_SDR104);
1017 if (!IS_ERR(state))
1018 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
1019
1020 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
1021 MMC_CAP_UHS_DDR50);
1022 if (!IS_ERR(state))
1023 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
1024
1025 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
1026 MMC_CAP_UHS_SDR50);
1027 if (!IS_ERR(state))
1028 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
1029
1030 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
1031 MMC_CAP_UHS_SDR25);
1032 if (!IS_ERR(state))
1033 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
1034
1035 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
1036 MMC_CAP_UHS_SDR12);
1037 if (!IS_ERR(state))
1038 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
1039
1040 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
1041 MMC_CAP_1_8V_DDR);
3f402878 1042 if (!IS_ERR(state)) {
8d20b2ea 1043 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
3f402878
KVA		 1044 } else {
1045 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
1046 caps,
1047 MMC_CAP_3_3V_DDR);
1048 if (!IS_ERR(state))
1049 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1050 }
8d20b2ea
KVA		 1051
1052 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1053 MMC_CAP_SD_HIGHSPEED);
1054 if (!IS_ERR(state))
1055 pinctrl_state[MMC_TIMING_SD_HS] = state;
1056
1057 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1058 MMC_CAP_MMC_HIGHSPEED);
1059 if (!IS_ERR(state))
1060 pinctrl_state[MMC_TIMING_MMC_HS] = state;
1061
1062 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
1063 MMC_CAP2_HS200_1_8V_SDR);
1064 if (!IS_ERR(state))
1065 pinctrl_state[MMC_TIMING_MMC_HS200] = state;
1066
1067 omap_host->pinctrl_state = pinctrl_state;
1068
1069 return 0;
1070}
1071
212f4f8a
KVA		 1072static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
1073 {
1074 .machine = "DRA7[45]*",
1075 .revision = "ES1.[01]",
1076 },
1077 {
1078 /* sentinel */
1079 }
1080};
1081
7d326930
KVA		 1082static int sdhci_omap_probe(struct platform_device *pdev)
1083{
1084 int ret;
1085 u32 offset;
1086 struct device *dev = &pdev->dev;
1087 struct sdhci_host *host;
1088 struct sdhci_pltfm_host *pltfm_host;
1089 struct sdhci_omap_host *omap_host;
1090 struct mmc_host *mmc;
1091 const struct of_device_id *match;
1092 struct sdhci_omap_data *data;
212f4f8a 1093 const struct soc_device_attribute *soc;
195fadb7 1094 struct resource *regs;
7d326930
KVA		 1095
1096 match = of_match_device(omap_sdhci_match, dev);
1097 if (!match)
1098 return -EINVAL;
1099
1100 data = (struct sdhci_omap_data *)match->data;
1101 if (!data) {
1102 dev_err(dev, "no sdhci omap data\n");
1103 return -EINVAL;
1104 }
1105 offset = data->offset;
1106
195fadb7
CZ		 1107 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1108 if (!regs)
1109 return -ENXIO;
1110
7d326930
KVA		 1111 host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
1112 sizeof(*omap_host));
1113 if (IS_ERR(host)) {
1114 dev_err(dev, "Failed sdhci_pltfm_init\n");
1115 return PTR_ERR(host);
1116 }
1117
1118 pltfm_host = sdhci_priv(host);
1119 omap_host = sdhci_pltfm_priv(pltfm_host);
1120 omap_host->host = host;
1121 omap_host->base = host->ioaddr;
1122 omap_host->dev = dev;
300df508 1123 omap_host->power_mode = MMC_POWER_UNDEFINED;
8d20b2ea
KVA		 1124 omap_host->timing = MMC_TIMING_LEGACY;
1125 omap_host->flags = data->flags;
7d326930 1126 host->ioaddr += offset;
195fadb7 1127 host->mapbase = regs->start + offset;
7d326930
KVA		 1128
1129 mmc = host->mmc;
1d3a2220 1130 sdhci_get_of_property(pdev);
7d326930
KVA		 1131 ret = mmc_of_parse(mmc);
1132 if (ret)
1133 goto err_pltfm_free;
1134
212f4f8a
KVA		 1135 soc = soc_device_match(sdhci_omap_soc_devices);
1136 if (soc) {
1137 omap_host->version = "rev11";
1138 if (!strcmp(dev_name(dev), "4809c000.mmc"))
1139 mmc->f_max = 96000000;
1140 if (!strcmp(dev_name(dev), "480b4000.mmc"))
1141 mmc->f_max = 48000000;
1142 if (!strcmp(dev_name(dev), "480ad000.mmc"))
1143 mmc->f_max = 48000000;
1144 }
1145
031d2ccc
KVA		 1146 if (!mmc_can_gpio_ro(mmc))
1147 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1148
7d326930
KVA		 1149 pltfm_host->clk = devm_clk_get(dev, "fck");
1150 if (IS_ERR(pltfm_host->clk)) {
1151 ret = PTR_ERR(pltfm_host->clk);
1152 goto err_pltfm_free;
1153 }
1154
1155 ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
1156 if (ret) {
1157 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
1158 goto err_pltfm_free;
1159 }
1160
1161 omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
1162 if (IS_ERR(omap_host->pbias)) {
1163 ret = PTR_ERR(omap_host->pbias);
1164 if (ret != -ENODEV)
1165 goto err_pltfm_free;
1166 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
1167 }
1168 omap_host->pbias_enabled = false;
1169
1170 /*
1171 * omap_device_pm_domain has callbacks to enable the main
1172 * functional clock, interface clock and also configure the
1173 * SYSCONFIG register of omap devices. The callback will be invoked
1174 * as part of pm_runtime_get_sync.
1175 */
1176 pm_runtime_enable(dev);
809ae4e1
TT		 1177 ret = pm_runtime_resume_and_get(dev);
1178 if (ret) {
7d326930 1179 dev_err(dev, "pm_runtime_get_sync failed\n");
7d326930
KVA		 1180 goto err_rpm_disable;
1181 }
1182
1183 ret = sdhci_omap_set_capabilities(omap_host);
1184 if (ret) {
1185 dev_err(dev, "failed to set system capabilities\n");
1186 goto err_put_sync;
1187 }
1188
7d326930
KVA		 1189 host->mmc_host_ops.start_signal_voltage_switch =
1190 sdhci_omap_start_signal_voltage_switch;
1191 host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
20ea26a1 1192 host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
9fc2cd76 1193 host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
efde12b2 1194 host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
7d326930 1195
195fadb7
CZ		 1196 /* Switch to external DMA only if there is the "dmas" property */
1197 if (of_find_property(dev->of_node, "dmas", NULL))
1198 sdhci_switch_external_dma(host, true);
1199
055e0483
UH		 1200 /* R1B responses is required to properly manage HW busy detection. */
1201 mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
1202
0ec4ee3c 1203 ret = sdhci_setup_host(host);
7d326930
KVA		 1204 if (ret)
1205 goto err_put_sync;
1206
0ec4ee3c
KVA		 1207 ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
1208 if (ret)
1209 goto err_cleanup_host;
1210
1211 ret = __sdhci_add_host(host);
1212 if (ret)
1213 goto err_cleanup_host;
1214
7d326930
KVA		 1215 return 0;
1216
0ec4ee3c
KVA		 1217err_cleanup_host:
1218 sdhci_cleanup_host(host);
1219
7d326930
KVA		 1220err_put_sync:
1221 pm_runtime_put_sync(dev);
1222
1223err_rpm_disable:
1224 pm_runtime_disable(dev);
1225
1226err_pltfm_free:
1227 sdhci_pltfm_free(pdev);
1228 return ret;
1229}
1230
1231static int sdhci_omap_remove(struct platform_device *pdev)
1232{
1233 struct device *dev = &pdev->dev;
1234 struct sdhci_host *host = platform_get_drvdata(pdev);
1235
1236 sdhci_remove_host(host, true);
1237 pm_runtime_put_sync(dev);
1238 pm_runtime_disable(dev);
1239 sdhci_pltfm_free(pdev);
1240
1241 return 0;
1242}
ee0f3092
FA		 1243#ifdef CONFIG_PM_SLEEP
1244static void sdhci_omap_context_save(struct sdhci_omap_host *omap_host)
1245{
1246 omap_host->con = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
1247 omap_host->hctl = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
1248 omap_host->capa = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
1249}
1250
1251static void sdhci_omap_context_restore(struct sdhci_omap_host *omap_host)
1252{
1253 sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, omap_host->con);
1254 sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, omap_host->hctl);
1255 sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, omap_host->capa);
1256}
1257
1258static int __maybe_unused sdhci_omap_suspend(struct device *dev)
1259{
1260 struct sdhci_host *host = dev_get_drvdata(dev);
1261 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1262 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1263
1264 sdhci_suspend_host(host);
1265
1266 sdhci_omap_context_save(omap_host);
1267
1268 pinctrl_pm_select_idle_state(dev);
1269
1270 pm_runtime_force_suspend(dev);
1271
1272 return 0;
1273}
1274
1275static int __maybe_unused sdhci_omap_resume(struct device *dev)
1276{
1277 struct sdhci_host *host = dev_get_drvdata(dev);
1278 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1279 struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
1280
1281 pm_runtime_force_resume(dev);
1282
1283 pinctrl_pm_select_default_state(dev);
1284
1285 sdhci_omap_context_restore(omap_host);
1286
1287 sdhci_resume_host(host);
1288
1289 return 0;
1290}
1291#endif
1292static SIMPLE_DEV_PM_OPS(sdhci_omap_dev_pm_ops, sdhci_omap_suspend,
1293 sdhci_omap_resume);
7d326930
KVA		 1294
1295static struct platform_driver sdhci_omap_driver = {
1296 .probe = sdhci_omap_probe,
1297 .remove = sdhci_omap_remove,
1298 .driver = {
1299 .name = "sdhci-omap",
a1a48919 1300 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
ee0f3092 1301 .pm = &sdhci_omap_dev_pm_ops,
7d326930
KVA		 1302 .of_match_table = omap_sdhci_match,
1303 },
1304};
1305
1306module_platform_driver(sdhci_omap_driver);
1307
1308MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
1309MODULE_AUTHOR("Texas Instruments Inc.");
1310MODULE_LICENSE("GPL v2");
1311MODULE_ALIAS("platform:sdhci_omap");
Linux 6.x block layer and io_uring tree(s)